Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3073

1

T1

4

T2

6

T13

4

auto[1]

306

1

T16

1

T75

7

T135

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T4	1		T46	2		T195	1
auto[134217728:268435455]	107	1			T18	1		T46	2		T5	2
auto[268435456:402653183]	87	1			T16	1		T189	1		T4	1
auto[402653184:536870911]	94	1			T1	1		T2	1		T34	1
auto[536870912:671088639]	91	1			T26	1		T43	1		T6	1
auto[671088640:805306367]	122	1			T34	1		T61	1		T4	1
auto[805306368:939524095]	110	1			T16	1		T5	1		T6	4
auto[939524096:1073741823]	107	1			T4	1		T46	1		T51	1
auto[1073741824:1207959551]	102	1			T61	1		T26	1		T46	3
auto[1207959552:1342177279]	102	1			T26	1		T51	1		T5	1
auto[1342177280:1476395007]	96	1			T17	1		T4	3		T46	3
auto[1476395008:1610612735]	90	1			T13	1		T34	1		T46	1
auto[1610612736:1744830463]	110	1			T13	1		T61	1		T46	1
auto[1744830464:1879048191]	98	1			T34	1		T4	1		T43	1
auto[1879048192:2013265919]	111	1			T13	1		T16	1		T4	1
auto[2013265920:2147483647]	106	1			T6	2		T222	1		T24	1
auto[2147483648:2281701375]	116	1			T2	1		T18	1		T4	2
auto[2281701376:2415919103]	111	1			T1	1		T34	1		T46	2
auto[2415919104:2550136831]	92	1			T16	1		T34	1		T26	1
auto[2550136832:2684354559]	98	1			T1	1		T16	1		T17	1
auto[2684354560:2818572287]	94	1			T18	1		T4	1		T46	2
auto[2818572288:2952790015]	105	1			T189	1		T4	1		T46	1
auto[2952790016:3087007743]	120	1			T2	1		T26	1		T46	1
auto[3087007744:3221225471]	111	1			T2	1		T16	1		T4	1
auto[3221225472:3355443199]	100	1			T46	2		T51	1		T5	2
auto[3355443200:3489660927]	116	1			T1	1		T74	1		T76	1
auto[3489660928:3623878655]	120	1			T34	1		T46	3		T43	1
auto[3623878656:3758096383]	111	1			T16	1		T17	1		T26	1
auto[3758096384:3892314111]	101	1			T2	1		T5	1		T74	1
auto[3892314112:4026531839]	122	1			T2	1		T13	1		T4	1
auto[4026531840:4160749567]	138	1			T16	1		T4	2		T51	1
auto[4160749568:4294967295]	96	1			T4	1		T46	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	82	1			T4	1		T46	2		T195	1
auto[0:134217727]	auto[1]	13	1			T136	1		T269	1		T123	1
auto[134217728:268435455]	auto[0]	98	1			T18	1		T46	2		T5	2
auto[134217728:268435455]	auto[1]	9	1			T389	1		T258	2		T383	1
auto[268435456:402653183]	auto[0]	80	1			T16	1		T189	1		T4	1
auto[268435456:402653183]	auto[1]	7	1			T366	1		T367	1		T258	1
auto[402653184:536870911]	auto[0]	81	1			T1	1		T2	1		T34	1
auto[402653184:536870911]	auto[1]	13	1			T269	1		T123	1		T238	3
auto[536870912:671088639]	auto[0]	79	1			T26	1		T43	1		T6	1
auto[536870912:671088639]	auto[1]	12	1			T136	1		T122	2		T123	1
auto[671088640:805306367]	auto[0]	116	1			T34	1		T61	1		T4	1
auto[671088640:805306367]	auto[1]	6	1			T135	1		T122	1		T123	1
auto[805306368:939524095]	auto[0]	99	1			T16	1		T5	1		T6	4
auto[805306368:939524095]	auto[1]	11	1			T121	1		T176	1		T122	2
auto[939524096:1073741823]	auto[0]	99	1			T4	1		T46	1		T51	1
auto[939524096:1073741823]	auto[1]	8	1			T75	1		T176	2		T214	1
auto[1073741824:1207959551]	auto[0]	93	1			T61	1		T26	1		T46	3
auto[1073741824:1207959551]	auto[1]	9	1			T176	1		T122	2		T295	1
auto[1207959552:1342177279]	auto[0]	94	1			T26	1		T51	1		T5	1
auto[1207959552:1342177279]	auto[1]	8	1			T136	1		T176	1		T122	1
auto[1342177280:1476395007]	auto[0]	88	1			T17	1		T4	3		T46	3
auto[1342177280:1476395007]	auto[1]	8	1			T120	1		T176	1		T214	1
auto[1476395008:1610612735]	auto[0]	83	1			T13	1		T34	1		T46	1
auto[1476395008:1610612735]	auto[1]	7	1			T120	1		T176	1		T366	1
auto[1610612736:1744830463]	auto[0]	102	1			T13	1		T61	1		T46	1
auto[1610612736:1744830463]	auto[1]	8	1			T123	1		T238	2		T343	1
auto[1744830464:1879048191]	auto[0]	86	1			T34	1		T4	1		T43	1
auto[1744830464:1879048191]	auto[1]	12	1			T75	1		T120	1		T366	1
auto[1879048192:2013265919]	auto[0]	104	1			T13	1		T16	1		T4	1
auto[1879048192:2013265919]	auto[1]	7	1			T120	1		T122	1		T123	1
auto[2013265920:2147483647]	auto[0]	91	1			T6	2		T222	1		T24	1
auto[2013265920:2147483647]	auto[1]	15	1			T176	1		T269	1		T295	1
auto[2147483648:2281701375]	auto[0]	104	1			T2	1		T18	1		T4	2
auto[2147483648:2281701375]	auto[1]	12	1			T122	1		T123	2		T214	1
auto[2281701376:2415919103]	auto[0]	100	1			T1	1		T34	1		T46	2
auto[2281701376:2415919103]	auto[1]	11	1			T123	2		T238	1		T258	1
auto[2415919104:2550136831]	auto[0]	83	1			T16	1		T34	1		T26	1
auto[2415919104:2550136831]	auto[1]	9	1			T295	1		T228	1		T343	1
auto[2550136832:2684354559]	auto[0]	93	1			T1	1		T16	1		T17	1
auto[2550136832:2684354559]	auto[1]	5	1			T135	1		T269	1		T389	1
auto[2684354560:2818572287]	auto[0]	89	1			T18	1		T4	1		T46	2
auto[2684354560:2818572287]	auto[1]	5	1			T123	1		T406	1		T388	1
auto[2818572288:2952790015]	auto[0]	98	1			T189	1		T4	1		T46	1
auto[2818572288:2952790015]	auto[1]	7	1			T121	1		T280	2		T343	1
auto[2952790016:3087007743]	auto[0]	104	1			T2	1		T26	1		T46	1
auto[2952790016:3087007743]	auto[1]	16	1			T136	2		T120	1		T122	2
auto[3087007744:3221225471]	auto[0]	100	1			T2	1		T16	1		T4	1
auto[3087007744:3221225471]	auto[1]	11	1			T296	1		T343	1		T386	1
auto[3221225472:3355443199]	auto[0]	92	1			T46	2		T51	1		T5	2
auto[3221225472:3355443199]	auto[1]	8	1			T75	1		T136	1		T122	1
auto[3355443200:3489660927]	auto[0]	109	1			T1	1		T74	1		T76	1
auto[3355443200:3489660927]	auto[1]	7	1			T295	1		T123	1		T366	1
auto[3489660928:3623878655]	auto[0]	109	1			T34	1		T46	3		T43	1
auto[3489660928:3623878655]	auto[1]	11	1			T75	1		T295	1		T228	2
auto[3623878656:3758096383]	auto[0]	107	1			T16	1		T17	1		T26	1
auto[3623878656:3758096383]	auto[1]	4	1			T75	1		T121	1		T383	1
auto[3758096384:3892314111]	auto[0]	91	1			T2	1		T5	1		T74	1
auto[3758096384:3892314111]	auto[1]	10	1			T122	1		T389	1		T275	2
auto[3892314112:4026531839]	auto[0]	111	1			T2	1		T13	1		T4	1
auto[3892314112:4026531839]	auto[1]	11	1			T75	1		T136	1		T238	1
auto[4026531840:4160749567]	auto[0]	122	1			T4	2		T51	1		T5	2
auto[4026531840:4160749567]	auto[1]	16	1			T16	1		T75	1		T390	1
auto[4160749568:4294967295]	auto[0]	86	1			T4	1		T46	1		T51	1
auto[4160749568:4294967295]	auto[1]	10	1			T122	1		T280	2		T296	1