Unified Coverage Report :: Group Instance : sealing_sw_binding_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1730

1

T1

2

T2

4

T3

1

auto[1]

1853

1

T1

2

T2

2

T16

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T18	1		T4	1		T46	2
auto[134217728:268435455]	112	1			T17	1		T46	1		T51	1
auto[268435456:402653183]	118	1			T1	1		T4	2		T46	1
auto[402653184:536870911]	107	1			T2	1		T18	1		T46	1
auto[536870912:671088639]	110	1			T1	1		T46	2		T43	1
auto[671088640:805306367]	111	1			T16	1		T61	1		T4	1
auto[805306368:939524095]	110	1			T2	1		T34	2		T46	2
auto[939524096:1073741823]	110	1			T13	1		T4	2		T46	2
auto[1073741824:1207959551]	132	1			T18	1		T26	1		T4	2
auto[1207959552:1342177279]	96	1			T16	1		T61	1		T26	1
auto[1342177280:1476395007]	100	1			T4	2		T46	1		T51	1
auto[1476395008:1610612735]	115	1			T46	3		T43	1		T51	2
auto[1610612736:1744830463]	113	1			T16	1		T34	1		T4	1
auto[1744830464:1879048191]	124	1			T2	1		T34	1		T4	1
auto[1879048192:2013265919]	91	1			T189	1		T46	3		T43	1
auto[2013265920:2147483647]	110	1			T26	2		T4	1		T46	1
auto[2147483648:2281701375]	112	1			T4	2		T46	1		T5	2
auto[2281701376:2415919103]	106	1			T34	1		T4	2		T46	2
auto[2415919104:2550136831]	121	1			T16	1		T34	1		T189	1
auto[2550136832:2684354559]	129	1			T4	1		T46	1		T5	2
auto[2684354560:2818572287]	112	1			T3	1		T17	1		T34	1
auto[2818572288:2952790015]	104	1			T1	1		T13	1		T46	1
auto[2952790016:3087007743]	113	1			T2	1		T16	2		T34	1
auto[3087007744:3221225471]	97	1			T61	1		T4	3		T43	2
auto[3221225472:3355443199]	125	1			T2	1		T34	1		T46	1
auto[3355443200:3489660927]	121	1			T46	1		T43	1		T76	1
auto[3489660928:3623878655]	111	1			T2	1		T17	1		T46	3
auto[3623878656:3758096383]	116	1			T1	1		T13	1		T16	1
auto[3758096384:3892314111]	103	1			T4	1		T43	2		T5	2
auto[3892314112:4026531839]	109	1			T61	1		T4	1		T46	1
auto[4026531840:4160749567]	119	1			T26	1		T4	1		T46	2
auto[4160749568:4294967295]	112	1			T13	1		T4	2		T46	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	65	1			T18	1		T4	1		T46	2
auto[0:134217727]	auto[1]	49	1			T179	1		T122	1		T112	1
auto[134217728:268435455]	auto[0]	55	1			T17	1		T51	1		T76	1
auto[134217728:268435455]	auto[1]	57	1			T46	1		T6	3		T52	1
auto[268435456:402653183]	auto[0]	56	1			T4	2		T46	1		T51	1
auto[268435456:402653183]	auto[1]	62	1			T1	1		T5	1		T6	1
auto[402653184:536870911]	auto[0]	51	1			T2	1		T46	1		T6	1
auto[402653184:536870911]	auto[1]	56	1			T18	1		T43	1		T135	1
auto[536870912:671088639]	auto[0]	55	1			T46	2		T5	1		T44	1
auto[536870912:671088639]	auto[1]	55	1			T1	1		T43	1		T5	2
auto[671088640:805306367]	auto[0]	55	1			T4	1		T46	1		T5	1
auto[671088640:805306367]	auto[1]	56	1			T16	1		T61	1		T51	2
auto[805306368:939524095]	auto[0]	48	1			T2	1		T34	2		T46	1
auto[805306368:939524095]	auto[1]	62	1			T46	1		T51	1		T6	1
auto[939524096:1073741823]	auto[0]	53	1			T13	1		T4	1		T5	1
auto[939524096:1073741823]	auto[1]	57	1			T4	1		T46	2		T51	1
auto[1073741824:1207959551]	auto[0]	67	1			T26	1		T4	1		T5	1
auto[1073741824:1207959551]	auto[1]	65	1			T18	1		T4	1		T46	2
auto[1207959552:1342177279]	auto[0]	43	1			T26	1		T46	2		T47	1
auto[1207959552:1342177279]	auto[1]	53	1			T16	1		T61	1		T5	3
auto[1342177280:1476395007]	auto[0]	45	1			T51	1		T6	2		T57	1
auto[1342177280:1476395007]	auto[1]	55	1			T4	2		T46	1		T135	1
auto[1476395008:1610612735]	auto[0]	63	1			T46	2		T43	1		T5	5
auto[1476395008:1610612735]	auto[1]	52	1			T46	1		T51	2		T5	1
auto[1610612736:1744830463]	auto[0]	52	1			T16	1		T34	1		T5	1
auto[1610612736:1744830463]	auto[1]	61	1			T4	1		T46	3		T51	1
auto[1744830464:1879048191]	auto[0]	59	1			T51	1		T76	1		T44	1
auto[1744830464:1879048191]	auto[1]	65	1			T2	1		T34	1		T4	1
auto[1879048192:2013265919]	auto[0]	51	1			T189	1		T46	2		T43	1
auto[1879048192:2013265919]	auto[1]	40	1			T46	1		T195	1		T78	1
auto[2013265920:2147483647]	auto[0]	58	1			T26	2		T5	1		T76	3
auto[2013265920:2147483647]	auto[1]	52	1			T4	1		T46	1		T51	4
auto[2147483648:2281701375]	auto[0]	59	1			T4	2		T5	2		T6	1
auto[2147483648:2281701375]	auto[1]	53	1			T46	1		T57	1		T377	1
auto[2281701376:2415919103]	auto[0]	53	1			T46	1		T51	1		T5	1
auto[2281701376:2415919103]	auto[1]	53	1			T34	1		T4	2		T46	1
auto[2415919104:2550136831]	auto[0]	64	1			T16	1		T46	1		T51	1
auto[2415919104:2550136831]	auto[1]	57	1			T34	1		T189	1		T4	1
auto[2550136832:2684354559]	auto[0]	53	1			T5	1		T74	1		T76	1
auto[2550136832:2684354559]	auto[1]	76	1			T4	1		T46	1		T5	1
auto[2684354560:2818572287]	auto[0]	51	1			T3	1		T17	1		T5	1
auto[2684354560:2818572287]	auto[1]	61	1			T34	1		T46	2		T5	1
auto[2818572288:2952790015]	auto[0]	51	1			T1	1		T13	1		T46	1
auto[2818572288:2952790015]	auto[1]	53	1			T51	2		T195	1		T45	1
auto[2952790016:3087007743]	auto[0]	52	1			T2	1		T34	1		T46	2
auto[2952790016:3087007743]	auto[1]	61	1			T16	2		T76	1		T6	1
auto[3087007744:3221225471]	auto[0]	43	1			T4	1		T5	1		T222	1
auto[3087007744:3221225471]	auto[1]	54	1			T61	1		T4	2		T43	2
auto[3221225472:3355443199]	auto[0]	53	1			T34	1		T135	1		T6	1
auto[3221225472:3355443199]	auto[1]	72	1			T2	1		T46	1		T81	1
auto[3355443200:3489660927]	auto[0]	54	1			T46	1		T43	1		T76	1
auto[3355443200:3489660927]	auto[1]	67	1			T44	1		T24	1		T235	1
auto[3489660928:3623878655]	auto[0]	51	1			T2	1		T17	1		T46	2
auto[3489660928:3623878655]	auto[1]	60	1			T46	1		T44	1		T6	1
auto[3623878656:3758096383]	auto[0]	57	1			T1	1		T13	1		T26	1
auto[3623878656:3758096383]	auto[1]	59	1			T16	1		T4	4		T46	1
auto[3758096384:3892314111]	auto[0]	52	1			T4	1		T43	1		T136	1
auto[3758096384:3892314111]	auto[1]	51	1			T43	1		T5	2		T176	1
auto[3892314112:4026531839]	auto[0]	49	1			T61	1		T57	1		T378	1
auto[3892314112:4026531839]	auto[1]	60	1			T4	1		T46	1		T51	1
auto[4026531840:4160749567]	auto[0]	59	1			T26	1		T5	1		T6	1
auto[4026531840:4160749567]	auto[1]	60	1			T4	1		T46	2		T75	1
auto[4160749568:4294967295]	auto[0]	53	1			T13	1		T5	2		T44	1
auto[4160749568:4294967295]	auto[1]	59	1			T4	2		T46	2		T5	2