Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4970

1

T1

4

T2

8

T13

8

auto[1]

2196

1

T1

4

T2

4

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	214	1			T1	2		T4	2		T43	2
auto[134217728:268435455]	240	1			T61	4		T4	2		T46	10
auto[268435456:402653183]	196	1			T34	2		T46	4		T5	4
auto[402653184:536870911]	264	1			T3	2		T34	2		T46	6
auto[536870912:671088639]	224	1			T13	2		T16	2		T34	2
auto[671088640:805306367]	250	1			T26	2		T46	2		T43	2
auto[805306368:939524095]	216	1			T61	2		T46	10		T51	2
auto[939524096:1073741823]	194	1			T4	4		T46	4		T43	2
auto[1073741824:1207959551]	222	1			T13	2		T4	4		T46	4
auto[1207959552:1342177279]	250	1			T16	2		T34	2		T4	2
auto[1342177280:1476395007]	250	1			T13	2		T34	2		T4	4
auto[1476395008:1610612735]	230	1			T2	2		T34	2		T61	2
auto[1610612736:1744830463]	216	1			T34	2		T4	2		T51	4
auto[1744830464:1879048191]	272	1			T2	2		T18	2		T26	2
auto[1879048192:2013265919]	234	1			T17	2		T189	2		T46	2
auto[2013265920:2147483647]	206	1			T1	2		T46	2		T5	4
auto[2147483648:2281701375]	198	1			T2	2		T74	2		T76	2
auto[2281701376:2415919103]	214	1			T189	2		T4	2		T46	2
auto[2415919104:2550136831]	196	1			T17	4		T4	2		T46	6
auto[2550136832:2684354559]	226	1			T34	2		T4	2		T51	2
auto[2684354560:2818572287]	190	1			T16	2		T46	4		T51	2
auto[2818572288:2952790015]	232	1			T2	2		T18	2		T4	4
auto[2952790016:3087007743]	216	1			T16	2		T26	2		T4	4
auto[3087007744:3221225471]	202	1			T4	2		T46	4		T5	4
auto[3221225472:3355443199]	188	1			T1	2		T4	2		T51	4
auto[3355443200:3489660927]	234	1			T13	2		T46	2		T43	2
auto[3489660928:3623878655]	260	1			T2	2		T4	2		T46	2
auto[3623878656:3758096383]	200	1			T4	2		T46	2		T51	2
auto[3758096384:3892314111]	270	1			T2	2		T16	4		T34	2
auto[3892314112:4026531839]	228	1			T1	2		T16	2		T4	2
auto[4026531840:4160749567]	232	1			T18	2		T4	2		T46	4
auto[4160749568:4294967295]	202	1			T26	2		T4	2		T43	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	140	1			T1	2		T43	2		T51	2
auto[0:134217727]	auto[1]	74	1			T4	2		T5	2		T135	2
auto[134217728:268435455]	auto[0]	178	1			T61	2		T4	2		T46	10
auto[134217728:268435455]	auto[1]	62	1			T61	2		T6	2		T24	2
auto[268435456:402653183]	auto[0]	154	1			T34	2		T46	4		T5	4
auto[268435456:402653183]	auto[1]	42	1			T64	2		T372	2		T58	2
auto[402653184:536870911]	auto[0]	178	1			T34	2		T46	6		T51	4
auto[402653184:536870911]	auto[1]	86	1			T3	2		T391	2		T82	2
auto[536870912:671088639]	auto[0]	170	1			T13	2		T16	2		T34	2
auto[536870912:671088639]	auto[1]	54	1			T4	2		T46	2		T104	2
auto[671088640:805306367]	auto[0]	156	1			T26	2		T46	2		T43	2
auto[671088640:805306367]	auto[1]	94	1			T45	2		T300	4		T57	2
auto[805306368:939524095]	auto[0]	162	1			T46	6		T51	2		T5	4
auto[805306368:939524095]	auto[1]	54	1			T61	2		T46	4		T5	2
auto[939524096:1073741823]	auto[0]	140	1			T4	2		T46	4		T43	2
auto[939524096:1073741823]	auto[1]	54	1			T4	2		T222	2		T45	4
auto[1073741824:1207959551]	auto[0]	176	1			T13	2		T4	4		T46	4
auto[1073741824:1207959551]	auto[1]	46	1			T124	2		T398	2		T83	2
auto[1207959552:1342177279]	auto[0]	170	1			T16	2		T34	2		T4	2
auto[1207959552:1342177279]	auto[1]	80	1			T46	2		T43	2		T135	2
auto[1342177280:1476395007]	auto[0]	178	1			T13	2		T34	2		T46	2
auto[1342177280:1476395007]	auto[1]	72	1			T4	4		T43	2		T51	2
auto[1476395008:1610612735]	auto[0]	154	1			T2	2		T34	2		T4	2
auto[1476395008:1610612735]	auto[1]	76	1			T61	2		T4	2		T51	2
auto[1610612736:1744830463]	auto[0]	142	1			T34	2		T4	2		T5	2
auto[1610612736:1744830463]	auto[1]	74	1			T51	4		T81	2		T6	4
auto[1744830464:1879048191]	auto[0]	180	1			T2	2		T18	2		T26	2
auto[1744830464:1879048191]	auto[1]	92	1			T4	2		T51	2		T6	2
auto[1879048192:2013265919]	auto[0]	180	1			T17	2		T189	2		T46	2
auto[1879048192:2013265919]	auto[1]	54	1			T57	2		T231	2		T370	2
auto[2013265920:2147483647]	auto[0]	136	1			T5	2		T6	2		T45	2
auto[2013265920:2147483647]	auto[1]	70	1			T1	2		T46	2		T5	2
auto[2147483648:2281701375]	auto[0]	118	1			T2	2		T76	2		T6	4
auto[2147483648:2281701375]	auto[1]	80	1			T74	2		T6	4		T52	2
auto[2281701376:2415919103]	auto[0]	144	1			T189	2		T46	2		T74	2
auto[2281701376:2415919103]	auto[1]	70	1			T4	2		T135	2		T6	2
auto[2415919104:2550136831]	auto[0]	128	1			T17	4		T46	6		T5	2
auto[2415919104:2550136831]	auto[1]	68	1			T4	2		T5	2		T6	2
auto[2550136832:2684354559]	auto[0]	150	1			T34	2		T4	2		T51	2
auto[2550136832:2684354559]	auto[1]	76	1			T6	2		T104	2		T345	2
auto[2684354560:2818572287]	auto[0]	126	1			T16	2		T46	4		T51	2
auto[2684354560:2818572287]	auto[1]	64	1			T6	2		T214	2		T125	2
auto[2818572288:2952790015]	auto[0]	164	1			T4	2		T46	4		T5	6
auto[2818572288:2952790015]	auto[1]	68	1			T2	2		T18	2		T4	2
auto[2952790016:3087007743]	auto[0]	152	1			T16	2		T4	2		T46	6
auto[2952790016:3087007743]	auto[1]	64	1			T26	2		T4	2		T64	2
auto[3087007744:3221225471]	auto[0]	146	1			T46	4		T5	4		T135	2
auto[3087007744:3221225471]	auto[1]	56	1			T4	2		T81	2		T52	2
auto[3221225472:3355443199]	auto[0]	118	1			T51	2		T5	2		T64	2
auto[3221225472:3355443199]	auto[1]	70	1			T1	2		T4	2		T51	2
auto[3355443200:3489660927]	auto[0]	162	1			T13	2		T46	2		T43	2
auto[3355443200:3489660927]	auto[1]	72	1			T5	4		T222	2		T64	2
auto[3489660928:3623878655]	auto[0]	156	1			T51	2		T5	2		T76	4
auto[3489660928:3623878655]	auto[1]	104	1			T2	2		T4	2		T46	2
auto[3623878656:3758096383]	auto[0]	142	1			T4	2		T46	2		T51	2
auto[3623878656:3758096383]	auto[1]	58	1			T5	2		T300	2		T393	2
auto[3758096384:3892314111]	auto[0]	194	1			T2	2		T16	4		T34	2
auto[3758096384:3892314111]	auto[1]	76	1			T46	2		T51	2		T45	2
auto[3892314112:4026531839]	auto[0]	164	1			T1	2		T16	2		T46	4
auto[3892314112:4026531839]	auto[1]	64	1			T4	2		T194	2		T395	2
auto[4026531840:4160749567]	auto[0]	164	1			T18	2		T4	2		T46	4
auto[4026531840:4160749567]	auto[1]	68	1			T56	2		T236	2		T111	2
auto[4160749568:4294967295]	auto[0]	148	1			T4	2		T43	2		T5	2
auto[4160749568:4294967295]	auto[1]	54	1			T26	2		T399	2		T400	2