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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.04 97.87 98.46 100.00 99.02 98.41 91.14


Total test records in report: 1090
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1010 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.65787103 Jul 01 10:34:23 AM PDT 24 Jul 01 10:34:25 AM PDT 24 14832941 ps
T152 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.990650826 Jul 01 10:34:16 AM PDT 24 Jul 01 10:34:24 AM PDT 24 173621508 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.575570822 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:06 AM PDT 24 147717056 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.913046832 Jul 01 10:34:28 AM PDT 24 Jul 01 10:34:31 AM PDT 24 94469869 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3069616457 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:17 AM PDT 24 75121280 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3995557755 Jul 01 10:34:12 AM PDT 24 Jul 01 10:34:26 AM PDT 24 3482133625 ps
T149 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2710345290 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:18 AM PDT 24 348376781 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1921167997 Jul 01 10:34:11 AM PDT 24 Jul 01 10:34:15 AM PDT 24 152361267 ps
T1016 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3608950011 Jul 01 10:34:23 AM PDT 24 Jul 01 10:34:25 AM PDT 24 104803658 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3255449567 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:09 AM PDT 24 2273752731 ps
T1018 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.360258535 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:05 AM PDT 24 33537319 ps
T157 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2894185113 Jul 01 10:34:20 AM PDT 24 Jul 01 10:34:28 AM PDT 24 233599380 ps
T1019 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3118156314 Jul 01 10:34:25 AM PDT 24 Jul 01 10:34:32 AM PDT 24 458882077 ps
T159 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.811763716 Jul 01 10:34:24 AM PDT 24 Jul 01 10:34:28 AM PDT 24 58103232 ps
T1020 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3316640663 Jul 01 10:34:20 AM PDT 24 Jul 01 10:34:27 AM PDT 24 27858231 ps
T1021 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1363351272 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:14 AM PDT 24 159891369 ps
T1022 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4251834917 Jul 01 10:34:05 AM PDT 24 Jul 01 10:34:10 AM PDT 24 227404655 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1662841902 Jul 01 10:34:14 AM PDT 24 Jul 01 10:34:19 AM PDT 24 389050991 ps
T1024 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2178858047 Jul 01 10:34:34 AM PDT 24 Jul 01 10:34:37 AM PDT 24 390666979 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2195284675 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:11 AM PDT 24 122067904 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3448677922 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:17 AM PDT 24 95241070 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2649366669 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:04 AM PDT 24 25639975 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2181137762 Jul 01 10:34:07 AM PDT 24 Jul 01 10:34:11 AM PDT 24 20918707 ps
T1029 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3060058203 Jul 01 10:34:24 AM PDT 24 Jul 01 10:34:26 AM PDT 24 39397432 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3885461344 Jul 01 10:34:01 AM PDT 24 Jul 01 10:34:04 AM PDT 24 209630172 ps
T1031 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2397862885 Jul 01 10:34:48 AM PDT 24 Jul 01 10:34:50 AM PDT 24 7738331 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3522711145 Jul 01 10:34:22 AM PDT 24 Jul 01 10:34:25 AM PDT 24 96669530 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4193801831 Jul 01 10:34:08 AM PDT 24 Jul 01 10:34:14 AM PDT 24 217688857 ps
T1034 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1473741470 Jul 01 10:34:11 AM PDT 24 Jul 01 10:34:26 AM PDT 24 4169508305 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.994084550 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:09 AM PDT 24 30360274 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1367543636 Jul 01 10:34:15 AM PDT 24 Jul 01 10:34:18 AM PDT 24 46248079 ps
T1037 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.231376808 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:18 AM PDT 24 89227253 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.817436959 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:18 AM PDT 24 23529207 ps
T1039 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1983817086 Jul 01 10:34:38 AM PDT 24 Jul 01 10:34:40 AM PDT 24 38560115 ps
T1040 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1860154995 Jul 01 10:34:33 AM PDT 24 Jul 01 10:34:36 AM PDT 24 129639562 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1106594904 Jul 01 10:34:31 AM PDT 24 Jul 01 10:34:32 AM PDT 24 82590839 ps
T1042 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1826717266 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:07 AM PDT 24 186372076 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1571198382 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:10 AM PDT 24 14183250 ps
T148 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4052306389 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:12 AM PDT 24 1660364511 ps
T1044 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.932927555 Jul 01 10:34:45 AM PDT 24 Jul 01 10:34:47 AM PDT 24 11082367 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3599021865 Jul 01 10:34:28 AM PDT 24 Jul 01 10:34:39 AM PDT 24 479073373 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3613129145 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:21 AM PDT 24 626252740 ps
T1047 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1377358450 Jul 01 10:34:23 AM PDT 24 Jul 01 10:34:37 AM PDT 24 744649660 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1100052069 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:18 AM PDT 24 672211144 ps
T162 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3237409798 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:15 AM PDT 24 54678777 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.6527353 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:07 AM PDT 24 128669078 ps
T1050 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.851631700 Jul 01 10:34:16 AM PDT 24 Jul 01 10:34:21 AM PDT 24 110380652 ps
T147 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3652130168 Jul 01 10:34:14 AM PDT 24 Jul 01 10:34:23 AM PDT 24 685076397 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4074282951 Jul 01 10:34:25 AM PDT 24 Jul 01 10:34:26 AM PDT 24 39944087 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4255103769 Jul 01 10:34:12 AM PDT 24 Jul 01 10:34:19 AM PDT 24 146411164 ps
T1053 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2847601745 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:17 AM PDT 24 63307008 ps
T1054 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2343561973 Jul 01 10:34:29 AM PDT 24 Jul 01 10:34:30 AM PDT 24 35241218 ps
T145 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1270396785 Jul 01 10:34:16 AM PDT 24 Jul 01 10:34:22 AM PDT 24 95850502 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2755221327 Jul 01 10:34:24 AM PDT 24 Jul 01 10:34:26 AM PDT 24 34752867 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1948615647 Jul 01 10:34:14 AM PDT 24 Jul 01 10:34:20 AM PDT 24 293221805 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2114966616 Jul 01 10:34:20 AM PDT 24 Jul 01 10:34:23 AM PDT 24 25748817 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1571361209 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:17 AM PDT 24 2158684129 ps
T1059 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1054519056 Jul 01 10:34:23 AM PDT 24 Jul 01 10:34:35 AM PDT 24 448288786 ps
T1060 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2551827174 Jul 01 10:34:12 AM PDT 24 Jul 01 10:34:20 AM PDT 24 803955642 ps
T1061 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.934511056 Jul 01 10:34:32 AM PDT 24 Jul 01 10:34:34 AM PDT 24 20720631 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2966615581 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:13 AM PDT 24 69737064 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.843113792 Jul 01 10:34:04 AM PDT 24 Jul 01 10:34:13 AM PDT 24 891211912 ps
T1064 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2841692359 Jul 01 10:34:05 AM PDT 24 Jul 01 10:34:08 AM PDT 24 11565671 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.344507381 Jul 01 10:34:07 AM PDT 24 Jul 01 10:34:12 AM PDT 24 31521981 ps
T1066 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4194364685 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:10 AM PDT 24 54430717 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.678568541 Jul 01 10:34:17 AM PDT 24 Jul 01 10:34:34 AM PDT 24 253855228 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2689371843 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:31 AM PDT 24 453004529 ps
T1069 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1075412310 Jul 01 10:34:17 AM PDT 24 Jul 01 10:34:21 AM PDT 24 28699020 ps
T1070 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2908492361 Jul 01 10:34:04 AM PDT 24 Jul 01 10:34:07 AM PDT 24 80832278 ps
T1071 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4090731525 Jul 01 10:34:24 AM PDT 24 Jul 01 10:34:26 AM PDT 24 67723247 ps
T1072 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4161252556 Jul 01 10:34:47 AM PDT 24 Jul 01 10:34:50 AM PDT 24 26082493 ps
T1073 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.360632242 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:21 AM PDT 24 168650165 ps
T1074 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1135122036 Jul 01 10:34:12 AM PDT 24 Jul 01 10:34:33 AM PDT 24 13783398 ps
T1075 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3180766618 Jul 01 10:34:35 AM PDT 24 Jul 01 10:34:45 AM PDT 24 1794488037 ps
T1076 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1816539138 Jul 01 10:34:20 AM PDT 24 Jul 01 10:34:23 AM PDT 24 12179662 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.324271621 Jul 01 10:34:14 AM PDT 24 Jul 01 10:34:19 AM PDT 24 33672478 ps
T1078 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2791547562 Jul 01 10:34:34 AM PDT 24 Jul 01 10:34:36 AM PDT 24 15496054 ps
T1079 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.181474118 Jul 01 10:34:12 AM PDT 24 Jul 01 10:34:17 AM PDT 24 266646113 ps
T1080 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3156734600 Jul 01 10:34:34 AM PDT 24 Jul 01 10:34:37 AM PDT 24 87306180 ps
T1081 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.358929517 Jul 01 10:34:04 AM PDT 24 Jul 01 10:34:07 AM PDT 24 124313235 ps
T1082 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3531299380 Jul 01 10:34:27 AM PDT 24 Jul 01 10:34:29 AM PDT 24 144579099 ps
T1083 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3189163056 Jul 01 10:34:09 AM PDT 24 Jul 01 10:34:17 AM PDT 24 147008845 ps
T1084 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1179103497 Jul 01 10:34:13 AM PDT 24 Jul 01 10:34:19 AM PDT 24 825831007 ps
T151 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2456309574 Jul 01 10:34:18 AM PDT 24 Jul 01 10:34:23 AM PDT 24 53987589 ps
T1085 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.60926390 Jul 01 10:34:35 AM PDT 24 Jul 01 10:34:37 AM PDT 24 52842277 ps
T1086 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3607247849 Jul 01 10:34:14 AM PDT 24 Jul 01 10:34:21 AM PDT 24 680225017 ps
T1087 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2763293626 Jul 01 10:34:19 AM PDT 24 Jul 01 10:34:22 AM PDT 24 12335288 ps
T1088 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.993818537 Jul 01 10:34:05 AM PDT 24 Jul 01 10:34:11 AM PDT 24 110681187 ps
T1089 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.122313861 Jul 01 10:34:07 AM PDT 24 Jul 01 10:34:11 AM PDT 24 348455668 ps
T1090 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2206764002 Jul 01 10:34:56 AM PDT 24 Jul 01 10:34:58 AM PDT 24 23888422 ps

Test location /workspace/coverage/default/39.keymgr_custom_cm.662746397
Short name T3
Test name
Test status
Simulation time 288991575 ps
CPU time 5.8 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 218368 kb
Host smart-9ad53fa4-1ef7-4c1b-8ecd-3385e93e20b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662746397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.662746397
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2061279965
Short name T5
Test name
Test status
Simulation time 37359311574 ps
CPU time 309.43 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 220980 kb
Host smart-cd648552-e151-4c24-a1ec-897be66aa7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061279965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2061279965
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2370213920
Short name T46
Test name
Test status
Simulation time 3764758001 ps
CPU time 35.48 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:37 AM PDT 24
Peak memory 216196 kb
Host smart-4643b94e-1924-496c-9648-23fe98a28c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370213920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2370213920
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4119555968
Short name T57
Test name
Test status
Simulation time 602069449 ps
CPU time 8.62 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 218276 kb
Host smart-6d7ca2d5-b144-4816-8b02-d42ff5590a26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119555968 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4119555968
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1934151397
Short name T9
Test name
Test status
Simulation time 494127605 ps
CPU time 5.05 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 237228 kb
Host smart-ea128760-fad0-477e-acbb-4addc5810de7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934151397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1934151397
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3025905012
Short name T6
Test name
Test status
Simulation time 2059715357 ps
CPU time 54.41 seconds
Started Jul 01 10:59:43 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 222544 kb
Host smart-4294235a-168c-4195-8b04-0a87cad90076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025905012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3025905012
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3037463401
Short name T13
Test name
Test status
Simulation time 74163610 ps
CPU time 3.5 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:41 AM PDT 24
Peak memory 214256 kb
Host smart-90c8233e-d321-48c9-a441-63a85bd0d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037463401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3037463401
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3229382130
Short name T102
Test name
Test status
Simulation time 188278565 ps
CPU time 6.54 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 219776 kb
Host smart-4c61d4a3-2d73-472b-bba8-9b1d7768688c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229382130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3229382130
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3294843171
Short name T7
Test name
Test status
Simulation time 81203364 ps
CPU time 2.24 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:00:59 AM PDT 24
Peak memory 216488 kb
Host smart-028409a2-ea7b-40a9-86f3-6db403705640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294843171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3294843171
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1247399427
Short name T122
Test name
Test status
Simulation time 622802697 ps
CPU time 16.12 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 215576 kb
Host smart-6ee92a6f-6850-492b-8ce4-9d8fbd0abd38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247399427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1247399427
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.512704327
Short name T111
Test name
Test status
Simulation time 712358368 ps
CPU time 21.25 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 221264 kb
Host smart-e6e8a2de-643e-4e93-a6ab-fdeb13e2f12d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512704327 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.512704327
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.88203329
Short name T238
Test name
Test status
Simulation time 1134430772 ps
CPU time 14.15 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 215240 kb
Host smart-4c438da8-7e62-4c37-bdd2-f7859367364f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88203329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.88203329
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3410617805
Short name T45
Test name
Test status
Simulation time 40987442071 ps
CPU time 381.39 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:07:33 AM PDT 24
Peak memory 218980 kb
Host smart-4a3142f3-2d0c-45e0-8b4b-13c147cd575a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410617805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3410617805
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2929945000
Short name T384
Test name
Test status
Simulation time 1404162433 ps
CPU time 70.89 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:02:13 AM PDT 24
Peak memory 214620 kb
Host smart-5738d599-7f85-4d69-ba71-1a20dac7d24c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929945000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2929945000
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1491212798
Short name T85
Test name
Test status
Simulation time 54116965 ps
CPU time 3.15 seconds
Started Jul 01 10:59:02 AM PDT 24
Finished Jul 01 10:59:06 AM PDT 24
Peak memory 214320 kb
Host smart-3e12e24e-b2e1-4b4b-a341-97643c666bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491212798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1491212798
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2382332236
Short name T403
Test name
Test status
Simulation time 3135847564 ps
CPU time 83.5 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 217840 kb
Host smart-df88dd86-ad93-45e7-b303-68a4ac79a967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382332236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2382332236
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1914258443
Short name T16
Test name
Test status
Simulation time 46311468 ps
CPU time 2.77 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 222496 kb
Host smart-d9f50540-36d0-4119-87b4-c4c3bf74b20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914258443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1914258443
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3813101073
Short name T619
Test name
Test status
Simulation time 681995902 ps
CPU time 4.26 seconds
Started Jul 01 11:01:32 AM PDT 24
Finished Jul 01 11:01:37 AM PDT 24
Peak memory 214708 kb
Host smart-d35cfc4a-2751-4766-8326-32893a648cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813101073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3813101073
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2020810035
Short name T383
Test name
Test status
Simulation time 429742221 ps
CPU time 10.74 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 215264 kb
Host smart-3ec7a67b-0397-4035-aee7-589815a45548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020810035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2020810035
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2249193417
Short name T182
Test name
Test status
Simulation time 23671331354 ps
CPU time 482.05 seconds
Started Jul 01 10:59:46 AM PDT 24
Finished Jul 01 11:07:48 AM PDT 24
Peak memory 222548 kb
Host smart-25ed150e-4f92-4a86-8812-5c8a41d72c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249193417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2249193417
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1074105836
Short name T209
Test name
Test status
Simulation time 87720943 ps
CPU time 4.08 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 219464 kb
Host smart-24825fd1-a597-4907-9ddf-99fd7272322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074105836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1074105836
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2447636059
Short name T103
Test name
Test status
Simulation time 2582691022 ps
CPU time 11.68 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:46 AM PDT 24
Peak memory 220940 kb
Host smart-717faea2-afad-4fe9-91cc-dcc43743e4c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447636059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2447636059
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3384389668
Short name T140
Test name
Test status
Simulation time 784964263 ps
CPU time 5.6 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:14 AM PDT 24
Peak memory 222648 kb
Host smart-ac5c6489-0519-4f47-a8a4-cf7c287b549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384389668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3384389668
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.191990276
Short name T123
Test name
Test status
Simulation time 644402456 ps
CPU time 8.55 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 215556 kb
Host smart-854a0e9c-71cf-48d7-8f8f-9de9da282c4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191990276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.191990276
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1715640637
Short name T201
Test name
Test status
Simulation time 200298366 ps
CPU time 2.76 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 217836 kb
Host smart-17fdada1-9083-4d9a-bca9-df5db9356583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715640637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1715640637
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1492423422
Short name T269
Test name
Test status
Simulation time 306809687 ps
CPU time 3.65 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:10 AM PDT 24
Peak memory 214300 kb
Host smart-2a0eadee-c91d-4fa9-b747-a901a200b59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492423422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1492423422
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1883050763
Short name T75
Test name
Test status
Simulation time 186572428 ps
CPU time 9.57 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 214452 kb
Host smart-b20d759d-509c-4baa-96e7-29a1a4ad2572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883050763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1883050763
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2412894458
Short name T98
Test name
Test status
Simulation time 353684247 ps
CPU time 3.37 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 210128 kb
Host smart-641b75d1-7aee-49e9-a2a1-3a450c66a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412894458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2412894458
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3815789022
Short name T184
Test name
Test status
Simulation time 8793741736 ps
CPU time 173.23 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:03:00 AM PDT 24
Peak memory 222584 kb
Host smart-42e17800-badc-45d4-9ce0-8929a6f0e4ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815789022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3815789022
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.264150644
Short name T4
Test name
Test status
Simulation time 1380399644 ps
CPU time 46.52 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:45 AM PDT 24
Peak memory 222580 kb
Host smart-ca511df5-6076-43e0-acc5-a4ff20a400de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264150644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.264150644
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1022425741
Short name T100
Test name
Test status
Simulation time 39216000 ps
CPU time 0.84 seconds
Started Jul 01 10:59:30 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 206056 kb
Host smart-10fa223f-3fb3-41c5-a16e-3efc2297f83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022425741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1022425741
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2911078974
Short name T146
Test name
Test status
Simulation time 147344814 ps
CPU time 4.35 seconds
Started Jul 01 10:34:42 AM PDT 24
Finished Jul 01 10:34:47 AM PDT 24
Peak memory 205088 kb
Host smart-d3897ce4-49e0-4cde-8e38-54e75015d468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911078974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2911078974
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1645317538
Short name T81
Test name
Test status
Simulation time 1094561298 ps
CPU time 27.95 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:29 AM PDT 24
Peak memory 221436 kb
Host smart-9ad92cbf-2ecc-4418-a7fa-c42c8e4551f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645317538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1645317538
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.967193917
Short name T224
Test name
Test status
Simulation time 14639183949 ps
CPU time 60.77 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 11:00:37 AM PDT 24
Peak memory 216216 kb
Host smart-93088fe8-b752-4035-8da8-4c64da0da95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967193917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.967193917
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.651386935
Short name T212
Test name
Test status
Simulation time 892311980 ps
CPU time 12.53 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 214472 kb
Host smart-5579e03e-3c63-4d88-b113-92ea5d7ad24e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651386935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.651386935
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1869578669
Short name T354
Test name
Test status
Simulation time 98714591426 ps
CPU time 813.78 seconds
Started Jul 01 11:00:36 AM PDT 24
Finished Jul 01 11:14:10 AM PDT 24
Peak memory 222668 kb
Host smart-0c589ebc-8ce6-4cd0-9056-48870a60a1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869578669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1869578669
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4153313321
Short name T114
Test name
Test status
Simulation time 399885484 ps
CPU time 23.8 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:33 AM PDT 24
Peak memory 222716 kb
Host smart-7f9ec333-2a70-4e23-96f9-cdebb788657d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153313321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4153313321
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1668720031
Short name T167
Test name
Test status
Simulation time 2771696121 ps
CPU time 37.91 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 10:59:58 AM PDT 24
Peak memory 222556 kb
Host smart-a315eebd-41c3-440f-a51a-ea0c17030dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668720031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1668720031
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1385539992
Short name T22
Test name
Test status
Simulation time 183662913 ps
CPU time 3.86 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:53 AM PDT 24
Peak memory 222792 kb
Host smart-75bb4b98-a29a-4259-89aa-fa9b4353998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385539992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1385539992
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3177501633
Short name T139
Test name
Test status
Simulation time 87333778 ps
CPU time 2.5 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 217856 kb
Host smart-3a342e62-db23-419f-aeb8-d531e736d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177501633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3177501633
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2305235510
Short name T219
Test name
Test status
Simulation time 185845016 ps
CPU time 4.41 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 10:59:40 AM PDT 24
Peak memory 222544 kb
Host smart-3e5d9b43-9578-4eb0-ac39-c2fedcbbe6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305235510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2305235510
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4147020919
Short name T298
Test name
Test status
Simulation time 7203837274 ps
CPU time 80.13 seconds
Started Jul 01 11:00:27 AM PDT 24
Finished Jul 01 11:01:48 AM PDT 24
Peak memory 222580 kb
Host smart-fc952f23-2899-4218-ab7d-909ca24831e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147020919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4147020919
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1704961023
Short name T295
Test name
Test status
Simulation time 252808762 ps
CPU time 4.09 seconds
Started Jul 01 10:59:15 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 214328 kb
Host smart-27fee829-90b5-4971-bf1e-8221e370e2ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704961023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1704961023
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1143365130
Short name T120
Test name
Test status
Simulation time 72650928 ps
CPU time 4.54 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:00:50 AM PDT 24
Peak memory 215720 kb
Host smart-60a3e1a1-e709-4e5c-9978-8b7a75ff8bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143365130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1143365130
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3667566804
Short name T49
Test name
Test status
Simulation time 2457707310 ps
CPU time 27.48 seconds
Started Jul 01 11:00:46 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 217096 kb
Host smart-266c0224-4be7-411f-b82a-b7dccfbc1d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667566804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3667566804
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1639670129
Short name T138
Test name
Test status
Simulation time 36894590 ps
CPU time 2.5 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:10 AM PDT 24
Peak memory 217416 kb
Host smart-1164ba2d-d2d8-40e4-a6a0-cf45ca078472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639670129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1639670129
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2661340982
Short name T141
Test name
Test status
Simulation time 292932999 ps
CPU time 4.7 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 222620 kb
Host smart-1b43c3b5-4b51-4267-826f-b2e84282cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661340982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2661340982
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3315136916
Short name T48
Test name
Test status
Simulation time 78024259 ps
CPU time 1.73 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 214132 kb
Host smart-346cd9b4-1178-449c-90cc-58c7bb94d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315136916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3315136916
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.778154470
Short name T244
Test name
Test status
Simulation time 423971429 ps
CPU time 3.32 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 215444 kb
Host smart-f4ff85f5-56b9-427c-a802-aba32020780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778154470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.778154470
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4205632518
Short name T257
Test name
Test status
Simulation time 1761027441 ps
CPU time 23.41 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 208736 kb
Host smart-831cbfb7-3112-4bbf-8589-039a32dc2458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205632518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4205632518
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3439973670
Short name T206
Test name
Test status
Simulation time 2762065624 ps
CPU time 47.91 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:53 AM PDT 24
Peak memory 222532 kb
Host smart-7e1f73a6-163a-43be-84d7-d23405971418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439973670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3439973670
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2787530237
Short name T156
Test name
Test status
Simulation time 151674221 ps
CPU time 2.28 seconds
Started Jul 01 11:00:51 AM PDT 24
Finished Jul 01 11:00:54 AM PDT 24
Peak memory 210156 kb
Host smart-7b1fc99d-652d-45f4-8b35-fdb84d23f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787530237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2787530237
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1270396785
Short name T145
Test name
Test status
Simulation time 95850502 ps
CPU time 2.49 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 205288 kb
Host smart-d90029b6-df31-4bcc-9165-a53c7671d8be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270396785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1270396785
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2710345290
Short name T149
Test name
Test status
Simulation time 348376781 ps
CPU time 5.09 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 214824 kb
Host smart-b54fdfae-dbed-477b-9cfe-c18eed76fc36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710345290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2710345290
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2456309574
Short name T151
Test name
Test status
Simulation time 53987589 ps
CPU time 2.99 seconds
Started Jul 01 10:34:18 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 214712 kb
Host smart-1827c383-4a72-488e-ad2b-e26f04f9bd6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456309574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2456309574
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3652130168
Short name T147
Test name
Test status
Simulation time 685076397 ps
CPU time 5.61 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 213572 kb
Host smart-50454514-bf12-4f9e-b21b-4b22f8281085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652130168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3652130168
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2951841594
Short name T137
Test name
Test status
Simulation time 135993212 ps
CPU time 4.99 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 217820 kb
Host smart-94fa4bbd-897c-4c87-8c8b-b269ff99067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951841594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2951841594
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2351145635
Short name T425
Test name
Test status
Simulation time 67364879 ps
CPU time 3.42 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 208692 kb
Host smart-019eaef3-2b4f-4f0a-ac1e-bd5afd8788a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351145635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2351145635
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1082465840
Short name T96
Test name
Test status
Simulation time 471302098 ps
CPU time 21.21 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 220860 kb
Host smart-20a09596-0693-4bdd-a958-ca3ba3a7ea57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082465840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1082465840
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3989384298
Short name T850
Test name
Test status
Simulation time 590113282 ps
CPU time 6.06 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 214656 kb
Host smart-22028461-5458-4012-9cd2-947e0d1092bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989384298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3989384298
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2022181089
Short name T405
Test name
Test status
Simulation time 179254952 ps
CPU time 3.36 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 214352 kb
Host smart-435e5a5c-6f4b-472d-8381-44f2ebc63e9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022181089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2022181089
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.196952631
Short name T24
Test name
Test status
Simulation time 892324522 ps
CPU time 6.68 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 209400 kb
Host smart-63508c98-8bb6-4040-84e5-f918754a47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196952631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.196952631
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2490411900
Short name T61
Test name
Test status
Simulation time 65991953 ps
CPU time 3.57 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 209788 kb
Host smart-eb14cd74-98c2-4af2-bccc-d071165542d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490411900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2490411900
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3905983700
Short name T52
Test name
Test status
Simulation time 136941343 ps
CPU time 3.33 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 222520 kb
Host smart-83146fa4-043d-4430-aa6a-978dea926e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905983700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3905983700
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4141500246
Short name T15
Test name
Test status
Simulation time 218634184 ps
CPU time 3.12 seconds
Started Jul 01 10:59:08 AM PDT 24
Finished Jul 01 10:59:11 AM PDT 24
Peak memory 208408 kb
Host smart-bb39cbf9-0b06-432b-8955-eb7952743d1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141500246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4141500246
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3480375343
Short name T708
Test name
Test status
Simulation time 1738656197 ps
CPU time 30.67 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 222464 kb
Host smart-c782b797-98cf-4f02-9d4b-4d7f732d671c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480375343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3480375343
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.754519232
Short name T343
Test name
Test status
Simulation time 226716863 ps
CPU time 4.47 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 214316 kb
Host smart-724b897c-ccac-4891-9630-fa983053bef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754519232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.754519232
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3869384479
Short name T323
Test name
Test status
Simulation time 46190487 ps
CPU time 2.14 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:50 AM PDT 24
Peak memory 214336 kb
Host smart-6b06039e-b9e5-4872-9a13-f5d62428c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869384479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3869384479
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.849740344
Short name T124
Test name
Test status
Simulation time 1966595931 ps
CPU time 12.2 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 214308 kb
Host smart-9d53e423-cc65-47ef-9ad9-7bd54c902aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849740344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.849740344
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1530492053
Short name T600
Test name
Test status
Simulation time 93056670 ps
CPU time 2 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 214308 kb
Host smart-32abf7d2-b716-4820-8be2-34552c437436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530492053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1530492053
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3990306275
Short name T388
Test name
Test status
Simulation time 155807478 ps
CPU time 8.01 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 222412 kb
Host smart-054c29aa-40ba-4c17-bd62-36ad41246e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990306275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3990306275
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3796640362
Short name T329
Test name
Test status
Simulation time 54965307 ps
CPU time 3.77 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:11 AM PDT 24
Peak memory 215152 kb
Host smart-59f135ae-b9d5-42a0-b97f-9cee56fbb647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796640362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3796640362
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3019767096
Short name T351
Test name
Test status
Simulation time 5414211700 ps
CPU time 78.47 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:01:35 AM PDT 24
Peak memory 214408 kb
Host smart-a51bf9e9-43a0-43e9-94d8-d0fc29a68e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019767096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3019767096
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4266079630
Short name T250
Test name
Test status
Simulation time 260297282 ps
CPU time 4.15 seconds
Started Jul 01 11:00:17 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 218536 kb
Host smart-2e2897b1-9089-48dd-a332-9ff45479e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266079630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4266079630
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4249212966
Short name T40
Test name
Test status
Simulation time 472930797 ps
CPU time 9.07 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:35 AM PDT 24
Peak memory 211020 kb
Host smart-7c7075e8-2a02-4bef-be46-1fb22ee76929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249212966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4249212966
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2068464508
Short name T153
Test name
Test status
Simulation time 295574638 ps
CPU time 5 seconds
Started Jul 01 10:34:15 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 205384 kb
Host smart-6c3dc121-6c17-4544-8cde-cbde0b012b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068464508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2068464508
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3237409798
Short name T162
Test name
Test status
Simulation time 54678777 ps
CPU time 2.62 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 213580 kb
Host smart-57d964fe-89c8-46fa-8226-e7d5dc7a3c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237409798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3237409798
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.811763716
Short name T159
Test name
Test status
Simulation time 58103232 ps
CPU time 3.14 seconds
Started Jul 01 10:34:24 AM PDT 24
Finished Jul 01 10:34:28 AM PDT 24
Peak memory 214752 kb
Host smart-a4ddec40-09a5-4466-8bd9-ddf82324b497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811763716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.811763716
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.32304981
Short name T160
Test name
Test status
Simulation time 283663359 ps
CPU time 5.48 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 213540 kb
Host smart-d77ab1fb-4cd3-49f7-9df6-381411702c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.32304981
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.990650826
Short name T152
Test name
Test status
Simulation time 173621508 ps
CPU time 4.82 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 205368 kb
Host smart-c0b18086-8d6f-4b47-bf6a-8ad5150b25f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990650826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
990650826
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2186013232
Short name T89
Test name
Test status
Simulation time 434449635 ps
CPU time 8.39 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 221232 kb
Host smart-383ef659-8fef-48ed-9604-c7289df31f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186013232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2186013232
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4047512004
Short name T10
Test name
Test status
Simulation time 960342375 ps
CPU time 5.76 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:13 AM PDT 24
Peak memory 228968 kb
Host smart-11ce7a39-6d24-4b7e-b1de-f3ac947bc291
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047512004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4047512004
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.666687344
Short name T155
Test name
Test status
Simulation time 30050648 ps
CPU time 1.78 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 210204 kb
Host smart-2f6ec042-3b08-43c8-b983-a19c63e93755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666687344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.666687344
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2628492900
Short name T143
Test name
Test status
Simulation time 38364144 ps
CPU time 3.1 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 222720 kb
Host smart-5cfd31e5-6eb4-4378-9dde-17f856fbd701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628492900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2628492900
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.960458411
Short name T142
Test name
Test status
Simulation time 385875897 ps
CPU time 3.53 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 216904 kb
Host smart-5cdf369e-957a-4ede-9f48-8bd4044cefce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960458411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.960458411
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3118156314
Short name T1019
Test name
Test status
Simulation time 458882077 ps
CPU time 5.88 seconds
Started Jul 01 10:34:25 AM PDT 24
Finished Jul 01 10:34:32 AM PDT 24
Peak memory 213600 kb
Host smart-c0828e14-a954-491d-8923-e04fc8b7717c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118156314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3118156314
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4052306389
Short name T148
Test name
Test status
Simulation time 1660364511 ps
CPU time 3.56 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 213588 kb
Host smart-b1af6153-c217-4b57-9033-2f136cfcc00e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052306389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4052306389
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1245440856
Short name T356
Test name
Test status
Simulation time 137961445 ps
CPU time 2.62 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:08 AM PDT 24
Peak memory 207104 kb
Host smart-7d1f04b7-a7ee-485c-9415-4e5234d68dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245440856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1245440856
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2515759199
Short name T288
Test name
Test status
Simulation time 657989387 ps
CPU time 4.46 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:34 AM PDT 24
Peak memory 215316 kb
Host smart-e7c640a5-7448-4fa9-98a1-91b9deff5ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515759199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2515759199
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1497511197
Short name T275
Test name
Test status
Simulation time 91064226 ps
CPU time 3.46 seconds
Started Jul 01 10:59:27 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 214340 kb
Host smart-f63a8cc8-85c5-4cc5-bd90-0242e89c5fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497511197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1497511197
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1387651143
Short name T481
Test name
Test status
Simulation time 151368445 ps
CPU time 5.05 seconds
Started Jul 01 10:59:28 AM PDT 24
Finished Jul 01 10:59:34 AM PDT 24
Peak memory 207476 kb
Host smart-a596bdf6-79d3-4299-b370-24539049475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387651143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1387651143
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1021615011
Short name T840
Test name
Test status
Simulation time 182342374 ps
CPU time 3.04 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:40 AM PDT 24
Peak memory 216324 kb
Host smart-4616c566-7d0b-4361-8a80-3e23a0b37c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021615011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1021615011
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2977089795
Short name T233
Test name
Test status
Simulation time 544204051 ps
CPU time 5.38 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 220256 kb
Host smart-0989772f-25c5-41b4-a162-601859998516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977089795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2977089795
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1153057040
Short name T198
Test name
Test status
Simulation time 2971208350 ps
CPU time 40.12 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 221264 kb
Host smart-52f94dd3-9a62-4f38-b413-abd0c3e1a3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153057040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1153057040
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1729540704
Short name T864
Test name
Test status
Simulation time 126868793 ps
CPU time 2.61 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 214460 kb
Host smart-be4a9987-64f2-40ec-bfc4-a5be8d392834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729540704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1729540704
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1807591633
Short name T309
Test name
Test status
Simulation time 327412742 ps
CPU time 9.87 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 214492 kb
Host smart-39b44234-4fb6-4e29-95f1-467c0d74ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807591633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1807591633
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1069649128
Short name T23
Test name
Test status
Simulation time 127607164 ps
CPU time 2.96 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 222816 kb
Host smart-fa817b54-ee00-4b29-8024-79fe67cad875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069649128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1069649128
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2973599183
Short name T303
Test name
Test status
Simulation time 145474292 ps
CPU time 1.76 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 214444 kb
Host smart-140ddeaf-a6ad-494a-9459-8d9d5afd8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973599183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2973599183
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1818905032
Short name T322
Test name
Test status
Simulation time 85948710 ps
CPU time 4.21 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 214304 kb
Host smart-4310d346-96bf-4781-8297-bd831b856a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818905032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1818905032
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4167970392
Short name T333
Test name
Test status
Simulation time 102185064 ps
CPU time 4.77 seconds
Started Jul 01 11:00:28 AM PDT 24
Finished Jul 01 11:00:33 AM PDT 24
Peak memory 209192 kb
Host smart-f57f5bd6-6146-4e71-9a98-3433a8972780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167970392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4167970392
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3570812517
Short name T282
Test name
Test status
Simulation time 157895961 ps
CPU time 4.47 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:37 AM PDT 24
Peak memory 222508 kb
Host smart-ab4a89d1-ee9a-4b8d-831b-0f9a1a378bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570812517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3570812517
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1635744210
Short name T207
Test name
Test status
Simulation time 50427939 ps
CPU time 3.15 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 209764 kb
Host smart-6e79408d-c730-4919-b822-ce0fc83e5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635744210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1635744210
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.968584803
Short name T44
Test name
Test status
Simulation time 375776508 ps
CPU time 4.51 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:05 AM PDT 24
Peak memory 222432 kb
Host smart-0f4ee23d-2311-4e5d-a06f-8fa670d841c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968584803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.968584803
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3958932171
Short name T247
Test name
Test status
Simulation time 70976492 ps
CPU time 3.61 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:06 AM PDT 24
Peak memory 214308 kb
Host smart-6878c074-edb6-4dcb-9fee-3b00e249458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958932171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3958932171
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2767186085
Short name T228
Test name
Test status
Simulation time 48056803 ps
CPU time 3.79 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 214348 kb
Host smart-02053532-2d21-468c-af4b-66ffbd14ee43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767186085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2767186085
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3116920855
Short name T208
Test name
Test status
Simulation time 379181334 ps
CPU time 16.88 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 222608 kb
Host smart-020eb888-1571-4b16-9395-fcbf209efb12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116920855 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3116920855
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3241434770
Short name T197
Test name
Test status
Simulation time 143454066 ps
CPU time 2.68 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:24 AM PDT 24
Peak memory 209424 kb
Host smart-83760cbe-2d0c-47ae-a861-2038ed2f9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241434770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3241434770
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.911596583
Short name T56
Test name
Test status
Simulation time 652604631 ps
CPU time 4.11 seconds
Started Jul 01 11:00:54 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 222696 kb
Host smart-e52d4f71-f25b-4580-95d0-d2aea81a68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911596583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.911596583
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2616079563
Short name T949
Test name
Test status
Simulation time 526203943 ps
CPU time 7.99 seconds
Started Jul 01 10:34:09 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 205356 kb
Host smart-0560a252-7021-4741-93d7-dae8ed42d631
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616079563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
616079563
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1520464234
Short name T187
Test name
Test status
Simulation time 580071924 ps
CPU time 14.91 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 205300 kb
Host smart-8db15c43-9045-4ffb-b8ae-62f809cca28d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520464234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
520464234
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.994084550
Short name T1035
Test name
Test status
Simulation time 30360274 ps
CPU time 1.03 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 205276 kb
Host smart-7bc342e1-760f-4dc0-9397-cc013b9f2fc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994084550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.994084550
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2649366669
Short name T1027
Test name
Test status
Simulation time 25639975 ps
CPU time 1.88 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 221796 kb
Host smart-e947b8a4-6f49-4d7a-b588-c2d3a3658d38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649366669 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2649366669
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1571198382
Short name T1043
Test name
Test status
Simulation time 14183250 ps
CPU time 1.17 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 205308 kb
Host smart-f4cabb60-87be-4b0d-b158-6a1651fc935d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571198382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1571198382
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2130493402
Short name T991
Test name
Test status
Simulation time 45685085 ps
CPU time 0.66 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 205272 kb
Host smart-36889db4-34be-421e-a5af-97498ba6fcd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130493402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2130493402
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1921167997
Short name T1015
Test name
Test status
Simulation time 152361267 ps
CPU time 1.97 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 205372 kb
Host smart-bf71bf06-c405-4c13-bf4e-9f4d52af91f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921167997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1921167997
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.6527353
Short name T1049
Test name
Test status
Simulation time 128669078 ps
CPU time 2.36 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 213832 kb
Host smart-6e2f70d5-6edc-41a1-b30c-21f6246ff3ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6527353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_r
eg_errors.6527353
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3846121133
Short name T110
Test name
Test status
Simulation time 114827564 ps
CPU time 4.8 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 213772 kb
Host smart-c5aaad0b-8419-42b5-b4b4-71612c25ba18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846121133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3846121133
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4061611921
Short name T929
Test name
Test status
Simulation time 34990371 ps
CPU time 2.56 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 216592 kb
Host smart-2847bf42-6ff4-46a4-934a-c7e45fa8b388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061611921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4061611921
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3755529267
Short name T154
Test name
Test status
Simulation time 198339755 ps
CPU time 2.71 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 213612 kb
Host smart-98f84509-ae33-47f9-82b4-f90efcd1e8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755529267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3755529267
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2357459950
Short name T948
Test name
Test status
Simulation time 455639774 ps
CPU time 8.31 seconds
Started Jul 01 10:33:59 AM PDT 24
Finished Jul 01 10:34:08 AM PDT 24
Peak memory 205360 kb
Host smart-1da15184-2a83-4b6a-945e-6aec1dea9e16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357459950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
357459950
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2689371843
Short name T1068
Test name
Test status
Simulation time 453004529 ps
CPU time 12.42 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 205332 kb
Host smart-164b41b2-2a5c-4113-9771-ea33bf280485
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689371843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
689371843
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.575570822
Short name T1011
Test name
Test status
Simulation time 147717056 ps
CPU time 1.12 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:06 AM PDT 24
Peak memory 205468 kb
Host smart-4a483f9e-cc4a-4eac-aa0a-eb738abc713b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575570822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.575570822
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1721782879
Short name T970
Test name
Test status
Simulation time 21016295 ps
CPU time 1.72 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 217572 kb
Host smart-e564bae3-cf9e-4b79-8218-337d5b4c312e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721782879 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1721782879
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.358929517
Short name T1081
Test name
Test status
Simulation time 124313235 ps
CPU time 1.37 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 205376 kb
Host smart-e6a936d9-2440-4211-99a2-757f4ed236e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358929517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.358929517
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.213260190
Short name T931
Test name
Test status
Simulation time 24745009 ps
CPU time 0.86 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 205140 kb
Host smart-41293a42-b780-40ae-a898-7b5b06ae3429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213260190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.213260190
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.913046832
Short name T1012
Test name
Test status
Simulation time 94469869 ps
CPU time 2.41 seconds
Started Jul 01 10:34:28 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 205300 kb
Host smart-f4987d7d-d06f-4019-84bc-5dc551148444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913046832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.913046832
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.642579901
Short name T945
Test name
Test status
Simulation time 218571874 ps
CPU time 1.71 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 213956 kb
Host smart-eef69b5c-a5be-4f05-941a-8246c2d20138
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642579901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.642579901
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1054519056
Short name T1059
Test name
Test status
Simulation time 448288786 ps
CPU time 10.66 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:35 AM PDT 24
Peak memory 213908 kb
Host smart-2c379748-c91d-4605-912d-ef56bed4b966
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054519056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1054519056
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2213490985
Short name T173
Test name
Test status
Simulation time 125685879 ps
CPU time 3.04 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 216620 kb
Host smart-7f61a4fe-368e-4756-9e58-1849f43dd6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213490985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2213490985
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2182648070
Short name T952
Test name
Test status
Simulation time 196836015 ps
CPU time 3.59 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 213564 kb
Host smart-644a4a72-9666-4a05-920b-e747a9cd518b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182648070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2182648070
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1106594904
Short name T1041
Test name
Test status
Simulation time 82590839 ps
CPU time 1.02 seconds
Started Jul 01 10:34:31 AM PDT 24
Finished Jul 01 10:34:32 AM PDT 24
Peak memory 205184 kb
Host smart-1c22986e-ce07-49e1-afd8-1506bb909a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106594904 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1106594904
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.586360577
Short name T976
Test name
Test status
Simulation time 13795511 ps
CPU time 1.17 seconds
Started Jul 01 10:34:18 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 205420 kb
Host smart-4637b671-d547-4bce-a8fb-373e854c6fac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586360577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.586360577
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4074282951
Short name T1051
Test name
Test status
Simulation time 39944087 ps
CPU time 0.73 seconds
Started Jul 01 10:34:25 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 205208 kb
Host smart-f0be495f-1821-4ca2-a0a3-4d5c943ed1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074282951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4074282951
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.691349660
Short name T133
Test name
Test status
Simulation time 104675558 ps
CPU time 3.19 seconds
Started Jul 01 10:34:26 AM PDT 24
Finished Jul 01 10:34:30 AM PDT 24
Peak memory 205408 kb
Host smart-b078a59d-4749-4b74-a715-362460316013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691349660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.691349660
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.758703829
Short name T107
Test name
Test status
Simulation time 119231700 ps
CPU time 1.64 seconds
Started Jul 01 10:34:24 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 213764 kb
Host smart-1b56e930-5c76-4adf-b82b-563c6da93e3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758703829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.758703829
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3180766618
Short name T1075
Test name
Test status
Simulation time 1794488037 ps
CPU time 9.06 seconds
Started Jul 01 10:34:35 AM PDT 24
Finished Jul 01 10:34:45 AM PDT 24
Peak memory 213768 kb
Host smart-240bb456-df70-4fb0-b1a9-97351a906c6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180766618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3180766618
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.122313861
Short name T1089
Test name
Test status
Simulation time 348455668 ps
CPU time 2.51 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 213652 kb
Host smart-e229467a-b049-4d25-8a84-d1e863b894e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122313861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.122313861
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3187061617
Short name T947
Test name
Test status
Simulation time 223994088 ps
CPU time 1.59 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 213664 kb
Host smart-b79b26ac-a0d9-4228-a5a4-1c28d7fbfcb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187061617 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3187061617
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2841692359
Short name T1064
Test name
Test status
Simulation time 11565671 ps
CPU time 0.83 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:08 AM PDT 24
Peak memory 205316 kb
Host smart-0cdc1aa0-7801-41df-a7b6-586f1ac6b730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841692359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2841692359
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1664970686
Short name T963
Test name
Test status
Simulation time 72438688 ps
CPU time 0.79 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 205200 kb
Host smart-c7c62d0b-00bc-4728-93bd-6d1ad117bb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664970686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1664970686
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2075353446
Short name T961
Test name
Test status
Simulation time 36009975 ps
CPU time 2.12 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 205404 kb
Host smart-96fa983c-60c3-4d06-9a5c-06cc3174b378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075353446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2075353446
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3435238808
Short name T109
Test name
Test status
Simulation time 297737667 ps
CPU time 3.09 seconds
Started Jul 01 10:34:22 AM PDT 24
Finished Jul 01 10:34:27 AM PDT 24
Peak memory 213888 kb
Host smart-8e5d6edf-abcb-4573-8625-49aa4bdf8635
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435238808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3435238808
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3613129145
Short name T1046
Test name
Test status
Simulation time 626252740 ps
CPU time 5.99 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 219764 kb
Host smart-70c2c4d9-544a-41d9-8d13-d438efd7dec3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613129145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3613129145
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.851631700
Short name T1050
Test name
Test status
Simulation time 110380652 ps
CPU time 2.35 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213592 kb
Host smart-c164b8c3-7e3c-4fc0-9e58-08bb955b1019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851631700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.851631700
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1363351272
Short name T1021
Test name
Test status
Simulation time 159891369 ps
CPU time 1.42 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 205328 kb
Host smart-57aadb4f-ea9a-4217-9b82-f2d85ead6146
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363351272 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1363351272
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.609265588
Short name T975
Test name
Test status
Simulation time 26908176 ps
CPU time 1.41 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 205356 kb
Host smart-0032e80f-cf91-4a93-a729-4f12f111494b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609265588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.609265588
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4082821567
Short name T930
Test name
Test status
Simulation time 25823756 ps
CPU time 0.83 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 205264 kb
Host smart-e02e27e4-b341-4e2f-8a99-1b700fb9f5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082821567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4082821567
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4141212357
Short name T956
Test name
Test status
Simulation time 198022937 ps
CPU time 1.63 seconds
Started Jul 01 10:34:27 AM PDT 24
Finished Jul 01 10:34:29 AM PDT 24
Peak memory 205440 kb
Host smart-124bc698-1792-4619-a632-3a7012d89816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141212357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4141212357
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1035387292
Short name T108
Test name
Test status
Simulation time 803436502 ps
CPU time 4.59 seconds
Started Jul 01 10:34:15 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 213832 kb
Host smart-c05d182d-9636-44b0-83a6-2159cb838754
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035387292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1035387292
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.897620532
Short name T971
Test name
Test status
Simulation time 29233273 ps
CPU time 2.36 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:36 AM PDT 24
Peak memory 213560 kb
Host smart-05ac1050-b31e-45dd-b603-81bf0ca16b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897620532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.897620532
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2042233196
Short name T1004
Test name
Test status
Simulation time 197753952 ps
CPU time 2.94 seconds
Started Jul 01 10:34:15 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213428 kb
Host smart-db2c8201-dc7b-42d5-ba4a-8d8ecaa87e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042233196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2042233196
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1011927003
Short name T968
Test name
Test status
Simulation time 120743611 ps
CPU time 1.26 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 205396 kb
Host smart-5daf30ef-d63c-4629-bde3-8a7a93deeb3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011927003 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1011927003
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2114966616
Short name T1057
Test name
Test status
Simulation time 25748817 ps
CPU time 1.52 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 205296 kb
Host smart-dd4a834d-f325-4221-8cab-539f87b3e9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114966616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2114966616
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1961978430
Short name T967
Test name
Test status
Simulation time 48264125 ps
CPU time 0.71 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 205272 kb
Host smart-b92cbca3-a4fb-4555-bd35-bb1e08eb70d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961978430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1961978430
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2798080148
Short name T946
Test name
Test status
Simulation time 91131361 ps
CPU time 2.19 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 213576 kb
Host smart-07736dbb-f122-463a-825f-24d75d65cfd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798080148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2798080148
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1179103497
Short name T1084
Test name
Test status
Simulation time 825831007 ps
CPU time 3.12 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 213628 kb
Host smart-945c667f-fb7d-4f27-9013-1a76c96c5c68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179103497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1179103497
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1377358450
Short name T1047
Test name
Test status
Simulation time 744649660 ps
CPU time 12.26 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:37 AM PDT 24
Peak memory 221980 kb
Host smart-b4d1af06-b42f-4280-960c-975fda669cb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377358450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1377358450
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1464602591
Short name T944
Test name
Test status
Simulation time 160760032 ps
CPU time 5.1 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 221840 kb
Host smart-21d1e7a3-ec6b-4c95-87ac-63ea7ce51aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464602591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1464602591
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1004248766
Short name T995
Test name
Test status
Simulation time 30367899 ps
CPU time 1.77 seconds
Started Jul 01 10:34:29 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 213616 kb
Host smart-8dd3d54f-1a63-4edd-bf12-2af6b52d7d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004248766 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1004248766
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1462008951
Short name T129
Test name
Test status
Simulation time 39139864 ps
CPU time 0.79 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 205260 kb
Host smart-934b1721-38a3-423e-8e9f-a521be726aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462008951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1462008951
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1135122036
Short name T1074
Test name
Test status
Simulation time 13783398 ps
CPU time 0.69 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:33 AM PDT 24
Peak memory 205380 kb
Host smart-07b4967e-45f6-4e47-975a-91e93d0f4aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135122036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1135122036
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3547797965
Short name T1007
Test name
Test status
Simulation time 88475515 ps
CPU time 1.39 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:35 AM PDT 24
Peak memory 205404 kb
Host smart-6200f65e-e44a-43a8-848a-9bc8897f607a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547797965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3547797965
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1069014074
Short name T951
Test name
Test status
Simulation time 163604884 ps
CPU time 2.86 seconds
Started Jul 01 10:34:21 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 213828 kb
Host smart-84358745-90b4-446f-9fe4-20e557fbdad0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069014074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1069014074
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1948615647
Short name T1056
Test name
Test status
Simulation time 293221805 ps
CPU time 3.83 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 219816 kb
Host smart-ecd81257-b4fc-4a8a-9623-e22f61619b1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948615647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1948615647
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1100052069
Short name T1048
Test name
Test status
Simulation time 672211144 ps
CPU time 2.57 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 215972 kb
Host smart-872dc9fa-ea5c-420f-b8ed-b3eb36763c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100052069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1100052069
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3531299380
Short name T1082
Test name
Test status
Simulation time 144579099 ps
CPU time 1.48 seconds
Started Jul 01 10:34:27 AM PDT 24
Finished Jul 01 10:34:29 AM PDT 24
Peak memory 213616 kb
Host smart-95ce4f44-c77e-4f21-bd82-7c2031506ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531299380 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3531299380
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1515695130
Short name T1002
Test name
Test status
Simulation time 18729611 ps
CPU time 1.2 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 205388 kb
Host smart-b358bb50-6f7e-4cec-abbc-0ec850956f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515695130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1515695130
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3725664377
Short name T997
Test name
Test status
Simulation time 30573919 ps
CPU time 0.66 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 205148 kb
Host smart-3c852827-4ccf-40d3-9b5b-d50b96a5d348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725664377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3725664377
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1860154995
Short name T1040
Test name
Test status
Simulation time 129639562 ps
CPU time 2.04 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:36 AM PDT 24
Peak memory 205404 kb
Host smart-df7fe291-05bd-48b4-bfe8-1713e2b4377b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860154995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1860154995
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4255103769
Short name T1052
Test name
Test status
Simulation time 146411164 ps
CPU time 3.97 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 213840 kb
Host smart-dff82616-04c7-46af-a3c0-9cbee0d1ec9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255103769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4255103769
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3838491405
Short name T983
Test name
Test status
Simulation time 206888255 ps
CPU time 6.43 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:40 AM PDT 24
Peak memory 219976 kb
Host smart-9a241a20-6e2d-45a9-82c6-da0f9800407a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838491405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3838491405
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.366045300
Short name T940
Test name
Test status
Simulation time 348835426 ps
CPU time 2.27 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 216668 kb
Host smart-a3e1bea7-b27f-46af-99df-e17f3c397e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366045300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.366045300
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4058342279
Short name T994
Test name
Test status
Simulation time 78052791 ps
CPU time 1.62 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 213592 kb
Host smart-71b7bb28-8eea-4966-91fe-0ae7c3e07a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058342279 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.4058342279
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2452414406
Short name T130
Test name
Test status
Simulation time 12737758 ps
CPU time 0.87 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:34 AM PDT 24
Peak memory 205256 kb
Host smart-4d11d5f2-64f7-4070-9ef9-e08fc3f3e2e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452414406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2452414406
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3036970568
Short name T959
Test name
Test status
Simulation time 9886849 ps
CPU time 0.71 seconds
Started Jul 01 10:34:30 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 205208 kb
Host smart-cd34936a-a15e-401e-b811-100a6fa19f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036970568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3036970568
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4215129400
Short name T1000
Test name
Test status
Simulation time 244800865 ps
CPU time 2.18 seconds
Started Jul 01 10:34:36 AM PDT 24
Finished Jul 01 10:34:38 AM PDT 24
Peak memory 205320 kb
Host smart-41ed7f6f-aeee-4c37-9989-60191f3be691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215129400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4215129400
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.887431017
Short name T988
Test name
Test status
Simulation time 104117350 ps
CPU time 3.28 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:43 AM PDT 24
Peak memory 213756 kb
Host smart-2edd5cb8-8b87-4dae-96a0-413fc3a8750d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887431017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.887431017
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1473741470
Short name T1034
Test name
Test status
Simulation time 4169508305 ps
CPU time 12.98 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 213876 kb
Host smart-e9243b83-2578-4191-b441-cdafe4524a17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473741470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1473741470
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1537999565
Short name T950
Test name
Test status
Simulation time 174686926 ps
CPU time 1.97 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 215740 kb
Host smart-eedbd2d1-57f9-46fd-a78a-2bf3ba827c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537999565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1537999565
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1141110998
Short name T144
Test name
Test status
Simulation time 488889512 ps
CPU time 3.75 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 205388 kb
Host smart-cde44e5a-b339-4eba-9e68-b85d6895cce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141110998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1141110998
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.535528418
Short name T932
Test name
Test status
Simulation time 69743618 ps
CPU time 1.25 seconds
Started Jul 01 10:34:22 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 205484 kb
Host smart-49813ec0-129f-43e0-8df2-2c425b06a11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535528418 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.535528418
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.436412655
Short name T985
Test name
Test status
Simulation time 26620748 ps
CPU time 1.15 seconds
Started Jul 01 10:34:34 AM PDT 24
Finished Jul 01 10:34:36 AM PDT 24
Peak memory 205448 kb
Host smart-a1ee0243-a92e-4d3e-a4e9-f96e71fef538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436412655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.436412655
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2572325495
Short name T999
Test name
Test status
Simulation time 8015971 ps
CPU time 0.76 seconds
Started Jul 01 10:34:37 AM PDT 24
Finished Jul 01 10:34:38 AM PDT 24
Peak memory 205276 kb
Host smart-a4f35685-8942-42ca-bbdf-be48aecdafbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572325495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2572325495
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3263956508
Short name T1006
Test name
Test status
Simulation time 144364008 ps
CPU time 1.99 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 205400 kb
Host smart-540dd2f5-ac4b-47f5-8a66-5d553b9f6679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263956508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3263956508
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.181474118
Short name T1079
Test name
Test status
Simulation time 266646113 ps
CPU time 2.38 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 213804 kb
Host smart-e4598b8b-03e1-4d99-ac01-f526b1ba7d21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181474118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.181474118
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2811855440
Short name T101
Test name
Test status
Simulation time 79641625 ps
CPU time 3.62 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 213968 kb
Host smart-f87bfaba-ff79-4f87-94f7-04ee3466c489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811855440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2811855440
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2139003663
Short name T957
Test name
Test status
Simulation time 359514655 ps
CPU time 3.22 seconds
Started Jul 01 10:34:31 AM PDT 24
Finished Jul 01 10:34:35 AM PDT 24
Peak memory 213628 kb
Host smart-0e54889a-8213-4971-a825-2417e6c62c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139003663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2139003663
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3975331024
Short name T984
Test name
Test status
Simulation time 96908312 ps
CPU time 2.02 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 217196 kb
Host smart-6e5a14db-588a-4f89-a893-3e1063c3fd84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975331024 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3975331024
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2160253401
Short name T134
Test name
Test status
Simulation time 28218856 ps
CPU time 1.09 seconds
Started Jul 01 10:34:27 AM PDT 24
Finished Jul 01 10:34:28 AM PDT 24
Peak memory 205412 kb
Host smart-0090e101-11b1-45ae-9da2-4d5183783fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160253401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2160253401
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.688200757
Short name T942
Test name
Test status
Simulation time 45069478 ps
CPU time 0.68 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 205252 kb
Host smart-d3293b1f-5305-4b14-85a5-efdab35a06d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688200757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.688200757
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2847601745
Short name T1053
Test name
Test status
Simulation time 63307008 ps
CPU time 1.62 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 205316 kb
Host smart-a51b4e40-8972-42bb-b955-e089fb58263d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847601745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2847601745
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3069616457
Short name T1013
Test name
Test status
Simulation time 75121280 ps
CPU time 1.47 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 213892 kb
Host smart-11afee53-4249-4f48-bb10-e46ae5b7f885
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069616457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3069616457
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2551827174
Short name T1060
Test name
Test status
Simulation time 803955642 ps
CPU time 5.23 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 213920 kb
Host smart-639abdc0-17e1-4f7e-8d6a-9973a185d7c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551827174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2551827174
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2399412860
Short name T998
Test name
Test status
Simulation time 209723137 ps
CPU time 3.51 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 216788 kb
Host smart-95f75dd2-f8dc-4837-bd83-7310abf207ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399412860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2399412860
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1765761574
Short name T161
Test name
Test status
Simulation time 597634324 ps
CPU time 4.94 seconds
Started Jul 01 10:34:35 AM PDT 24
Finished Jul 01 10:34:41 AM PDT 24
Peak memory 205620 kb
Host smart-8afc43cf-04b8-49a9-96a7-81c791c35114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765761574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1765761574
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.60926390
Short name T1085
Test name
Test status
Simulation time 52842277 ps
CPU time 1.51 seconds
Started Jul 01 10:34:35 AM PDT 24
Finished Jul 01 10:34:37 AM PDT 24
Peak memory 213608 kb
Host smart-5742758e-2d7d-48b7-846c-70fe12e6b869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60926390 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.60926390
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3843373576
Short name T960
Test name
Test status
Simulation time 13448907 ps
CPU time 0.95 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 205312 kb
Host smart-28d3af73-9e9f-4af7-a8a3-d56c5d85638e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843373576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3843373576
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.92685662
Short name T934
Test name
Test status
Simulation time 17747530 ps
CPU time 0.71 seconds
Started Jul 01 10:34:26 AM PDT 24
Finished Jul 01 10:34:27 AM PDT 24
Peak memory 205096 kb
Host smart-c7120199-07aa-49a5-8ae7-96b4a67d2d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92685662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.92685662
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3156734600
Short name T1080
Test name
Test status
Simulation time 87306180 ps
CPU time 1.7 seconds
Started Jul 01 10:34:34 AM PDT 24
Finished Jul 01 10:34:37 AM PDT 24
Peak memory 205668 kb
Host smart-df7587ee-9b77-4bb1-a1f8-814b54f7f8e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156734600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3156734600
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3448677922
Short name T1026
Test name
Test status
Simulation time 95241070 ps
CPU time 2.08 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 213860 kb
Host smart-09150ecc-b1e8-4c75-82a2-fad3f6397ab3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448677922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3448677922
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2178858047
Short name T1024
Test name
Test status
Simulation time 390666979 ps
CPU time 1.84 seconds
Started Jul 01 10:34:34 AM PDT 24
Finished Jul 01 10:34:37 AM PDT 24
Peak memory 213532 kb
Host smart-02ce1021-f4a0-42fa-97c0-fd7a9627080f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178858047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2178858047
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.993818537
Short name T1088
Test name
Test status
Simulation time 110681187 ps
CPU time 4.38 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 205240 kb
Host smart-f0ef252d-a36e-4d88-b266-5ea436c4b926
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993818537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.993818537
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1571361209
Short name T1058
Test name
Test status
Simulation time 2158684129 ps
CPU time 12.31 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 205388 kb
Host smart-03e058c3-451d-45d0-a2ab-39ea8e075f3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571361209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
571361209
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4138401779
Short name T972
Test name
Test status
Simulation time 58014855 ps
CPU time 1.57 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 213580 kb
Host smart-711603e3-4534-4eab-90b1-3cf7425444f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138401779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
138401779
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3885461344
Short name T1030
Test name
Test status
Simulation time 209630172 ps
CPU time 1.63 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 213600 kb
Host smart-262d71c3-0a3e-45e2-aef5-ed6d467cff6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885461344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3885461344
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2966615581
Short name T1062
Test name
Test status
Simulation time 69737064 ps
CPU time 0.98 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 205236 kb
Host smart-c52873cf-1086-4ba6-a0cf-19f69d3b2b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966615581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2966615581
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.360258535
Short name T1018
Test name
Test status
Simulation time 33537319 ps
CPU time 0.85 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:05 AM PDT 24
Peak memory 205268 kb
Host smart-76e7ba32-bbc3-4141-917c-fc00d1101c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360258535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.360258535
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.324271621
Short name T1077
Test name
Test status
Simulation time 33672478 ps
CPU time 2.33 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 205352 kb
Host smart-d6d31d43-d5fd-4e1d-9b1b-a9208bae8833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324271621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.324271621
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3255449567
Short name T1017
Test name
Test status
Simulation time 2273752731 ps
CPU time 4.5 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 213988 kb
Host smart-b6c91b91-eb64-4d6a-b74f-994e35d8524e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255449567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3255449567
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.360632242
Short name T1073
Test name
Test status
Simulation time 168650165 ps
CPU time 8.86 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213756 kb
Host smart-e833e40d-4d6f-469f-a14b-5736f4655171
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360632242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.360632242
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3522711145
Short name T1032
Test name
Test status
Simulation time 96669530 ps
CPU time 1.72 seconds
Started Jul 01 10:34:22 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 213552 kb
Host smart-713e5481-2e75-4dbd-b1d8-72fe4eaf6f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522711145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3522711145
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3786613431
Short name T364
Test name
Test status
Simulation time 563155608 ps
CPU time 3.41 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 205372 kb
Host smart-d3e3b984-ec4f-45d7-a652-fb5999949a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786613431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3786613431
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2206764002
Short name T1090
Test name
Test status
Simulation time 23888422 ps
CPU time 0.7 seconds
Started Jul 01 10:34:56 AM PDT 24
Finished Jul 01 10:34:58 AM PDT 24
Peak memory 205284 kb
Host smart-1835ba12-0034-4f41-8699-e52756055b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206764002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2206764002
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2378326942
Short name T980
Test name
Test status
Simulation time 10505341 ps
CPU time 0.79 seconds
Started Jul 01 10:34:40 AM PDT 24
Finished Jul 01 10:34:42 AM PDT 24
Peak memory 205248 kb
Host smart-9d741ecb-ebd2-4117-adae-d7ce3a7478a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378326942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2378326942
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4044962324
Short name T996
Test name
Test status
Simulation time 20592057 ps
CPU time 0.8 seconds
Started Jul 01 10:34:42 AM PDT 24
Finished Jul 01 10:34:44 AM PDT 24
Peak memory 204968 kb
Host smart-3ed49ff9-7c5c-41ec-afc2-e6193ff7069d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044962324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4044962324
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4000476017
Short name T966
Test name
Test status
Simulation time 108383969 ps
CPU time 0.77 seconds
Started Jul 01 10:34:44 AM PDT 24
Finished Jul 01 10:34:45 AM PDT 24
Peak memory 205204 kb
Host smart-168d14d4-c15c-4d96-9448-ba0e8734ad42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000476017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4000476017
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2291137979
Short name T992
Test name
Test status
Simulation time 43253340 ps
CPU time 0.79 seconds
Started Jul 01 10:34:31 AM PDT 24
Finished Jul 01 10:34:33 AM PDT 24
Peak memory 205196 kb
Host smart-d8b837f2-5bfe-4116-8e88-6b266f5acb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291137979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2291137979
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4087759279
Short name T962
Test name
Test status
Simulation time 18551610 ps
CPU time 0.78 seconds
Started Jul 01 10:34:42 AM PDT 24
Finished Jul 01 10:34:44 AM PDT 24
Peak memory 205204 kb
Host smart-36489b1f-5e84-4449-baa8-85f8a0820ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087759279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4087759279
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2905707495
Short name T986
Test name
Test status
Simulation time 40738365 ps
CPU time 0.71 seconds
Started Jul 01 10:34:35 AM PDT 24
Finished Jul 01 10:34:36 AM PDT 24
Peak memory 205280 kb
Host smart-8f0e907a-6018-476b-a131-42ff65ad6825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905707495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2905707495
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3159011753
Short name T941
Test name
Test status
Simulation time 7382358 ps
CPU time 0.82 seconds
Started Jul 01 10:34:33 AM PDT 24
Finished Jul 01 10:34:35 AM PDT 24
Peak memory 205192 kb
Host smart-ffa53e12-fe21-487f-a355-663b86526d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159011753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3159011753
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2397862885
Short name T1031
Test name
Test status
Simulation time 7738331 ps
CPU time 0.79 seconds
Started Jul 01 10:34:48 AM PDT 24
Finished Jul 01 10:34:50 AM PDT 24
Peak memory 205392 kb
Host smart-9b3a608f-9b58-4e28-8b32-736a5ef25c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397862885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2397862885
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2343561973
Short name T1054
Test name
Test status
Simulation time 35241218 ps
CPU time 0.72 seconds
Started Jul 01 10:34:29 AM PDT 24
Finished Jul 01 10:34:30 AM PDT 24
Peak memory 205264 kb
Host smart-80a5234a-92cd-4125-8870-aaf78602fc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343561973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2343561973
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2452172287
Short name T1008
Test name
Test status
Simulation time 1457578361 ps
CPU time 9.17 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:20 AM PDT 24
Peak memory 205424 kb
Host smart-a281b94b-b0b3-4431-95c4-81b1b8a615a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452172287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
452172287
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.678568541
Short name T1067
Test name
Test status
Simulation time 253855228 ps
CPU time 14.29 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:34 AM PDT 24
Peak memory 205448 kb
Host smart-acc317ec-d674-43b5-9e4f-a4ed077c762a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678568541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.678568541
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2906822429
Short name T924
Test name
Test status
Simulation time 30124042 ps
CPU time 1.25 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 205344 kb
Host smart-f7a11a4e-9eb9-4717-a0ff-ecd6f33d34ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906822429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
906822429
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2755221327
Short name T1055
Test name
Test status
Simulation time 34752867 ps
CPU time 1.1 seconds
Started Jul 01 10:34:24 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 213600 kb
Host smart-727ba872-b76e-43d5-9a2e-fcaad0950883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755221327 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2755221327
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1636391658
Short name T127
Test name
Test status
Simulation time 44910533 ps
CPU time 1.04 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 205232 kb
Host smart-64e4bae7-ff12-4263-a848-d377f647e725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636391658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1636391658
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2763293626
Short name T1087
Test name
Test status
Simulation time 12335288 ps
CPU time 0.7 seconds
Started Jul 01 10:34:19 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 205212 kb
Host smart-a13a5025-e182-47c6-9609-4bfcac790097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763293626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2763293626
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1662841902
Short name T1023
Test name
Test status
Simulation time 389050991 ps
CPU time 2.64 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 205324 kb
Host smart-4d4b31c8-5c04-4b2d-85f3-82c114920cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662841902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1662841902
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2195284675
Short name T1025
Test name
Test status
Simulation time 122067904 ps
CPU time 2.21 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 213688 kb
Host smart-11923290-52f8-405b-95d6-e8b8a4e22687
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195284675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2195284675
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3607247849
Short name T1086
Test name
Test status
Simulation time 680225017 ps
CPU time 4.66 seconds
Started Jul 01 10:34:14 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213836 kb
Host smart-0ca32e5f-1dcd-4847-8f93-9d7bfb8c97db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607247849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3607247849
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2017815243
Short name T939
Test name
Test status
Simulation time 43377743 ps
CPU time 1.59 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 213668 kb
Host smart-0d4d6c69-ff2e-4f18-84d3-7d151fb1b8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017815243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2017815243
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1983817086
Short name T1039
Test name
Test status
Simulation time 38560115 ps
CPU time 0.7 seconds
Started Jul 01 10:34:38 AM PDT 24
Finished Jul 01 10:34:40 AM PDT 24
Peak memory 205280 kb
Host smart-e9a46b22-dc58-4b97-9a6a-2069734eaab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983817086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1983817086
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3385363387
Short name T937
Test name
Test status
Simulation time 11181117 ps
CPU time 0.74 seconds
Started Jul 01 10:34:38 AM PDT 24
Finished Jul 01 10:34:40 AM PDT 24
Peak memory 205192 kb
Host smart-bfcac133-1acc-4d8f-842e-dd66be5f6b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385363387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3385363387
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2591618481
Short name T923
Test name
Test status
Simulation time 19672616 ps
CPU time 0.86 seconds
Started Jul 01 10:34:21 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 205280 kb
Host smart-b8aa9fb5-595d-407f-a92b-84949a018b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591618481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2591618481
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2244574277
Short name T982
Test name
Test status
Simulation time 190585055 ps
CPU time 0.77 seconds
Started Jul 01 10:34:43 AM PDT 24
Finished Jul 01 10:34:45 AM PDT 24
Peak memory 205220 kb
Host smart-4b2dfee0-ec78-4353-8059-77e1dcad340b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244574277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2244574277
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3561633232
Short name T936
Test name
Test status
Simulation time 43393708 ps
CPU time 0.7 seconds
Started Jul 01 10:34:30 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 205204 kb
Host smart-83933350-1cf1-4fa4-aa4e-59016e9227f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561633232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3561633232
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3799477871
Short name T943
Test name
Test status
Simulation time 17760737 ps
CPU time 0.68 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 205280 kb
Host smart-a2a42893-3bda-41bb-a530-89f3452463e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799477871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3799477871
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2448202522
Short name T1003
Test name
Test status
Simulation time 11419034 ps
CPU time 0.82 seconds
Started Jul 01 10:34:22 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 205272 kb
Host smart-d6b5062f-c581-444a-8010-1031bd4c76ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448202522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2448202522
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3060058203
Short name T1029
Test name
Test status
Simulation time 39397432 ps
CPU time 0.81 seconds
Started Jul 01 10:34:24 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 205176 kb
Host smart-23dfed8f-975b-45ea-ae8a-2bc0683721d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060058203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3060058203
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3316640663
Short name T1020
Test name
Test status
Simulation time 27858231 ps
CPU time 0.7 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:27 AM PDT 24
Peak memory 205280 kb
Host smart-fb8aaee7-ccee-4a04-9896-1d7c99903963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316640663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3316640663
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.932927555
Short name T1044
Test name
Test status
Simulation time 11082367 ps
CPU time 0.82 seconds
Started Jul 01 10:34:45 AM PDT 24
Finished Jul 01 10:34:47 AM PDT 24
Peak memory 205128 kb
Host smart-a14e3d06-8030-491e-bbc2-62fabfa275c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932927555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.932927555
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2003456209
Short name T131
Test name
Test status
Simulation time 922412137 ps
CPU time 16.64 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 205268 kb
Host smart-ff599640-4af5-4c65-8bc1-505a41ca350e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003456209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
003456209
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3278992853
Short name T365
Test name
Test status
Simulation time 433875582 ps
CPU time 12.69 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:30 AM PDT 24
Peak memory 205304 kb
Host smart-0179282a-2618-4d3f-9dfb-25c5280a0150
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278992853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
278992853
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4194364685
Short name T1066
Test name
Test status
Simulation time 54430717 ps
CPU time 1.33 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 205220 kb
Host smart-29ed167a-3a03-4405-8975-3752400dd97e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194364685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
194364685
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.735153392
Short name T989
Test name
Test status
Simulation time 51260510 ps
CPU time 1.54 seconds
Started Jul 01 10:34:19 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 213616 kb
Host smart-631f5d7a-87d2-4c5a-bbbe-73112ee7a8fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735153392 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.735153392
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3609692643
Short name T954
Test name
Test status
Simulation time 14178222 ps
CPU time 1.22 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 205280 kb
Host smart-c4f2c4b5-cda3-4d1b-8bb9-7b04be3a1c80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609692643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3609692643
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2598291640
Short name T927
Test name
Test status
Simulation time 142872681 ps
CPU time 0.78 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 205200 kb
Host smart-5cb60964-311e-41e2-af18-3e9ef6d80449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598291640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2598291640
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1826717266
Short name T1042
Test name
Test status
Simulation time 186372076 ps
CPU time 2 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 213668 kb
Host smart-c85c5dc5-2dde-400a-b401-c014dfa452e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826717266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1826717266
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4193801831
Short name T1033
Test name
Test status
Simulation time 217688857 ps
CPU time 3.23 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 213752 kb
Host smart-20e38c5a-fda4-4d50-a14e-1cfe75e42fa6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193801831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.4193801831
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1938186888
Short name T990
Test name
Test status
Simulation time 377884202 ps
CPU time 6.06 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 219744 kb
Host smart-547bb326-d419-4216-8464-d2e0aed54201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938186888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1938186888
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.344507381
Short name T1065
Test name
Test status
Simulation time 31521981 ps
CPU time 2.16 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 215780 kb
Host smart-703c7490-40fd-4a08-95a2-9df13fd9c3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344507381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.344507381
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.961532773
Short name T1005
Test name
Test status
Simulation time 62929456 ps
CPU time 3.11 seconds
Started Jul 01 10:34:16 AM PDT 24
Finished Jul 01 10:34:22 AM PDT 24
Peak memory 213592 kb
Host smart-445d9dda-1072-46f0-b0e2-ce125b6a51fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961532773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
961532773
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.934511056
Short name T1061
Test name
Test status
Simulation time 20720631 ps
CPU time 0.98 seconds
Started Jul 01 10:34:32 AM PDT 24
Finished Jul 01 10:34:34 AM PDT 24
Peak memory 205364 kb
Host smart-deaa1ec0-e336-415c-b1d6-bfb25713a1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934511056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.934511056
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1602115524
Short name T925
Test name
Test status
Simulation time 13135823 ps
CPU time 0.71 seconds
Started Jul 01 10:34:37 AM PDT 24
Finished Jul 01 10:34:38 AM PDT 24
Peak memory 205276 kb
Host smart-9c16ac45-aa2a-4d0a-904d-b28735fb44e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602115524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1602115524
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2791547562
Short name T1078
Test name
Test status
Simulation time 15496054 ps
CPU time 0.89 seconds
Started Jul 01 10:34:34 AM PDT 24
Finished Jul 01 10:34:36 AM PDT 24
Peak memory 205452 kb
Host smart-d729a92a-5766-495e-8db2-fbd9ce928137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791547562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2791547562
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.347931556
Short name T953
Test name
Test status
Simulation time 19959974 ps
CPU time 0.69 seconds
Started Jul 01 10:34:26 AM PDT 24
Finished Jul 01 10:34:28 AM PDT 24
Peak memory 205196 kb
Host smart-638f3db6-97b8-4090-b6ce-93eeb43a82eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347931556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.347931556
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1816539138
Short name T1076
Test name
Test status
Simulation time 12179662 ps
CPU time 0.68 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 205272 kb
Host smart-7636c79f-a6fe-4efb-be6b-ec5101f00303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816539138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1816539138
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1406202168
Short name T935
Test name
Test status
Simulation time 15056556 ps
CPU time 0.87 seconds
Started Jul 01 10:34:40 AM PDT 24
Finished Jul 01 10:34:43 AM PDT 24
Peak memory 205192 kb
Host smart-4e24a31b-fc9a-4635-9018-24cf61e4bb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406202168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1406202168
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1058989154
Short name T922
Test name
Test status
Simulation time 43436763 ps
CPU time 0.72 seconds
Started Jul 01 10:34:19 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 205280 kb
Host smart-d98317da-d416-4c70-8c70-edf788651761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058989154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1058989154
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.354579033
Short name T974
Test name
Test status
Simulation time 46175728 ps
CPU time 0.67 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 205252 kb
Host smart-2e2b5cbe-6fe5-44a8-97ae-aa33ac7716a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354579033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.354579033
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3919082443
Short name T928
Test name
Test status
Simulation time 60675484 ps
CPU time 0.74 seconds
Started Jul 01 10:34:27 AM PDT 24
Finished Jul 01 10:34:34 AM PDT 24
Peak memory 205280 kb
Host smart-1c7e2ff0-ff50-46b9-b001-7c5e13d6cc4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919082443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3919082443
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.65787103
Short name T1010
Test name
Test status
Simulation time 14832941 ps
CPU time 0.73 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 205060 kb
Host smart-58a8cf49-ac40-47d8-bd99-1d671de23359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65787103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.65787103
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2908492361
Short name T1070
Test name
Test status
Simulation time 80832278 ps
CPU time 1.15 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 205424 kb
Host smart-cd136d3c-4abc-4a4f-9e0b-afcba484a053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908492361 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2908492361
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.265687163
Short name T132
Test name
Test status
Simulation time 44990058 ps
CPU time 1.21 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 205476 kb
Host smart-8a2e4a79-8cdf-491f-a81c-2cba407f7fd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265687163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.265687163
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1782005040
Short name T969
Test name
Test status
Simulation time 71042469 ps
CPU time 0.79 seconds
Started Jul 01 10:34:18 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 205104 kb
Host smart-441b1c5e-4b0a-4191-9140-81744bfcb1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782005040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1782005040
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.367684664
Short name T965
Test name
Test status
Simulation time 91006356 ps
CPU time 2.19 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 205364 kb
Host smart-f300cecf-3d8b-40ff-8215-95c803db97ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367684664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.367684664
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.288983021
Short name T105
Test name
Test status
Simulation time 69751018 ps
CPU time 2.37 seconds
Started Jul 01 10:34:09 AM PDT 24
Finished Jul 01 10:34:14 AM PDT 24
Peak memory 213824 kb
Host smart-2615c3a6-e951-445b-9d14-a86df1c435fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288983021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.288983021
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3290798738
Short name T981
Test name
Test status
Simulation time 630957874 ps
CPU time 11.25 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 213748 kb
Host smart-65092110-f709-46bd-88ae-bed4330920b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290798738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3290798738
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2901600016
Short name T1009
Test name
Test status
Simulation time 187167436 ps
CPU time 3.05 seconds
Started Jul 01 10:34:19 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 216584 kb
Host smart-de2d75cd-e106-4eda-9686-dc5faffc76c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901600016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2901600016
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3608950011
Short name T1016
Test name
Test status
Simulation time 104803658 ps
CPU time 1.2 seconds
Started Jul 01 10:34:23 AM PDT 24
Finished Jul 01 10:34:25 AM PDT 24
Peak memory 213592 kb
Host smart-18978b6a-cb4b-4ccc-a763-f9fba6a95526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608950011 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3608950011
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1655725078
Short name T987
Test name
Test status
Simulation time 206479807 ps
CPU time 1.16 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 205348 kb
Host smart-b5f7069f-3361-450d-be11-ec61eb4894c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655725078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1655725078
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.814501277
Short name T926
Test name
Test status
Simulation time 21721242 ps
CPU time 0.78 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 205272 kb
Host smart-abf7c08e-5f35-4458-8b0b-e41aef138e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814501277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.814501277
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2520158924
Short name T964
Test name
Test status
Simulation time 22796921 ps
CPU time 1.75 seconds
Started Jul 01 10:34:11 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 205664 kb
Host smart-b12e3ac5-43ef-4bbb-877b-f43057acfe23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520158924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2520158924
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4251834917
Short name T1022
Test name
Test status
Simulation time 227404655 ps
CPU time 3.32 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 213808 kb
Host smart-74e53b10-9207-485b-8842-39c8539ef93e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251834917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4251834917
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.843113792
Short name T1063
Test name
Test status
Simulation time 891211912 ps
CPU time 7.6 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 219992 kb
Host smart-215e8f47-c66b-4d14-93e7-88e75c0976cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843113792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.843113792
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2284548835
Short name T978
Test name
Test status
Simulation time 514252394 ps
CPU time 2.84 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 213608 kb
Host smart-9b0ee3c8-4db4-42c1-b373-3cbf538341be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284548835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2284548835
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2747364801
Short name T938
Test name
Test status
Simulation time 466077572 ps
CPU time 1.54 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:15 AM PDT 24
Peak memory 213592 kb
Host smart-f36b2421-fb91-48b2-b9eb-f3165d782553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747364801 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2747364801
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2181137762
Short name T1028
Test name
Test status
Simulation time 20918707 ps
CPU time 0.92 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 205244 kb
Host smart-fad9c2a8-fce7-483c-906f-db3070991d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181137762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2181137762
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.817436959
Short name T1038
Test name
Test status
Simulation time 23529207 ps
CPU time 0.71 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 205216 kb
Host smart-566f8b48-5c49-4bfc-b17a-af09e256f316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817436959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.817436959
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3617137943
Short name T128
Test name
Test status
Simulation time 53667407 ps
CPU time 1.38 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 205380 kb
Host smart-31f4cdf3-e57f-42d8-b159-6de3feef9bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617137943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3617137943
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.231376808
Short name T1037
Test name
Test status
Simulation time 89227253 ps
CPU time 2.09 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 213792 kb
Host smart-285f2909-d8f0-40fa-a510-997ae0adb689
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231376808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.231376808
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3189163056
Short name T1083
Test name
Test status
Simulation time 147008845 ps
CPU time 6.1 seconds
Started Jul 01 10:34:09 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 213960 kb
Host smart-538a875c-f9df-4af1-9e8a-f8d370aeedd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189163056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3189163056
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4161252556
Short name T1072
Test name
Test status
Simulation time 26082493 ps
CPU time 1.9 seconds
Started Jul 01 10:34:47 AM PDT 24
Finished Jul 01 10:34:50 AM PDT 24
Peak memory 215760 kb
Host smart-83940725-acf2-43da-bcb3-7c0fe6f5254f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161252556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4161252556
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2894185113
Short name T157
Test name
Test status
Simulation time 233599380 ps
CPU time 5.63 seconds
Started Jul 01 10:34:20 AM PDT 24
Finished Jul 01 10:34:28 AM PDT 24
Peak memory 213604 kb
Host smart-796ea01b-4e6a-47ef-8a83-69f7fa5c28ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894185113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2894185113
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1075412310
Short name T1069
Test name
Test status
Simulation time 28699020 ps
CPU time 1.59 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213572 kb
Host smart-93bbd879-14fd-49a1-8100-177f50365bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075412310 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1075412310
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1800877263
Short name T958
Test name
Test status
Simulation time 14228470 ps
CPU time 0.91 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 205252 kb
Host smart-7590d862-3503-45f4-93e9-05ac586e51a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800877263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1800877263
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1367543636
Short name T1036
Test name
Test status
Simulation time 46248079 ps
CPU time 0.73 seconds
Started Jul 01 10:34:15 AM PDT 24
Finished Jul 01 10:34:18 AM PDT 24
Peak memory 205268 kb
Host smart-42a5b9d9-557a-4b49-a621-7447c73a2817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367543636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1367543636
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.91363724
Short name T993
Test name
Test status
Simulation time 90097723 ps
CPU time 3.25 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 205408 kb
Host smart-312438c2-3280-42b7-8916-599a97a1389a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91363724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same
_csr_outstanding.91363724
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1998674891
Short name T977
Test name
Test status
Simulation time 50712254 ps
CPU time 1.38 seconds
Started Jul 01 10:34:15 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 213788 kb
Host smart-4a91d50a-a40c-4aab-8137-e971fb0df970
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998674891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1998674891
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3995557755
Short name T1014
Test name
Test status
Simulation time 3482133625 ps
CPU time 11.3 seconds
Started Jul 01 10:34:12 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 213840 kb
Host smart-4cd5a4f7-38d3-4c96-a7a7-0c27e9cb5d59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995557755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3995557755
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1778653662
Short name T955
Test name
Test status
Simulation time 125788952 ps
CPU time 4.08 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 221720 kb
Host smart-9e848563-b460-4240-b710-66ac3e1f81cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778653662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1778653662
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.503274255
Short name T973
Test name
Test status
Simulation time 29916145 ps
CPU time 1.48 seconds
Started Jul 01 10:34:13 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 205164 kb
Host smart-07533364-4a34-473d-8443-d35d7f19d673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503274255 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.503274255
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4090731525
Short name T1071
Test name
Test status
Simulation time 67723247 ps
CPU time 1.14 seconds
Started Jul 01 10:34:24 AM PDT 24
Finished Jul 01 10:34:26 AM PDT 24
Peak memory 205492 kb
Host smart-25deaf34-098a-4bf6-887e-144bd104da85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090731525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4090731525
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3589033844
Short name T933
Test name
Test status
Simulation time 38516213 ps
CPU time 0.83 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 205252 kb
Host smart-cebae904-a4e1-4c59-a0e2-ae5ba2b504b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589033844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3589033844
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.746065780
Short name T979
Test name
Test status
Simulation time 190651565 ps
CPU time 2.19 seconds
Started Jul 01 10:34:19 AM PDT 24
Finished Jul 01 10:34:23 AM PDT 24
Peak memory 205304 kb
Host smart-56aa56eb-08ab-42c2-932e-ce7bb7d3a5f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746065780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.746065780
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.623781563
Short name T106
Test name
Test status
Simulation time 165338445 ps
CPU time 1.88 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 213828 kb
Host smart-51ce3790-3b24-420b-9902-d9113b3ce256
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623781563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.623781563
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3599021865
Short name T1045
Test name
Test status
Simulation time 479073373 ps
CPU time 9.74 seconds
Started Jul 01 10:34:28 AM PDT 24
Finished Jul 01 10:34:39 AM PDT 24
Peak memory 213904 kb
Host smart-cd10d946-6d33-4322-820a-7c2d154d55c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599021865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3599021865
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.798527519
Short name T1001
Test name
Test status
Simulation time 23267280 ps
CPU time 1.6 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 213548 kb
Host smart-c7aa55ab-2786-43c5-8027-bd4a5d3721cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798527519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.798527519
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.380685115
Short name T435
Test name
Test status
Simulation time 49430522 ps
CPU time 0.75 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 205996 kb
Host smart-5270f737-1b83-4a92-8b5c-8df3d92c0018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380685115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.380685115
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3545265565
Short name T404
Test name
Test status
Simulation time 186266185 ps
CPU time 6.06 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 215500 kb
Host smart-a6a8e438-465c-494b-97aa-7e41dd0def85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545265565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3545265565
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.861544087
Short name T706
Test name
Test status
Simulation time 177537182 ps
CPU time 1.62 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:08 AM PDT 24
Peak memory 218836 kb
Host smart-87ca9617-b77f-4ead-af29-eba1153b3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861544087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.861544087
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2870264873
Short name T822
Test name
Test status
Simulation time 253645061 ps
CPU time 3.97 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:11 AM PDT 24
Peak memory 214320 kb
Host smart-09e98b3e-4965-4669-8d4a-ded3e4b3c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870264873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2870264873
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.88727244
Short name T607
Test name
Test status
Simulation time 661210278 ps
CPU time 5.52 seconds
Started Jul 01 10:59:04 AM PDT 24
Finished Jul 01 10:59:10 AM PDT 24
Peak memory 208092 kb
Host smart-b830e275-61ef-4637-969b-636a8a5682e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88727244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.88727244
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3791391202
Short name T647
Test name
Test status
Simulation time 67626639 ps
CPU time 2.75 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 208724 kb
Host smart-385242e4-f79c-4f73-8c5d-e73aae9d2a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791391202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3791391202
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.35415070
Short name T848
Test name
Test status
Simulation time 511901922 ps
CPU time 3.91 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:24 AM PDT 24
Peak memory 207108 kb
Host smart-795494c1-e1a4-40a1-93a9-f778a6da95b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.35415070
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3555139042
Short name T672
Test name
Test status
Simulation time 295404097 ps
CPU time 3.4 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 206884 kb
Host smart-d378f44f-2851-46b2-813c-64220a9154aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555139042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3555139042
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2801117491
Short name T446
Test name
Test status
Simulation time 3091176981 ps
CPU time 5.13 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 208012 kb
Host smart-f49f3bfd-07c4-4175-bf05-5e5dc389c42a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801117491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2801117491
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2220373790
Short name T598
Test name
Test status
Simulation time 47580844 ps
CPU time 2.52 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 209892 kb
Host smart-5350ecd2-9932-486e-bcc0-c7567cf9445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220373790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2220373790
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3970287795
Short name T517
Test name
Test status
Simulation time 887323799 ps
CPU time 18.06 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 208848 kb
Host smart-e5315fe9-d907-46c7-9bcc-d583efcef9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970287795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3970287795
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4011514142
Short name T58
Test name
Test status
Simulation time 1207586557 ps
CPU time 30.19 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:36 AM PDT 24
Peak memory 220184 kb
Host smart-1ad8f163-5066-4ed9-a56c-6465fb57414b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011514142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4011514142
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2521457509
Short name T300
Test name
Test status
Simulation time 843962497 ps
CPU time 4.94 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 209128 kb
Host smart-483637b4-2b9b-427c-831e-eef2c6c2d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521457509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2521457509
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3273795407
Short name T512
Test name
Test status
Simulation time 289019484 ps
CPU time 3.03 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 210492 kb
Host smart-77e7acda-5510-40ab-bd21-df0292a014fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273795407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3273795407
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1851518152
Short name T728
Test name
Test status
Simulation time 72416727 ps
CPU time 0.82 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 205996 kb
Host smart-6a365183-ff9b-4f98-aa63-d645bc1245be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851518152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1851518152
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1120029992
Short name T393
Test name
Test status
Simulation time 224786069 ps
CPU time 3.15 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 208252 kb
Host smart-88e0cb1b-7530-449c-a99c-9697d1e1c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120029992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1120029992
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1441155384
Short name T289
Test name
Test status
Simulation time 16806544795 ps
CPU time 100.38 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 214376 kb
Host smart-074a6b07-8359-413d-a298-c44a87966f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441155384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1441155384
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2131319288
Short name T305
Test name
Test status
Simulation time 1901040774 ps
CPU time 3.6 seconds
Started Jul 01 10:59:15 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 214296 kb
Host smart-5020e7dc-a189-41f5-b642-35e28b879234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131319288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2131319288
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.799064703
Short name T485
Test name
Test status
Simulation time 308956375 ps
CPU time 2.37 seconds
Started Jul 01 10:59:14 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 214340 kb
Host smart-bda508cb-2cce-4a64-a931-13e1cd643a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799064703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.799064703
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2643745447
Short name T18
Test name
Test status
Simulation time 33960411 ps
CPU time 2.67 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 207896 kb
Host smart-22b2280b-a61a-44e1-bd08-5e9e947adfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643745447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2643745447
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1177935820
Short name T42
Test name
Test status
Simulation time 835348272 ps
CPU time 18.85 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:41 AM PDT 24
Peak memory 231324 kb
Host smart-453427e5-b06a-44d7-b6ad-6d15154a60c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177935820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1177935820
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3027697643
Short name T787
Test name
Test status
Simulation time 1964396760 ps
CPU time 8.8 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 208184 kb
Host smart-3ae6195a-e307-49a7-a471-74db6077f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027697643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3027697643
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.46806154
Short name T798
Test name
Test status
Simulation time 85657541 ps
CPU time 3.67 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 208100 kb
Host smart-2e9a5dd5-ed8e-4646-90b1-6e935a548f15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46806154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.46806154
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.92500294
Short name T20
Test name
Test status
Simulation time 303631009 ps
CPU time 4.85 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 207880 kb
Host smart-ae0726a1-20d9-428b-8bd9-2d743312f700
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92500294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.92500294
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2635992057
Short name T789
Test name
Test status
Simulation time 49263952 ps
CPU time 2.54 seconds
Started Jul 01 10:59:08 AM PDT 24
Finished Jul 01 10:59:11 AM PDT 24
Peak memory 214332 kb
Host smart-1db5b28a-30d7-4828-885c-255772ee108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635992057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2635992057
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2707656972
Short name T882
Test name
Test status
Simulation time 35821426 ps
CPU time 2.56 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 208620 kb
Host smart-31c8b46e-9231-4cd0-ba1b-4cd864b9c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707656972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2707656972
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1145560334
Short name T62
Test name
Test status
Simulation time 15667522928 ps
CPU time 178.31 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 11:02:05 AM PDT 24
Peak memory 216600 kb
Host smart-d98839dc-5b1a-4321-b95c-3391881a78ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145560334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1145560334
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1823230805
Short name T169
Test name
Test status
Simulation time 748089992 ps
CPU time 16.04 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 222640 kb
Host smart-563b1926-7d9a-48f5-96d0-981c17e40409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823230805 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1823230805
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4042448654
Short name T195
Test name
Test status
Simulation time 92144609 ps
CPU time 3.22 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:08 AM PDT 24
Peak memory 207772 kb
Host smart-5e6f67f2-5d3d-40d6-9f51-ae0e1b2ca73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042448654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4042448654
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3547753109
Short name T452
Test name
Test status
Simulation time 72991569 ps
CPU time 1.83 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 209824 kb
Host smart-6dd1eaf0-0da6-4f9b-aa15-f47cb1af69df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547753109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3547753109
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4022020888
Short name T628
Test name
Test status
Simulation time 847457376 ps
CPU time 3.68 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 209752 kb
Host smart-00caa7ac-7033-4147-a9b5-0fcc97b13cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022020888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4022020888
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1370794324
Short name T765
Test name
Test status
Simulation time 105508390 ps
CPU time 2.7 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 210180 kb
Host smart-435b8f9e-dec5-44a3-aad1-7b5732e18c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370794324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1370794324
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.550304941
Short name T263
Test name
Test status
Simulation time 64764489 ps
CPU time 2.72 seconds
Started Jul 01 10:59:25 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 221308 kb
Host smart-147254d3-1017-4819-b5b1-0c34738b8334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550304941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.550304941
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2700800738
Short name T572
Test name
Test status
Simulation time 278891610 ps
CPU time 2.76 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 214292 kb
Host smart-69712f4a-97b4-4775-acea-4c3ab918fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700800738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2700800738
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3626408147
Short name T391
Test name
Test status
Simulation time 131977366 ps
CPU time 3.77 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 222396 kb
Host smart-55140a5f-5e30-4310-a602-aa41c60fa820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626408147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3626408147
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3159752021
Short name T524
Test name
Test status
Simulation time 76638209 ps
CPU time 3.77 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 208376 kb
Host smart-ebec6051-1810-4bc8-a416-cd7d41006f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159752021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3159752021
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1068660478
Short name T912
Test name
Test status
Simulation time 59572867 ps
CPU time 2.99 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 208668 kb
Host smart-faa27a47-84ef-4b50-a528-9c67f5bc2aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068660478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1068660478
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1670834093
Short name T414
Test name
Test status
Simulation time 3309572371 ps
CPU time 23.54 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:47 AM PDT 24
Peak memory 206948 kb
Host smart-2a4c6640-33b7-404c-8d09-978168252d1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670834093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1670834093
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1182854467
Short name T540
Test name
Test status
Simulation time 361376103 ps
CPU time 4.53 seconds
Started Jul 01 10:59:25 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 208780 kb
Host smart-5ac86e5e-6827-4f18-849c-1485ae2875ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182854467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1182854467
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.842354417
Short name T849
Test name
Test status
Simulation time 89257591 ps
CPU time 2.22 seconds
Started Jul 01 10:59:28 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 209536 kb
Host smart-ee1b8e53-3551-445b-b647-8dcb8c149401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842354417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.842354417
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2613063782
Short name T423
Test name
Test status
Simulation time 398237831 ps
CPU time 3.43 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 208700 kb
Host smart-1338f296-77f3-437d-b6da-7e7c33e2205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613063782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2613063782
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.44578985
Short name T170
Test name
Test status
Simulation time 1375466986 ps
CPU time 12.95 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:38 AM PDT 24
Peak memory 219304 kb
Host smart-96add9de-aa46-4f02-bc37-fd0940b8ccd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44578985 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.44578985
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1857298925
Short name T587
Test name
Test status
Simulation time 208331137 ps
CPU time 2.28 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 207864 kb
Host smart-a487953d-b6ac-46ca-8788-e143795233ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857298925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1857298925
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.664039858
Short name T745
Test name
Test status
Simulation time 109590321 ps
CPU time 1.73 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 210084 kb
Host smart-86007915-f7d9-40a7-b9ea-dfa9b4ce0e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664039858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.664039858
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3166596669
Short name T868
Test name
Test status
Simulation time 11387348 ps
CPU time 0.84 seconds
Started Jul 01 10:59:33 AM PDT 24
Finished Jul 01 10:59:34 AM PDT 24
Peak memory 206072 kb
Host smart-04a14c50-e4d1-401a-b9c3-7f81f224419f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166596669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3166596669
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2043775092
Short name T467
Test name
Test status
Simulation time 524659800 ps
CPU time 1.99 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 209016 kb
Host smart-a1ef144d-faa9-4898-a124-e02cf42ac48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043775092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2043775092
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3970901609
Short name T591
Test name
Test status
Simulation time 280111773 ps
CPU time 2.24 seconds
Started Jul 01 10:59:30 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 214300 kb
Host smart-26407b51-c639-40ca-a09f-f9e9aa0eb8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970901609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3970901609
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2360139480
Short name T866
Test name
Test status
Simulation time 312461026 ps
CPU time 4.25 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 214168 kb
Host smart-7b0610dc-2109-47b1-b97e-f41c9b8592fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360139480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2360139480
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4251495403
Short name T285
Test name
Test status
Simulation time 171343857 ps
CPU time 4.73 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 215500 kb
Host smart-1e08f718-bfcf-4e15-af62-120d8a712bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251495403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4251495403
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4098057991
Short name T447
Test name
Test status
Simulation time 431588902 ps
CPU time 5.02 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 209736 kb
Host smart-a1212d27-85db-4fd6-b8e6-b84225813bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098057991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4098057991
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4192049036
Short name T633
Test name
Test status
Simulation time 173711242 ps
CPU time 3.97 seconds
Started Jul 01 10:59:32 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 207544 kb
Host smart-215ef000-3c47-4cc6-bfce-c46b275ed8bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192049036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4192049036
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.265384394
Short name T723
Test name
Test status
Simulation time 63244419 ps
CPU time 2.35 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 207372 kb
Host smart-86218d77-d35f-42bc-94e7-a4451446572b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265384394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.265384394
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.57622384
Short name T623
Test name
Test status
Simulation time 46186652 ps
CPU time 2.55 seconds
Started Jul 01 10:59:25 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 208060 kb
Host smart-0828da86-ed7c-4189-a413-3498c8f75a6c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57622384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.57622384
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2381402979
Short name T511
Test name
Test status
Simulation time 285293917 ps
CPU time 3.73 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 10:59:40 AM PDT 24
Peak memory 215976 kb
Host smart-e3e67e7d-2d37-410e-8d0f-95a7466e5cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381402979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2381402979
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1074900489
Short name T438
Test name
Test status
Simulation time 144595210 ps
CPU time 4.49 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 208296 kb
Host smart-88b98471-adfa-4ea5-8c46-83a0968d5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074900489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1074900489
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3065085317
Short name T729
Test name
Test status
Simulation time 4684711608 ps
CPU time 23.97 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 222520 kb
Host smart-18de8f93-4978-4d0b-b685-ecb4f4d4a4f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065085317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3065085317
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.146723563
Short name T875
Test name
Test status
Simulation time 328781410 ps
CPU time 19.99 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:52 AM PDT 24
Peak memory 222592 kb
Host smart-d43bf286-1d59-4707-bd00-8deed069e370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146723563 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.146723563
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1577626145
Short name T299
Test name
Test status
Simulation time 200517313 ps
CPU time 4.93 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 214276 kb
Host smart-d81acef6-43dd-4212-8214-519e700a7c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577626145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1577626145
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2265398287
Short name T163
Test name
Test status
Simulation time 80275416 ps
CPU time 2.98 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 210564 kb
Host smart-0fc15d4e-073f-4b36-adac-c4854684783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265398287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2265398287
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.818700569
Short name T453
Test name
Test status
Simulation time 77304758 ps
CPU time 0.81 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 206072 kb
Host smart-10534e8a-5216-4520-a3d2-5ff7352e4f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818700569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.818700569
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4283837210
Short name T711
Test name
Test status
Simulation time 63795401 ps
CPU time 4.39 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 10:59:36 AM PDT 24
Peak memory 215576 kb
Host smart-ecaf669b-8fe4-4409-807d-5ed8057088cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283837210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4283837210
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2693153729
Short name T487
Test name
Test status
Simulation time 84330590 ps
CPU time 3.32 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:41 AM PDT 24
Peak memory 218456 kb
Host smart-fce7ffd7-0141-4b4c-8965-b0e0596ca748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693153729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2693153729
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3797199943
Short name T890
Test name
Test status
Simulation time 81252855 ps
CPU time 1.51 seconds
Started Jul 01 10:59:30 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 207952 kb
Host smart-614a311b-a389-42ca-a0ec-030f8329b9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797199943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3797199943
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2241555553
Short name T211
Test name
Test status
Simulation time 1466223200 ps
CPU time 10.49 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:48 AM PDT 24
Peak memory 214424 kb
Host smart-c50f0932-b0e2-4098-b784-0915a23b54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241555553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2241555553
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3874184484
Short name T531
Test name
Test status
Simulation time 1841829595 ps
CPU time 4.6 seconds
Started Jul 01 10:59:34 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 214300 kb
Host smart-49c6ab12-82fd-4bbf-9eca-cffbd41676b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874184484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3874184484
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1890579323
Short name T764
Test name
Test status
Simulation time 1205578647 ps
CPU time 3.98 seconds
Started Jul 01 10:59:32 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 208992 kb
Host smart-de5ac0e7-a840-4ec5-946b-84bdcd8de772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890579323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1890579323
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3231521888
Short name T229
Test name
Test status
Simulation time 301442965 ps
CPU time 6.2 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 10:59:42 AM PDT 24
Peak memory 214364 kb
Host smart-ceaa8943-18ee-4691-ab43-e426b0c186f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231521888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3231521888
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3315969544
Short name T375
Test name
Test status
Simulation time 88186336 ps
CPU time 3.16 seconds
Started Jul 01 10:59:34 AM PDT 24
Finished Jul 01 10:59:38 AM PDT 24
Peak memory 208444 kb
Host smart-23d41ecf-36da-4684-b9d6-fae1cb5f3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315969544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3315969544
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.607563372
Short name T413
Test name
Test status
Simulation time 4977387832 ps
CPU time 46.87 seconds
Started Jul 01 10:59:31 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 209180 kb
Host smart-1168a006-d8a1-46c6-88bd-42ee1cc94081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607563372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.607563372
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1563270876
Short name T845
Test name
Test status
Simulation time 259228968 ps
CPU time 4.26 seconds
Started Jul 01 10:59:36 AM PDT 24
Finished Jul 01 10:59:41 AM PDT 24
Peak memory 206920 kb
Host smart-35716314-78cb-435d-a0b1-46c28ce74f87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563270876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1563270876
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3015445471
Short name T335
Test name
Test status
Simulation time 1866340454 ps
CPU time 61.6 seconds
Started Jul 01 10:59:32 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 208572 kb
Host smart-5c9e07eb-3536-4c7b-acbc-7c0ae2b607a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015445471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3015445471
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3555943535
Short name T525
Test name
Test status
Simulation time 100799066 ps
CPU time 2.48 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 209036 kb
Host smart-8fec3834-ee0c-4f11-aee0-166115a59c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555943535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3555943535
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3137397328
Short name T603
Test name
Test status
Simulation time 1052465040 ps
CPU time 3.18 seconds
Started Jul 01 10:59:36 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 208488 kb
Host smart-b75857a1-580a-4df1-b319-ce94f714d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137397328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3137397328
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3912946545
Short name T253
Test name
Test status
Simulation time 174682683 ps
CPU time 6.79 seconds
Started Jul 01 10:59:34 AM PDT 24
Finished Jul 01 10:59:42 AM PDT 24
Peak memory 214312 kb
Host smart-4806fae4-e169-4808-8380-67b8ce459a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912946545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3912946545
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3245070471
Short name T843
Test name
Test status
Simulation time 338577678 ps
CPU time 2.73 seconds
Started Jul 01 10:59:38 AM PDT 24
Finished Jul 01 10:59:41 AM PDT 24
Peak memory 210532 kb
Host smart-a9038cb5-c031-4471-854c-f1ebd87ed35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245070471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3245070471
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1469575347
Short name T428
Test name
Test status
Simulation time 149761891 ps
CPU time 0.81 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:50 AM PDT 24
Peak memory 206052 kb
Host smart-42237fdf-0709-4674-a901-463233c59e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469575347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1469575347
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2048860841
Short name T387
Test name
Test status
Simulation time 68107134 ps
CPU time 4.11 seconds
Started Jul 01 10:59:34 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 214596 kb
Host smart-ce920238-aa5a-4038-ace2-fd10acdde8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048860841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2048860841
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4003827283
Short name T217
Test name
Test status
Simulation time 196257190 ps
CPU time 1.76 seconds
Started Jul 01 10:59:40 AM PDT 24
Finished Jul 01 10:59:42 AM PDT 24
Peak memory 207392 kb
Host smart-ec166cbe-b209-4785-8312-7c63e49a7eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003827283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4003827283
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3896634681
Short name T514
Test name
Test status
Simulation time 358855730 ps
CPU time 4.68 seconds
Started Jul 01 10:59:33 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 214324 kb
Host smart-1279965b-f37e-4f3f-8f5b-1ac2c3c4225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896634681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3896634681
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4142119516
Short name T618
Test name
Test status
Simulation time 37603475 ps
CPU time 1.98 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 222464 kb
Host smart-dd3df6c8-d7cc-40b0-a29b-b61624e71941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142119516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4142119516
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2820046762
Short name T605
Test name
Test status
Simulation time 703568896 ps
CPU time 5.39 seconds
Started Jul 01 10:59:38 AM PDT 24
Finished Jul 01 10:59:44 AM PDT 24
Peak memory 208192 kb
Host smart-1d83994b-0719-43ea-b323-ebfacb7ef790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820046762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2820046762
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1592241640
Short name T490
Test name
Test status
Simulation time 3579645933 ps
CPU time 5.82 seconds
Started Jul 01 10:59:36 AM PDT 24
Finished Jul 01 10:59:43 AM PDT 24
Peak memory 206904 kb
Host smart-86b5ced5-b5f9-45a6-bcd0-5c1a8f737645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592241640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1592241640
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.138421148
Short name T368
Test name
Test status
Simulation time 121928133 ps
CPU time 3.26 seconds
Started Jul 01 10:59:42 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 207020 kb
Host smart-092d75da-d365-499b-b626-aa7976e7eb75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138421148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.138421148
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4165637347
Short name T715
Test name
Test status
Simulation time 199480715 ps
CPU time 5.66 seconds
Started Jul 01 10:59:35 AM PDT 24
Finished Jul 01 10:59:41 AM PDT 24
Peak memory 207988 kb
Host smart-425a458c-41bf-45a5-87a2-b539f4c032dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165637347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4165637347
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2831866338
Short name T443
Test name
Test status
Simulation time 2206504289 ps
CPU time 16.74 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 207984 kb
Host smart-14f24d91-9037-440b-86ed-79b429bbe12f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831866338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2831866338
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3170097368
Short name T751
Test name
Test status
Simulation time 89455563 ps
CPU time 2.41 seconds
Started Jul 01 10:59:34 AM PDT 24
Finished Jul 01 10:59:37 AM PDT 24
Peak memory 209484 kb
Host smart-be9b9d30-a682-4488-92f0-fb700f130d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170097368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3170097368
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3601559719
Short name T585
Test name
Test status
Simulation time 626329251 ps
CPU time 3.47 seconds
Started Jul 01 10:59:52 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 208656 kb
Host smart-4c43abc7-0ee7-413f-b915-adbcd491b005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601559719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3601559719
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3011940012
Short name T168
Test name
Test status
Simulation time 305485850 ps
CPU time 11.28 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 218768 kb
Host smart-c94cc230-c222-4cbc-b8f6-604b125a2543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011940012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3011940012
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.18350003
Short name T222
Test name
Test status
Simulation time 11097945066 ps
CPU time 49.31 seconds
Started Jul 01 10:59:36 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 214368 kb
Host smart-6ef9c38a-ca3f-4b18-8e53-cba11e8d0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18350003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.18350003
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2451430446
Short name T158
Test name
Test status
Simulation time 433834963 ps
CPU time 11.76 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 210316 kb
Host smart-f64e2c62-d5a9-4700-9d36-2a86290a60ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451430446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2451430446
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.188001960
Short name T99
Test name
Test status
Simulation time 19335303 ps
CPU time 0.97 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:50 AM PDT 24
Peak memory 206180 kb
Host smart-1431e745-8a8e-469f-9147-80ddb9d3b776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188001960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.188001960
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.7038660
Short name T885
Test name
Test status
Simulation time 66211618 ps
CPU time 3.87 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 214344 kb
Host smart-36b6b18f-8f00-417f-b699-4e7211fcfe45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7038660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.7038660
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2549678374
Short name T752
Test name
Test status
Simulation time 411252536 ps
CPU time 2.93 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 208864 kb
Host smart-7f21e8d0-f93a-471a-ba85-0fa6e78efe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549678374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2549678374
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1524519249
Short name T345
Test name
Test status
Simulation time 96336355 ps
CPU time 4.11 seconds
Started Jul 01 10:59:39 AM PDT 24
Finished Jul 01 10:59:44 AM PDT 24
Peak memory 218444 kb
Host smart-51eebc48-7098-44d9-8c26-f4c0393514ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524519249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1524519249
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.492893906
Short name T94
Test name
Test status
Simulation time 202285443 ps
CPU time 2.6 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 221296 kb
Host smart-1ff29cda-ca21-4cb1-acd1-9d69d621a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492893906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.492893906
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1541199884
Short name T310
Test name
Test status
Simulation time 174187982 ps
CPU time 3.04 seconds
Started Jul 01 10:59:40 AM PDT 24
Finished Jul 01 10:59:44 AM PDT 24
Peak memory 214280 kb
Host smart-9df99807-4d84-4333-a827-701999395108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541199884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1541199884
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1736414853
Short name T727
Test name
Test status
Simulation time 285350848 ps
CPU time 2.62 seconds
Started Jul 01 10:59:52 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 206728 kb
Host smart-66033935-4a34-475f-98a4-623b59dc798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736414853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1736414853
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2916957309
Short name T860
Test name
Test status
Simulation time 1031699259 ps
CPU time 11.58 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:11 AM PDT 24
Peak memory 218224 kb
Host smart-72f59cfd-1561-4f5a-baae-a000abcce6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916957309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2916957309
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.470490874
Short name T175
Test name
Test status
Simulation time 90844195 ps
CPU time 3.85 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 209260 kb
Host smart-cf6073ce-7eb7-4c59-8b47-6f96da028fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470490874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.470490874
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1744838924
Short name T834
Test name
Test status
Simulation time 465763764 ps
CPU time 4.23 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 208428 kb
Host smart-c592b923-cd8a-4d93-98c0-8e16cf4d4628
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744838924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1744838924
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1062978545
Short name T331
Test name
Test status
Simulation time 808348497 ps
CPU time 8.5 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 209032 kb
Host smart-4281ef1d-7dbb-4fce-8343-1a8405bc7101
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062978545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1062978545
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1146139689
Short name T836
Test name
Test status
Simulation time 631423426 ps
CPU time 5.23 seconds
Started Jul 01 10:59:40 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 208396 kb
Host smart-6dcbbaf6-d935-462c-959d-832425b88967
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146139689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1146139689
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.386743315
Short name T370
Test name
Test status
Simulation time 410733437 ps
CPU time 4.92 seconds
Started Jul 01 10:59:42 AM PDT 24
Finished Jul 01 10:59:48 AM PDT 24
Peak memory 218508 kb
Host smart-0fbaf372-ef17-474a-89e6-3db3aedfc4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386743315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.386743315
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2430765700
Short name T829
Test name
Test status
Simulation time 972928495 ps
CPU time 13.88 seconds
Started Jul 01 10:59:46 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 208084 kb
Host smart-6b619f5f-2453-42f3-87f5-dfc683521df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430765700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2430765700
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2883339647
Short name T746
Test name
Test status
Simulation time 118167962 ps
CPU time 5.22 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 210116 kb
Host smart-9a1d89ec-5972-4d93-9200-bed52519bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883339647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2883339647
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3493875347
Short name T627
Test name
Test status
Simulation time 62929489 ps
CPU time 1.86 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 210520 kb
Host smart-86f194a4-1a9e-4fa6-9fc4-1bd665479998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493875347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3493875347
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3021246285
Short name T712
Test name
Test status
Simulation time 16378069 ps
CPU time 0.81 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 206056 kb
Host smart-f70196cc-702d-41aa-b2f9-5c7a4c4636e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021246285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3021246285
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.708820622
Short name T38
Test name
Test status
Simulation time 141434460 ps
CPU time 2.67 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:50 AM PDT 24
Peak memory 217868 kb
Host smart-c7f14aa5-500c-403f-ab81-f70412a9e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708820622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.708820622
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4232497796
Short name T554
Test name
Test status
Simulation time 103918211 ps
CPU time 3.27 seconds
Started Jul 01 10:59:45 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 209156 kb
Host smart-58cbec93-54a7-413c-894f-0bba387bdf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232497796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4232497796
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3665883470
Short name T919
Test name
Test status
Simulation time 747811145 ps
CPU time 6.37 seconds
Started Jul 01 11:00:04 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 208572 kb
Host smart-6bd13af2-1c0f-4220-bb86-fd3d2dcaf96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665883470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3665883470
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1548619830
Short name T342
Test name
Test status
Simulation time 147042675 ps
CPU time 5.41 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 214236 kb
Host smart-723bdce5-d7f8-4ec6-9a4a-e2223b3715b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548619830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1548619830
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3051094976
Short name T754
Test name
Test status
Simulation time 122986250 ps
CPU time 5.8 seconds
Started Jul 01 10:59:45 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 220624 kb
Host smart-ccf6be1a-63c9-4924-ac89-1e7862f29fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051094976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3051094976
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3045361903
Short name T720
Test name
Test status
Simulation time 615836325 ps
CPU time 5.64 seconds
Started Jul 01 10:59:43 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 207788 kb
Host smart-5c1232fc-cf50-4593-8f1b-06fab82a47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045361903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3045361903
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3536466789
Short name T418
Test name
Test status
Simulation time 149212175 ps
CPU time 2.26 seconds
Started Jul 01 10:59:52 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 206944 kb
Host smart-344be178-19b5-4d6e-83bd-d21eb7490cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536466789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3536466789
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2351630616
Short name T659
Test name
Test status
Simulation time 1344807936 ps
CPU time 5.8 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 207944 kb
Host smart-f73f2b6e-92b0-4e7b-911a-9543fe276c58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351630616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2351630616
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2382483300
Short name T824
Test name
Test status
Simulation time 67006411 ps
CPU time 2.84 seconds
Started Jul 01 10:59:37 AM PDT 24
Finished Jul 01 10:59:40 AM PDT 24
Peak memory 206840 kb
Host smart-82628df7-31c6-4b26-a09b-5610c86af820
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382483300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2382483300
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1436877537
Short name T801
Test name
Test status
Simulation time 231811958 ps
CPU time 3.28 seconds
Started Jul 01 10:59:43 AM PDT 24
Finished Jul 01 10:59:47 AM PDT 24
Peak memory 207360 kb
Host smart-d4f51743-0ad6-4545-b5fd-284e2dfa0516
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436877537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1436877537
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3641675184
Short name T416
Test name
Test status
Simulation time 353294069 ps
CPU time 6.89 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 208636 kb
Host smart-2ff6df40-5d71-4462-a0d6-7e85840b637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641675184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3641675184
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3669704480
Short name T550
Test name
Test status
Simulation time 103086651 ps
CPU time 3.89 seconds
Started Jul 01 10:59:42 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 208596 kb
Host smart-ed327a3f-40df-430c-9f62-6681bae61647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669704480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3669704480
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.4172290159
Short name T663
Test name
Test status
Simulation time 276818322 ps
CPU time 18.92 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 222624 kb
Host smart-cb60c01c-8be2-4377-9686-f5fa8c98e350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172290159 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.4172290159
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2563921524
Short name T535
Test name
Test status
Simulation time 834246366 ps
CPU time 5.82 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 208696 kb
Host smart-e05a2f6f-1899-4373-ba5c-4eae25723b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563921524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2563921524
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3893733993
Short name T671
Test name
Test status
Simulation time 405339819 ps
CPU time 2.63 seconds
Started Jul 01 10:59:45 AM PDT 24
Finished Jul 01 10:59:48 AM PDT 24
Peak memory 210396 kb
Host smart-6d8fb7ca-8d42-4c62-bcaf-14d3f1b241d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893733993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3893733993
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1599725197
Short name T902
Test name
Test status
Simulation time 31051038 ps
CPU time 0.85 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 206052 kb
Host smart-cb32dfff-e273-435b-9e65-d0ec34094e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599725197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1599725197
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2895766648
Short name T28
Test name
Test status
Simulation time 797117580 ps
CPU time 4.64 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 221880 kb
Host smart-da772f35-701e-4f11-93cf-b5c85ca8102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895766648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2895766648
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1188599153
Short name T552
Test name
Test status
Simulation time 34902201 ps
CPU time 1.73 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 207216 kb
Host smart-e199146e-a0ae-4c8a-8334-4280a49d97aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188599153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1188599153
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2338009678
Short name T491
Test name
Test status
Simulation time 106370229 ps
CPU time 4.22 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:52 AM PDT 24
Peak memory 222408 kb
Host smart-f1aa007c-b383-427c-8815-6d6e1b11112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338009678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2338009678
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.598340826
Short name T270
Test name
Test status
Simulation time 1641720391 ps
CPU time 8.5 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 222368 kb
Host smart-6b08bd33-355f-4412-a943-6bc3329b1a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598340826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.598340826
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1620063449
Short name T786
Test name
Test status
Simulation time 127169308 ps
CPU time 4.04 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:53 AM PDT 24
Peak memory 214344 kb
Host smart-0269a4ab-be22-462e-9255-a5827467fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620063449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1620063449
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1011848194
Short name T260
Test name
Test status
Simulation time 51203805 ps
CPU time 3.23 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 208000 kb
Host smart-be91eba8-15d0-4fa1-bf12-74995a28d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011848194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1011848194
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2270615465
Short name T681
Test name
Test status
Simulation time 258510294 ps
CPU time 3 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 206672 kb
Host smart-4d0f9d75-9d4e-4bcd-a5b6-5afae709ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270615465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2270615465
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1206537248
Short name T493
Test name
Test status
Simulation time 993019427 ps
CPU time 6.4 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 207976 kb
Host smart-47f577bd-4d8f-4d53-9619-64bd3be8f0e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206537248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1206537248
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.71397558
Short name T529
Test name
Test status
Simulation time 923989474 ps
CPU time 20.7 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 209056 kb
Host smart-8d610999-9ddc-455f-b056-b6463adb4677
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71397558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.71397558
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1402972166
Short name T816
Test name
Test status
Simulation time 34788981 ps
CPU time 2.25 seconds
Started Jul 01 10:59:46 AM PDT 24
Finished Jul 01 10:59:48 AM PDT 24
Peak memory 206776 kb
Host smart-805644e6-d4af-445d-955b-3c3f3c321039
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402972166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1402972166
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3740636136
Short name T543
Test name
Test status
Simulation time 890590056 ps
CPU time 4.13 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 210316 kb
Host smart-069adfe7-7cb0-40a1-afae-e2d2604b2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740636136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3740636136
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1639207093
Short name T698
Test name
Test status
Simulation time 54244072 ps
CPU time 2.51 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 207020 kb
Host smart-c8c0d1fa-e914-444c-ab76-5a86f90b3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639207093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1639207093
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.389462240
Short name T644
Test name
Test status
Simulation time 29020726856 ps
CPU time 155.91 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:02:33 AM PDT 24
Peak memory 217512 kb
Host smart-ac5dc37c-703f-4a1f-a9c2-51c753275e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389462240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.389462240
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2422492394
Short name T721
Test name
Test status
Simulation time 192557496 ps
CPU time 3.32 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 209740 kb
Host smart-46bdf494-29dc-499a-98f9-a1735068a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422492394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2422492394
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.165982700
Short name T150
Test name
Test status
Simulation time 198108931 ps
CPU time 2.72 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 210120 kb
Host smart-c00d2a7b-001f-4d93-839c-699d96777aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165982700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.165982700
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2807892171
Short name T422
Test name
Test status
Simulation time 17598793 ps
CPU time 0.72 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 206048 kb
Host smart-213ca33c-197a-4cf7-a550-133a2e6f50cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807892171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2807892171
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1378465915
Short name T807
Test name
Test status
Simulation time 2280565988 ps
CPU time 3.3 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 214488 kb
Host smart-0e050c43-84ea-4632-9c60-67db9408123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378465915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1378465915
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3973048186
Short name T379
Test name
Test status
Simulation time 206046310 ps
CPU time 2.03 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 207048 kb
Host smart-706fb9e0-d6a3-42c4-aaa8-29697b9bbe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973048186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3973048186
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_random.951722391
Short name T234
Test name
Test status
Simulation time 7435196567 ps
CPU time 27.44 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 219696 kb
Host smart-f46e7a8c-1be6-4f6a-b3d1-2273ceac198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951722391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.951722391
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2452402
Short name T319
Test name
Test status
Simulation time 28568735 ps
CPU time 2.16 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 208872 kb
Host smart-a9b7a005-1372-4c1a-b0bb-e53764309a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2452402
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2552744480
Short name T799
Test name
Test status
Simulation time 117303656 ps
CPU time 2.38 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 208412 kb
Host smart-fb7c0d1f-5d84-4708-8303-b3f034effc4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552744480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2552744480
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1679419642
Short name T502
Test name
Test status
Simulation time 452213927 ps
CPU time 4.1 seconds
Started Jul 01 10:59:46 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 207024 kb
Host smart-0c742010-361a-4794-b7f3-d274e06d5d2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679419642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1679419642
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3308499432
Short name T178
Test name
Test status
Simulation time 853488927 ps
CPU time 5.94 seconds
Started Jul 01 11:00:04 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 208616 kb
Host smart-76b9730b-2919-421c-a409-777269c8a563
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308499432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3308499432
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3352062041
Short name T456
Test name
Test status
Simulation time 54337608 ps
CPU time 2.31 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:51 AM PDT 24
Peak memory 209340 kb
Host smart-8a2100c0-b03f-406c-9083-2ca2f175ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352062041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3352062041
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.683252565
Short name T814
Test name
Test status
Simulation time 77513099 ps
CPU time 3.14 seconds
Started Jul 01 10:59:48 AM PDT 24
Finished Jul 01 10:59:52 AM PDT 24
Peak memory 208780 kb
Host smart-61ffd421-5312-4243-aaaa-75b183206b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683252565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.683252565
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1196218561
Short name T353
Test name
Test status
Simulation time 92362398 ps
CPU time 3.2 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 214336 kb
Host smart-f7708282-2e03-4cd3-a069-2b2b0c48962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196218561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1196218561
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.110989908
Short name T772
Test name
Test status
Simulation time 68259342 ps
CPU time 1.37 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 10:59:48 AM PDT 24
Peak memory 210056 kb
Host smart-1279dd69-3773-4693-a44e-920eff8c147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110989908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.110989908
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.377724137
Short name T556
Test name
Test status
Simulation time 38444038 ps
CPU time 0.72 seconds
Started Jul 01 10:59:54 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 206064 kb
Host smart-e68fc978-0ba4-4f46-8ca4-013c04d41a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377724137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.377724137
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.128299353
Short name T861
Test name
Test status
Simulation time 47573813 ps
CPU time 1.66 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 208504 kb
Host smart-6ed5ae27-fc0e-4592-bc00-55672ce3a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128299353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.128299353
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2799620367
Short name T464
Test name
Test status
Simulation time 61297408 ps
CPU time 1.93 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 209156 kb
Host smart-1001c3ed-6e81-4b87-8664-2ca788686e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799620367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2799620367
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2636516477
Short name T835
Test name
Test status
Simulation time 373549259 ps
CPU time 4.4 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 214288 kb
Host smart-78471ecb-0f61-462f-8a1c-36be1b39d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636516477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2636516477
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1590136212
Short name T204
Test name
Test status
Simulation time 136712622 ps
CPU time 3.97 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 219812 kb
Host smart-09eb4f5a-9f97-451c-89ba-bfdb63d686b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590136212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1590136212
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.32653174
Short name T724
Test name
Test status
Simulation time 489272617 ps
CPU time 14.84 seconds
Started Jul 01 10:59:47 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 208468 kb
Host smart-e34d39be-7eba-4e07-bbac-8acf59c8d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32653174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.32653174
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2927782386
Short name T713
Test name
Test status
Simulation time 687364643 ps
CPU time 4.01 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 207120 kb
Host smart-a929fe4c-9249-4ff0-86c7-028cd9502e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927782386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2927782386
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2276949643
Short name T817
Test name
Test status
Simulation time 37194891 ps
CPU time 2.51 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 208588 kb
Host smart-bb082673-d6a7-47aa-b3d3-8f9e81d7204c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276949643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2276949643
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.605643628
Short name T471
Test name
Test status
Simulation time 127482636 ps
CPU time 3.84 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 207016 kb
Host smart-44c8343c-57d2-4112-b782-19c06ee5c264
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605643628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.605643628
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.40298746
Short name T842
Test name
Test status
Simulation time 445269169 ps
CPU time 4.18 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 206872 kb
Host smart-2a09538b-f802-48a1-bc92-807c9750296e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.40298746
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.114387822
Short name T580
Test name
Test status
Simulation time 33679133 ps
CPU time 1.61 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 207184 kb
Host smart-0c777cc6-289b-4117-8ad1-3d4b6348ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114387822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.114387822
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.210230313
Short name T797
Test name
Test status
Simulation time 120646464 ps
CPU time 2.74 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 206868 kb
Host smart-290d7426-88ab-435e-9cdb-eb0b7a3676dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210230313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.210230313
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3670360960
Short name T125
Test name
Test status
Simulation time 1044561737 ps
CPU time 32.36 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 215456 kb
Host smart-0a403f28-c9a7-4299-9453-d8d681eb873c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670360960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3670360960
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1072049902
Short name T104
Test name
Test status
Simulation time 313697454 ps
CPU time 16.92 seconds
Started Jul 01 10:59:49 AM PDT 24
Finished Jul 01 11:00:07 AM PDT 24
Peak memory 221276 kb
Host smart-37ca9572-058e-4844-9941-40af2cf6f92c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072049902 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1072049902
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.889889502
Short name T602
Test name
Test status
Simulation time 73629637 ps
CPU time 2.58 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 214328 kb
Host smart-dbe3cbed-364f-4b78-82e3-ddf017937fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889889502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.889889502
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1340643355
Short name T718
Test name
Test status
Simulation time 183341781 ps
CPU time 2.55 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 211100 kb
Host smart-65e32ffc-4cf4-4d7d-ae81-ae6a1227518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340643355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1340643355
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.874716693
Short name T526
Test name
Test status
Simulation time 56536160 ps
CPU time 0.98 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 206176 kb
Host smart-a796e172-8637-41dd-bf82-32c236083f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874716693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.874716693
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1370011489
Short name T296
Test name
Test status
Simulation time 55931508 ps
CPU time 4.03 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 214364 kb
Host smart-6cc97965-4dee-4a5c-acdf-d7d1b60df72f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370011489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1370011489
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1541297367
Short name T699
Test name
Test status
Simulation time 359576755 ps
CPU time 2.78 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 10:59:55 AM PDT 24
Peak memory 207236 kb
Host smart-fe08602c-ab3d-47e9-a91e-9ae56212c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541297367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1541297367
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2452709736
Short name T84
Test name
Test status
Simulation time 292650128 ps
CPU time 2.59 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 214188 kb
Host smart-56034529-9393-4a76-931e-a10e28be450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452709736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2452709736
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4279247683
Short name T324
Test name
Test status
Simulation time 76403225 ps
CPU time 2.36 seconds
Started Jul 01 11:00:02 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 214312 kb
Host smart-479734eb-3eb4-4c3e-9460-b1415c0486e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279247683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4279247683
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.1715463667
Short name T838
Test name
Test status
Simulation time 418999491 ps
CPU time 11.14 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 207532 kb
Host smart-24afdb33-604e-44c2-9d61-e00b17bebe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715463667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1715463667
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1782240040
Short name T667
Test name
Test status
Simulation time 941930539 ps
CPU time 3.34 seconds
Started Jul 01 10:59:50 AM PDT 24
Finished Jul 01 10:59:54 AM PDT 24
Peak memory 207152 kb
Host smart-7ccbfd9e-40e6-4d93-a63f-44afea747e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782240040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1782240040
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3990169754
Short name T726
Test name
Test status
Simulation time 3174491774 ps
CPU time 21.17 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 208072 kb
Host smart-ad5a9edf-a1b4-436b-9b8b-449e02f0a355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990169754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3990169754
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2570957085
Short name T371
Test name
Test status
Simulation time 1416143164 ps
CPU time 5.11 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 208404 kb
Host smart-1b59495b-0d02-42b3-8689-155a7a2ce0ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570957085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2570957085
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2708140450
Short name T420
Test name
Test status
Simulation time 149443890 ps
CPU time 3.17 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:11 AM PDT 24
Peak memory 208724 kb
Host smart-6eeeedc5-e7b0-465b-902e-672733def796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708140450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2708140450
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3780277836
Short name T410
Test name
Test status
Simulation time 237902178 ps
CPU time 2.6 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 208572 kb
Host smart-49329935-896a-41c2-b2ed-e2b74c969d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780277836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3780277836
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2773421756
Short name T601
Test name
Test status
Simulation time 375038776 ps
CPU time 7.33 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 209320 kb
Host smart-099e8ee8-809c-4ab1-a9da-0ce394c1d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773421756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2773421756
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3673510036
Short name T362
Test name
Test status
Simulation time 89119475 ps
CPU time 1.89 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 210312 kb
Host smart-0e0a596c-4a0c-4287-b863-ebf9cad5d2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673510036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3673510036
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4147926517
Short name T497
Test name
Test status
Simulation time 12628497 ps
CPU time 0.87 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 206060 kb
Host smart-94df25e2-301b-4f3e-bff2-03d0a880e1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147926517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4147926517
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1199471626
Short name T386
Test name
Test status
Simulation time 327125064 ps
CPU time 9.34 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 215264 kb
Host smart-d83df512-bf23-4be7-a374-4cb59ec2bf0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199471626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1199471626
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1233864275
Short name T804
Test name
Test status
Simulation time 78995473 ps
CPU time 2.53 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:10 AM PDT 24
Peak memory 209976 kb
Host smart-d87983b1-8f7b-4558-af3c-a8d7d887d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233864275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1233864275
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2766090717
Short name T66
Test name
Test status
Simulation time 212314976 ps
CPU time 2.42 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:09 AM PDT 24
Peak memory 207456 kb
Host smart-23d92aa1-d41c-4be3-ba8a-88db7357589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766090717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2766090717
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.771627809
Short name T358
Test name
Test status
Simulation time 298260733 ps
CPU time 4.82 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 221096 kb
Host smart-b31f7088-4648-4111-bd4e-3e20f20b4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771627809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.771627809
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3753284080
Short name T466
Test name
Test status
Simulation time 120858983 ps
CPU time 3.66 seconds
Started Jul 01 10:59:06 AM PDT 24
Finished Jul 01 10:59:11 AM PDT 24
Peak memory 222400 kb
Host smart-7795653b-112a-44e0-a4bb-8cc9b31c6bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753284080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3753284080
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1576394052
Short name T230
Test name
Test status
Simulation time 249356838 ps
CPU time 3.94 seconds
Started Jul 01 10:59:14 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 214392 kb
Host smart-799e7082-00ee-49c2-83bf-83ec0deb2435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576394052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1576394052
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.540442429
Short name T41
Test name
Test status
Simulation time 1311893836 ps
CPU time 11.93 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 230608 kb
Host smart-2c1c5bee-5f54-486b-a99d-61b9c3350787
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540442429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.540442429
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2569543214
Short name T475
Test name
Test status
Simulation time 530535914 ps
CPU time 6.12 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 207836 kb
Host smart-559d3bc9-e1f7-4969-a7e5-2e602b62b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569543214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2569543214
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1407965508
Short name T908
Test name
Test status
Simulation time 514009846 ps
CPU time 9.29 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 208088 kb
Host smart-834209a1-0cc3-467b-bcae-04ac525e01b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407965508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1407965508
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1302844620
Short name T548
Test name
Test status
Simulation time 449581878 ps
CPU time 8.45 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 208144 kb
Host smart-a5aa488e-5f5f-4baa-85d7-fb45f483b3d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302844620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1302844620
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3641697742
Short name T534
Test name
Test status
Simulation time 94212828 ps
CPU time 3.86 seconds
Started Jul 01 10:59:15 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 208436 kb
Host smart-1b3b4fc6-c997-4c81-bbdc-3a97ecc9b9ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641697742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3641697742
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2002130832
Short name T685
Test name
Test status
Simulation time 1050449766 ps
CPU time 6.82 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 210132 kb
Host smart-205f1d17-1c23-4588-ac21-f9f00abfb4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002130832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2002130832
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2340251935
Short name T483
Test name
Test status
Simulation time 191961341 ps
CPU time 5.34 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 208496 kb
Host smart-b79f9721-33d9-441c-82e7-99329c407a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340251935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2340251935
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3340805677
Short name T69
Test name
Test status
Simulation time 619405850 ps
CPU time 18.78 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 220732 kb
Host smart-78f8451e-5eef-4f66-bf54-29c6ea00eea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340805677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3340805677
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1760535399
Short name T199
Test name
Test status
Simulation time 503022027 ps
CPU time 22.12 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 222588 kb
Host smart-3fd68712-dc82-4bd8-887e-c0415ee4180a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760535399 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1760535399
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.336009357
Short name T714
Test name
Test status
Simulation time 300268168 ps
CPU time 6.16 seconds
Started Jul 01 10:59:08 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 214300 kb
Host smart-209fa233-28b3-40ae-9ee2-d811bae45436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336009357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.336009357
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.258743888
Short name T853
Test name
Test status
Simulation time 95099201 ps
CPU time 3.05 seconds
Started Jul 01 10:59:07 AM PDT 24
Finished Jul 01 10:59:10 AM PDT 24
Peak memory 210380 kb
Host smart-2212fc3a-5b3a-43d9-a4f8-e995028843f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258743888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.258743888
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.128920929
Short name T433
Test name
Test status
Simulation time 200940315 ps
CPU time 0.8 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 205976 kb
Host smart-a9fd2678-d13c-426c-8005-a2ef742acd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128920929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.128920929
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2278611100
Short name T503
Test name
Test status
Simulation time 285052143 ps
CPU time 11.95 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 209776 kb
Host smart-0901d22c-4c8b-4a1a-bbae-aacb114717fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278611100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2278611100
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3255162483
Short name T262
Test name
Test status
Simulation time 116956058 ps
CPU time 2.46 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 208784 kb
Host smart-8c875f7b-84c2-48b9-9580-95a56577bd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255162483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3255162483
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3430893797
Short name T577
Test name
Test status
Simulation time 328204224 ps
CPU time 2.58 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 220100 kb
Host smart-72b12410-5c56-4598-b9ed-63fc38b7f3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430893797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3430893797
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1659698238
Short name T468
Test name
Test status
Simulation time 382131936 ps
CPU time 4.42 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:14 AM PDT 24
Peak memory 208104 kb
Host smart-1dfbe8c9-fede-4361-8af6-b14dce2d2e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659698238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1659698238
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.371541125
Short name T767
Test name
Test status
Simulation time 134089369 ps
CPU time 4.32 seconds
Started Jul 01 10:59:52 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 208896 kb
Host smart-9ae97c09-d0bd-474c-ace0-2406a1589c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371541125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.371541125
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2259353332
Short name T455
Test name
Test status
Simulation time 707532005 ps
CPU time 5.82 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 208488 kb
Host smart-6d70f953-5999-416f-b2e7-dbe4a47d4d9f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259353332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2259353332
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3144078603
Short name T582
Test name
Test status
Simulation time 3992928987 ps
CPU time 7.56 seconds
Started Jul 01 10:59:51 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 208792 kb
Host smart-b982895f-99de-4802-ae85-65a31cfe88a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144078603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3144078603
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2403439993
Short name T226
Test name
Test status
Simulation time 56454037 ps
CPU time 2.85 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 208508 kb
Host smart-02c5e689-8fa7-41de-973d-d9cb33ff5390
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403439993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2403439993
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1909612100
Short name T784
Test name
Test status
Simulation time 169547972 ps
CPU time 5.81 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 214136 kb
Host smart-6d123045-f362-4549-a4d6-f1249b7f65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909612100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1909612100
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1944122719
Short name T904
Test name
Test status
Simulation time 377527811 ps
CPU time 4.31 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 206752 kb
Host smart-77800dfd-0ba2-4d8c-89b9-a15d9d538537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944122719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1944122719
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2718617675
Short name T653
Test name
Test status
Simulation time 14124559243 ps
CPU time 40.16 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 215280 kb
Host smart-3cdae2dc-4d72-420e-bbd2-5a2bf9889874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718617675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2718617675
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2847756507
Short name T43
Test name
Test status
Simulation time 832186190 ps
CPU time 9.71 seconds
Started Jul 01 10:59:54 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 222604 kb
Host smart-9ddf0250-76ff-4931-9fd1-11911f859ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847756507 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2847756507
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2749613383
Short name T179
Test name
Test status
Simulation time 75107266 ps
CPU time 3.32 seconds
Started Jul 01 10:59:53 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 214320 kb
Host smart-7aac0fa7-00fa-4599-900f-9b466cf54fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749613383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2749613383
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2563879798
Short name T893
Test name
Test status
Simulation time 327464739 ps
CPU time 8.05 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 210852 kb
Host smart-a6bb369d-a908-41cd-9d37-5efe18e82c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563879798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2563879798
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.508847576
Short name T508
Test name
Test status
Simulation time 47076705 ps
CPU time 0.82 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 206064 kb
Host smart-83f588ef-060c-432d-a0ae-94ba6885eae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508847576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.508847576
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1594003943
Short name T214
Test name
Test status
Simulation time 61255422 ps
CPU time 4.05 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 215196 kb
Host smart-5a2aeebb-0feb-483c-b03b-1a75a1b82d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594003943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1594003943
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3554124479
Short name T242
Test name
Test status
Simulation time 1266175427 ps
CPU time 4.36 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 210048 kb
Host smart-f177e58c-5d87-4368-8102-cc2438d75447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554124479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3554124479
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.383236292
Short name T218
Test name
Test status
Simulation time 31887305 ps
CPU time 1.76 seconds
Started Jul 01 10:59:54 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 214276 kb
Host smart-edae4a58-7b6f-4fb9-9238-2b375f281b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383236292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.383236292
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1823027378
Short name T165
Test name
Test status
Simulation time 248909966 ps
CPU time 3.03 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 219724 kb
Host smart-22a75472-d042-4178-94cd-79df6a9c8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823027378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1823027378
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4141248609
Short name T599
Test name
Test status
Simulation time 127424209 ps
CPU time 4 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 207660 kb
Host smart-f2d5e607-8681-459a-8a02-dba8fae793d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141248609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4141248609
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2215544295
Short name T918
Test name
Test status
Simulation time 200485454 ps
CPU time 5.1 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 206860 kb
Host smart-839b4193-9e69-4f4b-a657-758ad9875175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215544295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2215544295
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1962598708
Short name T350
Test name
Test status
Simulation time 185508035 ps
CPU time 5 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:03 AM PDT 24
Peak memory 207852 kb
Host smart-2d443f02-e4a1-487f-969b-2175e8eaf242
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962598708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1962598708
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3216605272
Short name T177
Test name
Test status
Simulation time 312089815 ps
CPU time 8.48 seconds
Started Jul 01 11:00:18 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 208888 kb
Host smart-7967a343-ec08-41ef-98b2-e37312539973
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216605272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3216605272
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3390757642
Short name T509
Test name
Test status
Simulation time 801028862 ps
CPU time 27.92 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 208976 kb
Host smart-fa080ff6-668c-4512-b929-07cbfbe82ffd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390757642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3390757642
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2728881852
Short name T606
Test name
Test status
Simulation time 90127767 ps
CPU time 2.57 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 209020 kb
Host smart-25e0f6d1-b079-492f-bc63-77192f2f48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728881852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2728881852
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.454994823
Short name T376
Test name
Test status
Simulation time 420292096 ps
CPU time 3.27 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 206940 kb
Host smart-8b69981a-3726-4395-9b56-d4b6efaacc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454994823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.454994823
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2268675136
Short name T200
Test name
Test status
Simulation time 478119168 ps
CPU time 16.53 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:33 AM PDT 24
Peak memory 215464 kb
Host smart-8060d6cd-dc84-4f64-9253-c1ef24d667e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268675136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2268675136
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3555629114
Short name T638
Test name
Test status
Simulation time 55578457 ps
CPU time 3.08 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 208024 kb
Host smart-109e8a8d-6a66-45f6-aa6e-3eb291fd0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555629114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3555629114
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4197657982
Short name T360
Test name
Test status
Simulation time 100406756 ps
CPU time 1.2 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 209804 kb
Host smart-98a25282-7fec-49b9-87cb-6f6065109f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197657982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4197657982
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2236735178
Short name T612
Test name
Test status
Simulation time 98168715 ps
CPU time 0.88 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 206056 kb
Host smart-67e7a196-fbc9-4201-b5dc-eaf665634e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236735178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2236735178
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.903545711
Short name T276
Test name
Test status
Simulation time 78368978 ps
CPU time 4.64 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:00:02 AM PDT 24
Peak memory 215276 kb
Host smart-3d2c024b-ca4d-4587-8e57-b0ac17f5dc73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903545711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.903545711
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1774672783
Short name T739
Test name
Test status
Simulation time 38072595 ps
CPU time 2.73 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 208324 kb
Host smart-1d153503-5509-4caa-a1aa-e6f34950cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774672783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1774672783
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3430040795
Short name T773
Test name
Test status
Simulation time 729953375 ps
CPU time 4.32 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 214648 kb
Host smart-7b000921-6813-4add-b77f-7e32ffdbfffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430040795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3430040795
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1074472539
Short name T878
Test name
Test status
Simulation time 80233978 ps
CPU time 2.01 seconds
Started Jul 01 10:59:58 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 221152 kb
Host smart-36b40bef-d0cb-4f7c-8e74-f5f32a4ebcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074472539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1074472539
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3007200333
Short name T733
Test name
Test status
Simulation time 461795848 ps
CPU time 3.94 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 210532 kb
Host smart-644e7ac9-71ab-4569-ac97-028248abfadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007200333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3007200333
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1831324429
Short name T272
Test name
Test status
Simulation time 62901411 ps
CPU time 3.23 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 208360 kb
Host smart-87d849f5-e0e9-43a2-8d7b-813aeec70ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831324429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1831324429
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1982266975
Short name T689
Test name
Test status
Simulation time 140950044 ps
CPU time 2.41 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 10:59:59 AM PDT 24
Peak memory 206908 kb
Host smart-da9cb1df-8526-4f36-9ee0-e1cb8e4980be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982266975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1982266975
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3039953123
Short name T237
Test name
Test status
Simulation time 49392086 ps
CPU time 2.74 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 206932 kb
Host smart-c28be7cf-d7a7-488b-bedd-8a05b195bcef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039953123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3039953123
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3649288528
Short name T547
Test name
Test status
Simulation time 171863224 ps
CPU time 1.86 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 206944 kb
Host smart-f82d6d83-690d-4807-ae4b-56e497a3be57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649288528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3649288528
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2621677013
Short name T193
Test name
Test status
Simulation time 138854225 ps
CPU time 2.3 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:00 AM PDT 24
Peak memory 207288 kb
Host smart-aa0a60e7-a31a-4f3f-83b6-e21d375a5d43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621677013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2621677013
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1523084401
Short name T590
Test name
Test status
Simulation time 144157396 ps
CPU time 2.08 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 215436 kb
Host smart-b047606a-7b6b-4362-98a9-d4014583e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523084401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1523084401
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2948357073
Short name T578
Test name
Test status
Simulation time 1631351666 ps
CPU time 30.71 seconds
Started Jul 01 10:59:55 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 207844 kb
Host smart-32155a2c-81c6-4f0e-a666-eab53462d72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948357073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2948357073
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1493534207
Short name T717
Test name
Test status
Simulation time 1107222879 ps
CPU time 23.65 seconds
Started Jul 01 11:00:04 AM PDT 24
Finished Jul 01 11:00:29 AM PDT 24
Peak memory 216532 kb
Host smart-32a1ee7a-2298-4b72-8fa2-cecfa23b992b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493534207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1493534207
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2639244119
Short name T645
Test name
Test status
Simulation time 110113711 ps
CPU time 4.44 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:11 AM PDT 24
Peak memory 209744 kb
Host smart-78c3dd01-2985-430a-9b2d-e379d73e7a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639244119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2639244119
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4192930417
Short name T680
Test name
Test status
Simulation time 15326950 ps
CPU time 0.99 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 206176 kb
Host smart-3b61ce50-6ec1-41e8-8b44-98ecb7cd9aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192930417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4192930417
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.108671114
Short name T314
Test name
Test status
Simulation time 513964742 ps
CPU time 7.41 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:28 AM PDT 24
Peak memory 215836 kb
Host smart-111e03f7-4184-4052-863c-89c51adfb3f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108671114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.108671114
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3770227421
Short name T63
Test name
Test status
Simulation time 499501627 ps
CPU time 4.14 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 222836 kb
Host smart-aba8443c-919e-4b45-b7d4-241f40aed90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770227421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3770227421
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4078931632
Short name T549
Test name
Test status
Simulation time 208516855 ps
CPU time 2.72 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 208216 kb
Host smart-631f5c21-999a-4dc8-8243-685ba1ec1e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078931632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4078931632
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1447895166
Short name T25
Test name
Test status
Simulation time 589828319 ps
CPU time 3.35 seconds
Started Jul 01 11:00:02 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 214228 kb
Host smart-7d350211-8397-4a5c-9352-33e00f5cbf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447895166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1447895166
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.674097094
Short name T26
Test name
Test status
Simulation time 154767021 ps
CPU time 3.37 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 211336 kb
Host smart-8a18edc6-0701-4a4f-bd75-89ecd634e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674097094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.674097094
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1324897030
Short name T498
Test name
Test status
Simulation time 277102371 ps
CPU time 2.55 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 220128 kb
Host smart-2fd3b0cd-8988-4393-8d6b-038e17fa67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324897030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1324897030
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3315053916
Short name T374
Test name
Test status
Simulation time 110795353 ps
CPU time 5.1 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 209720 kb
Host smart-91e8a7ea-5d27-4305-a554-88fcdb40ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315053916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3315053916
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2020433807
Short name T880
Test name
Test status
Simulation time 388815334 ps
CPU time 3.02 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 207112 kb
Host smart-bea070f0-7a05-4030-a2b0-5a872b4d4b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020433807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2020433807
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.479611234
Short name T516
Test name
Test status
Simulation time 31101564 ps
CPU time 2.18 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 206940 kb
Host smart-1d606203-5a85-46ff-9282-eab6f1800dbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479611234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.479611234
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2527557720
Short name T683
Test name
Test status
Simulation time 2572346334 ps
CPU time 32.45 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:33 AM PDT 24
Peak memory 209100 kb
Host smart-3ae213e7-b005-4966-b29d-ed76486a088f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527557720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2527557720
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1908148535
Short name T227
Test name
Test status
Simulation time 1087544751 ps
CPU time 27.49 seconds
Started Jul 01 10:59:57 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 208604 kb
Host smart-44342a2a-e20a-43f0-b93f-feb07abb990a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908148535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1908148535
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1806151134
Short name T315
Test name
Test status
Simulation time 117820452 ps
CPU time 4.87 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 218596 kb
Host smart-e728506c-be33-45ca-9ef1-ec8866cf74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806151134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1806151134
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3296036899
Short name T857
Test name
Test status
Simulation time 738137784 ps
CPU time 19.94 seconds
Started Jul 01 10:59:56 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 208740 kb
Host smart-f6e2d7b3-c37a-49f7-9602-7bff9353a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296036899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3296036899
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1963626140
Short name T68
Test name
Test status
Simulation time 2352330040 ps
CPU time 37.55 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 217020 kb
Host smart-3b916d37-cf70-4dec-810f-6ca0ec4bd35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963626140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1963626140
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.556243747
Short name T887
Test name
Test status
Simulation time 916488327 ps
CPU time 10.36 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 222608 kb
Host smart-1fc80f9b-7e3d-4d0d-9960-8a521e8cb00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556243747 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.556243747
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1212396498
Short name T844
Test name
Test status
Simulation time 383611114 ps
CPU time 3.6 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 207564 kb
Host smart-a1e5e6a3-30a1-4a1b-a0c4-35523125309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212396498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1212396498
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3312393583
Short name T35
Test name
Test status
Simulation time 69770770 ps
CPU time 2.19 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 210172 kb
Host smart-c815dcf7-a08b-49ad-95b8-2f34cddeda70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312393583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3312393583
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3155298501
Short name T510
Test name
Test status
Simulation time 11559725 ps
CPU time 0.85 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 206056 kb
Host smart-555441e5-db47-45ed-acbe-a84b817cf671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155298501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3155298501
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3536069056
Short name T869
Test name
Test status
Simulation time 251596279 ps
CPU time 3.16 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 214332 kb
Host smart-4ce0e0fd-34f8-41ae-b0d0-e45369859c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536069056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3536069056
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1550103397
Short name T635
Test name
Test status
Simulation time 180939861 ps
CPU time 3.8 seconds
Started Jul 01 10:59:59 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 207524 kb
Host smart-80d10e6c-b93c-43ec-b8d8-6a1cd8184834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550103397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1550103397
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3910439778
Short name T876
Test name
Test status
Simulation time 51824310 ps
CPU time 3.23 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 214272 kb
Host smart-c9af25ae-19dc-49dd-9143-7b882f00cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910439778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3910439778
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2090255335
Short name T907
Test name
Test status
Simulation time 398403570 ps
CPU time 3.49 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 206248 kb
Host smart-23680cbe-85c5-4d9b-bfbb-aebc4ae56259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090255335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2090255335
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3664699114
Short name T203
Test name
Test status
Simulation time 40411626 ps
CPU time 2.73 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 214336 kb
Host smart-80c59771-8b14-4790-a121-8540486bc341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664699114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3664699114
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.242239190
Short name T617
Test name
Test status
Simulation time 129751942 ps
CPU time 5.96 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 210560 kb
Host smart-f1c87efb-470e-4e4d-b936-11bc071d57b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242239190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.242239190
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3852890445
Short name T284
Test name
Test status
Simulation time 87959006 ps
CPU time 3.3 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 208472 kb
Host smart-4b3964c9-c593-470f-9ef7-d584a70ac57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852890445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3852890445
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.117224391
Short name T688
Test name
Test status
Simulation time 543080394 ps
CPU time 4.26 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 208712 kb
Host smart-8656f3c6-4ddd-49d7-a14a-62b3bab539b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117224391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.117224391
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1949757515
Short name T897
Test name
Test status
Simulation time 22195690 ps
CPU time 1.87 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 208640 kb
Host smart-a6ef3079-0c2f-45fa-ad46-c6f55f1c98b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949757515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1949757515
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2177645411
Short name T553
Test name
Test status
Simulation time 45685612 ps
CPU time 2.97 seconds
Started Jul 01 11:00:02 AM PDT 24
Finished Jul 01 11:00:07 AM PDT 24
Peak memory 209176 kb
Host smart-4c1988c7-7928-4f1e-97f3-f2023c7cbd34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177645411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2177645411
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1671169822
Short name T874
Test name
Test status
Simulation time 236212533 ps
CPU time 3.3 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 215620 kb
Host smart-52a20e3e-e405-450d-98fe-9c131c1bb0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671169822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1671169822
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1039977292
Short name T500
Test name
Test status
Simulation time 450433907 ps
CPU time 10.93 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 207924 kb
Host smart-7bb11938-a52e-4554-b0f6-0bbbb6de651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039977292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1039977292
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4266897370
Short name T800
Test name
Test status
Simulation time 346467497 ps
CPU time 4.19 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 218152 kb
Host smart-d8b63779-602d-4224-84ec-b46c11c02d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266897370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4266897370
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3334369074
Short name T825
Test name
Test status
Simulation time 24333540 ps
CPU time 0.85 seconds
Started Jul 01 11:00:02 AM PDT 24
Finished Jul 01 11:00:04 AM PDT 24
Peak memory 206064 kb
Host smart-9c18ff00-d029-4dc4-a5d9-08ab5a0ab7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334369074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3334369074
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2313032952
Short name T27
Test name
Test status
Simulation time 974287218 ps
CPU time 3.93 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 221980 kb
Host smart-46f34ef6-c369-49d4-a193-00994ea69c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313032952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2313032952
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3533283375
Short name T673
Test name
Test status
Simulation time 748319730 ps
CPU time 5.41 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 208988 kb
Host smart-c66df06c-ca1a-48b0-9305-49cc04477465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533283375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3533283375
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1698183612
Short name T264
Test name
Test status
Simulation time 1151011457 ps
CPU time 5.79 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 214280 kb
Host smart-86453c6c-4847-4650-9ae8-74b21c366f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698183612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1698183612
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2634673733
Short name T883
Test name
Test status
Simulation time 140050586 ps
CPU time 2.14 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:05 AM PDT 24
Peak memory 209496 kb
Host smart-77ad525d-084f-492a-a884-ff9f3f161530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634673733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2634673733
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1981625916
Short name T641
Test name
Test status
Simulation time 198975461 ps
CPU time 5.6 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 208984 kb
Host smart-c4f3c614-b7f0-4fb5-b613-266d9f45e109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981625916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1981625916
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3396483003
Short name T586
Test name
Test status
Simulation time 39715694 ps
CPU time 2.22 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 206920 kb
Host smart-e2d0aca5-db8f-4e7b-9e8e-ff7ac057d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396483003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3396483003
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2987713529
Short name T181
Test name
Test status
Simulation time 33179397 ps
CPU time 2.33 seconds
Started Jul 01 11:00:03 AM PDT 24
Finished Jul 01 11:00:07 AM PDT 24
Peak memory 206916 kb
Host smart-baeb0cb5-dacf-4b7b-a9d1-3d0b8f1cf355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987713529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2987713529
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3401543909
Short name T542
Test name
Test status
Simulation time 122957503 ps
CPU time 3.67 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 208548 kb
Host smart-5304eac7-25f3-44e3-9070-60c0258a8a07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401543909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3401543909
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1597667008
Short name T277
Test name
Test status
Simulation time 33763259 ps
CPU time 2.37 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 206980 kb
Host smart-1de99da3-1573-4951-88a1-00a64584e514
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597667008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1597667008
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.150658691
Short name T894
Test name
Test status
Simulation time 382428909 ps
CPU time 3.77 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 207588 kb
Host smart-47f605b6-2c9b-4959-987e-03c32ad2d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150658691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.150658691
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2759877997
Short name T551
Test name
Test status
Simulation time 250477954 ps
CPU time 3.54 seconds
Started Jul 01 11:00:00 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 208628 kb
Host smart-4043c42e-691c-484d-83c6-e9cc6f6ca161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759877997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2759877997
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.864790506
Short name T732
Test name
Test status
Simulation time 108040707 ps
CPU time 3.25 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:15 AM PDT 24
Peak memory 208708 kb
Host smart-46e3fe63-5ebd-4ddb-89d7-a6356518fbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864790506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.864790506
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1433295164
Short name T621
Test name
Test status
Simulation time 183389659 ps
CPU time 4.24 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 210168 kb
Host smart-39b29036-5f1f-4918-a934-7abd8b781de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433295164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1433295164
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3661894261
Short name T903
Test name
Test status
Simulation time 348745045 ps
CPU time 2.48 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 210040 kb
Host smart-014da123-638e-4a18-b25f-1436e0e0fe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661894261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3661894261
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3350123529
Short name T541
Test name
Test status
Simulation time 12743490 ps
CPU time 0.72 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 206044 kb
Host smart-abb53152-3798-46b8-bc9b-0b10e1ea75d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350123529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3350123529
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3477480443
Short name T31
Test name
Test status
Simulation time 47918256 ps
CPU time 2.35 seconds
Started Jul 01 11:00:04 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 214316 kb
Host smart-69a32167-22f4-4c96-a3c5-6ccd8ee30cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477480443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3477480443
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1393942933
Short name T892
Test name
Test status
Simulation time 239737915 ps
CPU time 3.73 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 209244 kb
Host smart-83b4c67f-0423-4a98-b365-26b171667a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393942933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1393942933
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.340379484
Short name T88
Test name
Test status
Simulation time 253776433 ps
CPU time 3.59 seconds
Started Jul 01 11:00:05 AM PDT 24
Finished Jul 01 11:00:11 AM PDT 24
Peak memory 209576 kb
Host smart-0e3a2c7b-ba1d-44be-8473-f125865d7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340379484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.340379484
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2529205884
Short name T448
Test name
Test status
Simulation time 150952000 ps
CPU time 2.89 seconds
Started Jul 01 11:00:04 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 220868 kb
Host smart-0005bfa2-6725-42cc-9685-0ac1cebac087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529205884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2529205884
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1372267328
Short name T316
Test name
Test status
Simulation time 3012760470 ps
CPU time 9.29 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 209976 kb
Host smart-22300bc9-0ec2-4e7e-a1d9-fd3c9be644b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372267328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1372267328
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1712400317
Short name T870
Test name
Test status
Simulation time 869092506 ps
CPU time 3.24 seconds
Started Jul 01 11:00:02 AM PDT 24
Finished Jul 01 11:00:06 AM PDT 24
Peak memory 206800 kb
Host smart-62790df1-f5be-42d3-8f20-5e5bfaf4ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712400317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1712400317
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.163818144
Short name T564
Test name
Test status
Simulation time 391855986 ps
CPU time 5.71 seconds
Started Jul 01 11:00:01 AM PDT 24
Finished Jul 01 11:00:08 AM PDT 24
Peak memory 208172 kb
Host smart-e8a22b11-d94f-4564-a258-3e1f473e9770
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163818144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.163818144
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4261434617
Short name T643
Test name
Test status
Simulation time 24857490 ps
CPU time 1.97 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 208664 kb
Host smart-742514fb-9d48-4983-90f1-17871410d2c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261434617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4261434617
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1306369676
Short name T654
Test name
Test status
Simulation time 726192475 ps
CPU time 3.95 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 206996 kb
Host smart-a0139971-f62a-4d95-9d71-fd69c6e19fb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306369676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1306369676
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1338008538
Short name T266
Test name
Test status
Simulation time 101877509 ps
CPU time 2.46 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 218448 kb
Host smart-46ea6b54-b3e4-4107-8457-6c400676b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338008538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1338008538
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3548215039
Short name T369
Test name
Test status
Simulation time 364053531 ps
CPU time 3.03 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 206856 kb
Host smart-6d881839-0f89-4298-baa5-ccde7b981be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548215039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3548215039
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.617620091
Short name T785
Test name
Test status
Simulation time 293516021 ps
CPU time 17.09 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 222652 kb
Host smart-66afc569-97d3-4fc5-9938-00a6423c3d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617620091 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.617620091
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.820998928
Short name T513
Test name
Test status
Simulation time 178779896 ps
CPU time 2.2 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 207468 kb
Host smart-d4d15c14-be9a-4989-9d78-dd442a06dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820998928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.820998928
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2060278271
Short name T54
Test name
Test status
Simulation time 89354622 ps
CPU time 2.2 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 210160 kb
Host smart-267c9094-c9dd-4601-9831-4cdfaabbab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060278271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2060278271
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.728789549
Short name T766
Test name
Test status
Simulation time 12524887 ps
CPU time 0.89 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 206072 kb
Host smart-04a83706-a0ce-45dc-aefe-fc5bf92840c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728789549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.728789549
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.94748818
Short name T574
Test name
Test status
Simulation time 105022423 ps
CPU time 3.37 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 208176 kb
Host smart-9df55d33-17a1-4c9f-9879-b8c119195ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94748818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.94748818
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3778791880
Short name T735
Test name
Test status
Simulation time 87383141 ps
CPU time 3.34 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 222416 kb
Host smart-4e1a3106-f8bf-4755-a070-8d90fd58065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778791880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3778791880
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4211659040
Short name T249
Test name
Test status
Simulation time 120095535 ps
CPU time 3.6 seconds
Started Jul 01 11:00:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 222460 kb
Host smart-016b20be-ec3a-4773-93da-da8b255680e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211659040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4211659040
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.335083750
Short name T34
Test name
Test status
Simulation time 181629350 ps
CPU time 6.86 seconds
Started Jul 01 11:00:07 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 210744 kb
Host smart-2d928e68-0e69-4194-abbc-a959c72988cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335083750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.335083750
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1595291292
Short name T888
Test name
Test status
Simulation time 210691337 ps
CPU time 3.08 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 207888 kb
Host smart-d302ec64-8eaf-40c4-8135-6050426159c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595291292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1595291292
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.847248450
Short name T782
Test name
Test status
Simulation time 2207398806 ps
CPU time 9.35 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 208680 kb
Host smart-3caed54e-66b6-4dcf-86c8-25e9dc61274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847248450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.847248450
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2477577632
Short name T650
Test name
Test status
Simulation time 60659299 ps
CPU time 2.34 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:12 AM PDT 24
Peak memory 206788 kb
Host smart-d3854ca2-09e3-467f-a2c9-f4d570610bed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477577632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2477577632
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4132501740
Short name T328
Test name
Test status
Simulation time 323748821 ps
CPU time 4.56 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 208944 kb
Host smart-d7d0d2a7-5325-4cac-9155-366afcb530d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132501740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4132501740
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1885053087
Short name T705
Test name
Test status
Simulation time 137812710 ps
CPU time 2.57 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:10 AM PDT 24
Peak memory 207628 kb
Host smart-d4d44781-0a0b-4c5c-99c1-dd76fe3d800a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885053087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1885053087
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.724933097
Short name T174
Test name
Test status
Simulation time 222927094 ps
CPU time 2.63 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 207268 kb
Host smart-f2965e97-df08-4099-917b-b6c6ea625095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724933097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.724933097
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1874127013
Short name T740
Test name
Test status
Simulation time 582231657 ps
CPU time 3.68 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 208476 kb
Host smart-a7a409e8-8bf9-441f-89bc-e3a4c837fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874127013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1874127013
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2270651175
Short name T544
Test name
Test status
Simulation time 417283890 ps
CPU time 16.39 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 222092 kb
Host smart-fbc18352-9f87-4148-800c-cd22b73ccf8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270651175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2270651175
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3007276563
Short name T905
Test name
Test status
Simulation time 845955651 ps
CPU time 8.43 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:27 AM PDT 24
Peak memory 222476 kb
Host smart-6beb83bb-acc4-47fa-98fd-114231641973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007276563 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3007276563
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2556839903
Short name T297
Test name
Test status
Simulation time 268578584 ps
CPU time 6.43 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 208732 kb
Host smart-87ceeaa2-6e70-4172-ae98-f33e08d24c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556839903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2556839903
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1184116383
Short name T382
Test name
Test status
Simulation time 80915174 ps
CPU time 2.51 seconds
Started Jul 01 11:00:23 AM PDT 24
Finished Jul 01 11:00:31 AM PDT 24
Peak memory 210896 kb
Host smart-b317193a-5614-4501-9801-967857c63fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184116383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1184116383
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3333139714
Short name T913
Test name
Test status
Simulation time 17592742 ps
CPU time 0.84 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 206044 kb
Host smart-c5d31ec0-1b43-4cb9-b2a4-e01e01e06838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333139714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3333139714
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3505372131
Short name T135
Test name
Test status
Simulation time 57269447 ps
CPU time 2.66 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 214236 kb
Host smart-6f9b5a61-a3cf-4676-a308-665d61147017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505372131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3505372131
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1163309083
Short name T743
Test name
Test status
Simulation time 655854358 ps
CPU time 18.62 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 222808 kb
Host smart-05aa0e0d-1c54-4d80-a97e-748f5cf446df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163309083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1163309083
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1865614786
Short name T595
Test name
Test status
Simulation time 97925594 ps
CPU time 2.64 seconds
Started Jul 01 11:00:08 AM PDT 24
Finished Jul 01 11:00:14 AM PDT 24
Peak memory 207600 kb
Host smart-cfae2c6d-da37-4061-85ad-64c2eda0dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865614786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1865614786
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.711292015
Short name T78
Test name
Test status
Simulation time 440674315 ps
CPU time 5.32 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 220720 kb
Host smart-3e28e00f-00a4-4ca0-aaff-2e0c1d9f4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711292015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.711292015
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4236895090
Short name T325
Test name
Test status
Simulation time 544341137 ps
CPU time 6.33 seconds
Started Jul 01 11:00:16 AM PDT 24
Finished Jul 01 11:00:27 AM PDT 24
Peak memory 214200 kb
Host smart-acbfaf58-f1a2-4443-b1ab-79d9f98aa3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236895090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4236895090
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4251633276
Short name T444
Test name
Test status
Simulation time 33636283 ps
CPU time 2.66 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 208204 kb
Host smart-19f301ba-13b5-4e89-a654-29d2dec37125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251633276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4251633276
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2888029394
Short name T334
Test name
Test status
Simulation time 285719023 ps
CPU time 4.01 seconds
Started Jul 01 11:00:09 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 214308 kb
Host smart-cffa6494-06f0-4d92-9728-f8821a8f1a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888029394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2888029394
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3964608683
Short name T813
Test name
Test status
Simulation time 40984851 ps
CPU time 1.79 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 207304 kb
Host smart-56d44860-1052-4b86-be50-d745bca4cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964608683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3964608683
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4155283170
Short name T294
Test name
Test status
Simulation time 65649465 ps
CPU time 3.16 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 208560 kb
Host smart-42eb017a-49d9-4574-bd1d-880c39dbec8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155283170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4155283170
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.698314101
Short name T261
Test name
Test status
Simulation time 460866214 ps
CPU time 6.66 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 208304 kb
Host smart-87f98301-38f2-4919-9ffc-8219f179a9c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698314101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.698314101
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.408176812
Short name T571
Test name
Test status
Simulation time 214542144 ps
CPU time 5.92 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 208820 kb
Host smart-2c45ee73-2422-4c15-83eb-8d9b8cb70ecd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408176812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.408176812
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2984584286
Short name T609
Test name
Test status
Simulation time 29432505 ps
CPU time 2.22 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 207844 kb
Host smart-3fb8e5f5-651f-4058-836d-c00ba37f63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984584286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2984584286
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2918648608
Short name T731
Test name
Test status
Simulation time 66097983 ps
CPU time 2.18 seconds
Started Jul 01 11:00:06 AM PDT 24
Finished Jul 01 11:00:09 AM PDT 24
Peak memory 207044 kb
Host smart-25b641bd-061b-4164-863a-b43c41eac6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918648608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2918648608
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2475977086
Short name T917
Test name
Test status
Simulation time 327103096 ps
CPU time 4.03 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 207280 kb
Host smart-a92d07a2-cddf-4bcc-a6c5-9a9812a9deef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475977086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2475977086
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1297956240
Short name T59
Test name
Test status
Simulation time 112983855 ps
CPU time 2.44 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 210188 kb
Host smart-c59552c6-ad3d-496a-803a-e0311e9082b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297956240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1297956240
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3977880302
Short name T411
Test name
Test status
Simulation time 28735467 ps
CPU time 0.79 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:16 AM PDT 24
Peak memory 206036 kb
Host smart-10f8fb0a-78f7-42f6-892a-4cb0d0dbf263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977880302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3977880302
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1975500628
Short name T847
Test name
Test status
Simulation time 11789816 ps
CPU time 1.15 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 207000 kb
Host smart-5cdbb56b-948e-4c27-89e9-cb780f02534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975500628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1975500628
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3554937004
Short name T340
Test name
Test status
Simulation time 251627270 ps
CPU time 2.21 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 214252 kb
Host smart-dbbc8b42-a55a-4efc-921c-adb4218c2b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554937004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3554937004
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3761064109
Short name T246
Test name
Test status
Simulation time 150905118 ps
CPU time 2.93 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 214288 kb
Host smart-d6ada93d-59d0-4c52-bce3-1a90ba06c054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761064109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3761064109
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3644289773
Short name T821
Test name
Test status
Simulation time 559192759 ps
CPU time 2.51 seconds
Started Jul 01 11:00:14 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 222412 kb
Host smart-1c2ff8ba-617c-4e8f-a55f-4b8866ef1a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644289773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3644289773
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1670787689
Short name T347
Test name
Test status
Simulation time 3151142444 ps
CPU time 28.3 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 208768 kb
Host smart-8772a30f-e254-45c4-a601-1743138a6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670787689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1670787689
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1160415659
Short name T622
Test name
Test status
Simulation time 96949599 ps
CPU time 3.27 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:20 AM PDT 24
Peak memory 206876 kb
Host smart-4d963030-a0d9-491d-9da3-ba55af753e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160415659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1160415659
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.987526494
Short name T426
Test name
Test status
Simulation time 65304890 ps
CPU time 2.19 seconds
Started Jul 01 11:00:18 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 207024 kb
Host smart-2a59df79-d257-478e-aa99-6d798b4778b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987526494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.987526494
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4091558539
Short name T716
Test name
Test status
Simulation time 193935126 ps
CPU time 4.89 seconds
Started Jul 01 11:00:44 AM PDT 24
Finished Jul 01 11:00:50 AM PDT 24
Peak memory 208464 kb
Host smart-0b6912a8-5709-4e9e-8136-e77e27345281
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091558539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4091558539
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1704918982
Short name T781
Test name
Test status
Simulation time 150224040 ps
CPU time 2.47 seconds
Started Jul 01 11:00:12 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 206948 kb
Host smart-d44744ed-f617-4b21-ac8d-0cc83c6d50f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704918982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1704918982
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2119042875
Short name T119
Test name
Test status
Simulation time 121962403 ps
CPU time 3.05 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 207128 kb
Host smart-0e0441b8-5948-49d8-8f1f-c056474af90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119042875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2119042875
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.571022153
Short name T183
Test name
Test status
Simulation time 2221065648 ps
CPU time 50.8 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:01:18 AM PDT 24
Peak memory 222592 kb
Host smart-7d25b645-a2f7-4899-8bc8-e6918978d236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571022153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.571022153
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.397923625
Short name T172
Test name
Test status
Simulation time 676559511 ps
CPU time 14.09 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 219632 kb
Host smart-e224dcd5-8f28-4a12-8371-6dd76c8ebdbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397923625 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.397923625
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3301918934
Short name T695
Test name
Test status
Simulation time 449836798 ps
CPU time 3.65 seconds
Started Jul 01 11:00:16 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 207600 kb
Host smart-c98c7fab-2ce6-4fe9-a4d2-964ff827e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301918934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3301918934
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2711111425
Short name T703
Test name
Test status
Simulation time 308092783 ps
CPU time 2.31 seconds
Started Jul 01 11:00:13 AM PDT 24
Finished Jul 01 11:00:21 AM PDT 24
Peak memory 210160 kb
Host smart-5e70c733-4790-4ee1-98ed-ba8c12fa61b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711111425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2711111425
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3815657967
Short name T461
Test name
Test status
Simulation time 24235248 ps
CPU time 0.75 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:07 AM PDT 24
Peak memory 206024 kb
Host smart-92a320e0-a6fa-475e-82f5-fea42090a47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815657967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3815657967
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3275722446
Short name T916
Test name
Test status
Simulation time 235023502 ps
CPU time 4.36 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 210936 kb
Host smart-b8df669d-96ac-4dc3-b356-0693b2d6da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275722446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3275722446
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2043009797
Short name T652
Test name
Test status
Simulation time 1030354805 ps
CPU time 24.68 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:36 AM PDT 24
Peak memory 218404 kb
Host smart-98c740dd-f47b-45e8-999b-07054db6a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043009797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2043009797
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3731412496
Short name T802
Test name
Test status
Simulation time 243124707 ps
CPU time 4.43 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 215308 kb
Host smart-edb2da3a-83cc-4be5-b5a0-c4f02f9fe673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731412496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3731412496
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2802805904
Short name T220
Test name
Test status
Simulation time 153459112 ps
CPU time 1.81 seconds
Started Jul 01 10:59:08 AM PDT 24
Finished Jul 01 10:59:11 AM PDT 24
Peak memory 214304 kb
Host smart-db137678-f01a-4248-ace2-4474c294be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802805904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2802805904
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1923335151
Short name T392
Test name
Test status
Simulation time 78383458 ps
CPU time 2.58 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 209608 kb
Host smart-7817d6d3-9814-494f-ae92-40baffe36c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923335151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1923335151
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1942189354
Short name T499
Test name
Test status
Simulation time 229471634 ps
CPU time 6.58 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 208556 kb
Host smart-8b200741-4bbc-4275-857d-6d3442fe0603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942189354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1942189354
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.394296799
Short name T11
Test name
Test status
Simulation time 1024407140 ps
CPU time 5.77 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 230908 kb
Host smart-4de0cde5-eba9-4f19-86a6-25d1e145cd96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394296799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.394296799
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3660213502
Short name T670
Test name
Test status
Simulation time 80993735 ps
CPU time 2.62 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:13 AM PDT 24
Peak memory 208380 kb
Host smart-b41c1afc-d8f6-4ed3-b8d5-c1030114efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660213502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3660213502
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3218853746
Short name T380
Test name
Test status
Simulation time 39521256 ps
CPU time 2.38 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:13 AM PDT 24
Peak memory 208200 kb
Host smart-479ebc33-1458-45a7-8ea1-9e9bf83fa395
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218853746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3218853746
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1222289584
Short name T241
Test name
Test status
Simulation time 24029025 ps
CPU time 1.86 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 207064 kb
Host smart-9b06a370-49e2-492b-b09f-cd4a48b2a24f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222289584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1222289584
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3798083818
Short name T910
Test name
Test status
Simulation time 50223534 ps
CPU time 2.67 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 208556 kb
Host smart-ba45c0e1-4dcb-459b-a8dc-4a24034a5f60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798083818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3798083818
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.786676821
Short name T818
Test name
Test status
Simulation time 115679289 ps
CPU time 1.76 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:13 AM PDT 24
Peak memory 209548 kb
Host smart-58e7a114-8500-4dde-aa05-cf13d0c77e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786676821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.786676821
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4238452825
Short name T563
Test name
Test status
Simulation time 150410631 ps
CPU time 3.08 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 208784 kb
Host smart-37431a1b-5955-4530-b750-eec7de6eb955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238452825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4238452825
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2498022775
Short name T287
Test name
Test status
Simulation time 3029678423 ps
CPU time 93.2 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 222476 kb
Host smart-6cfeab21-4a21-4f61-9340-89ea3687c4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498022775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2498022775
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.71942414
Short name T565
Test name
Test status
Simulation time 767344035 ps
CPU time 14.94 seconds
Started Jul 01 10:59:08 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 222520 kb
Host smart-ed2c7d5a-5ce0-4514-baff-2267e7aa5171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71942414 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.71942414
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3878823587
Short name T722
Test name
Test status
Simulation time 56491731 ps
CPU time 3.37 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 209336 kb
Host smart-35d46249-b672-4073-a529-f0be04f3b462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878823587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3878823587
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1463633056
Short name T496
Test name
Test status
Simulation time 174784486 ps
CPU time 1.47 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:14 AM PDT 24
Peak memory 208832 kb
Host smart-ab1dcf1c-75e6-4d7e-9e43-ae9cb7cfc8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463633056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1463633056
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3948630424
Short name T642
Test name
Test status
Simulation time 21141861 ps
CPU time 0.78 seconds
Started Jul 01 11:00:17 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 206052 kb
Host smart-e0b9329d-bc85-4f30-8e97-ca914961c639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948630424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3948630424
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1509911415
Short name T823
Test name
Test status
Simulation time 5590044825 ps
CPU time 73.58 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:01:40 AM PDT 24
Peak memory 215120 kb
Host smart-9f4c2553-a2b0-4a26-b9c5-71692efc62bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509911415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1509911415
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2935332155
Short name T691
Test name
Test status
Simulation time 343285348 ps
CPU time 3.56 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 209464 kb
Host smart-10102463-702d-47b2-b674-8d15183d3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935332155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2935332155
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2403282722
Short name T65
Test name
Test status
Simulation time 369359988 ps
CPU time 7.75 seconds
Started Jul 01 11:00:19 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 208392 kb
Host smart-193c0587-c9a1-4946-a1c1-ffecf9bccfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403282722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2403282722
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1449660405
Short name T225
Test name
Test status
Simulation time 13754327059 ps
CPU time 80.54 seconds
Started Jul 01 11:00:34 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 214340 kb
Host smart-b8bf3292-7c9a-4b86-ae03-7aab8baf5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449660405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1449660405
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3973454107
Short name T82
Test name
Test status
Simulation time 65471833 ps
CPU time 2.4 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 214264 kb
Host smart-b0fd1b12-30e9-4ac3-a602-25d1093ca73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973454107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3973454107
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.1760752705
Short name T473
Test name
Test status
Simulation time 105670558 ps
CPU time 3.46 seconds
Started Jul 01 11:00:16 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 214240 kb
Host smart-bcb900b3-1c7e-46e8-a746-946a6c8ef7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760752705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1760752705
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3735605805
Short name T793
Test name
Test status
Simulation time 496653470 ps
CPU time 2.34 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 206732 kb
Host smart-e246365d-91d2-4ef3-b265-c93d794564c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735605805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3735605805
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2781438363
Short name T301
Test name
Test status
Simulation time 34851214 ps
CPU time 1.88 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:22 AM PDT 24
Peak memory 208064 kb
Host smart-6f5b863e-31f2-4ad9-9e4c-7166ee7e99b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781438363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2781438363
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1174525636
Short name T779
Test name
Test status
Simulation time 245009174 ps
CPU time 3.06 seconds
Started Jul 01 11:00:19 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 208748 kb
Host smart-62785057-1626-440b-83f3-c2c2f93b016d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174525636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1174525636
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1838109049
Short name T470
Test name
Test status
Simulation time 180465784 ps
CPU time 4.98 seconds
Started Jul 01 11:00:43 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 208428 kb
Host smart-8c9702ee-5c24-475d-abd1-226419e0792a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838109049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1838109049
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1315233417
Short name T573
Test name
Test status
Simulation time 100625042 ps
CPU time 2.43 seconds
Started Jul 01 11:00:46 AM PDT 24
Finished Jul 01 11:00:49 AM PDT 24
Peak memory 209732 kb
Host smart-173a20b0-4c89-4677-ac99-4504813b78b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315233417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1315233417
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3596599430
Short name T77
Test name
Test status
Simulation time 40116420 ps
CPU time 1.72 seconds
Started Jul 01 11:00:11 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 207272 kb
Host smart-ab6bd5ff-2d87-4e7e-b0c6-b50906041daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596599430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3596599430
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2279806364
Short name T462
Test name
Test status
Simulation time 107899356 ps
CPU time 4.86 seconds
Started Jul 01 11:00:26 AM PDT 24
Finished Jul 01 11:00:32 AM PDT 24
Peak memory 207804 kb
Host smart-1d2f8bd7-733d-4b75-bf06-a8d86c513c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279806364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2279806364
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.515685054
Short name T620
Test name
Test status
Simulation time 290865276 ps
CPU time 4.78 seconds
Started Jul 01 11:00:15 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 210720 kb
Host smart-28d16152-25aa-47dd-9924-fa758f4f49c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515685054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.515685054
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1657639711
Short name T408
Test name
Test status
Simulation time 138114112 ps
CPU time 0.77 seconds
Started Jul 01 11:00:20 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 206072 kb
Host smart-e27a3da4-7094-4ec8-8b87-e1aacd04ef22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657639711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1657639711
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.924879553
Short name T280
Test name
Test status
Simulation time 171199921 ps
CPU time 3.12 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 214312 kb
Host smart-1e78a2c8-8722-4452-83b4-eb3f9a327dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924879553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.924879553
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.736247525
Short name T921
Test name
Test status
Simulation time 105335375 ps
CPU time 4.88 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:32 AM PDT 24
Peak memory 210544 kb
Host smart-d5c86c25-4e91-4785-b230-cd0f5156e27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736247525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.736247525
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.473588588
Short name T476
Test name
Test status
Simulation time 47189255 ps
CPU time 2.09 seconds
Started Jul 01 11:00:42 AM PDT 24
Finished Jul 01 11:00:45 AM PDT 24
Peak memory 207568 kb
Host smart-704470fe-6b8d-4803-ba6c-ead17bb215d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473588588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.473588588
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.154179000
Short name T611
Test name
Test status
Simulation time 220586287 ps
CPU time 2.02 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:29 AM PDT 24
Peak memory 214268 kb
Host smart-8ed21bac-7a9d-41aa-a828-1790c694e7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154179000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.154179000
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3473428641
Short name T803
Test name
Test status
Simulation time 104247881 ps
CPU time 3.56 seconds
Started Jul 01 11:00:47 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 214344 kb
Host smart-e0dc5b8e-2d23-4d57-932b-892328d44c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473428641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3473428641
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1842677905
Short name T690
Test name
Test status
Simulation time 667049713 ps
CPU time 7.39 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 209088 kb
Host smart-2101d1e4-d77a-4e6a-b480-9054d2c517ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842677905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1842677905
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1053944445
Short name T790
Test name
Test status
Simulation time 181777581 ps
CPU time 2.61 seconds
Started Jul 01 11:00:42 AM PDT 24
Finished Jul 01 11:00:45 AM PDT 24
Peak memory 206880 kb
Host smart-cd588eef-54b8-4135-a67a-c34ed387926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053944445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1053944445
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.148105724
Short name T494
Test name
Test status
Simulation time 262867636 ps
CPU time 4.11 seconds
Started Jul 01 11:00:36 AM PDT 24
Finished Jul 01 11:00:41 AM PDT 24
Peak memory 208648 kb
Host smart-506bc689-2c32-4cdf-9df5-a6191a5c3a09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148105724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.148105724
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2439801175
Short name T95
Test name
Test status
Simulation time 121711405 ps
CPU time 2.37 seconds
Started Jul 01 11:00:54 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 206964 kb
Host smart-b380a5bf-26c0-4fa0-b450-716038a93cc7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439801175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2439801175
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.764083276
Short name T530
Test name
Test status
Simulation time 48050063 ps
CPU time 2.05 seconds
Started Jul 01 11:00:24 AM PDT 24
Finished Jul 01 11:00:28 AM PDT 24
Peak memory 208756 kb
Host smart-068287b2-e3ce-416a-a788-9e6cfe6b4e7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764083276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.764083276
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3475994902
Short name T759
Test name
Test status
Simulation time 191531463 ps
CPU time 1.83 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 209324 kb
Host smart-abad6f46-455a-4066-add6-6e98101cda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475994902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3475994902
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1438172571
Short name T442
Test name
Test status
Simulation time 1760715965 ps
CPU time 10.88 seconds
Started Jul 01 11:00:23 AM PDT 24
Finished Jul 01 11:00:35 AM PDT 24
Peak memory 206788 kb
Host smart-ed3b4136-e3ea-45d2-bee8-d5e70afe4f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438172571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1438172571
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2860617917
Short name T70
Test name
Test status
Simulation time 20725242988 ps
CPU time 215.05 seconds
Started Jul 01 11:00:33 AM PDT 24
Finished Jul 01 11:04:09 AM PDT 24
Peak memory 222444 kb
Host smart-5fbf1a61-b89a-483b-af72-0dd2d0f0b879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860617917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2860617917
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1313998128
Short name T113
Test name
Test status
Simulation time 1024190710 ps
CPU time 10.11 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 222568 kb
Host smart-aa674dfe-db79-450b-b66d-16c1ea24572a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313998128 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1313998128
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.958200333
Short name T479
Test name
Test status
Simulation time 169207345 ps
CPU time 3.95 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:39 AM PDT 24
Peak memory 208708 kb
Host smart-5cf17c4b-4a53-4668-aa5f-ed688df0ac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958200333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.958200333
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.778836606
Short name T597
Test name
Test status
Simulation time 14789930 ps
CPU time 0.9 seconds
Started Jul 01 11:00:24 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 206096 kb
Host smart-9a43193f-e4a6-471d-b466-6b3b9ff0622f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778836606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.778836606
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2068336138
Short name T397
Test name
Test status
Simulation time 275817049 ps
CPU time 3.58 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 215448 kb
Host smart-ec6ff8e2-c9c6-4111-987d-ec4aea27eb35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068336138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2068336138
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.925244846
Short name T30
Test name
Test status
Simulation time 469196528 ps
CPU time 3.06 seconds
Started Jul 01 11:00:43 AM PDT 24
Finished Jul 01 11:00:46 AM PDT 24
Peak memory 219448 kb
Host smart-44f80d18-283c-42d4-b8e5-81d0aed7d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925244846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.925244846
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1779668207
Short name T906
Test name
Test status
Simulation time 46418402 ps
CPU time 2 seconds
Started Jul 01 11:00:43 AM PDT 24
Finished Jul 01 11:00:46 AM PDT 24
Peak memory 210176 kb
Host smart-74e78e4a-98eb-43a3-b316-735ea9d50604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779668207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1779668207
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4243345109
Short name T307
Test name
Test status
Simulation time 532046457 ps
CPU time 6.07 seconds
Started Jul 01 11:00:28 AM PDT 24
Finished Jul 01 11:00:35 AM PDT 24
Peak memory 214676 kb
Host smart-bb8daf0a-b954-42dc-9d3f-622d7ea121ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243345109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4243345109
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2022025518
Short name T281
Test name
Test status
Simulation time 214477313 ps
CPU time 3.24 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 214348 kb
Host smart-98c3dc78-fa58-4bd5-b874-a916fb9d5f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022025518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2022025518
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3160554331
Short name T865
Test name
Test status
Simulation time 112611820 ps
CPU time 2.56 seconds
Started Jul 01 11:00:24 AM PDT 24
Finished Jul 01 11:00:28 AM PDT 24
Peak memory 220012 kb
Host smart-4ec42612-b50c-424a-b5bd-482964a44061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160554331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3160554331
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2415871254
Short name T569
Test name
Test status
Simulation time 362636810 ps
CPU time 4.1 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 208420 kb
Host smart-ae296db0-614c-4f42-b783-b90f8956499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415871254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2415871254
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1267593247
Short name T293
Test name
Test status
Simulation time 77115283 ps
CPU time 3.71 seconds
Started Jul 01 11:00:20 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 208816 kb
Host smart-abfc94b6-77be-4435-b109-7d4f78e9f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267593247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1267593247
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3557014038
Short name T14
Test name
Test status
Simulation time 226776675 ps
CPU time 2.61 seconds
Started Jul 01 11:00:22 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 206996 kb
Host smart-7aeaa3b6-c688-48fa-b55e-a26112f8d66e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557014038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3557014038
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1015259635
Short name T546
Test name
Test status
Simulation time 138635158 ps
CPU time 4.56 seconds
Started Jul 01 11:00:20 AM PDT 24
Finished Jul 01 11:00:27 AM PDT 24
Peak memory 208988 kb
Host smart-7d223936-a379-42a8-bf88-3b7f89e41c6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015259635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1015259635
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2288249319
Short name T507
Test name
Test status
Simulation time 19225026 ps
CPU time 1.64 seconds
Started Jul 01 11:00:19 AM PDT 24
Finished Jul 01 11:00:24 AM PDT 24
Peak memory 206960 kb
Host smart-4c725567-9903-4063-8dd0-2014ebb92c0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288249319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2288249319
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.329992824
Short name T536
Test name
Test status
Simulation time 46167936 ps
CPU time 2.49 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 215976 kb
Host smart-6a0b7d19-2f34-4475-8c5b-ceedbd41ace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329992824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.329992824
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2009970720
Short name T419
Test name
Test status
Simulation time 465956860 ps
CPU time 2.28 seconds
Started Jul 01 11:00:23 AM PDT 24
Finished Jul 01 11:00:26 AM PDT 24
Peak memory 206732 kb
Host smart-1bc82fa5-0354-45ac-b0ed-9d06727cc8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009970720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2009970720
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3684236245
Short name T166
Test name
Test status
Simulation time 5054839475 ps
CPU time 26.94 seconds
Started Jul 01 11:00:26 AM PDT 24
Finished Jul 01 11:00:54 AM PDT 24
Peak memory 223284 kb
Host smart-9689337c-6fde-466c-a8ef-b272d02ef7d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684236245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3684236245
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2100057480
Short name T756
Test name
Test status
Simulation time 53048890 ps
CPU time 2.4 seconds
Started Jul 01 11:00:26 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 210572 kb
Host smart-744b2566-5bbc-41d2-9fa2-a2dab7671479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100057480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2100057480
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2061185227
Short name T93
Test name
Test status
Simulation time 10442900 ps
CPU time 0.84 seconds
Started Jul 01 11:00:30 AM PDT 24
Finished Jul 01 11:00:31 AM PDT 24
Peak memory 206044 kb
Host smart-05c14f4a-c229-441d-ba46-152e7557703d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061185227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2061185227
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2298528072
Short name T37
Test name
Test status
Simulation time 433261607 ps
CPU time 4.32 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:31 AM PDT 24
Peak memory 220356 kb
Host smart-526ae5c8-2880-477f-9abc-de2302a2b27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298528072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2298528072
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2720572527
Short name T560
Test name
Test status
Simulation time 443892481 ps
CPU time 2.18 seconds
Started Jul 01 11:00:40 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 210040 kb
Host smart-215db737-d88d-43a6-876c-970fc0bdccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720572527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2720572527
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.42709099
Short name T86
Test name
Test status
Simulation time 70533076 ps
CPU time 3.38 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 214332 kb
Host smart-5d8040fd-5bf3-41a9-80e4-b0930a7a182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42709099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.42709099
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1290178077
Short name T871
Test name
Test status
Simulation time 1235498073 ps
CPU time 9.63 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 214292 kb
Host smart-97e3c47a-d711-4238-bb74-e70d8da7f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290178077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1290178077
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2119918015
Short name T694
Test name
Test status
Simulation time 301295477 ps
CPU time 2.13 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:29 AM PDT 24
Peak memory 206124 kb
Host smart-c4be303a-7df3-4d94-b215-3c12891f3f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119918015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2119918015
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3978979251
Short name T377
Test name
Test status
Simulation time 717789163 ps
CPU time 5.52 seconds
Started Jul 01 11:00:28 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 207868 kb
Host smart-35c9ddb3-eec9-4649-bf8c-ba4ccba02c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978979251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3978979251
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2009224224
Short name T348
Test name
Test status
Simulation time 36422023 ps
CPU time 2.45 seconds
Started Jul 01 11:00:30 AM PDT 24
Finished Jul 01 11:00:33 AM PDT 24
Peak memory 206920 kb
Host smart-45c9701c-5144-4ad7-8d63-7675e4ea3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009224224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2009224224
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4018073334
Short name T792
Test name
Test status
Simulation time 165067384 ps
CPU time 4.45 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 208632 kb
Host smart-ce9e34a0-daef-4c43-bb08-3163b93820a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018073334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4018073334
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.41850027
Short name T575
Test name
Test status
Simulation time 139937477 ps
CPU time 4.56 seconds
Started Jul 01 11:00:27 AM PDT 24
Finished Jul 01 11:00:32 AM PDT 24
Peak memory 207132 kb
Host smart-27bb563c-3da6-4ca9-82af-cc3d616494de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41850027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.41850027
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1350222021
Short name T657
Test name
Test status
Simulation time 617807004 ps
CPU time 3.33 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 206948 kb
Host smart-92e593fe-6cf6-4ea5-a696-32b44c3dd458
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350222021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1350222021
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.752809858
Short name T434
Test name
Test status
Simulation time 75619064 ps
CPU time 2.57 seconds
Started Jul 01 11:00:25 AM PDT 24
Finished Jul 01 11:00:29 AM PDT 24
Peak memory 209444 kb
Host smart-45a8fd62-f325-4bd6-b2d5-f51631be9c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752809858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.752809858
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1085408017
Short name T881
Test name
Test status
Simulation time 4441702693 ps
CPU time 22.73 seconds
Started Jul 01 11:00:27 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 208728 kb
Host smart-ecac8978-17ee-457f-8534-4267c0d222eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085408017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1085408017
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.737755819
Short name T895
Test name
Test status
Simulation time 9261273226 ps
CPU time 53.09 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 222472 kb
Host smart-d3fecc5f-b208-4f06-a608-fa27c963d244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737755819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.737755819
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2793693224
Short name T171
Test name
Test status
Simulation time 680705692 ps
CPU time 11.34 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 222632 kb
Host smart-1de30cb0-a0d8-446f-9f0a-0c0f91ae6faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793693224 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2793693224
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.795772434
Short name T593
Test name
Test status
Simulation time 95802839 ps
CPU time 3.44 seconds
Started Jul 01 11:00:27 AM PDT 24
Finished Jul 01 11:00:32 AM PDT 24
Peak memory 210016 kb
Host smart-a3860e7a-46d4-4365-97ad-a2c6fd4a1125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795772434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.795772434
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1618915952
Short name T53
Test name
Test status
Simulation time 99123814 ps
CPU time 1.94 seconds
Started Jul 01 11:00:27 AM PDT 24
Finished Jul 01 11:00:30 AM PDT 24
Peak memory 209756 kb
Host smart-0377b740-223a-4a64-832d-44d74898d802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618915952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1618915952
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2305569700
Short name T805
Test name
Test status
Simulation time 12629592 ps
CPU time 0.73 seconds
Started Jul 01 11:00:33 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 206020 kb
Host smart-db6a2dbd-dfc9-415a-854f-889fefdde5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305569700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2305569700
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4028526118
Short name T33
Test name
Test status
Simulation time 107438853 ps
CPU time 3.29 seconds
Started Jul 01 11:00:48 AM PDT 24
Finished Jul 01 11:00:52 AM PDT 24
Peak memory 222144 kb
Host smart-8a77ce45-45f9-4841-b28a-f6a15ee227e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028526118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4028526118
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.833669598
Short name T737
Test name
Test status
Simulation time 39994547 ps
CPU time 1.82 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:00:32 AM PDT 24
Peak memory 207408 kb
Host smart-f8816ff9-ac6b-4b35-adf4-ddae58deb638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833669598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.833669598
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1559047161
Short name T83
Test name
Test status
Simulation time 51599255 ps
CPU time 2.75 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 214264 kb
Host smart-8d8bbbba-b471-4280-863e-db72a626c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559047161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1559047161
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3769322671
Short name T440
Test name
Test status
Simulation time 238917367 ps
CPU time 2.25 seconds
Started Jul 01 11:00:48 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 205796 kb
Host smart-f741f496-fccc-404f-8627-def8cf9a7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769322671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3769322671
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1609816349
Short name T624
Test name
Test status
Simulation time 802430777 ps
CPU time 6.91 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 214408 kb
Host smart-ab373fef-2272-4cc2-9fda-0783b2759bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609816349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1609816349
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3790852832
Short name T521
Test name
Test status
Simulation time 199905803 ps
CPU time 2.42 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 206856 kb
Host smart-d4a0a915-e391-463c-bba0-f794a4187b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790852832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3790852832
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.176260887
Short name T704
Test name
Test status
Simulation time 11835750986 ps
CPU time 19.34 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:53 AM PDT 24
Peak memory 208064 kb
Host smart-9f7aebdc-c9c7-4764-bd17-7da7ef9f4f74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176260887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.176260887
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.603509852
Short name T436
Test name
Test status
Simulation time 347545923 ps
CPU time 3.58 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:37 AM PDT 24
Peak memory 206908 kb
Host smart-cba3134e-b94e-4ce2-a39d-3f8bbaf7ef17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603509852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.603509852
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1603366637
Short name T180
Test name
Test status
Simulation time 324856456 ps
CPU time 6.57 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 208944 kb
Host smart-98928e51-bec0-4717-9f50-3de4e4193da6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603366637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1603366637
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.230563026
Short name T538
Test name
Test status
Simulation time 206943327 ps
CPU time 2.82 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:04 AM PDT 24
Peak memory 209204 kb
Host smart-a208f1d8-a16a-48d4-908f-670a2ff10c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230563026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.230563026
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2034905804
Short name T819
Test name
Test status
Simulation time 171929118 ps
CPU time 4.1 seconds
Started Jul 01 11:00:30 AM PDT 24
Finished Jul 01 11:00:34 AM PDT 24
Peak memory 206896 kb
Host smart-5465f107-f8db-4053-95b4-d110e9744954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034905804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2034905804
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2692891694
Short name T185
Test name
Test status
Simulation time 5978900162 ps
CPU time 35.84 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 221836 kb
Host smart-c3683858-d3af-43bb-af9a-80530e343c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692891694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2692891694
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.794970178
Short name T273
Test name
Test status
Simulation time 5522358267 ps
CPU time 36.76 seconds
Started Jul 01 11:00:29 AM PDT 24
Finished Jul 01 11:01:06 AM PDT 24
Peak memory 214400 kb
Host smart-24983dbd-0e07-4224-9839-da60c236c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794970178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.794970178
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1866801943
Short name T900
Test name
Test status
Simulation time 166575950 ps
CPU time 3.15 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 209956 kb
Host smart-c268d87c-3ad2-4205-8018-e18c51768664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866801943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1866801943
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.204678017
Short name T431
Test name
Test status
Simulation time 12287808 ps
CPU time 0.9 seconds
Started Jul 01 11:00:38 AM PDT 24
Finished Jul 01 11:00:39 AM PDT 24
Peak memory 206080 kb
Host smart-d8fbb222-6925-4761-bf83-e78851a74d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204678017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.204678017
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.837198946
Short name T136
Test name
Test status
Simulation time 42339627 ps
CPU time 3.04 seconds
Started Jul 01 11:00:44 AM PDT 24
Finished Jul 01 11:00:47 AM PDT 24
Peak memory 214284 kb
Host smart-8c18b377-e700-4026-8d23-e2b73cd69c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837198946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.837198946
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1003357378
Short name T359
Test name
Test status
Simulation time 774748817 ps
CPU time 3.14 seconds
Started Jul 01 11:00:48 AM PDT 24
Finished Jul 01 11:00:52 AM PDT 24
Peak memory 221304 kb
Host smart-74dec4f3-dbf6-4117-b3cc-2f8f4d089e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003357378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1003357378
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2519161080
Short name T630
Test name
Test status
Simulation time 3900122779 ps
CPU time 11.3 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 209336 kb
Host smart-1011e350-5fb3-4213-96f1-9e2adac19f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519161080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2519161080
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1960951334
Short name T581
Test name
Test status
Simulation time 33470746 ps
CPU time 2.31 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:00:59 AM PDT 24
Peak memory 214348 kb
Host smart-d2083ee2-20f7-4e5e-b450-6ebe39b55d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960951334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1960951334
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2267949200
Short name T221
Test name
Test status
Simulation time 127513291 ps
CPU time 2.66 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 211508 kb
Host smart-1ae62b19-ed49-4f7e-b334-41ea551b1332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267949200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2267949200
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.1632778151
Short name T349
Test name
Test status
Simulation time 1085662529 ps
CPU time 9.9 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 222424 kb
Host smart-3481c7e9-d366-4376-b599-89a7a4bbc160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632778151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1632778151
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4059919533
Short name T594
Test name
Test status
Simulation time 117953302 ps
CPU time 3.3 seconds
Started Jul 01 11:00:35 AM PDT 24
Finished Jul 01 11:00:39 AM PDT 24
Peak memory 206832 kb
Host smart-4a9d3787-9eb2-4532-af96-76e6f4e4a13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059919533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4059919533
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4097831872
Short name T520
Test name
Test status
Simulation time 184629482 ps
CPU time 4.09 seconds
Started Jul 01 11:00:47 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 208976 kb
Host smart-271d55e0-501f-4bc8-8e36-a205837b06c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097831872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4097831872
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1216660885
Short name T664
Test name
Test status
Simulation time 1032807655 ps
CPU time 7.5 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 208756 kb
Host smart-06400c15-848f-4834-a5a4-02b86e5edb43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216660885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1216660885
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1224981874
Short name T492
Test name
Test status
Simulation time 281648043 ps
CPU time 3.47 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:36 AM PDT 24
Peak memory 209176 kb
Host smart-a9d71f41-a151-4da9-9fe1-574865359583
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224981874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1224981874
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3798827631
Short name T235
Test name
Test status
Simulation time 317063390 ps
CPU time 3.8 seconds
Started Jul 01 11:00:52 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 214328 kb
Host smart-b1f40a2b-e0a1-4125-832a-5c947fc78ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798827631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3798827631
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1827826673
Short name T568
Test name
Test status
Simulation time 1999197814 ps
CPU time 18.68 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 207828 kb
Host smart-8592a265-66d4-4767-b150-38ee9d71d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827826673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1827826673
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1070214530
Short name T64
Test name
Test status
Simulation time 664493332 ps
CPU time 10.39 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 222520 kb
Host smart-b2d5336f-af2f-4936-9960-5f495d871ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070214530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1070214530
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3623954640
Short name T488
Test name
Test status
Simulation time 566884218 ps
CPU time 3.21 seconds
Started Jul 01 11:00:32 AM PDT 24
Finished Jul 01 11:00:35 AM PDT 24
Peak memory 218268 kb
Host smart-418c00a8-6134-4f62-aa72-0ffaf8d34dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623954640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3623954640
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.4106983640
Short name T474
Test name
Test status
Simulation time 60536835 ps
CPU time 1.74 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 210120 kb
Host smart-63ea6f42-8fdd-4ecc-ae09-9e03a4840eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106983640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4106983640
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1280978576
Short name T407
Test name
Test status
Simulation time 40083601 ps
CPU time 0.79 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:38 AM PDT 24
Peak memory 206032 kb
Host smart-03f58e70-d45f-4206-8a22-3f24b2cd9f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280978576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1280978576
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1863276060
Short name T390
Test name
Test status
Simulation time 135179240 ps
CPU time 2.46 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 214340 kb
Host smart-88de7135-e07e-4525-b9b5-4a47b1026a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863276060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1863276060
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.574934618
Short name T8
Test name
Test status
Simulation time 169877242 ps
CPU time 2.85 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 222784 kb
Host smart-57408d7f-7db6-4461-b90e-299973ad058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574934618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.574934618
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2855439109
Short name T810
Test name
Test status
Simulation time 42809034 ps
CPU time 2.17 seconds
Started Jul 01 11:00:36 AM PDT 24
Finished Jul 01 11:00:39 AM PDT 24
Peak memory 207604 kb
Host smart-8d996fe9-6903-480e-be17-387c340f0c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855439109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2855439109
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1369047022
Short name T395
Test name
Test status
Simulation time 926895485 ps
CPU time 7.53 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:05 AM PDT 24
Peak memory 215380 kb
Host smart-3f5d1c3a-aa0b-472d-a472-a074583e2f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369047022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1369047022
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3190838960
Short name T777
Test name
Test status
Simulation time 113035436 ps
CPU time 5.03 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 219432 kb
Host smart-d60ffeec-cfa5-4695-b9c3-421c8e7b0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190838960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3190838960
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3186284268
Short name T312
Test name
Test status
Simulation time 121416816 ps
CPU time 4.56 seconds
Started Jul 01 11:00:36 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 208580 kb
Host smart-3907f450-8c10-43fc-9e7a-56eaad765f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186284268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3186284268
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2409621643
Short name T831
Test name
Test status
Simulation time 374730254 ps
CPU time 3.42 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 208796 kb
Host smart-b4c97f83-f9ac-4242-92de-21d3efcdcf5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409621643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2409621643
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3806642691
Short name T501
Test name
Test status
Simulation time 719131466 ps
CPU time 8.41 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 208580 kb
Host smart-4f6ad893-42be-41ff-a35a-ebe7e05a04be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806642691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3806642691
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1058810952
Short name T213
Test name
Test status
Simulation time 50052609 ps
CPU time 2.83 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 206944 kb
Host smart-1635af2f-110e-43ba-86f3-e23badaeee99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058810952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1058810952
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2384494821
Short name T332
Test name
Test status
Simulation time 246163526 ps
CPU time 3.26 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 209144 kb
Host smart-a47d783d-b87b-4509-b545-6e25065f47ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384494821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2384494821
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4273388104
Short name T631
Test name
Test status
Simulation time 182800967 ps
CPU time 2.39 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 208608 kb
Host smart-95edc6cb-4dfe-41fc-a247-e04aba481069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273388104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4273388104
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1036754704
Short name T243
Test name
Test status
Simulation time 1227456413 ps
CPU time 36.31 seconds
Started Jul 01 11:00:38 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 222512 kb
Host smart-f2c288ac-5714-4c57-b8a4-b8b9ae4acc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036754704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1036754704
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2357527917
Short name T236
Test name
Test status
Simulation time 814485449 ps
CPU time 7.11 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:01:04 AM PDT 24
Peak memory 219436 kb
Host smart-6b7663bf-aaf9-4807-bb79-4258a4148f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357527917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2357527917
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3698269524
Short name T36
Test name
Test status
Simulation time 56154382 ps
CPU time 1.58 seconds
Started Jul 01 11:00:44 AM PDT 24
Finished Jul 01 11:00:46 AM PDT 24
Peak memory 209888 kb
Host smart-64cf142a-539f-4fbd-b4c9-1f013daceb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698269524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3698269524
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3581041412
Short name T427
Test name
Test status
Simulation time 48134816 ps
CPU time 0.7 seconds
Started Jul 01 11:00:40 AM PDT 24
Finished Jul 01 11:00:41 AM PDT 24
Peak memory 205912 kb
Host smart-001b1bc8-1abb-4e48-a23a-1b7c006acb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581041412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3581041412
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2003773233
Short name T258
Test name
Test status
Simulation time 250008364 ps
CPU time 13.74 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:52 AM PDT 24
Peak memory 214320 kb
Host smart-dc995120-fcd2-46bf-b51b-bdfba31ca6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003773233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2003773233
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.69376751
Short name T32
Test name
Test status
Simulation time 378882323 ps
CPU time 3.34 seconds
Started Jul 01 11:00:49 AM PDT 24
Finished Jul 01 11:00:53 AM PDT 24
Peak memory 220012 kb
Host smart-32817e34-0978-4c81-a31e-7b1290ae1d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69376751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.69376751
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3086221598
Short name T741
Test name
Test status
Simulation time 156853007 ps
CPU time 1.42 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 209160 kb
Host smart-2db54d22-5a5d-4eb4-8f0f-aa89ae2343dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086221598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3086221598
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1493564281
Short name T675
Test name
Test status
Simulation time 271427589 ps
CPU time 7.83 seconds
Started Jul 01 11:00:54 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 214336 kb
Host smart-38a55e3b-c548-4944-abf1-a43e57cf165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493564281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1493564281
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2675980443
Short name T879
Test name
Test status
Simulation time 35435254 ps
CPU time 2.28 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 219896 kb
Host smart-0487fdc5-a3b3-4c10-89b6-0787d424a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675980443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2675980443
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.853512730
Short name T286
Test name
Test status
Simulation time 744602368 ps
CPU time 6.82 seconds
Started Jul 01 11:00:54 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 214332 kb
Host smart-7cb641c6-e29b-4617-b851-b4aacf07ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853512730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.853512730
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2300794372
Short name T254
Test name
Test status
Simulation time 84801502 ps
CPU time 2.79 seconds
Started Jul 01 11:00:50 AM PDT 24
Finished Jul 01 11:00:53 AM PDT 24
Peak memory 208300 kb
Host smart-2fda9c62-0363-4e8a-a92f-691cc3e83336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300794372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2300794372
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.156361328
Short name T409
Test name
Test status
Simulation time 608808753 ps
CPU time 4.56 seconds
Started Jul 01 11:00:40 AM PDT 24
Finished Jul 01 11:00:45 AM PDT 24
Peak memory 207984 kb
Host smart-35e79813-0b05-47b2-ac50-40fa2e5130da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156361328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.156361328
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3571450786
Short name T736
Test name
Test status
Simulation time 68407079 ps
CPU time 3.53 seconds
Started Jul 01 11:00:43 AM PDT 24
Finished Jul 01 11:00:47 AM PDT 24
Peak memory 208856 kb
Host smart-acfdcb1b-636f-453d-a290-f2404943ce06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571450786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3571450786
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2416102222
Short name T579
Test name
Test status
Simulation time 65784967 ps
CPU time 3.18 seconds
Started Jul 01 11:00:53 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 208200 kb
Host smart-3ff3e5e2-dfc9-4708-8667-a4e848391d6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416102222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2416102222
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4127731053
Short name T783
Test name
Test status
Simulation time 598364321 ps
CPU time 4.38 seconds
Started Jul 01 11:00:37 AM PDT 24
Finished Jul 01 11:00:42 AM PDT 24
Peak memory 208012 kb
Host smart-9dd6e0b4-eb5b-433a-95ee-7d356e02e66d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127731053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4127731053
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.216561516
Short name T686
Test name
Test status
Simulation time 159967530 ps
CPU time 3.38 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:01:00 AM PDT 24
Peak memory 207248 kb
Host smart-31971c3b-4dc4-4b96-aa9b-61fcbcbe929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216561516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.216561516
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3024132522
Short name T558
Test name
Test status
Simulation time 295544159 ps
CPU time 3.64 seconds
Started Jul 01 11:00:36 AM PDT 24
Finished Jul 01 11:00:40 AM PDT 24
Peak memory 206856 kb
Host smart-fffc9c62-ec17-4c2b-84e6-173f2834d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024132522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3024132522
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4182772468
Short name T651
Test name
Test status
Simulation time 6024859445 ps
CPU time 144.84 seconds
Started Jul 01 11:00:52 AM PDT 24
Finished Jul 01 11:03:17 AM PDT 24
Peak memory 222428 kb
Host smart-b95ddb99-832c-41cf-bd40-91a66dc9d5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182772468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4182772468
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4129635941
Short name T748
Test name
Test status
Simulation time 154999772 ps
CPU time 1.93 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 208116 kb
Host smart-a1e9f365-8a33-4975-bf7f-fda480043b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129635941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4129635941
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2929078339
Short name T515
Test name
Test status
Simulation time 1035872063 ps
CPU time 7.22 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:49 AM PDT 24
Peak memory 211024 kb
Host smart-13aa5a3e-2a5a-43b2-9a90-4643ed82cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929078339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2929078339
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.957536639
Short name T634
Test name
Test status
Simulation time 15790755 ps
CPU time 0.83 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 206052 kb
Host smart-8c564e44-00d7-48e6-b6ea-3b264104873a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957536639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.957536639
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4230849504
Short name T302
Test name
Test status
Simulation time 39874422 ps
CPU time 2.32 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 209308 kb
Host smart-10a22139-ad68-4828-881d-fcd60699ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230849504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4230849504
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3286239576
Short name T341
Test name
Test status
Simulation time 118013256 ps
CPU time 2.61 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 214324 kb
Host smart-abf1a575-ab35-48fb-9fe2-d926e5b7c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286239576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3286239576
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3693356769
Short name T326
Test name
Test status
Simulation time 131112633 ps
CPU time 2.46 seconds
Started Jul 01 11:00:44 AM PDT 24
Finished Jul 01 11:00:46 AM PDT 24
Peak memory 214268 kb
Host smart-ff1ca352-2359-4c0c-8743-8b983ba2e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693356769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3693356769
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1233007041
Short name T76
Test name
Test status
Simulation time 284446976 ps
CPU time 4.76 seconds
Started Jul 01 11:00:42 AM PDT 24
Finished Jul 01 11:00:47 AM PDT 24
Peak memory 214408 kb
Host smart-b5680e31-b4ac-486f-b162-75076e8b1a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233007041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1233007041
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.47296792
Short name T734
Test name
Test status
Simulation time 528886884 ps
CPU time 5.41 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 207068 kb
Host smart-f60be2e8-c1fc-4c5c-b38d-d1fd71a1d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47296792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.47296792
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2760554633
Short name T450
Test name
Test status
Simulation time 123974721 ps
CPU time 4.68 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 208516 kb
Host smart-2afaff09-132d-423f-8944-1d778d4e7a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760554633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2760554633
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4171035174
Short name T701
Test name
Test status
Simulation time 2127063910 ps
CPU time 32.73 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:35 AM PDT 24
Peak memory 208424 kb
Host smart-89d8eccb-8ba6-4271-a713-9513bf2ff0e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171035174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4171035174
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.217252027
Short name T872
Test name
Test status
Simulation time 60539076 ps
CPU time 3.26 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:45 AM PDT 24
Peak memory 208772 kb
Host smart-2847e4b4-94d8-4178-867a-20d7d22af906
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217252027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.217252027
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2479921365
Short name T614
Test name
Test status
Simulation time 1257443373 ps
CPU time 10.41 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:21 AM PDT 24
Peak memory 207880 kb
Host smart-4909de4e-1336-4e9a-ae0e-61aada0cae34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479921365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2479921365
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2166138337
Short name T268
Test name
Test status
Simulation time 301634158 ps
CPU time 3.81 seconds
Started Jul 01 11:01:04 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 209816 kb
Host smart-d17cc924-4716-4b28-9a68-6fc5a2688d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166138337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2166138337
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.907139816
Short name T522
Test name
Test status
Simulation time 10937989474 ps
CPU time 30.66 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 208640 kb
Host smart-4dc6dd49-c2e3-4662-a58f-71df1567c065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907139816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.907139816
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4122405359
Short name T561
Test name
Test status
Simulation time 403844962 ps
CPU time 15.39 seconds
Started Jul 01 11:00:42 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 222400 kb
Host smart-84042046-1faf-422f-94d3-03a75db4892f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122405359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4122405359
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1260001257
Short name T279
Test name
Test status
Simulation time 1075201521 ps
CPU time 18.82 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 222624 kb
Host smart-5c3e24b9-c363-4f2d-abca-d2bc6baa655f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260001257 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1260001257
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2780484637
Short name T661
Test name
Test status
Simulation time 315308252 ps
CPU time 3.49 seconds
Started Jul 01 11:00:39 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 218396 kb
Host smart-0eee2774-bfd7-493b-b87b-003650fa9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780484637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2780484637
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.45951262
Short name T164
Test name
Test status
Simulation time 378871000 ps
CPU time 7.06 seconds
Started Jul 01 11:00:41 AM PDT 24
Finished Jul 01 11:00:49 AM PDT 24
Peak memory 210036 kb
Host smart-72a1da3f-d0b5-45f3-9fea-adb79574b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45951262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.45951262
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2323956072
Short name T12
Test name
Test status
Simulation time 17669248 ps
CPU time 0.73 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 206064 kb
Host smart-4032a5b7-3544-4c56-b8db-f973ced3c4d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323956072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2323956072
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1536639865
Short name T366
Test name
Test status
Simulation time 42150726 ps
CPU time 3.12 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 214192 kb
Host smart-bfc05102-381d-4e43-b787-648161d392e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536639865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1536639865
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1798734696
Short name T231
Test name
Test status
Simulation time 882674339 ps
CPU time 3.72 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 208480 kb
Host smart-fbdb9dcd-bef4-4ab2-a2b3-ec86e6d1f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798734696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1798734696
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2998048433
Short name T399
Test name
Test status
Simulation time 293298382 ps
CPU time 2.86 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 207040 kb
Host smart-b3786e71-69a9-4127-b02a-241c5877fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998048433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2998048433
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.945832084
Short name T504
Test name
Test status
Simulation time 667176897 ps
CPU time 4.7 seconds
Started Jul 01 11:01:05 AM PDT 24
Finished Jul 01 11:01:18 AM PDT 24
Peak memory 210204 kb
Host smart-2b80ca00-0186-4e26-8ad4-5f18a369a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945832084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.945832084
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3471951403
Short name T791
Test name
Test status
Simulation time 1069473383 ps
CPU time 4.44 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:00 AM PDT 24
Peak memory 214192 kb
Host smart-d08cbdfe-be06-4ff7-88ad-b9a172837a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471951403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3471951403
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3777499425
Short name T318
Test name
Test status
Simulation time 47176573 ps
CPU time 2.52 seconds
Started Jul 01 11:00:40 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 206888 kb
Host smart-39c6b6a1-15c2-4699-9300-1457c1c41adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777499425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3777499425
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2911371786
Short name T884
Test name
Test status
Simulation time 226908728 ps
CPU time 2.88 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 207876 kb
Host smart-cbbb5b65-a92a-471f-9ae4-19f5e2fc62ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911371786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2911371786
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3616439584
Short name T859
Test name
Test status
Simulation time 316030902 ps
CPU time 3.41 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 208852 kb
Host smart-cb4288aa-dbca-4b0b-95be-c9b4fe7d8603
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616439584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3616439584
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3009106621
Short name T445
Test name
Test status
Simulation time 84041275 ps
CPU time 2.41 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 206812 kb
Host smart-3e8b2ebd-f74a-44a6-87ef-3186a5cfbbcc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009106621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3009106621
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.419727114
Short name T398
Test name
Test status
Simulation time 138705742 ps
CPU time 5.36 seconds
Started Jul 01 11:00:50 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 215952 kb
Host smart-28efcdd9-a766-4c20-9c6d-3f87264d13e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419727114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.419727114
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.374722081
Short name T482
Test name
Test status
Simulation time 892174089 ps
CPU time 4.08 seconds
Started Jul 01 11:00:40 AM PDT 24
Finished Jul 01 11:00:45 AM PDT 24
Peak memory 207872 kb
Host smart-278a5896-3f28-4eaa-b195-258df4ab941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374722081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.374722081
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.367201450
Short name T555
Test name
Test status
Simulation time 145674468 ps
CPU time 6.52 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 215212 kb
Host smart-37539d60-6db0-49a7-b32d-f7e919c6a547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367201450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.367201450
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3557865788
Short name T898
Test name
Test status
Simulation time 4086819307 ps
CPU time 22.3 seconds
Started Jul 01 11:00:47 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 222648 kb
Host smart-cbe6f40d-3fa2-463f-ac52-2a58dfc7df27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557865788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3557865788
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1801851637
Short name T774
Test name
Test status
Simulation time 749834212 ps
CPU time 4.5 seconds
Started Jul 01 11:00:45 AM PDT 24
Finished Jul 01 11:00:50 AM PDT 24
Peak memory 209936 kb
Host smart-b1e0f2bc-17bb-48bb-b18f-dfc70d9b215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801851637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1801851637
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1368673443
Short name T852
Test name
Test status
Simulation time 176273533 ps
CPU time 4 seconds
Started Jul 01 11:00:44 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 210460 kb
Host smart-156312b9-8c58-47c7-9780-9da009cda211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368673443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1368673443
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1279734290
Short name T710
Test name
Test status
Simulation time 185767838 ps
CPU time 0.76 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 206012 kb
Host smart-38ebd133-256e-4724-af44-a7e69618a4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279734290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1279734290
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3948878577
Short name T292
Test name
Test status
Simulation time 309919109 ps
CPU time 3.84 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 214328 kb
Host smart-8634c5c3-6465-4466-af1e-6b83e654afdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948878577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3948878577
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1616198445
Short name T489
Test name
Test status
Simulation time 416418800 ps
CPU time 2.28 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 207424 kb
Host smart-835d1a51-5a63-4a20-bcd5-5f4aae109bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616198445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1616198445
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3363240478
Short name T87
Test name
Test status
Simulation time 190660919 ps
CPU time 6.77 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 209300 kb
Host smart-c2185f8e-2049-412f-b7b3-0bb5aa8964cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363240478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3363240478
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2257825982
Short name T47
Test name
Test status
Simulation time 34088931 ps
CPU time 2.22 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 214188 kb
Host smart-8cd06191-be58-4a44-abb6-eee691a52760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257825982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2257825982
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3176723252
Short name T394
Test name
Test status
Simulation time 214530238 ps
CPU time 2.87 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 220476 kb
Host smart-e1c14706-1ac4-4652-b410-e421dcccae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176723252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3176723252
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.299173808
Short name T1
Test name
Test status
Simulation time 144443837 ps
CPU time 2.75 seconds
Started Jul 01 10:59:15 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 207628 kb
Host smart-36a89d59-e870-45c6-b980-95dca41cdd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299173808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.299173808
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2678569087
Short name T669
Test name
Test status
Simulation time 82685543 ps
CPU time 1.71 seconds
Started Jul 01 10:59:09 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 206836 kb
Host smart-dc00e01b-2d86-4b8b-9ea4-858556483ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678569087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2678569087
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.622596758
Short name T629
Test name
Test status
Simulation time 76535410 ps
CPU time 1.77 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 206912 kb
Host smart-c814731e-ecdd-41d2-bb23-a4b8841d214b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622596758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.622596758
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.757779028
Short name T346
Test name
Test status
Simulation time 35295764 ps
CPU time 2.55 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 208616 kb
Host smart-e7fea598-2762-4879-90d8-f0a99466ab70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757779028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.757779028
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2827369847
Short name T72
Test name
Test status
Simulation time 80042141 ps
CPU time 2.5 seconds
Started Jul 01 10:59:05 AM PDT 24
Finished Jul 01 10:59:08 AM PDT 24
Peak memory 206816 kb
Host smart-952803c4-3df2-444e-9acb-c6858b58064d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827369847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2827369847
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.362273018
Short name T920
Test name
Test status
Simulation time 378597345 ps
CPU time 3.71 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 209536 kb
Host smart-b751691c-28f7-428f-840b-0bc362a030b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362273018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.362273018
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3821642822
Short name T429
Test name
Test status
Simulation time 3647256911 ps
CPU time 16.35 seconds
Started Jul 01 10:59:15 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 208740 kb
Host smart-c4a6562b-7917-4c12-a8c8-6acb44f7f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821642822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3821642822
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.420610622
Short name T51
Test name
Test status
Simulation time 15065336619 ps
CPU time 248.17 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 11:03:32 AM PDT 24
Peak memory 219040 kb
Host smart-3bdd18f6-6bd5-4b6e-9ec7-615b128a8ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420610622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.420610622
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1587277386
Short name T656
Test name
Test status
Simulation time 666571825 ps
CPU time 27.84 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 222556 kb
Host smart-01a04707-0c12-4565-b72d-efa803109647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587277386 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1587277386
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1969624240
Short name T692
Test name
Test status
Simulation time 140635995 ps
CPU time 5.01 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 207448 kb
Host smart-8631c458-851c-47e7-a14b-83c76173f447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969624240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1969624240
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.407622357
Short name T188
Test name
Test status
Simulation time 115614818 ps
CPU time 2.63 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 210268 kb
Host smart-6ccdcd2e-c8f3-4847-819b-b069ac3093df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407622357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.407622357
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3085124389
Short name T604
Test name
Test status
Simulation time 76016646 ps
CPU time 0.75 seconds
Started Jul 01 11:00:47 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 206064 kb
Host smart-6287d2c7-267a-48b1-935a-fce58ba6b152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085124389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3085124389
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3271023790
Short name T215
Test name
Test status
Simulation time 205891580 ps
CPU time 4.55 seconds
Started Jul 01 11:00:46 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 214252 kb
Host smart-5aa6e4a3-d134-49d8-b379-75467345532d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271023790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3271023790
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.47972779
Short name T223
Test name
Test status
Simulation time 149458200 ps
CPU time 3.72 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 214440 kb
Host smart-8974ca60-185e-46c9-9c03-f24293476dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47972779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.47972779
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1418390643
Short name T702
Test name
Test status
Simulation time 171399215 ps
CPU time 4.24 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 221156 kb
Host smart-a072b1eb-2564-485a-97e4-a7aaa095fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418390643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1418390643
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.278606719
Short name T265
Test name
Test status
Simulation time 29921206 ps
CPU time 2.18 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 214312 kb
Host smart-a3efaa86-7fd4-4266-bfa0-6cf51ed4f4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278606719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.278606719
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_random.3777700110
Short name T283
Test name
Test status
Simulation time 68092887 ps
CPU time 3.54 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 210432 kb
Host smart-12ef589f-e984-4209-8bca-51addda616df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777700110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3777700110
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3759443286
Short name T518
Test name
Test status
Simulation time 170589665 ps
CPU time 2.66 seconds
Started Jul 01 11:00:50 AM PDT 24
Finished Jul 01 11:00:53 AM PDT 24
Peak memory 206924 kb
Host smart-f01f77f4-9e87-44be-a675-04bf4698b1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759443286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3759443286
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.470622467
Short name T707
Test name
Test status
Simulation time 801985888 ps
CPU time 2.5 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 208324 kb
Host smart-b26dfd36-3536-420b-b558-b25d6511ecf4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470622467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.470622467
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2102566832
Short name T192
Test name
Test status
Simulation time 177640493 ps
CPU time 5.09 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 208404 kb
Host smart-e80972ab-98d7-441f-adbd-6cc76b624e92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102566832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2102566832
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.943063341
Short name T679
Test name
Test status
Simulation time 505215178 ps
CPU time 4.2 seconds
Started Jul 01 11:00:47 AM PDT 24
Finished Jul 01 11:00:52 AM PDT 24
Peak memory 207332 kb
Host smart-846ac765-e466-4cea-af51-0ba6078ebe9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943063341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.943063341
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3270653182
Short name T846
Test name
Test status
Simulation time 207541907 ps
CPU time 4.2 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 214316 kb
Host smart-06fde9fa-b54e-44ae-a436-6998960c2f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270653182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3270653182
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1429541615
Short name T780
Test name
Test status
Simulation time 124667188 ps
CPU time 3.53 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 206924 kb
Host smart-ac8a9434-d6e6-41a3-98e6-1edddfd5cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429541615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1429541615
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2023549001
Short name T761
Test name
Test status
Simulation time 225308354 ps
CPU time 6.22 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 215688 kb
Host smart-99f47a6b-a005-4ad1-bb1b-4946170a1245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023549001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2023549001
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2630125640
Short name T50
Test name
Test status
Simulation time 274687040 ps
CPU time 10.34 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 222628 kb
Host smart-fb8f8cb2-1ff2-4a73-bdb6-371817b57561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630125640 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2630125640
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.164902599
Short name T252
Test name
Test status
Simulation time 596995169 ps
CPU time 8.41 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214304 kb
Host smart-ffa21973-f65d-47f7-95f8-219b7ad29dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164902599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.164902599
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3475761011
Short name T186
Test name
Test status
Simulation time 60720701 ps
CPU time 1.76 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:04 AM PDT 24
Peak memory 210012 kb
Host smart-68e79e5c-cf29-491c-8a5b-a150536b60d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475761011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3475761011
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2220535414
Short name T811
Test name
Test status
Simulation time 17067445 ps
CPU time 0.8 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 205968 kb
Host smart-a2f8053c-0eef-4485-a85f-aa8d1492d140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220535414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2220535414
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.625840476
Short name T121
Test name
Test status
Simulation time 152415669 ps
CPU time 3.22 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 214344 kb
Host smart-276968c1-7dda-47c0-aaf4-151f5a0a109e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625840476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.625840476
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2078774697
Short name T855
Test name
Test status
Simulation time 69495741 ps
CPU time 2.48 seconds
Started Jul 01 11:00:53 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 207572 kb
Host smart-80f29dae-652f-4b7e-b501-05528bc1b719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078774697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2078774697
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.45503070
Short name T794
Test name
Test status
Simulation time 163902762 ps
CPU time 2.55 seconds
Started Jul 01 11:01:19 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 214344 kb
Host smart-3c6ab859-7182-4dd1-8942-bcfd4c068187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45503070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.45503070
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.417565774
Short name T336
Test name
Test status
Simulation time 182968012 ps
CPU time 2.9 seconds
Started Jul 01 11:00:49 AM PDT 24
Finished Jul 01 11:00:53 AM PDT 24
Peak memory 220740 kb
Host smart-51ee25c8-c5cc-43ac-805f-ea69b49d73db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417565774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.417565774
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.473528580
Short name T274
Test name
Test status
Simulation time 257209271 ps
CPU time 3.53 seconds
Started Jul 01 11:00:52 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 209672 kb
Host smart-c432915d-681f-4313-9bf0-7d7007d138b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473528580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.473528580
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.75861357
Short name T327
Test name
Test status
Simulation time 346038705 ps
CPU time 3.52 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214260 kb
Host smart-1a7a01aa-6e97-492d-9855-f6cafdbffe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75861357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.75861357
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.431132330
Short name T527
Test name
Test status
Simulation time 426903330 ps
CPU time 1.95 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:06 AM PDT 24
Peak memory 208664 kb
Host smart-768f5337-6e20-4e3e-a04c-d90db97176fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431132330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.431132330
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1180723970
Short name T583
Test name
Test status
Simulation time 154944326 ps
CPU time 4.26 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 206676 kb
Host smart-113ee583-1ea5-4567-acdd-50d3b5b6c411
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180723970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1180723970
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1702145183
Short name T191
Test name
Test status
Simulation time 157140070 ps
CPU time 4.09 seconds
Started Jul 01 11:00:52 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 207016 kb
Host smart-28e0d4e7-0487-459b-8645-3ded9b776c83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702145183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1702145183
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3403900825
Short name T815
Test name
Test status
Simulation time 130258606 ps
CPU time 2.82 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 206940 kb
Host smart-10f0ed04-bb2c-43ea-849b-6eee5d8e6230
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403900825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3403900825
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1604197142
Short name T189
Test name
Test status
Simulation time 367535974 ps
CPU time 1.93 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 214168 kb
Host smart-bec77b19-3440-437c-a7f5-1230865d2598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604197142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1604197142
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.376269505
Short name T750
Test name
Test status
Simulation time 192276611 ps
CPU time 3.64 seconds
Started Jul 01 11:01:05 AM PDT 24
Finished Jul 01 11:01:13 AM PDT 24
Peak memory 208580 kb
Host smart-f5da210a-4ffe-4c0a-a4e2-d21e252aff75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376269505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.376269505
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2876947307
Short name T344
Test name
Test status
Simulation time 865853227 ps
CPU time 13.33 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 222640 kb
Host smart-f672720a-4355-496a-9453-4c822be6da83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876947307 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2876947307
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2706287534
Short name T2
Test name
Test status
Simulation time 85134360 ps
CPU time 3.64 seconds
Started Jul 01 11:00:50 AM PDT 24
Finished Jul 01 11:00:54 AM PDT 24
Peak memory 209520 kb
Host smart-f9499a97-ad3f-4008-aac6-f2d8acbf9399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706287534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2706287534
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1380531568
Short name T615
Test name
Test status
Simulation time 657811654 ps
CPU time 4.31 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 211096 kb
Host smart-2cd72378-3ad1-41f2-b9d2-435c8227eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380531568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1380531568
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2714612454
Short name T753
Test name
Test status
Simulation time 12208849 ps
CPU time 0.75 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:04 AM PDT 24
Peak memory 206044 kb
Host smart-9071fdec-e634-400d-b19e-f8f751ebdd1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714612454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2714612454
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2815663253
Short name T367
Test name
Test status
Simulation time 474388554 ps
CPU time 2.66 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 214344 kb
Host smart-3dbe2a33-6843-4934-b266-97b88e0ee24c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815663253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2815663253
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1767972868
Short name T808
Test name
Test status
Simulation time 116768878 ps
CPU time 5.26 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 209176 kb
Host smart-5983d1c6-d947-4498-adc1-838c94dddf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767972868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1767972868
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3804836069
Short name T841
Test name
Test status
Simulation time 42116466 ps
CPU time 2.09 seconds
Started Jul 01 11:00:54 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 208924 kb
Host smart-98288a1b-cefa-4ef8-aa29-f79f64d44622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804836069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3804836069
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4073640343
Short name T742
Test name
Test status
Simulation time 792580254 ps
CPU time 6.37 seconds
Started Jul 01 11:00:51 AM PDT 24
Finished Jul 01 11:00:58 AM PDT 24
Peak memory 209336 kb
Host smart-9944b4b7-01db-4533-b2ce-1a508afb8ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073640343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4073640343
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2436332435
Short name T576
Test name
Test status
Simulation time 55625568 ps
CPU time 3 seconds
Started Jul 01 11:00:52 AM PDT 24
Finished Jul 01 11:00:55 AM PDT 24
Peak memory 214268 kb
Host smart-a0b8e988-82aa-424a-8d52-2156e861c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436332435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2436332435
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.631334185
Short name T126
Test name
Test status
Simulation time 1567456846 ps
CPU time 3.5 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 214368 kb
Host smart-4590c779-69c0-4de9-96cb-920fb7b0db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631334185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.631334185
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3888787527
Short name T352
Test name
Test status
Simulation time 782998647 ps
CPU time 16.13 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 208672 kb
Host smart-2720c484-3b85-492e-b32e-b29dff451644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888787527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3888787527
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1575206740
Short name T539
Test name
Test status
Simulation time 1043181406 ps
CPU time 24.18 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:29 AM PDT 24
Peak memory 208028 kb
Host smart-1b38c292-ac98-4828-862c-7a069137acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575206740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1575206740
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2058004853
Short name T465
Test name
Test status
Simulation time 198054565 ps
CPU time 2.8 seconds
Started Jul 01 11:00:51 AM PDT 24
Finished Jul 01 11:00:55 AM PDT 24
Peak memory 206948 kb
Host smart-f2f46b77-cf56-4706-bb21-c518401885b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058004853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2058004853
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1101895067
Short name T570
Test name
Test status
Simulation time 88819509 ps
CPU time 3.95 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 208868 kb
Host smart-cd4649a5-bd83-408e-8912-5ef9f2073e23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101895067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1101895067
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3327549434
Short name T854
Test name
Test status
Simulation time 446112091 ps
CPU time 5.18 seconds
Started Jul 01 11:00:51 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 208764 kb
Host smart-4ebdd93a-a8d6-4910-ae57-07274e98dfe4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327549434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3327549434
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2187783886
Short name T533
Test name
Test status
Simulation time 470606263 ps
CPU time 3.08 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 208996 kb
Host smart-0b4c315a-bf2a-44b4-9140-a2f90ee4f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187783886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2187783886
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3357704234
Short name T417
Test name
Test status
Simulation time 275377408 ps
CPU time 5.84 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:04 AM PDT 24
Peak memory 208440 kb
Host smart-8bbe9551-61bf-46bb-b87a-2a3091c3c497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357704234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3357704234
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3205159763
Short name T899
Test name
Test status
Simulation time 12199092501 ps
CPU time 138.7 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:03:14 AM PDT 24
Peak memory 219808 kb
Host smart-bc3924c7-88b6-4d51-a547-15a0b93d582e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205159763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3205159763
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.467424672
Short name T320
Test name
Test status
Simulation time 795901114 ps
CPU time 12.31 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 222564 kb
Host smart-511d4f19-f760-4622-b300-2c854d15dbf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467424672 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.467424672
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2866313549
Short name T255
Test name
Test status
Simulation time 426944590 ps
CPU time 6.46 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 209212 kb
Host smart-88b35aa3-6c01-4141-a3a4-bded592d5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866313549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2866313549
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3291245377
Short name T655
Test name
Test status
Simulation time 48753399 ps
CPU time 0.75 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 206060 kb
Host smart-f06478d0-da01-4c07-b72b-7474c080bcce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291245377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3291245377
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.514617935
Short name T389
Test name
Test status
Simulation time 165892235 ps
CPU time 8.59 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 214840 kb
Host smart-30e5802e-59f3-4440-98cd-954e24d7b29c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514617935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.514617935
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2778380020
Short name T738
Test name
Test status
Simulation time 84542326 ps
CPU time 3.16 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214728 kb
Host smart-73be80a5-47f1-4b0f-bfc0-58b23e3b66df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778380020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2778380020
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.866237927
Short name T357
Test name
Test status
Simulation time 48185537 ps
CPU time 3.09 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 218348 kb
Host smart-547d972c-18d3-447a-95c8-87fafda69a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866237927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.866237927
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4052355347
Short name T311
Test name
Test status
Simulation time 1114774465 ps
CPU time 2.77 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 222452 kb
Host smart-9169aba7-6f80-487b-8532-7963df151db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052355347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4052355347
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1331158907
Short name T589
Test name
Test status
Simulation time 232634012 ps
CPU time 2.85 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 220020 kb
Host smart-1ec553a1-3427-4fc9-ac7a-706ef67a397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331158907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1331158907
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3421325973
Short name T867
Test name
Test status
Simulation time 75292952 ps
CPU time 3.81 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:06 AM PDT 24
Peak memory 207276 kb
Host smart-2e09cad1-eb18-4228-b590-7b033c97dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421325973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3421325973
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4065615842
Short name T769
Test name
Test status
Simulation time 108466203 ps
CPU time 2.43 seconds
Started Jul 01 11:00:53 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 207212 kb
Host smart-7654148c-e241-44e5-9d4d-21c30fb303ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065615842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4065615842
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1029240248
Short name T519
Test name
Test status
Simulation time 67676915 ps
CPU time 2.3 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:13 AM PDT 24
Peak memory 206904 kb
Host smart-cee1dd22-46e7-4d2a-94f9-845e85becd56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029240248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1029240248
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1308340155
Short name T891
Test name
Test status
Simulation time 84948010 ps
CPU time 1.91 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 207412 kb
Host smart-cc8480d4-798d-445b-84ce-5b2df159efb1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308340155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1308340155
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4001912013
Short name T770
Test name
Test status
Simulation time 35624036 ps
CPU time 2.52 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 206928 kb
Host smart-be3341d5-e099-4513-9ada-3ded4d0c1c64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001912013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4001912013
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1348591261
Short name T451
Test name
Test status
Simulation time 53076569 ps
CPU time 2.18 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 207004 kb
Host smart-9f2d1647-0dc0-4794-b8ac-c0f68af1ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348591261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1348591261
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1908529147
Short name T744
Test name
Test status
Simulation time 114369620 ps
CPU time 2.23 seconds
Started Jul 01 11:00:51 AM PDT 24
Finished Jul 01 11:00:54 AM PDT 24
Peak memory 208520 kb
Host smart-c06e6fe0-cf44-4fc5-a7ad-81904c79d6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908529147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1908529147
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.357893975
Short name T856
Test name
Test status
Simulation time 201610147 ps
CPU time 7.97 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:07 AM PDT 24
Peak memory 218292 kb
Host smart-89ca908b-9b18-465b-869d-78243de8ab9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357893975 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.357893975
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.822461242
Short name T378
Test name
Test status
Simulation time 684639151 ps
CPU time 10.26 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 222496 kb
Host smart-fcd06343-552f-483f-80ad-becf8d5bb881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822461242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.822461242
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3899669203
Short name T858
Test name
Test status
Simulation time 340232905 ps
CPU time 2.09 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 210032 kb
Host smart-4fe096ad-9209-4386-a587-e919ffe56cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899669203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3899669203
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1525316478
Short name T432
Test name
Test status
Simulation time 54635865 ps
CPU time 0.78 seconds
Started Jul 01 11:00:56 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 206032 kb
Host smart-530ac857-9c0d-402a-a71f-4a89bd7ce027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525316478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1525316478
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3718787552
Short name T406
Test name
Test status
Simulation time 200962195 ps
CPU time 4.43 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 222512 kb
Host smart-f75955c8-ae2b-430d-9faa-f6143016e781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718787552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3718787552
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3981207637
Short name T889
Test name
Test status
Simulation time 161396735 ps
CPU time 5.23 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 210584 kb
Host smart-db892f3e-92e3-4fa1-9486-ca3fe4d1b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981207637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3981207637
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.878844443
Short name T588
Test name
Test status
Simulation time 470183829 ps
CPU time 5.75 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 208512 kb
Host smart-4bc0e58e-7f23-4759-b4cb-f496e44f184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878844443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.878844443
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3358115299
Short name T90
Test name
Test status
Simulation time 1152882211 ps
CPU time 35.5 seconds
Started Jul 01 11:01:00 AM PDT 24
Finished Jul 01 11:01:39 AM PDT 24
Peak memory 214308 kb
Host smart-da6513df-6d52-48e9-be45-b4b5b84eddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358115299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3358115299
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2574582369
Short name T372
Test name
Test status
Simulation time 172312127 ps
CPU time 2.54 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214324 kb
Host smart-b57d03de-2096-440a-9e8a-789b04620da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574582369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2574582369
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1976589104
Short name T74
Test name
Test status
Simulation time 354663383 ps
CPU time 9.39 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 218428 kb
Host smart-defa2c8c-586e-4564-b004-06e97ca58026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976589104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1976589104
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2096226988
Short name T190
Test name
Test status
Simulation time 168268528 ps
CPU time 4.2 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 208700 kb
Host smart-23058078-d783-450f-9396-b2fec29aec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096226988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2096226988
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.444039134
Short name T830
Test name
Test status
Simulation time 292489970 ps
CPU time 4.01 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 208692 kb
Host smart-13a6a8f7-b3df-4960-a92c-2f65646e5052
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444039134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.444039134
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4145073109
Short name T755
Test name
Test status
Simulation time 1784754595 ps
CPU time 34.45 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 208660 kb
Host smart-a242a592-a1d3-4744-8669-3d378fd1dc94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145073109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4145073109
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3584273950
Short name T592
Test name
Test status
Simulation time 194323972 ps
CPU time 6.72 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:19 AM PDT 24
Peak memory 208536 kb
Host smart-8dda4908-0aea-4aa9-b15f-29269d9857b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584273950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3584273950
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.542206950
Short name T437
Test name
Test status
Simulation time 574774549 ps
CPU time 5.06 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 208796 kb
Host smart-3a089716-8c6e-4455-a9ee-09c7667a99b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542206950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.542206950
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.221344992
Short name T674
Test name
Test status
Simulation time 5094117814 ps
CPU time 26.63 seconds
Started Jul 01 11:01:36 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 208036 kb
Host smart-0eaa5924-f9df-43e8-8225-25c5c6e6f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221344992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.221344992
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3484623097
Short name T112
Test name
Test status
Simulation time 1100843288 ps
CPU time 18.4 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:25 AM PDT 24
Peak memory 222616 kb
Host smart-a44fe126-64f0-40d5-9988-f1878aa91697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484623097 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3484623097
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.381980940
Short name T820
Test name
Test status
Simulation time 246793827 ps
CPU time 4.74 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 209956 kb
Host smart-e11a37f4-45b6-40ca-b2ce-5b7394c63aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381980940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.381980940
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4146684798
Short name T827
Test name
Test status
Simulation time 253950211 ps
CPU time 3.23 seconds
Started Jul 01 11:00:55 AM PDT 24
Finished Jul 01 11:00:59 AM PDT 24
Peak memory 210336 kb
Host smart-59135376-f951-4a8f-9fe5-a46716d8ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146684798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4146684798
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2752409915
Short name T463
Test name
Test status
Simulation time 16223977 ps
CPU time 0.74 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:06 AM PDT 24
Peak memory 206076 kb
Host smart-5a66be8e-91e2-43da-a6b6-9b6e5b2a219f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752409915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2752409915
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.934659444
Short name T396
Test name
Test status
Simulation time 198085517 ps
CPU time 3.68 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 214284 kb
Host smart-aeddb926-948e-49b7-a2f7-6126a065bf97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934659444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.934659444
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.306975251
Short name T60
Test name
Test status
Simulation time 79970327 ps
CPU time 4.37 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 222872 kb
Host smart-8f7d328a-2b1f-4f57-82d7-8b7a1fa5ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306975251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.306975251
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3655500166
Short name T719
Test name
Test status
Simulation time 29167989 ps
CPU time 1.36 seconds
Started Jul 01 11:00:57 AM PDT 24
Finished Jul 01 11:01:01 AM PDT 24
Peak memory 207148 kb
Host smart-398dac95-f242-48cd-8483-9227fb4e73f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655500166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3655500166
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4134912284
Short name T537
Test name
Test status
Simulation time 105027711 ps
CPU time 2.84 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214472 kb
Host smart-c3566ab6-be30-468b-a56a-3167286bd2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134912284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4134912284
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3262349116
Short name T666
Test name
Test status
Simulation time 384347810 ps
CPU time 2.9 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:05 AM PDT 24
Peak memory 214336 kb
Host smart-eb3cd1d5-dffd-4aa9-8a3c-280261f8a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262349116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3262349116
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.3496095782
Short name T660
Test name
Test status
Simulation time 240553531 ps
CPU time 6.04 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:13 AM PDT 24
Peak memory 207492 kb
Host smart-9cc581c0-8e42-4c00-bc8f-5ade9be16d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496095782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3496095782
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.798244067
Short name T415
Test name
Test status
Simulation time 623896565 ps
CPU time 4.5 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 207116 kb
Host smart-6aead2cd-4f0a-42e9-8fb9-9ef8d1f9b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798244067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.798244067
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1385904593
Short name T684
Test name
Test status
Simulation time 260370547 ps
CPU time 3.52 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 208740 kb
Host smart-8fae5019-ad7a-4132-9b7e-53324b2174e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385904593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1385904593
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3958937366
Short name T472
Test name
Test status
Simulation time 106664149 ps
CPU time 4.18 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 206728 kb
Host smart-77b677f2-2835-4c5e-be59-b435489a736a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958937366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3958937366
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2221145165
Short name T290
Test name
Test status
Simulation time 6862725468 ps
CPU time 38.41 seconds
Started Jul 01 11:01:19 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 208616 kb
Host smart-ac0c6f77-be9b-4ee5-bc7a-29d7205c2788
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221145165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2221145165
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3792139245
Short name T271
Test name
Test status
Simulation time 26530615 ps
CPU time 1.78 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 218160 kb
Host smart-86e6d543-3413-436c-9861-5739cca2a978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792139245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3792139245
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1721351218
Short name T495
Test name
Test status
Simulation time 763777796 ps
CPU time 6.65 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 208728 kb
Host smart-eb403d86-9100-49d8-ba06-73c583b197f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721351218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1721351218
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3138239110
Short name T115
Test name
Test status
Simulation time 748654323 ps
CPU time 17.29 seconds
Started Jul 01 11:01:41 AM PDT 24
Finished Jul 01 11:01:59 AM PDT 24
Peak memory 222632 kb
Host smart-205b15c2-3e17-4442-a3ae-c975a5e28247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138239110 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3138239110
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.642631105
Short name T278
Test name
Test status
Simulation time 79723946 ps
CPU time 4.05 seconds
Started Jul 01 11:01:20 AM PDT 24
Finished Jul 01 11:01:24 AM PDT 24
Peak memory 210064 kb
Host smart-da6ec6c5-d52a-4e8d-9b70-2d05f6290f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642631105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.642631105
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3164760353
Short name T39
Test name
Test status
Simulation time 330033975 ps
CPU time 2.48 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 209580 kb
Host smart-4c1061fd-d696-41b9-8a8b-a9e7bf02cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164760353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3164760353
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1304942735
Short name T826
Test name
Test status
Simulation time 14107065 ps
CPU time 0.9 seconds
Started Jul 01 11:01:13 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 206068 kb
Host smart-3cb24565-afca-422d-8972-2e0c5ca925d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304942735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1304942735
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3884620913
Short name T67
Test name
Test status
Simulation time 132644306 ps
CPU time 1.96 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 207568 kb
Host smart-dbd63d7f-5daf-4b2c-8a9c-667363be33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884620913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3884620913
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4274165230
Short name T696
Test name
Test status
Simulation time 293103298 ps
CPU time 3.59 seconds
Started Jul 01 11:00:59 AM PDT 24
Finished Jul 01 11:01:05 AM PDT 24
Peak memory 222516 kb
Host smart-97cb1b14-2a9a-4fe8-bf73-36f593373fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274165230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4274165230
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4054120653
Short name T665
Test name
Test status
Simulation time 1202208298 ps
CPU time 2.72 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 214304 kb
Host smart-551a16d5-83ad-4c64-b06c-bd801e51be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054120653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4054120653
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.696230264
Short name T625
Test name
Test status
Simulation time 480676241 ps
CPU time 2.21 seconds
Started Jul 01 11:01:19 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 214812 kb
Host smart-a5b158c4-7bab-49d2-8db7-a05e8e94bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696230264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.696230264
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1337051118
Short name T725
Test name
Test status
Simulation time 415600601 ps
CPU time 4.6 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 210024 kb
Host smart-f3d400d1-17a4-499f-ac55-4601cd4a6646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337051118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1337051118
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2000661876
Short name T259
Test name
Test status
Simulation time 2132991862 ps
CPU time 24.87 seconds
Started Jul 01 11:01:12 AM PDT 24
Finished Jul 01 11:01:39 AM PDT 24
Peak memory 207964 kb
Host smart-693f4e5d-b843-4c46-a519-26143b8545ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000661876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2000661876
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3466900670
Short name T851
Test name
Test status
Simulation time 66467678 ps
CPU time 3.26 seconds
Started Jul 01 11:01:20 AM PDT 24
Finished Jul 01 11:01:24 AM PDT 24
Peak memory 208836 kb
Host smart-e7e794e1-5675-4ba5-b713-6347224a3082
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466900670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3466900670
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.4250864753
Short name T480
Test name
Test status
Simulation time 130362363 ps
CPU time 2.29 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 207032 kb
Host smart-6c77080c-0832-449b-a062-8ef320207b05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250864753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.4250864753
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1539027933
Short name T528
Test name
Test status
Simulation time 128618761 ps
CPU time 3.82 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 208640 kb
Host smart-1083a009-d067-4538-9f6c-afd2113260b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539027933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1539027933
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1680281032
Short name T401
Test name
Test status
Simulation time 276004499 ps
CPU time 4.1 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 208212 kb
Host smart-0166960b-6518-407f-8d40-c6a8b208ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680281032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1680281032
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2811035837
Short name T117
Test name
Test status
Simulation time 2329251250 ps
CPU time 4.53 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 207040 kb
Host smart-cd90dbc8-d8d8-48d0-a8b8-1cc819f05ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811035837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2811035837
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3905988890
Short name T313
Test name
Test status
Simulation time 670747324 ps
CPU time 22.87 seconds
Started Jul 01 11:01:04 AM PDT 24
Finished Jul 01 11:01:31 AM PDT 24
Peak memory 216756 kb
Host smart-814ca9fe-4701-4ce3-a48c-367e7852a107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905988890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3905988890
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2057026636
Short name T321
Test name
Test status
Simulation time 612182599 ps
CPU time 9.59 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 222644 kb
Host smart-10d93be5-d671-46b8-abe1-a6b74f5ceb0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057026636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2057026636
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3105358782
Short name T812
Test name
Test status
Simulation time 3709988512 ps
CPU time 34.28 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:01:53 AM PDT 24
Peak memory 214072 kb
Host smart-57ff89f8-2aa9-4d72-a9c6-6371b162d650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105358782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3105358782
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3917390200
Short name T381
Test name
Test status
Simulation time 428964818 ps
CPU time 4.5 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 210700 kb
Host smart-31691ea1-0388-4905-8f00-e37c7ea6b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917390200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3917390200
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4047417910
Short name T460
Test name
Test status
Simulation time 35088005 ps
CPU time 0.79 seconds
Started Jul 01 11:01:27 AM PDT 24
Finished Jul 01 11:01:34 AM PDT 24
Peak memory 206008 kb
Host smart-57b224ae-e48f-4686-9108-3353dce3615b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047417910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4047417910
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4195287175
Short name T626
Test name
Test status
Simulation time 117380300 ps
CPU time 3.68 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 209064 kb
Host smart-072563c2-feb1-4e75-a4f0-b06de74b589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195287175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4195287175
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2123253371
Short name T71
Test name
Test status
Simulation time 125206617 ps
CPU time 2.18 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214340 kb
Host smart-90329f38-0afa-4948-a374-f775eac19c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123253371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2123253371
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1053842396
Short name T771
Test name
Test status
Simulation time 1136514164 ps
CPU time 3.59 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 220992 kb
Host smart-5f675523-c3cb-4cd0-b69b-ae47d5670c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053842396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1053842396
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1922386297
Short name T55
Test name
Test status
Simulation time 86900574 ps
CPU time 3.81 seconds
Started Jul 01 11:01:05 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 214304 kb
Host smart-832ddae2-15d4-48aa-b974-29fe6930e8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922386297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1922386297
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.812799893
Short name T757
Test name
Test status
Simulation time 97037380 ps
CPU time 2.74 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 214316 kb
Host smart-c36cf89f-3de5-4fa1-b9a2-e9656f8c26b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812799893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.812799893
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.865712992
Short name T400
Test name
Test status
Simulation time 954497706 ps
CPU time 28.68 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 220420 kb
Host smart-865ab890-6d4f-4049-9792-c43cbbec040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865712992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.865712992
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.222366623
Short name T677
Test name
Test status
Simulation time 230479642 ps
CPU time 2.42 seconds
Started Jul 01 11:00:58 AM PDT 24
Finished Jul 01 11:01:02 AM PDT 24
Peak memory 206896 kb
Host smart-6bfdd6ec-94ed-4c00-a710-6af4599097ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222366623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.222366623
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2393840517
Short name T697
Test name
Test status
Simulation time 359519649 ps
CPU time 2.86 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 206904 kb
Host smart-fdf9350a-a673-43db-a521-dc1531cd2ab3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393840517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2393840517
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1342422500
Short name T646
Test name
Test status
Simulation time 78637243 ps
CPU time 3.74 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 209492 kb
Host smart-0e7e13c2-90a0-4305-917c-307282ea82fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342422500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1342422500
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.840406920
Short name T678
Test name
Test status
Simulation time 73064999 ps
CPU time 1.9 seconds
Started Jul 01 11:01:09 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 206916 kb
Host smart-6688e687-aea2-428e-91ba-5a5fa7986cbc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840406920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.840406920
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1019980463
Short name T839
Test name
Test status
Simulation time 237866301 ps
CPU time 7.77 seconds
Started Jul 01 11:01:33 AM PDT 24
Finished Jul 01 11:01:41 AM PDT 24
Peak memory 214312 kb
Host smart-6a6b951b-6566-4177-9f10-ceeced63900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019980463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1019980463
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3655670788
Short name T832
Test name
Test status
Simulation time 617988158 ps
CPU time 4.58 seconds
Started Jul 01 11:01:05 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 206876 kb
Host smart-499f3909-19da-4568-81ed-9d8d9c8244ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655670788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3655670788
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1074545805
Short name T205
Test name
Test status
Simulation time 645249989 ps
CPU time 13.99 seconds
Started Jul 01 11:01:13 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 214336 kb
Host smart-e5241317-39ad-4772-9d68-daf06518a922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074545805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1074545805
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3121180391
Short name T613
Test name
Test status
Simulation time 1344916585 ps
CPU time 18.56 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:01:51 AM PDT 24
Peak memory 222560 kb
Host smart-c3c01b77-dcb0-4518-9632-126fc3d6f042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121180391 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3121180391
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4058909849
Short name T216
Test name
Test status
Simulation time 571259005 ps
CPU time 6.38 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:12 AM PDT 24
Peak memory 207824 kb
Host smart-54a5fb8f-7420-4eea-a455-36c64b00cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058909849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4058909849
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.76620083
Short name T363
Test name
Test status
Simulation time 175251121 ps
CPU time 2.66 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 210436 kb
Host smart-d1047846-c7db-49d1-bf4d-980f24e1f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76620083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.76620083
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3456756166
Short name T73
Test name
Test status
Simulation time 13604973 ps
CPU time 0.9 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:20 AM PDT 24
Peak memory 206164 kb
Host smart-94b5a599-e146-4bc7-ad8d-f9db0a296dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456756166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3456756166
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2149542128
Short name T402
Test name
Test status
Simulation time 200215851 ps
CPU time 10.62 seconds
Started Jul 01 11:01:10 AM PDT 24
Finished Jul 01 11:01:24 AM PDT 24
Peak memory 214296 kb
Host smart-d7729858-e2c0-45df-b8c4-4d977e952565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149542128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2149542128
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1436753587
Short name T637
Test name
Test status
Simulation time 781735660 ps
CPU time 2.23 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:01:20 AM PDT 24
Peak memory 209388 kb
Host smart-80023eeb-e464-4739-a87a-ca3bd7b49b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436753587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1436753587
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2189336104
Short name T616
Test name
Test status
Simulation time 73256938 ps
CPU time 1.82 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:01:21 AM PDT 24
Peak memory 208528 kb
Host smart-cacefa73-8a38-48c4-8bc1-e2b1d5d541af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189336104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2189336104
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3135474245
Short name T79
Test name
Test status
Simulation time 39514609 ps
CPU time 2.54 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 214448 kb
Host smart-ffd030a9-0ba7-4787-8965-fb0c5c3fb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135474245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3135474245
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2592811471
Short name T896
Test name
Test status
Simulation time 32745852 ps
CPU time 2.4 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 214260 kb
Host smart-58c1ff06-5c6c-4819-8737-20ad471279ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592811471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2592811471
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3699088342
Short name T196
Test name
Test status
Simulation time 61620296 ps
CPU time 4.06 seconds
Started Jul 01 11:01:12 AM PDT 24
Finished Jul 01 11:01:18 AM PDT 24
Peak memory 222524 kb
Host smart-cfd262ce-0fc9-4152-a925-6c0e235946be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699088342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3699088342
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.763467991
Short name T477
Test name
Test status
Simulation time 197529390 ps
CPU time 3.61 seconds
Started Jul 01 11:01:02 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 208364 kb
Host smart-184ac509-8011-4cae-8891-808d4ec49598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763467991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.763467991
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2561348157
Short name T911
Test name
Test status
Simulation time 165743396 ps
CPU time 3.69 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 206728 kb
Host smart-5b142a81-2a6a-4904-95cc-bb05e8f1a2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561348157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2561348157
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1307305343
Short name T449
Test name
Test status
Simulation time 57737956 ps
CPU time 2.22 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:31 AM PDT 24
Peak memory 206884 kb
Host smart-6d687457-76d6-4da7-81b6-ffc7456c252d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307305343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1307305343
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.421034569
Short name T632
Test name
Test status
Simulation time 175710529 ps
CPU time 2.6 seconds
Started Jul 01 11:01:14 AM PDT 24
Finished Jul 01 11:01:18 AM PDT 24
Peak memory 207012 kb
Host smart-c95f6219-2e4b-47ec-b933-2281c3f607ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421034569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.421034569
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4193991448
Short name T687
Test name
Test status
Simulation time 120983567 ps
CPU time 3.21 seconds
Started Jul 01 11:01:03 AM PDT 24
Finished Jul 01 11:01:10 AM PDT 24
Peak memory 208780 kb
Host smart-79b96699-dae8-4df5-b6d6-c506dc9e4236
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193991448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4193991448
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4044344438
Short name T596
Test name
Test status
Simulation time 64477114 ps
CPU time 3.34 seconds
Started Jul 01 11:01:29 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 209676 kb
Host smart-33ee4a99-3514-40d5-b4e8-5987820349d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044344438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4044344438
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2419447620
Short name T439
Test name
Test status
Simulation time 500487404 ps
CPU time 8.08 seconds
Started Jul 01 11:01:19 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 208508 kb
Host smart-c9c8ff13-efc6-42fc-b369-ca2c01988d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419447620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2419447620
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2189563603
Short name T355
Test name
Test status
Simulation time 146348699 ps
CPU time 8.13 seconds
Started Jul 01 11:01:14 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 217084 kb
Host smart-5de4b79a-d484-4620-8868-b4b07aaf629a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189563603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2189563603
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3924548356
Short name T256
Test name
Test status
Simulation time 300360433 ps
CPU time 6.28 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:19 AM PDT 24
Peak memory 209484 kb
Host smart-706daa3b-ae13-49d5-b0ea-c57a916467ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924548356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3924548356
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1194404448
Short name T373
Test name
Test status
Simulation time 997856901 ps
CPU time 1.98 seconds
Started Jul 01 11:01:01 AM PDT 24
Finished Jul 01 11:01:08 AM PDT 24
Peak memory 209864 kb
Host smart-f2f1b2b3-d9d8-48b5-91a7-d8103f021229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194404448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1194404448
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.307841728
Short name T668
Test name
Test status
Simulation time 9805371 ps
CPU time 0.74 seconds
Started Jul 01 11:01:09 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 206040 kb
Host smart-157c8111-2d95-49ea-b71f-a823cc3ce06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307841728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.307841728
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.960571515
Short name T330
Test name
Test status
Simulation time 329147179 ps
CPU time 4.01 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 222344 kb
Host smart-ddb4fef3-620f-4fe5-b2d0-7c7ff450638b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960571515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.960571515
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4229523821
Short name T21
Test name
Test status
Simulation time 90900883 ps
CPU time 1.89 seconds
Started Jul 01 11:01:43 AM PDT 24
Finished Jul 01 11:01:45 AM PDT 24
Peak memory 216844 kb
Host smart-e159ac8c-700c-49a8-a610-6dac0d6a8573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229523821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4229523821
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.156919778
Short name T809
Test name
Test status
Simulation time 440045741 ps
CPU time 5.25 seconds
Started Jul 01 11:01:33 AM PDT 24
Finished Jul 01 11:01:39 AM PDT 24
Peak memory 214324 kb
Host smart-45d5df99-e9f0-4c88-a22c-2eb4ef014c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156919778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.156919778
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4283463418
Short name T80
Test name
Test status
Simulation time 105643216 ps
CPU time 4.34 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 214308 kb
Host smart-875e057a-c694-49eb-9ddc-1372173252c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283463418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4283463418
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4004451452
Short name T245
Test name
Test status
Simulation time 136350903 ps
CPU time 2.49 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:13 AM PDT 24
Peak memory 221776 kb
Host smart-c8eede81-cdef-46aa-9895-dbfb00a7fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004451452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4004451452
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2416308670
Short name T763
Test name
Test status
Simulation time 273259022 ps
CPU time 3.71 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 215340 kb
Host smart-520c8acb-114a-4fd9-8972-059daf41e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416308670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2416308670
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3262670179
Short name T639
Test name
Test status
Simulation time 920644643 ps
CPU time 21.15 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:34 AM PDT 24
Peak memory 207036 kb
Host smart-217d2488-dd75-49f2-a507-96a7274881f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262670179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3262670179
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2760399726
Short name T118
Test name
Test status
Simulation time 34142705 ps
CPU time 2.32 seconds
Started Jul 01 11:01:04 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 206868 kb
Host smart-a0ba1fbe-5956-4cfa-b835-93f20cdabb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760399726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2760399726
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2117317536
Short name T457
Test name
Test status
Simulation time 273073028 ps
CPU time 3.76 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 207880 kb
Host smart-242822b9-e5ed-47e2-97c7-651262fd0f22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117317536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2117317536
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2443758401
Short name T557
Test name
Test status
Simulation time 624114438 ps
CPU time 7.14 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:19 AM PDT 24
Peak memory 207164 kb
Host smart-38ab9b9b-6d75-43c5-97cc-f7a93ad2367b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443758401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2443758401
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.730923364
Short name T863
Test name
Test status
Simulation time 78423493 ps
CPU time 3.5 seconds
Started Jul 01 11:01:23 AM PDT 24
Finished Jul 01 11:01:27 AM PDT 24
Peak memory 208484 kb
Host smart-ef90d172-18ec-4335-83bd-bb995c78a723
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730923364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.730923364
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.323616986
Short name T682
Test name
Test status
Simulation time 36600381 ps
CPU time 1.5 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:21 AM PDT 24
Peak memory 214420 kb
Host smart-0712178c-cb90-489b-843e-4d5e25697d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323616986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.323616986
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1056972633
Short name T877
Test name
Test status
Simulation time 743308964 ps
CPU time 4.28 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:16 AM PDT 24
Peak memory 208236 kb
Host smart-d99a604c-a07f-4cc8-a241-6279d7041ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056972633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1056972633
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3383018505
Short name T202
Test name
Test status
Simulation time 1269868601 ps
CPU time 30.9 seconds
Started Jul 01 11:01:05 AM PDT 24
Finished Jul 01 11:01:40 AM PDT 24
Peak memory 220988 kb
Host smart-50ea8a0a-861c-4f9c-8d8e-da02b6bae470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383018505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3383018505
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.14485270
Short name T662
Test name
Test status
Simulation time 149382556 ps
CPU time 8.55 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:39 AM PDT 24
Peak memory 220916 kb
Host smart-b4309e72-ca58-449d-bcbf-db624d1feaa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14485270 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.14485270
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.42326169
Short name T337
Test name
Test status
Simulation time 770479279 ps
CPU time 8.95 seconds
Started Jul 01 11:01:11 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 207472 kb
Host smart-547d97d2-0ce2-4de5-8837-7005691ad864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42326169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.42326169
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.936661444
Short name T862
Test name
Test status
Simulation time 330781667 ps
CPU time 4.79 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 210420 kb
Host smart-0fc10757-4f3f-4476-b8a3-bf1f04c87f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936661444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.936661444
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.430714989
Short name T901
Test name
Test status
Simulation time 12693662 ps
CPU time 0.74 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 205844 kb
Host smart-0e1d870e-0aa4-4736-b157-a718f6196338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430714989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.430714989
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.842782634
Short name T385
Test name
Test status
Simulation time 55147114 ps
CPU time 4.13 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 214200 kb
Host smart-e9c87621-c84f-4b8a-b3f5-02762c85c86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842782634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.842782634
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2500955757
Short name T693
Test name
Test status
Simulation time 151259244 ps
CPU time 3.43 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 221764 kb
Host smart-93a3b62a-0b3e-4529-8c55-71a841e4b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500955757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2500955757
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1438155711
Short name T97
Test name
Test status
Simulation time 430140355 ps
CPU time 9.48 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 209284 kb
Host smart-77ee0ff0-890d-4da9-97ca-87509d9da0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438155711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1438155711
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2922560928
Short name T17
Test name
Test status
Simulation time 80045260 ps
CPU time 4.05 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 214280 kb
Host smart-5d711b72-d505-400e-8ccf-34dbaa03f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922560928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2922560928
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2206918573
Short name T308
Test name
Test status
Simulation time 52301988 ps
CPU time 2.57 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:24 AM PDT 24
Peak memory 214276 kb
Host smart-23dc8c8f-86a5-4d21-a7d4-c5866a71df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206918573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2206918573
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.100508309
Short name T339
Test name
Test status
Simulation time 619667792 ps
CPU time 6.27 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:34 AM PDT 24
Peak memory 214184 kb
Host smart-033c2c11-991b-4fb4-a466-efe508d95aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100508309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.100508309
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4277198767
Short name T523
Test name
Test status
Simulation time 167844750 ps
CPU time 5.47 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 208776 kb
Host smart-98559688-827d-48f0-83db-730f4c209a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277198767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4277198767
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1201420057
Short name T19
Test name
Test status
Simulation time 99540852 ps
CPU time 3.09 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 208768 kb
Host smart-1c2680d0-706f-4f1e-a90e-0db894d15566
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201420057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1201420057
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2540437294
Short name T658
Test name
Test status
Simulation time 112456513 ps
CPU time 3.16 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 206828 kb
Host smart-b8686025-334d-42b5-8ffd-0f63e9321c0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540437294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2540437294
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3385796662
Short name T806
Test name
Test status
Simulation time 248802704 ps
CPU time 3.26 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 10:59:24 AM PDT 24
Peak memory 208648 kb
Host smart-be7a7f3f-bd77-4de9-aaa2-7fd9ffbe2782
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385796662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3385796662
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1517464713
Short name T484
Test name
Test status
Simulation time 1588299708 ps
CPU time 27.53 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 222392 kb
Host smart-4dba7f2b-92db-41d7-8b11-695898ade3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517464713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1517464713
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.697367638
Short name T749
Test name
Test status
Simulation time 173278436 ps
CPU time 4.8 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 208584 kb
Host smart-22f5917d-b758-496c-b49d-b995a2cfd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697367638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.697367638
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3189021839
Short name T506
Test name
Test status
Simulation time 314540090 ps
CPU time 11.23 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 222660 kb
Host smart-aad2b1fe-89a0-42db-a20f-cb2116243359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189021839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3189021839
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3793906765
Short name T240
Test name
Test status
Simulation time 153250364 ps
CPU time 6.37 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 210316 kb
Host smart-592c680d-a88f-42b2-ab5e-62d121601d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793906765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3793906765
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3077688183
Short name T914
Test name
Test status
Simulation time 162557812 ps
CPU time 2.01 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 209816 kb
Host smart-049a256e-d7ca-4f1c-9391-6af80abb47cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077688183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3077688183
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3256876964
Short name T610
Test name
Test status
Simulation time 25573507 ps
CPU time 0.77 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 205852 kb
Host smart-a01d7a14-48c5-4f50-ba1e-d4517721ecef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256876964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3256876964
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3810958544
Short name T776
Test name
Test status
Simulation time 1434592427 ps
CPU time 33.71 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:58 AM PDT 24
Peak memory 214756 kb
Host smart-6967dbcc-bb87-45d1-906e-531196c9df03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810958544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3810958544
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.986834752
Short name T458
Test name
Test status
Simulation time 37069285 ps
CPU time 1.88 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:14 AM PDT 24
Peak memory 207464 kb
Host smart-07a409e4-7d10-44eb-b887-49f7739f228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986834752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.986834752
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1296503304
Short name T317
Test name
Test status
Simulation time 388502517 ps
CPU time 6.27 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 214288 kb
Host smart-7016dc49-7121-494a-b6e2-b6605f47c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296503304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1296503304
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3204998979
Short name T248
Test name
Test status
Simulation time 253727381 ps
CPU time 5.53 seconds
Started Jul 01 10:59:13 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 222356 kb
Host smart-3f1ace03-8d45-429a-9ab6-f52739c904c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204998979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3204998979
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2611006965
Short name T833
Test name
Test status
Simulation time 65669307 ps
CPU time 2.55 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 209648 kb
Host smart-2bb21f2a-a82d-43b0-a0c7-d862af26a02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611006965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2611006965
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1310404931
Short name T795
Test name
Test status
Simulation time 215594123 ps
CPU time 3.33 seconds
Started Jul 01 10:59:10 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 218232 kb
Host smart-db509161-5609-4b70-9b92-59da37c55ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310404931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1310404931
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1509212743
Short name T267
Test name
Test status
Simulation time 83083991 ps
CPU time 3.58 seconds
Started Jul 01 10:59:12 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 208548 kb
Host smart-f4604514-8903-48d1-90e9-a9d86005629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509212743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1509212743
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4278507038
Short name T545
Test name
Test status
Simulation time 55969368 ps
CPU time 2.76 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 206848 kb
Host smart-2f6d1d06-fb61-43ca-a151-8decda42fe30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278507038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4278507038
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1792661296
Short name T478
Test name
Test status
Simulation time 181192761 ps
CPU time 2.8 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 207000 kb
Host smart-e44ee728-cc06-4fef-9220-0fc2b26bc4a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792661296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1792661296
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3222467126
Short name T566
Test name
Test status
Simulation time 935775335 ps
CPU time 27.28 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:46 AM PDT 24
Peak memory 208384 kb
Host smart-a571c144-e64a-46eb-b015-512f913742a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222467126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3222467126
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3148489042
Short name T608
Test name
Test status
Simulation time 145268678 ps
CPU time 2.28 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 209388 kb
Host smart-6736fe83-d01f-4f5d-9bff-a688350901a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148489042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3148489042
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1138612459
Short name T486
Test name
Test status
Simulation time 717189333 ps
CPU time 5.53 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 208032 kb
Host smart-17a1efb7-6089-48d3-a31a-6ff2a26a5126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138612459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1138612459
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.951455317
Short name T760
Test name
Test status
Simulation time 105801747 ps
CPU time 3.61 seconds
Started Jul 01 10:59:14 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 206980 kb
Host smart-3b98c522-e16e-47af-8a0c-fac59a3a59e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951455317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.951455317
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2948820080
Short name T116
Test name
Test status
Simulation time 3023570205 ps
CPU time 10.76 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 222500 kb
Host smart-89e5340d-e353-4c62-bfbb-7d720afa00e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948820080 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2948820080
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.4254422756
Short name T251
Test name
Test status
Simulation time 149302813 ps
CPU time 6.47 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:18 AM PDT 24
Peak memory 210452 kb
Host smart-4b303f4e-79f7-4dc3-956d-c523e5c57d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254422756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.4254422756
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2923738558
Short name T567
Test name
Test status
Simulation time 50127173 ps
CPU time 1.89 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:21 AM PDT 24
Peak memory 210292 kb
Host smart-65eb007d-1eb3-41f0-8490-261ccfdf6b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923738558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2923738558
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.451301389
Short name T459
Test name
Test status
Simulation time 11060769 ps
CPU time 0.74 seconds
Started Jul 01 10:59:27 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 205920 kb
Host smart-42c3f2e7-bb72-45ff-859a-c8ad21092ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451301389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.451301389
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4273968967
Short name T788
Test name
Test status
Simulation time 124217631 ps
CPU time 3.06 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:24 AM PDT 24
Peak memory 209456 kb
Host smart-2f1cdd49-8c17-456e-ad86-a58067ac8241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273968967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4273968967
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3190726920
Short name T91
Test name
Test status
Simulation time 77488734 ps
CPU time 3.47 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 214448 kb
Host smart-8eeb6df3-a2b7-4995-884b-b0fc668bbdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190726920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3190726920
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2471260302
Short name T532
Test name
Test status
Simulation time 87476112 ps
CPU time 1.85 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:22 AM PDT 24
Peak memory 214240 kb
Host smart-f2f945f2-4ca9-43d4-bd50-e545f93c9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471260302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2471260302
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4004578756
Short name T636
Test name
Test status
Simulation time 401822859 ps
CPU time 2.6 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 218048 kb
Host smart-6b49c599-1bbc-4285-a580-96919bd2fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004578756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4004578756
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3416107442
Short name T421
Test name
Test status
Simulation time 414091921 ps
CPU time 4.71 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 209044 kb
Host smart-660b40fa-9b0e-4859-8439-dc4542e556cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416107442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3416107442
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.28406632
Short name T649
Test name
Test status
Simulation time 69310229 ps
CPU time 3.62 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 208188 kb
Host smart-21b720ed-b0fd-493d-93cb-6ea3cce6e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28406632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.28406632
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1458051391
Short name T441
Test name
Test status
Simulation time 569898196 ps
CPU time 4.64 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 206952 kb
Host smart-a23af044-39e7-49de-a9b9-a90d37e4cc37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458051391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1458051391
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.151982538
Short name T747
Test name
Test status
Simulation time 131925275 ps
CPU time 3.29 seconds
Started Jul 01 10:59:25 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 208588 kb
Host smart-92afc97a-8d4c-4929-9be5-d666721b0bc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151982538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.151982538
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1033411250
Short name T412
Test name
Test status
Simulation time 1427213718 ps
CPU time 5.88 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:30 AM PDT 24
Peak memory 207944 kb
Host smart-028f87da-8186-412e-8e6a-48906c67f323
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033411250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1033411250
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1488225168
Short name T796
Test name
Test status
Simulation time 53671052 ps
CPU time 1.93 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 207972 kb
Host smart-15c1195c-249a-499e-952e-11e7355be8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488225168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1488225168
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1313535076
Short name T762
Test name
Test status
Simulation time 752921989 ps
CPU time 7.07 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 208444 kb
Host smart-e063d0e2-ca69-44a0-b260-0b97865d899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313535076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1313535076
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3842248256
Short name T430
Test name
Test status
Simulation time 533366188 ps
CPU time 2.9 seconds
Started Jul 01 10:59:27 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 208404 kb
Host smart-f42e7f83-1aa4-4850-8670-de3028da0f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842248256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3842248256
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2406583568
Short name T338
Test name
Test status
Simulation time 84978056 ps
CPU time 4.23 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:21 AM PDT 24
Peak memory 209472 kb
Host smart-b12c46ce-9cea-4aa2-827f-336e2db74472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406583568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2406583568
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1116422240
Short name T768
Test name
Test status
Simulation time 160887939 ps
CPU time 2.63 seconds
Started Jul 01 10:59:11 AM PDT 24
Finished Jul 01 10:59:15 AM PDT 24
Peak memory 210700 kb
Host smart-652e114d-df45-4b5d-a50f-ae42e495fdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116422240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1116422240
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3989910563
Short name T909
Test name
Test status
Simulation time 25572911 ps
CPU time 1.01 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 206196 kb
Host smart-d7817779-9617-4b64-b3ca-f6d0529df7ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989910563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3989910563
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2544966491
Short name T291
Test name
Test status
Simulation time 49866981 ps
CPU time 3.55 seconds
Started Jul 01 10:59:29 AM PDT 24
Finished Jul 01 10:59:36 AM PDT 24
Peak memory 214232 kb
Host smart-139d066a-b757-4023-a145-70c54f1b6e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544966491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2544966491
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1411106567
Short name T676
Test name
Test status
Simulation time 34986453 ps
CPU time 1.54 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 207172 kb
Host smart-4a7ff642-33ac-49e9-8dce-084095176160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411106567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1411106567
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1983643163
Short name T210
Test name
Test status
Simulation time 43799974 ps
CPU time 3.08 seconds
Started Jul 01 10:59:28 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 214428 kb
Host smart-bdf8e6b5-6074-4d8f-851a-bfe48af06116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983643163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1983643163
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.12055739
Short name T304
Test name
Test status
Simulation time 38750078 ps
CPU time 1.88 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:19 AM PDT 24
Peak memory 215236 kb
Host smart-01eaeb77-ca78-4b49-a60f-2d77aef95b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12055739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.12055739
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_random.2485060968
Short name T886
Test name
Test status
Simulation time 324317378 ps
CPU time 6.29 seconds
Started Jul 01 10:59:19 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 214332 kb
Host smart-a06608e8-952a-459b-bbd0-d6b0cbb29f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485060968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2485060968
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.653254891
Short name T584
Test name
Test status
Simulation time 39426436 ps
CPU time 1.78 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 207416 kb
Host smart-f4c20b39-e8b6-4ef3-bc89-e5972871da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653254891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.653254891
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2006798857
Short name T562
Test name
Test status
Simulation time 1716553042 ps
CPU time 5.01 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 208964 kb
Host smart-dc78311e-49a3-4dd9-8290-13f4623972f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006798857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2006798857
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2616137337
Short name T648
Test name
Test status
Simulation time 61157786 ps
CPU time 2.96 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 208832 kb
Host smart-c59d2b49-542c-474f-a2d4-24df9213893d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616137337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2616137337
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.340880283
Short name T454
Test name
Test status
Simulation time 240627933 ps
CPU time 3.16 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 206868 kb
Host smart-a6d44c60-e7a2-43e3-92c2-51e1a4275ad6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340880283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.340880283
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2753429984
Short name T559
Test name
Test status
Simulation time 240117512 ps
CPU time 2.86 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 208816 kb
Host smart-b77aa126-f708-460f-889b-d7e4d6481810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753429984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2753429984
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2626436784
Short name T469
Test name
Test status
Simulation time 125075824 ps
CPU time 2.86 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 207132 kb
Host smart-25451895-36f7-42dc-9d20-35c90c0315df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626436784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2626436784
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.4223737446
Short name T239
Test name
Test status
Simulation time 26374066493 ps
CPU time 149.53 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 217296 kb
Host smart-997d72a7-43e0-4e16-8376-95d1848c91b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223737446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4223737446
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2676602802
Short name T700
Test name
Test status
Simulation time 439267638 ps
CPU time 8.93 seconds
Started Jul 01 10:59:21 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 222528 kb
Host smart-dba85d6f-eb98-4dd4-80a7-b6d50e4bcb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676602802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2676602802
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.296238952
Short name T640
Test name
Test status
Simulation time 132856466 ps
CPU time 3.94 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 214352 kb
Host smart-defe6f5d-affb-4eed-ad71-daa375999dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296238952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.296238952
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3104889659
Short name T361
Test name
Test status
Simulation time 81079935 ps
CPU time 1.69 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 210184 kb
Host smart-9067fd52-609e-4c09-83d7-1e3ecab193df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104889659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3104889659
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.379008695
Short name T730
Test name
Test status
Simulation time 15503007 ps
CPU time 0.77 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 205948 kb
Host smart-6edbd8dc-3872-4e55-a66b-68a8fa070097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379008695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.379008695
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3618581178
Short name T176
Test name
Test status
Simulation time 448969388 ps
CPU time 11.63 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:39 AM PDT 24
Peak memory 222280 kb
Host smart-de76bb4b-3b08-43c3-969a-3b6e1770a274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618581178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3618581178
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1390514397
Short name T29
Test name
Test status
Simulation time 125532566 ps
CPU time 3.02 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 222784 kb
Host smart-9ab07328-d9f3-4fdf-9cd2-c0daeedccdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390514397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1390514397
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2576633329
Short name T837
Test name
Test status
Simulation time 26256570 ps
CPU time 1.95 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 207256 kb
Host smart-a60e358e-9815-4a81-b22a-f3083abe3aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576633329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2576633329
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3670115761
Short name T92
Test name
Test status
Simulation time 179459947 ps
CPU time 3.83 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 210060 kb
Host smart-e7f87195-5da3-4104-b63e-16c3a39aa707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670115761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3670115761
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3398790692
Short name T306
Test name
Test status
Simulation time 84298431 ps
CPU time 4.21 seconds
Started Jul 01 10:59:27 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 214256 kb
Host smart-19f81558-6b69-432e-9834-4993dec809b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398790692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3398790692
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3104527202
Short name T505
Test name
Test status
Simulation time 1505480754 ps
CPU time 4.38 seconds
Started Jul 01 10:59:27 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 207420 kb
Host smart-fac52c1d-4ca2-4cd7-9b15-316575caba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104527202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3104527202
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2765156176
Short name T828
Test name
Test status
Simulation time 60487679 ps
CPU time 3.19 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 222512 kb
Host smart-f539152b-5157-444c-b287-d3cc067f9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765156176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2765156176
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4200668915
Short name T232
Test name
Test status
Simulation time 112588328 ps
CPU time 4.85 seconds
Started Jul 01 10:59:26 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 207292 kb
Host smart-ed2e1ea2-22da-4393-a96b-fe7017e4895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200668915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4200668915
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4101913281
Short name T915
Test name
Test status
Simulation time 177058305 ps
CPU time 6.06 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:29 AM PDT 24
Peak memory 207900 kb
Host smart-fd19c0dc-f3c9-4bf6-92b1-b0ff06d0377b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101913281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4101913281
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4111072522
Short name T709
Test name
Test status
Simulation time 195010220 ps
CPU time 3 seconds
Started Jul 01 10:59:23 AM PDT 24
Finished Jul 01 10:59:27 AM PDT 24
Peak memory 208544 kb
Host smart-f19881ad-df8c-4d5f-9725-df30708770dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111072522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4111072522
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.547482409
Short name T778
Test name
Test status
Simulation time 300224440 ps
CPU time 2.85 seconds
Started Jul 01 10:59:17 AM PDT 24
Finished Jul 01 10:59:21 AM PDT 24
Peak memory 207276 kb
Host smart-0078f35e-44af-4e5e-a029-d2e006015bc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547482409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.547482409
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2048872881
Short name T775
Test name
Test status
Simulation time 122166501 ps
CPU time 2.87 seconds
Started Jul 01 10:59:24 AM PDT 24
Finished Jul 01 10:59:28 AM PDT 24
Peak memory 210288 kb
Host smart-be302668-4f8f-4d57-9cd8-21a741eabfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048872881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2048872881
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3316179072
Short name T424
Test name
Test status
Simulation time 72457075 ps
CPU time 2.99 seconds
Started Jul 01 10:59:22 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 208536 kb
Host smart-ced97892-daf8-42b8-84fe-e9c40bcc5589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316179072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3316179072
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1082011577
Short name T758
Test name
Test status
Simulation time 630385824 ps
CPU time 12.12 seconds
Started Jul 01 10:59:18 AM PDT 24
Finished Jul 01 10:59:32 AM PDT 24
Peak memory 222480 kb
Host smart-b2de9046-f9f6-4f99-990c-4dbdbde52345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082011577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1082011577
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4055700051
Short name T194
Test name
Test status
Simulation time 324304451 ps
CPU time 4.92 seconds
Started Jul 01 10:59:20 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 207856 kb
Host smart-477acc02-9211-49c6-9709-2813c1c7f7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055700051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4055700051
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3381593609
Short name T873
Test name
Test status
Simulation time 50619344 ps
CPU time 2.57 seconds
Started Jul 01 10:59:16 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 209844 kb
Host smart-8b33c402-2506-470d-9123-c60c1b566b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381593609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3381593609
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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