Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
57596 |
1 |
|
|
T1 |
27 |
|
T2 |
186 |
|
T3 |
490 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
33569 |
1 |
|
|
T1 |
27 |
|
T2 |
114 |
|
T3 |
195 |
auto[1] |
24027 |
1 |
|
|
T2 |
72 |
|
T3 |
295 |
|
T11 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28671 |
1 |
|
|
T1 |
14 |
|
T2 |
94 |
|
T3 |
268 |
auto[1] |
28925 |
1 |
|
|
T1 |
13 |
|
T2 |
92 |
|
T3 |
222 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16845 |
1 |
|
|
T1 |
14 |
|
T2 |
58 |
|
T3 |
111 |
all_values[0] |
auto[0] |
auto[1] |
16724 |
1 |
|
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
84 |
all_values[0] |
auto[1] |
auto[0] |
11826 |
1 |
|
|
T2 |
36 |
|
T3 |
157 |
|
T11 |
17 |
all_values[0] |
auto[1] |
auto[1] |
12201 |
1 |
|
|
T2 |
36 |
|
T3 |
138 |
|
T11 |
16 |