Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717

1

T1

3

T2

7

T3

29

auto[1]

531

1

T3

2

T4

4

T40

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717

1

T1

3

T2

7

T3

29

auto[1]

531

1

T3

2

T4

4

T40

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4707

1

T1

3

T2

6

T3

30

auto[1]

541

1

T2

1

T3

1

T12

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4707

1

T1

3

T2

6

T3

30

auto[1]

541

1

T2

1

T3

1

T12

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	401	1			T1	1		T2	1		T3	3
auto[OpGenId]	1087	1			T1	1		T2	2		T3	9
auto[OpGenSwOut]	1162	1			T1	1		T2	2		T3	6
auto[OpGenHwOut]	2526	1			T2	2		T3	10		T4	6
auto[OpDisable]	72	1			T3	3		T40	2		T65	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	401	1			T1	1		T2	1		T3	3
auto[OpGenId]	1087	1			T1	1		T2	2		T3	9
auto[OpGenSwOut]	1162	1			T1	1		T2	2		T3	6
auto[OpGenHwOut]	2526	1			T2	2		T3	10		T4	6
auto[OpDisable]	72	1			T3	3		T40	2		T65	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4734

1

T1

3

T2

7

T3

30

auto[1]

514

1

T3

1

T4

6

T14

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4734

1

T1

3

T2

7

T3

30

auto[1]

514

1

T3

1

T4

6

T14

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5043

1

T1

3

T2

7

T3

31

auto[1]

205

1

T72

11

T112

3

T117

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1814	1			T1	1		T2	5		T3	13
auto[1]	646	1			T3	2		T4	4		T13	1
auto[2]	683	1			T3	2		T4	5		T13	1
auto[3]	724	1			T1	1		T2	1		T3	2
auto[4]	359	1			T3	5		T4	8		T13	1
auto[5]	338	1			T1	1		T3	1		T11	1
auto[6]	337	1			T3	2		T4	1		T13	1
auto[7]	347	1			T2	1		T3	4		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1381	1			T1	1		T2	1		T3	12
clear_one[1]	646	1			T3	2		T4	4		T13	1
clear_one[2]	683	1			T3	2		T4	5		T13	1
clear_one[3]	724	1			T1	1		T2	1		T3	2
clear_none	1814	1			T1	1		T2	5		T3	13

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T2	4		T3	3		T4	3
auto[StInit]	659	1			T1	1		T2	2		T3	2
auto[StCreatorRootKey]	573	1			T1	1		T3	5		T4	4
auto[StOwnerIntKey]	485	1			T1	1		T3	4		T4	4
auto[StOwnerKey]	476	1			T2	1		T3	5		T11	1
auto[StDisabled]	1760	1			T3	12		T12	1		T4	16
auto[StInvalid]	284	1			T29	3		T41	5		T42	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T2	4		T3	3		T4	3
auto[StInit]	659	1			T1	1		T2	2		T3	2
auto[StCreatorRootKey]	573	1			T1	1		T3	5		T4	4
auto[StOwnerIntKey]	485	1			T1	1		T3	4		T4	4
auto[StOwnerKey]	476	1			T2	1		T3	5		T11	1
auto[StDisabled]	1760	1			T3	12		T12	1		T4	16
auto[StInvalid]	284	1			T29	3		T41	5		T42	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T228	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	162	1			T2	2		T3	1		T40	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	174	1			T2	1		T4	2		T16	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	258	1			T3	2		T13	1		T14	2
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T2	1		T3	1		T4	1
auto[0]	auto[StInit]	auto[OpGenId]	83	1			T1	1		T11	1		T65	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	110	1			T12	1		T40	1		T113	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	165	1			T2	1		T4	1		T40	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T183	1		T229	1		T230	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	57	1			T3	2		T4	1		T197	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	52	1			T4	2		T192	1		T38	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	76	1			T3	2		T4	1		T40	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T48	1		T117	1		T62	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T56	1		T54	1		T231	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T3	1		T51	1		T134	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	53	1			T190	1		T200	1		T232	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T81	1		T233	1		T234	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T235	1		T134	1		T233	2
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T3	1		T196	1		T56	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T13	1		T40	1		T190	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	24	1			T117	1		T183	1		T51	2
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T3	1		T4	2		T72	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T12	1		T4	1		T72	3
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T4	1		T13	1		T14	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T3	2		T40	1		T56	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T236	1		T237	1		T238	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T43	1		T239	1		T181	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	20	1			T29	1		T42	2		T47	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	29	1			T29	1		T41	1		T240	1
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T46	1		T38	1		T241	2
auto[1]	auto[StReset]	auto[OpGenSwOut]	19	1			T15	1		T48	1		T50	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T46	1		T48	1		T242	1
auto[1]	auto[StInit]	auto[OpAdvance]	10	1			T72	1		T243	1		T244	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T245	1		T54	1		T44	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T233	1		T82	1		T246	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T3	1		T247	1		T248	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T120	1		T6	1		T233	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T72	1		T66	1		T249	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T3	1		T66	1		T51	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T13	1		T14	1		T72	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T121	2		T175	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T112	1		T59	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T112	1		T120	1		T212	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T16	1		T252	1		T66	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T4	1		T51	2		T175	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T48	1		T253	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T255	1		T66	1		T120	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T4	1		T252	1		T256	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T254	1		T257	1		T258	1
auto[1]	auto[StDisabled]	auto[OpGenId]	47	1			T4	1		T40	1		T38	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T4	1		T46	1		T38	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	127	1			T14	1		T116	1		T242	1
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T110	1		T60	1		T259	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T41	1		T260	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenId]	21	1			T41	1		T42	1		T43	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T239	1		T181	1		T91	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T42	1		T79	1		T262	1
auto[2]	auto[StReset]	auto[OpGenId]	11	1			T183	1		T233	1		T263	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T192	1		T38	1		T43	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	55	1			T242	1		T264	1		T247	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T265	1		T266	1		T257	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T46	1		T51	1		T206	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	16	1			T46	1		T48	1		T56	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T267	1		T176	1		T268	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T269	1		T186	2		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T40	1		T46	1		T243	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T29	1		T56	1		T131	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T271	1		T201	1		T272	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T72	1		T273	1		T274	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T116	1		T68	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T50	1		T81	1		T51	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T4	1		T14	1		T40	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T3	1		T48	1		T62	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T48	1		T276	1		T277	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T4	2		T72	1		T56	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T14	1		T40	1		T72	2
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T4	1		T72	1		T46	1
auto[2]	auto[StDisabled]	auto[OpGenId]	43	1			T40	1		T72	1		T56	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T3	1		T48	1		T56	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T4	1		T13	1		T199	1
auto[2]	auto[StDisabled]	auto[OpDisable]	14	1			T40	1		T48	1		T278	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T240	1		T91	1		T279	2
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T29	1		T239	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T41	1		T47	1		T236	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T42	1		T79	2		T91	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T48	1		T281	1		T51	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T40	1		T110	1		T51	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	44	1			T13	1		T192	1		T54	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T123	1		T78	1		T205	1
auto[3]	auto[StInit]	auto[OpGenId]	17	1			T48	1		T249	1		T34	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T172	1		T6	1		T233	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T15	1		T48	1		T242	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T265	1		T253	1		T282	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T278	1		T123	1		T172	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T156	1		T48	1		T54	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T46	1		T50	1		T283	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T4	1		T30	1		T284	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T119	1		T39	1		T285	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T1	1		T113	1		T48	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T13	1		T242	1		T264	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T40	1		T114	1		T56	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	6	1			T286	1		T39	1		T158	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T2	1		T194	1		T287	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T201	1		T60	1		T248	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T3	1		T243	1		T251	1
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T4	1		T112	1		T191	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T3	1		T4	1		T40	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	176	1			T14	1		T40	1		T46	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T56	1		T59	1		T153	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T240	1		T262	1		T288	1
auto[3]	auto[StInvalid]	auto[OpGenId]	8	1			T237	1		T289	1		T290	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T262	1		T291	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T236	1		T293	1		T99	1
auto[4]	auto[StReset]	auto[OpGenId]	14	1			T4	1		T54	1		T51	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T16	1		T121	1		T254	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T294	1		T176	1		T6	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T38	1		T6	1		T295	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T296	1		T297	1		T298	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T46	1		T299	1		T300	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	20	1			T14	1		T15	1		T156	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T113	1		T39	1		T295	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T54	1		T70	1		T301	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T56	1		T302	1		T174	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T303	1		T304	1		T305	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T40	1		T306	1		T307	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T218	1		T308	1		T299	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T4	2		T233	1		T68	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T3	2		T191	1		T247	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T122	1		T309	1		T310	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T3	1		T311	1		T172	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T16	1		T271	1		T54	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	8	1			T3	1		T267	1		T233	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T4	2		T40	1		T193	1
auto[4]	auto[StDisabled]	auto[OpGenId]	42	1			T4	2		T112	1		T56	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T4	1		T40	1		T194	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	60	1			T3	1		T13	1		T199	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T51	1		T233	1		T312	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T76	1		T313	1		T314	1
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T315	1		T316	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T43	1		T240	2		T238	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T76	1		T79	1		T317	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T111	1		T318	1		T226	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T15	1		T43	1		T50	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	20	1			T56	1		T47	1		T201	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T210	1		T319	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T121	2		T258	1		T234	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T320	1		T321	1		T322	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	16	1			T13	1		T56	1		T264	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T1	1		T323	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T22	1		T257	1		T226	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T110	1		T324	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T40	1		T190	1		T264	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T56	1		T39	1		T83	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T245	1		T258	1		T326	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T56	1		T211	1		T282	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T327	1		T328	1		T303	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T11	1		T39	1		T70	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T329	1		T330	1		T323	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T331	3		T153	1		T332	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T328	1		T294	1		T333	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	9	1			T48	1		T331	2		T334	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T3	1		T194	1		T56	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T46	1		T123	1		T253	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T13	1		T46	1		T56	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T65	1		T153	1		T335	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T236	1		T336	1		T315	1
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T293	1		T337	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T239	1		T260	2		T338	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T339	1		T340	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T16	1		T48	1		T326	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T27	1		T60	1		T266	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T13	1		T264	1		T43	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T205	1		T341	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T56	1		T22	1		T234	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T30	1		T342	1		T343	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	7	1			T47	1		T184	1		T344	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T345	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T30	1		T116	1		T241	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T16	1		T194	1		T254	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T199	1		T200	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T114	1		T296	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T70	1		T345	2		T347	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T46	1		T67	2		T273	3
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T272	1		T346	1		T34	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T285	1		T348	1		T162	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T285	1		T349	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T3	1		T351	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T56	1		T191	1		T200	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T4	1		T48	1		T56	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T352	1		T233	1		T68	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	16	1			T114	1		T66	1		T353	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T3	1		T40	1		T199	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T60	1		T320	1		T354	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T238	1		T280	1		T337	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T73	1		T238	2		T289	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T47	1		T79	1		T261	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T260	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T116	1		T331	1		T257	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T182	1		T51	1		T355	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T2	1		T13	1		T201	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T320	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T235	1		T356	1		T357	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T134	1		T285	1		T205	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T201	1		T22	1		T358	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T122	1		T250	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T180	1		T359	1		T250	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T134	1		T6	1		T360	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T56	1		T252	1		T184	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T361	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T3	1		T51	1		T67	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T359	1		T362	1		T300	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T48	1		T56	1		T271	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T54	1		T363	1		T244	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T266	1		T357	1		T296	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T231	1		T122	2		T364	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T199	1		T365	1		T346	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T113	1		T48	1		T359	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T3	2		T56	2		T191	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T38	1		T276	1		T355	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T14	1		T199	1		T197	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T3	1		T48	1		T366	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T79	1		T367	1		T315	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T41	1		T317	1		T293	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T181	1		T288	1		T279	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T337	1		-	-		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1381

1

T1

1

T2

1

T3

12

clear_one[1]

auto[0]

auto[0]

auto[0]

403

1

T3

2

T4

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

103

1

T4

2

T14

2

T72

1

clear_one[1]

auto[0]

auto[1]

auto[0]

112

1

T13

1

T16

1

T56

1

clear_one[1]

auto[0]

auto[1]

auto[1]

28

1

T46

1

T134

3

T254

1

clear_one[2]

auto[0]

auto[0]

auto[0]

379

1

T3

2

T4

3

T13

1

clear_one[2]

auto[0]

auto[0]

auto[1]

128

1

T14

2

T40

3

T72

6

clear_one[2]

auto[1]

auto[0]

auto[0]

136

1

T56

3

T62

1

T328

1

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T4

2

T46

1

T56

1

clear_one[3]

auto[0]

auto[0]

auto[0]

420

1

T1

1

T3

2

T4

3

clear_one[3]

auto[0]

auto[1]

auto[0]

140

1

T2

1

T13

1

T40

1

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T40

1

T46

1

T48

3

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T59

2

T182

1

T51

1

clear_none

auto[0]

auto[0]

auto[0]

1313

1

T1

1

T2

5

T3

10

clear_none

auto[0]

auto[0]

auto[1]

137

1

T4

1

T14

1

T72

4

clear_none

auto[0]

auto[1]

auto[0]

144

1

T12

1

T13

2

T40

2

clear_none

auto[0]

auto[1]

auto[1]

29

1

T3

1

T72

1

T48

1

clear_none

auto[1]

auto[0]

auto[0]

112

1

T3

2

T192

1

T56

1

clear_none

auto[1]

auto[0]

auto[1]

28

1

T4

1

T172

1

T368

1

clear_none

auto[1]

auto[1]

auto[0]

30

1

T4

1

T40

1

T117

7

clear_none

auto[1]

auto[1]

auto[1]

21

1

T66

1

T353

1

T271

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1322	1			T1	1		T2	1		T3	12
clear_all	auto[1]	59	1			T120	2		T121	1		T122	5
clear_one[1]	auto[0]	622	1			T3	2		T4	4		T13	1
clear_one[1]	auto[1]	24	1			T72	2		T112	1		T120	2
clear_one[2]	auto[0]	660	1			T3	2		T4	5		T13	1
clear_one[2]	auto[1]	23	1			T72	4		T121	1		T331	1
clear_one[3]	auto[0]	686	1			T1	1		T2	1		T3	2
clear_one[3]	auto[1]	38	1			T112	2		T131	2		T120	2
clear_none	auto[0]	1753	1			T1	1		T2	5		T3	13
clear_none	auto[1]	61	1			T72	5		T117	7		T131	1