Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11229

1

T1

4

T2

38

T3

70

auto[Attestation]

7565

1

T1

5

T2

21

T3

60

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2734	1			T2	11		T3	22		T11	1
auto[Aes]	3322	1			T1	2		T2	6		T3	17
auto[Kmac]	3383	1			T1	3		T2	9		T3	13
auto[Otbn]	3411	1			T1	2		T2	5		T3	27

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7675	1			T1	4		T2	32		T3	71
auto[OpGenId]	5944	1			T1	2		T2	28		T3	51
auto[OpGenSwOut]	5866	1			T1	2		T2	18		T3	40
auto[OpGenHwOut]	6984	1			T1	5		T2	13		T3	39
auto[OpDisable]	153	1			T3	5		T4	1		T40	4

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10624

1

T1

12

T2

40

T3

105

auto[OpDoneFail]

15998

1

T1

1

T2

51

T3

101

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6483	1			T1	1		T2	21		T3	30
auto[StInit]	3821	1			T1	2		T2	21		T3	34
auto[StCreatorRootKey]	3230	1			T1	1		T2	9		T3	30
auto[StOwnerIntKey]	2689	1			T1	3		T2	9		T3	32
auto[StOwnerKey]	2484	1			T1	6		T2	10		T3	18
auto[StDisabled]	7915	1			T2	21		T3	62		T12	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	313	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T2	1		T3	3		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T11	1		T12	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	79	1			T2	1		T46	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T3	1		T12	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	237	1			T2	2		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	333	1			T15	3		T16	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T3	1		T12	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	100	1			T3	1		T192	1		T156	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T2	2		T193	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	48	1			T3	1		T72	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	219	1			T2	1		T3	3		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	323	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T2	1		T4	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T3	2		T40	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T194	1		T32	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T1	1		T2	2		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T2	1		T12	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	330	1			T2	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T3	2		T15	2		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T3	1		T16	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T3	1		T4	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	69	1			T4	1		T195	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	202	1			T3	1		T4	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T4	1		T40	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T3	1		T46	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T4	2		T40	2		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T4	1		T197	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	72	1			T2	2		T196	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	202	1			T3	3		T4	2		T40	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T4	2		T40	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T2	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	70	1			T4	1		T16	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	61	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T3	1		T4	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	233	1			T3	2		T4	4		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T4	1		T40	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	84	1			T3	1		T4	2		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T4	1		T16	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T4	1		T40	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	74	1			T3	1		T40	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	216	1			T4	2		T40	3		T46	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	72	1			T2	1		T3	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	115	1			T3	1		T4	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T3	1		T40	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T3	2		T4	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T4	2		T116	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	203	1			T3	4		T4	4		T40	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	291	1			T2	1		T3	4		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T3	1		T4	1		T40	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T2	1		T3	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	51	1			T3	1		T4	2		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	66	1			T3	1		T4	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T3	1		T4	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	423	1			T16	1		T46	3		T192	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T2	2		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	127	1			T3	1		T4	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T3	2		T4	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T4	1		T48	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	280	1			T3	1		T40	2		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	513	1			T2	1		T3	2		T13	13
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T3	1		T13	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	122	1			T40	2		T35	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T3	1		T13	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	90	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	253	1			T4	1		T13	3		T40	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	513	1			T14	8		T15	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T2	1		T3	2		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T14	1		T40	2		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T3	3		T14	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	100	1			T1	1		T11	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	283	1			T3	2		T4	3		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T2	1		T4	1		T40	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T2	1		T4	2		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T3	1		T46	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T4	2		T197	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T40	1		T72	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	176	1			T3	1		T40	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	48	1			T3	1		T56	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T4	3		T15	2		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T3	1		T192	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T46	1		T32	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	94	1			T1	1		T11	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	270	1			T3	1		T4	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T2	1		T4	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T2	1		T3	3		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T13	1		T16	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T16	1		T199	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	77	1			T1	1		T2	1		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	275	1			T12	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T2	1		T4	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	130	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T4	1		T46	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T48	2		T200	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T3	3		T4	2		T14	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	206	1			T2	1		T3	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	677	1			T2	4		T3	5		T4	6
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	202	1			T2	2		T3	2		T72	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	672	1			T2	1		T3	4		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T1	1		T2	2		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	660	1			T2	3		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T3	2		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	663	1			T2	1		T3	4		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	201	1			T2	2		T4	3		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	394	1			T3	4		T4	3		T40	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	173	1			T1	1		T3	2		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	427	1			T2	1		T3	2		T4	7
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T3	1		T4	2		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	404	1			T3	1		T4	5		T40	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T3	3		T4	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	404	1			T2	1		T3	6		T4	6
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	188	1			T2	1		T3	4		T4	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	566	1			T2	1		T3	6		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	278	1			T3	2		T4	3		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	834	1			T2	2		T3	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	297	1			T1	1		T3	2		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	910	1			T2	1		T3	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	278	1			T1	1		T3	3		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	935	1			T2	1		T3	4		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	173	1			T3	1		T4	2		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	329	1			T2	2		T3	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T1	1		T3	1		T11	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	467	1			T3	2		T4	6		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	251	1			T1	1		T2	1		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	479	1			T2	2		T3	3		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	264	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	466	1			T2	1		T3	4		T4	4