Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32631

1

T1

15

T2

103

T3

236

auto[1]

220

1

T72

7

T117

8

T131

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32641	1			T1	15		T2	103		T3	236
auto[134217728:268435455]	7	1			T72	1		T123	1		T285	1
auto[268435456:402653183]	10	1			T117	1		T121	1		T295	2
auto[402653184:536870911]	10	1			T120	1		T122	1		T253	1
auto[536870912:671088639]	6	1			T253	1		T172	1		T258	1
auto[671088640:805306367]	8	1			T72	1		T331	1		T277	1
auto[805306368:939524095]	9	1			T120	1		T122	1		T253	1
auto[939524096:1073741823]	5	1			T117	1		T123	1		T253	1
auto[1073741824:1207959551]	13	1			T72	3		T117	1		T122	3
auto[1207959552:1342177279]	3	1			T384	1		T295	1		T396	1
auto[1342177280:1476395007]	6	1			T120	1		T121	1		T397	1
auto[1476395008:1610612735]	3	1			T172	1		T229	1		T398	1
auto[1610612736:1744830463]	1	1			T397	1		-	-		-	-
auto[1744830464:1879048191]	11	1			T119	1		T120	1		T331	1
auto[1879048192:2013265919]	12	1			T117	1		T120	2		T122	1
auto[2013265920:2147483647]	6	1			T72	1		T331	1		T273	1
auto[2147483648:2281701375]	4	1			T229	1		T384	1		T399	1
auto[2281701376:2415919103]	4	1			T345	3		T400	1		-	-
auto[2415919104:2550136831]	9	1			T273	1		T384	1		T285	1
auto[2550136832:2684354559]	10	1			T117	1		T120	1		T121	1
auto[2684354560:2818572287]	5	1			T331	1		T384	1		T285	1
auto[2818572288:2952790015]	8	1			T122	1		T123	1		T385	1
auto[2952790016:3087007743]	4	1			T117	1		T121	1		T285	1
auto[3087007744:3221225471]	4	1			T131	1		T121	1		T401	2
auto[3221225472:3355443199]	7	1			T123	1		T229	1		T285	1
auto[3355443200:3489660927]	10	1			T121	1		T253	2		T172	1
auto[3489660928:3623878655]	6	1			T122	1		T229	1		T402	2
auto[3623878656:3758096383]	4	1			T121	1		T383	1		T399	1
auto[3758096384:3892314111]	7	1			T72	1		T117	1		T331	1
auto[3892314112:4026531839]	6	1			T122	1		T258	1		T295	1
auto[4026531840:4160749567]	4	1			T117	1		T122	1		T123	1
auto[4160749568:4294967295]	8	1			T397	1		T277	1		T345	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32631	1			T1	15		T2	103		T3	236
auto[0:134217727]	auto[1]	10	1			T253	1		T229	1		T258	1
auto[134217728:268435455]	auto[1]	7	1			T72	1		T123	1		T285	1
auto[268435456:402653183]	auto[1]	10	1			T117	1		T121	1		T295	2
auto[402653184:536870911]	auto[1]	10	1			T120	1		T122	1		T253	1
auto[536870912:671088639]	auto[1]	6	1			T253	1		T172	1		T258	1
auto[671088640:805306367]	auto[1]	8	1			T72	1		T331	1		T277	1
auto[805306368:939524095]	auto[1]	9	1			T120	1		T122	1		T253	1
auto[939524096:1073741823]	auto[1]	5	1			T117	1		T123	1		T253	1
auto[1073741824:1207959551]	auto[1]	13	1			T72	3		T117	1		T122	3
auto[1207959552:1342177279]	auto[1]	3	1			T384	1		T295	1		T396	1
auto[1342177280:1476395007]	auto[1]	6	1			T120	1		T121	1		T397	1
auto[1476395008:1610612735]	auto[1]	3	1			T172	1		T229	1		T398	1
auto[1610612736:1744830463]	auto[1]	1	1			T397	1		-	-		-	-
auto[1744830464:1879048191]	auto[1]	11	1			T119	1		T120	1		T331	1
auto[1879048192:2013265919]	auto[1]	12	1			T117	1		T120	2		T122	1
auto[2013265920:2147483647]	auto[1]	6	1			T72	1		T331	1		T273	1
auto[2147483648:2281701375]	auto[1]	4	1			T229	1		T384	1		T399	1
auto[2281701376:2415919103]	auto[1]	4	1			T345	3		T400	1		-	-
auto[2415919104:2550136831]	auto[1]	9	1			T273	1		T384	1		T285	1
auto[2550136832:2684354559]	auto[1]	10	1			T117	1		T120	1		T121	1
auto[2684354560:2818572287]	auto[1]	5	1			T331	1		T384	1		T285	1
auto[2818572288:2952790015]	auto[1]	8	1			T122	1		T123	1		T385	1
auto[2952790016:3087007743]	auto[1]	4	1			T117	1		T121	1		T285	1
auto[3087007744:3221225471]	auto[1]	4	1			T131	1		T121	1		T401	2
auto[3221225472:3355443199]	auto[1]	7	1			T123	1		T229	1		T285	1
auto[3355443200:3489660927]	auto[1]	10	1			T121	1		T253	2		T172	1
auto[3489660928:3623878655]	auto[1]	6	1			T122	1		T229	1		T402	2
auto[3623878656:3758096383]	auto[1]	4	1			T121	1		T383	1		T399	1
auto[3758096384:3892314111]	auto[1]	7	1			T72	1		T117	1		T331	1
auto[3892314112:4026531839]	auto[1]	6	1			T122	1		T258	1		T295	1
auto[4026531840:4160749567]	auto[1]	4	1			T117	1		T122	1		T123	1
auto[4160749568:4294967295]	auto[1]	8	1			T397	1		T277	1		T345	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T2

2

T3

3

T11

1

auto[1]

1773

1

T2

4

T3

13

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T4	2		T16	1		T40	1
auto[134217728:268435455]	101	1			T2	1		T40	3		T196	1
auto[268435456:402653183]	97	1			T4	1		T40	1		T46	1
auto[402653184:536870911]	96	1			T4	1		T40	1		T30	1
auto[536870912:671088639]	85	1			T11	1		T4	1		T40	1
auto[671088640:805306367]	98	1			T3	1		T4	3		T29	1
auto[805306368:939524095]	97	1			T4	1		T15	1		T40	2
auto[939524096:1073741823]	118	1			T4	2		T40	2		T29	1
auto[1073741824:1207959551]	103	1			T46	1		T30	1		T193	1
auto[1207959552:1342177279]	100	1			T40	1		T41	2		T48	2
auto[1342177280:1476395007]	99	1			T2	1		T3	1		T4	1
auto[1476395008:1610612735]	94	1			T29	1		T46	1		T112	1
auto[1610612736:1744830463]	96	1			T2	1		T40	1		T46	1
auto[1744830464:1879048191]	108	1			T40	1		T192	1		T196	2
auto[1879048192:2013265919]	114	1			T3	1		T4	1		T40	1
auto[2013265920:2147483647]	117	1			T2	2		T3	2		T4	1
auto[2147483648:2281701375]	103	1			T3	1		T16	1		T72	1
auto[2281701376:2415919103]	106	1			T3	1		T4	2		T15	1
auto[2415919104:2550136831]	103	1			T3	1		T11	1		T40	2
auto[2550136832:2684354559]	114	1			T193	1		T48	2		T56	1
auto[2684354560:2818572287]	103	1			T4	1		T40	1		T48	1
auto[2818572288:2952790015]	100	1			T3	1		T40	1		T72	1
auto[2952790016:3087007743]	108	1			T3	1		T193	1		T114	1
auto[3087007744:3221225471]	123	1			T3	3		T4	3		T15	1
auto[3221225472:3355443199]	100	1			T4	1		T15	1		T56	5
auto[3355443200:3489660927]	114	1			T4	2		T16	1		T72	1
auto[3489660928:3623878655]	87	1			T11	1		T40	1		T197	1
auto[3623878656:3758096383]	118	1			T3	1		T40	2		T46	1
auto[3758096384:3892314111]	97	1			T15	2		T41	1		T114	1
auto[3892314112:4026531839]	98	1			T3	1		T4	3		T196	1
auto[4026531840:4160749567]	116	1			T2	1		T3	1		T4	2
auto[4160749568:4294967295]	105	1			T15	1		T16	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T16	1		T40	1		T46	1
auto[0:134217727]	auto[1]	51	1			T4	2		T66	2		T110	1
auto[134217728:268435455]	auto[0]	54	1			T40	1		T43	1		T62	1
auto[134217728:268435455]	auto[1]	47	1			T2	1		T40	2		T196	1
auto[268435456:402653183]	auto[0]	41	1			T46	1		T192	1		T38	1
auto[268435456:402653183]	auto[1]	56	1			T4	1		T40	1		T48	3
auto[402653184:536870911]	auto[0]	43	1			T30	1		T48	3		T59	1
auto[402653184:536870911]	auto[1]	53	1			T4	1		T40	1		T113	1
auto[536870912:671088639]	auto[0]	41	1			T40	1		T117	1		T239	1
auto[536870912:671088639]	auto[1]	44	1			T11	1		T4	1		T48	1
auto[671088640:805306367]	auto[0]	41	1			T3	1		T29	1		T208	1
auto[671088640:805306367]	auto[1]	57	1			T4	3		T112	1		T56	1
auto[805306368:939524095]	auto[0]	57	1			T4	1		T15	1		T197	1
auto[805306368:939524095]	auto[1]	40	1			T40	2		T113	1		T114	1
auto[939524096:1073741823]	auto[0]	51	1			T4	1		T40	1		T29	1
auto[939524096:1073741823]	auto[1]	67	1			T4	1		T40	1		T38	1
auto[1073741824:1207959551]	auto[0]	44	1			T46	1		T38	1		T48	1
auto[1073741824:1207959551]	auto[1]	59	1			T30	1		T193	1		T116	1
auto[1207959552:1342177279]	auto[0]	49	1			T40	1		T41	2		T48	2
auto[1207959552:1342177279]	auto[1]	51	1			T116	1		T56	3		T191	1
auto[1342177280:1476395007]	auto[0]	41	1			T2	1		T4	1		T15	1
auto[1342177280:1476395007]	auto[1]	58	1			T3	1		T56	1		T191	1
auto[1476395008:1610612735]	auto[0]	52	1			T29	1		T46	1		T112	1
auto[1476395008:1610612735]	auto[1]	42	1			T59	1		T265	1		T67	1
auto[1610612736:1744830463]	auto[0]	48	1			T2	1		T46	1		T48	2
auto[1610612736:1744830463]	auto[1]	48	1			T40	1		T193	1		T112	1
auto[1744830464:1879048191]	auto[0]	43	1			T48	1		T56	1		T54	1
auto[1744830464:1879048191]	auto[1]	65	1			T40	1		T192	1		T196	2
auto[1879048192:2013265919]	auto[0]	55	1			T4	1		T48	2		T59	1
auto[1879048192:2013265919]	auto[1]	59	1			T3	1		T40	1		T112	1
auto[2013265920:2147483647]	auto[0]	61	1			T3	1		T4	1		T29	1
auto[2013265920:2147483647]	auto[1]	56	1			T2	2		T3	1		T48	1
auto[2147483648:2281701375]	auto[0]	50	1			T16	1		T38	1		T48	2
auto[2147483648:2281701375]	auto[1]	53	1			T3	1		T72	1		T48	1
auto[2281701376:2415919103]	auto[0]	49	1			T4	1		T15	1		T48	1
auto[2281701376:2415919103]	auto[1]	57	1			T3	1		T4	1		T40	2
auto[2415919104:2550136831]	auto[0]	47	1			T11	1		T40	1		T48	1
auto[2415919104:2550136831]	auto[1]	56	1			T3	1		T40	1		T112	1
auto[2550136832:2684354559]	auto[0]	53	1			T193	1		T48	1		T56	1
auto[2550136832:2684354559]	auto[1]	61	1			T48	1		T66	2		T54	1
auto[2684354560:2818572287]	auto[0]	53	1			T4	1		T40	1		T56	2
auto[2684354560:2818572287]	auto[1]	50	1			T48	1		T241	1		T240	1
auto[2818572288:2952790015]	auto[0]	45	1			T40	1		T207	1		T111	1
auto[2818572288:2952790015]	auto[1]	55	1			T3	1		T72	1		T113	1
auto[2952790016:3087007743]	auto[0]	45	1			T114	1		T48	1		T56	1
auto[2952790016:3087007743]	auto[1]	63	1			T3	1		T193	1		T38	3
auto[3087007744:3221225471]	auto[0]	54	1			T4	1		T29	2		T48	2
auto[3087007744:3221225471]	auto[1]	69	1			T3	3		T4	2		T15	1
auto[3221225472:3355443199]	auto[0]	47	1			T4	1		T15	1		T47	2
auto[3221225472:3355443199]	auto[1]	53	1			T56	5		T73	1		T183	1
auto[3355443200:3489660927]	auto[0]	50	1			T72	1		T192	1		T48	1
auto[3355443200:3489660927]	auto[1]	64	1			T4	2		T16	1		T38	1
auto[3489660928:3623878655]	auto[0]	36	1			T197	1		T17	1		T60	1
auto[3489660928:3623878655]	auto[1]	51	1			T11	1		T40	1		T48	2
auto[3623878656:3758096383]	auto[0]	51	1			T38	1		T48	2		T56	1
auto[3623878656:3758096383]	auto[1]	67	1			T3	1		T40	2		T46	1
auto[3758096384:3892314111]	auto[0]	46	1			T15	1		T42	1		T241	1
auto[3758096384:3892314111]	auto[1]	51	1			T15	1		T41	1		T114	1
auto[3892314112:4026531839]	auto[0]	41	1			T3	1		T4	3		T196	1
auto[3892314112:4026531839]	auto[1]	57	1			T42	1		T50	1		T131	1
auto[4026531840:4160749567]	auto[0]	57	1			T4	2		T40	1		T46	1
auto[4026531840:4160749567]	auto[1]	59	1			T2	1		T3	1		T48	1
auto[4160749568:4294967295]	auto[0]	51	1			T15	1		T16	1		T29	1
auto[4160749568:4294967295]	auto[1]	54	1			T56	3		T59	1		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1557

1

T2

2

T3

4

T11

1

auto[1]

1754

1

T2

4

T3

12

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	82	1			T38	1		T48	3		T43	1
auto[134217728:268435455]	100	1			T3	2		T29	1		T56	3
auto[268435456:402653183]	120	1			T4	2		T40	1		T114	1
auto[402653184:536870911]	101	1			T4	1		T15	1		T40	1
auto[536870912:671088639]	113	1			T15	1		T29	1		T113	1
auto[671088640:805306367]	98	1			T2	1		T4	1		T40	2
auto[805306368:939524095]	101	1			T2	1		T114	1		T38	1
auto[939524096:1073741823]	115	1			T2	1		T4	2		T40	2
auto[1073741824:1207959551]	106	1			T4	1		T48	2		T56	2
auto[1207959552:1342177279]	105	1			T11	1		T40	2		T29	1
auto[1342177280:1476395007]	104	1			T11	1		T72	1		T192	1
auto[1476395008:1610612735]	103	1			T2	1		T3	1		T4	1
auto[1610612736:1744830463]	98	1			T4	1		T197	1		T41	1
auto[1744830464:1879048191]	99	1			T3	1		T16	1		T40	2
auto[1879048192:2013265919]	100	1			T4	1		T40	1		T196	1
auto[2013265920:2147483647]	110	1			T3	1		T46	2		T197	1
auto[2147483648:2281701375]	91	1			T4	1		T40	1		T29	1
auto[2281701376:2415919103]	111	1			T4	1		T40	1		T197	1
auto[2415919104:2550136831]	105	1			T4	1		T40	1		T72	1
auto[2550136832:2684354559]	96	1			T3	1		T4	1		T15	2
auto[2684354560:2818572287]	102	1			T3	1		T4	3		T15	1
auto[2818572288:2952790015]	108	1			T2	1		T40	2		T48	2
auto[2952790016:3087007743]	113	1			T3	1		T11	1		T4	2
auto[3087007744:3221225471]	89	1			T3	1		T4	2		T15	1
auto[3221225472:3355443199]	103	1			T3	2		T4	2		T29	1
auto[3355443200:3489660927]	98	1			T15	2		T40	1		T38	2
auto[3489660928:3623878655]	109	1			T4	1		T16	1		T29	1
auto[3623878656:3758096383]	108	1			T3	2		T4	1		T41	1
auto[3758096384:3892314111]	110	1			T4	3		T112	1		T48	5
auto[3892314112:4026531839]	97	1			T3	2		T16	1		T196	1
auto[4026531840:4160749567]	104	1			T16	1		T40	1		T193	1
auto[4160749568:4294967295]	112	1			T2	1		T3	1		T40	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T43	1		T59	1		T207	1
auto[0:134217727]	auto[1]	41	1			T38	1		T48	3		T50	1
auto[134217728:268435455]	auto[0]	38	1			T29	1		T208	1		T33	1
auto[134217728:268435455]	auto[1]	62	1			T3	2		T56	3		T50	1
auto[268435456:402653183]	auto[0]	57	1			T4	1		T40	1		T114	1
auto[268435456:402653183]	auto[1]	63	1			T4	1		T48	2		T116	1
auto[402653184:536870911]	auto[0]	44	1			T4	1		T15	1		T40	1
auto[402653184:536870911]	auto[1]	57	1			T38	1		T48	1		T241	1
auto[536870912:671088639]	auto[0]	52	1			T29	1		T48	4		T54	1
auto[536870912:671088639]	auto[1]	61	1			T15	1		T113	1		T251	1
auto[671088640:805306367]	auto[0]	44	1			T40	1		T46	1		T56	1
auto[671088640:805306367]	auto[1]	54	1			T2	1		T4	1		T40	1
auto[805306368:939524095]	auto[0]	39	1			T114	1		T38	1		T48	1
auto[805306368:939524095]	auto[1]	62	1			T2	1		T50	1		T117	1
auto[939524096:1073741823]	auto[0]	56	1			T2	1		T4	1		T40	1
auto[939524096:1073741823]	auto[1]	59	1			T4	1		T40	1		T30	1
auto[1073741824:1207959551]	auto[0]	51	1			T42	1		T27	1		T251	1
auto[1073741824:1207959551]	auto[1]	55	1			T4	1		T48	2		T56	2
auto[1207959552:1342177279]	auto[0]	45	1			T29	1		T48	2		T56	1
auto[1207959552:1342177279]	auto[1]	60	1			T11	1		T40	2		T56	1
auto[1342177280:1476395007]	auto[0]	51	1			T192	1		T41	1		T112	1
auto[1342177280:1476395007]	auto[1]	53	1			T11	1		T72	1		T112	1
auto[1476395008:1610612735]	auto[0]	43	1			T2	1		T4	1		T40	1
auto[1476395008:1610612735]	auto[1]	60	1			T3	1		T40	2		T193	1
auto[1610612736:1744830463]	auto[0]	51	1			T4	1		T41	1		T62	1
auto[1610612736:1744830463]	auto[1]	47	1			T197	1		T121	1		T403	1
auto[1744830464:1879048191]	auto[0]	50	1			T48	2		T47	1		T207	1
auto[1744830464:1879048191]	auto[1]	49	1			T3	1		T16	1		T40	2
auto[1879048192:2013265919]	auto[0]	48	1			T38	1		T56	3		T208	1
auto[1879048192:2013265919]	auto[1]	52	1			T4	1		T40	1		T196	1
auto[2013265920:2147483647]	auto[0]	50	1			T46	2		T47	1		T207	1
auto[2013265920:2147483647]	auto[1]	60	1			T3	1		T197	1		T48	1
auto[2147483648:2281701375]	auto[0]	50	1			T4	1		T29	1		T197	1
auto[2147483648:2281701375]	auto[1]	41	1			T40	1		T56	2		T28	1
auto[2281701376:2415919103]	auto[0]	47	1			T4	1		T38	1		T56	2
auto[2281701376:2415919103]	auto[1]	64	1			T40	1		T197	1		T48	4
auto[2415919104:2550136831]	auto[0]	59	1			T40	1		T72	1		T255	1
auto[2415919104:2550136831]	auto[1]	46	1			T4	1		T38	1		T48	1
auto[2550136832:2684354559]	auto[0]	41	1			T4	1		T15	2		T16	1
auto[2550136832:2684354559]	auto[1]	55	1			T3	1		T48	1		T50	2
auto[2684354560:2818572287]	auto[0]	50	1			T3	1		T4	1		T192	1
auto[2684354560:2818572287]	auto[1]	52	1			T4	2		T15	1		T40	1
auto[2818572288:2952790015]	auto[0]	48	1			T40	1		T76	1		T110	1
auto[2818572288:2952790015]	auto[1]	60	1			T2	1		T40	1		T48	2
auto[2952790016:3087007743]	auto[0]	50	1			T3	1		T11	1		T29	1
auto[2952790016:3087007743]	auto[1]	63	1			T4	2		T40	1		T38	1
auto[3087007744:3221225471]	auto[0]	44	1			T4	1		T15	1		T48	1
auto[3087007744:3221225471]	auto[1]	45	1			T3	1		T4	1		T38	1
auto[3221225472:3355443199]	auto[0]	55	1			T3	1		T4	2		T29	1
auto[3221225472:3355443199]	auto[1]	48	1			T3	1		T197	1		T193	1
auto[3355443200:3489660927]	auto[0]	46	1			T15	2		T40	1		T38	1
auto[3355443200:3489660927]	auto[1]	52	1			T38	1		T48	1		T59	1
auto[3489660928:3623878655]	auto[0]	49	1			T4	1		T16	1		T29	1
auto[3489660928:3623878655]	auto[1]	60	1			T46	1		T193	1		T48	1
auto[3623878656:3758096383]	auto[0]	47	1			T3	1		T41	1		T48	1
auto[3623878656:3758096383]	auto[1]	61	1			T3	1		T4	1		T56	1
auto[3758096384:3892314111]	auto[0]	63	1			T4	2		T48	4		T56	1
auto[3758096384:3892314111]	auto[1]	47	1			T4	1		T112	1		T48	1
auto[3892314112:4026531839]	auto[0]	49	1			T16	1		T196	1		T48	3
auto[3892314112:4026531839]	auto[1]	48	1			T3	2		T56	1		T43	1
auto[4026531840:4160749567]	auto[0]	47	1			T16	1		T48	1		T191	1
auto[4026531840:4160749567]	auto[1]	57	1			T40	1		T193	1		T112	1
auto[4160749568:4294967295]	auto[0]	52	1			T46	1		T48	3		T56	1
auto[4160749568:4294967295]	auto[1]	60	1			T2	1		T3	1		T40	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1564

1

T2

2

T3

5

T11

1

auto[1]

1746

1

T2

4

T3

11

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T4	1		T40	1		T192	2
auto[134217728:268435455]	110	1			T3	1		T4	2		T40	1
auto[268435456:402653183]	87	1			T3	2		T40	1		T113	1
auto[402653184:536870911]	108	1			T4	3		T40	2		T29	1
auto[536870912:671088639]	102	1			T4	2		T15	1		T40	1
auto[671088640:805306367]	117	1			T3	1		T4	2		T16	1
auto[805306368:939524095]	95	1			T2	1		T4	1		T72	1
auto[939524096:1073741823]	95	1			T3	1		T40	1		T197	1
auto[1073741824:1207959551]	121	1			T3	1		T11	1		T4	1
auto[1207959552:1342177279]	108	1			T3	1		T11	1		T46	1
auto[1342177280:1476395007]	124	1			T3	1		T40	1		T46	1
auto[1476395008:1610612735]	101	1			T3	1		T16	1		T40	1
auto[1610612736:1744830463]	99	1			T4	3		T197	1		T112	1
auto[1744830464:1879048191]	109	1			T2	1		T3	1		T4	5
auto[1879048192:2013265919]	120	1			T15	1		T16	1		T40	1
auto[2013265920:2147483647]	113	1			T2	1		T15	2		T193	1
auto[2147483648:2281701375]	118	1			T3	1		T4	1		T40	1
auto[2281701376:2415919103]	104	1			T15	1		T41	1		T38	1
auto[2415919104:2550136831]	93	1			T11	1		T40	1		T197	1
auto[2550136832:2684354559]	97	1			T15	1		T40	1		T196	1
auto[2684354560:2818572287]	90	1			T2	1		T3	1		T4	1
auto[2818572288:2952790015]	102	1			T2	1		T3	2		T16	1
auto[2952790016:3087007743]	91	1			T4	2		T48	2		T56	1
auto[3087007744:3221225471]	98	1			T40	1		T30	1		T48	2
auto[3221225472:3355443199]	99	1			T3	1		T4	1		T16	1
auto[3355443200:3489660927]	94	1			T3	1		T4	1		T46	1
auto[3489660928:3623878655]	106	1			T2	1		T4	1		T15	1
auto[3623878656:3758096383]	87	1			T40	1		T113	2		T48	3
auto[3758096384:3892314111]	87	1			T40	1		T193	1		T56	1
auto[3892314112:4026531839]	101	1			T4	1		T40	3		T192	1
auto[4026531840:4160749567]	118	1			T46	1		T197	1		T196	1
auto[4160749568:4294967295]	96	1			T29	1		T56	1		T50	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T192	1		T66	1		T271	1
auto[0:134217727]	auto[1]	60	1			T4	1		T40	1		T192	1
auto[134217728:268435455]	auto[0]	55	1			T4	1		T40	1		T114	1
auto[134217728:268435455]	auto[1]	55	1			T3	1		T4	1		T48	1
auto[268435456:402653183]	auto[0]	45	1			T3	1		T113	1		T38	1
auto[268435456:402653183]	auto[1]	42	1			T3	1		T40	1		T48	1
auto[402653184:536870911]	auto[0]	59	1			T4	2		T40	1		T29	1
auto[402653184:536870911]	auto[1]	49	1			T4	1		T40	1		T48	2
auto[536870912:671088639]	auto[0]	52	1			T4	1		T15	1		T40	1
auto[536870912:671088639]	auto[1]	50	1			T4	1		T196	1		T38	1
auto[671088640:805306367]	auto[0]	53	1			T4	1		T50	1		T47	1
auto[671088640:805306367]	auto[1]	64	1			T3	1		T4	1		T16	1
auto[805306368:939524095]	auto[0]	43	1			T192	1		T41	1		T56	1
auto[805306368:939524095]	auto[1]	52	1			T2	1		T4	1		T72	1
auto[939524096:1073741823]	auto[0]	41	1			T40	1		T38	1		T48	3
auto[939524096:1073741823]	auto[1]	54	1			T3	1		T197	1		T113	1
auto[1073741824:1207959551]	auto[0]	59	1			T11	1		T40	1		T29	1
auto[1073741824:1207959551]	auto[1]	62	1			T3	1		T4	1		T40	2
auto[1207959552:1342177279]	auto[0]	65	1			T46	1		T191	1		T50	1
auto[1207959552:1342177279]	auto[1]	43	1			T3	1		T11	1		T48	2
auto[1342177280:1476395007]	auto[0]	54	1			T40	1		T46	1		T41	1
auto[1342177280:1476395007]	auto[1]	70	1			T3	1		T48	1		T56	1
auto[1476395008:1610612735]	auto[0]	50	1			T3	1		T16	1		T40	1
auto[1476395008:1610612735]	auto[1]	51	1			T38	1		T56	2		T66	1
auto[1610612736:1744830463]	auto[0]	41	1			T4	2		T114	1		T56	1
auto[1610612736:1744830463]	auto[1]	58	1			T4	1		T197	1		T112	1
auto[1744830464:1879048191]	auto[0]	61	1			T2	1		T4	3		T15	1
auto[1744830464:1879048191]	auto[1]	48	1			T3	1		T4	2		T114	1
auto[1879048192:2013265919]	auto[0]	52	1			T15	1		T16	1		T40	1
auto[1879048192:2013265919]	auto[1]	68	1			T112	1		T114	1		T38	1
auto[2013265920:2147483647]	auto[0]	49	1			T15	1		T48	1		T191	2
auto[2013265920:2147483647]	auto[1]	64	1			T2	1		T15	1		T193	1
auto[2147483648:2281701375]	auto[0]	61	1			T3	1		T29	1		T56	1
auto[2147483648:2281701375]	auto[1]	57	1			T4	1		T40	1		T48	2
auto[2281701376:2415919103]	auto[0]	52	1			T15	1		T41	1		T38	1
auto[2281701376:2415919103]	auto[1]	52	1			T24	1		T54	1		T110	1
auto[2415919104:2550136831]	auto[0]	39	1			T38	1		T48	4		T59	1
auto[2415919104:2550136831]	auto[1]	54	1			T11	1		T40	1		T197	1
auto[2550136832:2684354559]	auto[0]	36	1			T40	1		T196	1		T48	1
auto[2550136832:2684354559]	auto[1]	61	1			T15	1		T38	1		T48	2
auto[2684354560:2818572287]	auto[0]	48	1			T2	1		T4	1		T40	2
auto[2684354560:2818572287]	auto[1]	42	1			T3	1		T40	1		T38	1
auto[2818572288:2952790015]	auto[0]	44	1			T3	1		T16	1		T119	1
auto[2818572288:2952790015]	auto[1]	58	1			T2	1		T3	1		T30	1
auto[2952790016:3087007743]	auto[0]	38	1			T48	2		T47	1		T207	1
auto[2952790016:3087007743]	auto[1]	53	1			T4	2		T56	1		T388	1
auto[3087007744:3221225471]	auto[0]	36	1			T30	1		T48	1		T208	1
auto[3087007744:3221225471]	auto[1]	62	1			T40	1		T48	1		T66	1
auto[3221225472:3355443199]	auto[0]	45	1			T3	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[1]	54	1			T38	1		T56	1		T50	1
auto[3355443200:3489660927]	auto[0]	39	1			T4	1		T46	1		T38	1
auto[3355443200:3489660927]	auto[1]	55	1			T3	1		T56	2		T50	1
auto[3489660928:3623878655]	auto[0]	54	1			T4	1		T15	1		T197	2
auto[3489660928:3623878655]	auto[1]	52	1			T2	1		T40	1		T72	1
auto[3623878656:3758096383]	auto[0]	37	1			T48	2		T59	1		T249	1
auto[3623878656:3758096383]	auto[1]	50	1			T40	1		T113	2		T48	1
auto[3758096384:3892314111]	auto[0]	35	1			T47	1		T76	1		T54	1
auto[3758096384:3892314111]	auto[1]	52	1			T40	1		T193	1		T56	1
auto[3892314112:4026531839]	auto[0]	52	1			T192	1		T41	1		T48	1
auto[3892314112:4026531839]	auto[1]	49	1			T4	1		T40	3		T56	2
auto[4026531840:4160749567]	auto[0]	54	1			T46	1		T48	1		T66	1
auto[4026531840:4160749567]	auto[1]	64	1			T197	1		T196	1		T48	2
auto[4160749568:4294967295]	auto[0]	55	1			T29	1		T66	1		T243	1
auto[4160749568:4294967295]	auto[1]	41	1			T56	1		T50	2		T51	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1563

1

T2

1

T3

4

T11

1

auto[1]

1748

1

T2

5

T3

12

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T4	2		T16	1		T112	1
auto[134217728:268435455]	108	1			T3	1		T4	2		T197	1
auto[268435456:402653183]	110	1			T3	2		T4	1		T72	1
auto[402653184:536870911]	90	1			T4	1		T15	1		T40	1
auto[536870912:671088639]	96	1			T2	1		T11	1		T16	1
auto[671088640:805306367]	106	1			T3	1		T193	1		T48	2
auto[805306368:939524095]	100	1			T40	2		T41	1		T48	2
auto[939524096:1073741823]	122	1			T3	1		T4	1		T40	2
auto[1073741824:1207959551]	114	1			T3	1		T4	1		T40	1
auto[1207959552:1342177279]	97	1			T4	2		T16	1		T116	1
auto[1342177280:1476395007]	102	1			T3	1		T72	1		T48	3
auto[1476395008:1610612735]	92	1			T4	1		T16	1		T40	2
auto[1610612736:1744830463]	108	1			T4	1		T15	1		T40	2
auto[1744830464:1879048191]	103	1			T3	1		T40	1		T30	1
auto[1879048192:2013265919]	104	1			T4	3		T40	1		T29	1
auto[2013265920:2147483647]	102	1			T4	1		T112	1		T48	2
auto[2147483648:2281701375]	101	1			T2	1		T11	1		T15	1
auto[2281701376:2415919103]	100	1			T2	1		T4	1		T40	1
auto[2415919104:2550136831]	101	1			T15	1		T29	1		T46	1
auto[2550136832:2684354559]	98	1			T3	2		T40	1		T46	1
auto[2684354560:2818572287]	111	1			T41	2		T38	1		T48	2
auto[2818572288:2952790015]	109	1			T2	1		T3	1		T46	1
auto[2952790016:3087007743]	111	1			T2	1		T4	2		T15	1
auto[3087007744:3221225471]	97	1			T40	2		T29	1		T197	1
auto[3221225472:3355443199]	109	1			T3	1		T4	2		T15	1
auto[3355443200:3489660927]	101	1			T2	1		T3	1		T15	1
auto[3489660928:3623878655]	101	1			T4	1		T40	1		T114	1
auto[3623878656:3758096383]	116	1			T3	2		T4	2		T29	1
auto[3758096384:3892314111]	95	1			T3	1		T11	1		T48	1
auto[3892314112:4026531839]	101	1			T72	1		T46	2		T30	1
auto[4026531840:4160749567]	101	1			T4	2		T40	2		T38	1
auto[4160749568:4294967295]	92	1			T4	2		T15	1		T40	2