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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2879 1 T2 6 T3 12 T11 3
auto[1] 244 1 T72 11 T112 2 T117 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 83 1 T2 1 T38 1 T48 2
auto[134217728:268435455] 95 1 T40 1 T41 1 T48 2
auto[268435456:402653183] 86 1 T40 1 T72 3 T112 1
auto[402653184:536870911] 111 1 T3 1 T4 1 T40 1
auto[536870912:671088639] 99 1 T4 1 T16 1 T40 1
auto[671088640:805306367] 98 1 T3 1 T4 1 T40 1
auto[805306368:939524095] 120 1 T2 2 T3 1 T15 1
auto[939524096:1073741823] 92 1 T40 1 T48 2 T56 1
auto[1073741824:1207959551] 87 1 T4 1 T15 1 T40 1
auto[1207959552:1342177279] 124 1 T3 1 T40 1 T72 2
auto[1342177280:1476395007] 104 1 T4 1 T40 2 T72 1
auto[1476395008:1610612735] 96 1 T15 1 T29 1 T46 2
auto[1610612736:1744830463] 79 1 T16 1 T40 1 T29 1
auto[1744830464:1879048191] 103 1 T4 1 T197 1 T193 1
auto[1879048192:2013265919] 97 1 T2 1 T3 1 T114 1
auto[2013265920:2147483647] 103 1 T2 1 T3 1 T4 1
auto[2147483648:2281701375] 101 1 T4 1 T113 1 T48 4
auto[2281701376:2415919103] 83 1 T15 1 T16 1 T40 1
auto[2415919104:2550136831] 99 1 T15 1 T40 2 T197 1
auto[2550136832:2684354559] 100 1 T11 1 T4 1 T16 1
auto[2684354560:2818572287] 97 1 T11 1 T4 2 T40 1
auto[2818572288:2952790015] 91 1 T3 1 T4 1 T15 2
auto[2952790016:3087007743] 103 1 T15 1 T40 1 T72 1
auto[3087007744:3221225471] 99 1 T3 1 T40 1 T48 2
auto[3221225472:3355443199] 105 1 T3 1 T4 1 T29 1
auto[3355443200:3489660927] 93 1 T3 1 T29 1 T48 3
auto[3489660928:3623878655] 93 1 T4 2 T40 2 T72 1
auto[3623878656:3758096383] 104 1 T4 2 T40 1 T29 1
auto[3758096384:3892314111] 111 1 T3 1 T38 1 T48 2
auto[3892314112:4026531839] 82 1 T2 1 T40 1 T56 2
auto[4026531840:4160749567] 91 1 T11 1 T4 2 T40 1
auto[4160749568:4294967295] 94 1 T3 1 T72 1 T113 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 79 1 T2 1 T38 1 T48 2
auto[0:134217727] auto[1] 4 1 T131 1 T258 1 T396 1
auto[134217728:268435455] auto[0] 89 1 T40 1 T41 1 T48 2
auto[134217728:268435455] auto[1] 6 1 T121 1 T258 1 T273 1
auto[268435456:402653183] auto[0] 78 1 T40 1 T72 2 T48 2
auto[268435456:402653183] auto[1] 8 1 T72 1 T112 1 T131 1
auto[402653184:536870911] auto[0] 99 1 T3 1 T4 1 T40 1
auto[402653184:536870911] auto[1] 12 1 T131 1 T121 1 T123 1
auto[536870912:671088639] auto[0] 90 1 T4 1 T16 1 T40 1
auto[536870912:671088639] auto[1] 9 1 T117 1 T123 1 T331 1
auto[671088640:805306367] auto[0] 93 1 T3 1 T4 1 T40 1
auto[671088640:805306367] auto[1] 5 1 T112 1 T172 1 T229 1
auto[805306368:939524095] auto[0] 110 1 T2 2 T3 1 T15 1
auto[805306368:939524095] auto[1] 10 1 T123 1 T331 1 T258 1
auto[939524096:1073741823] auto[0] 85 1 T40 1 T48 2 T56 1
auto[939524096:1073741823] auto[1] 7 1 T273 2 T397 1 T402 1
auto[1073741824:1207959551] auto[0] 78 1 T4 1 T15 1 T40 1
auto[1073741824:1207959551] auto[1] 9 1 T117 1 T229 1 T385 1
auto[1207959552:1342177279] auto[0] 117 1 T3 1 T40 1 T46 1
auto[1207959552:1342177279] auto[1] 7 1 T72 2 T117 1 T120 1
auto[1342177280:1476395007] auto[0] 97 1 T4 1 T40 2 T197 1
auto[1342177280:1476395007] auto[1] 7 1 T72 1 T285 2 T398 1
auto[1476395008:1610612735] auto[0] 93 1 T15 1 T29 1 T46 2
auto[1476395008:1610612735] auto[1] 3 1 T398 1 T345 1 T228 1
auto[1610612736:1744830463] auto[0] 73 1 T16 1 T40 1 T29 1
auto[1610612736:1744830463] auto[1] 6 1 T131 1 T123 1 T258 1
auto[1744830464:1879048191] auto[0] 97 1 T4 1 T197 1 T193 1
auto[1744830464:1879048191] auto[1] 6 1 T385 2 T398 1 T250 1
auto[1879048192:2013265919] auto[0] 94 1 T2 1 T3 1 T114 1
auto[1879048192:2013265919] auto[1] 3 1 T120 1 T285 1 T404 1
auto[2013265920:2147483647] auto[0] 96 1 T2 1 T3 1 T4 1
auto[2013265920:2147483647] auto[1] 7 1 T120 1 T122 1 T253 1
auto[2147483648:2281701375] auto[0] 94 1 T4 1 T113 1 T48 4
auto[2147483648:2281701375] auto[1] 7 1 T123 1 T258 1 T295 1
auto[2281701376:2415919103] auto[0] 76 1 T15 1 T16 1 T40 1
auto[2281701376:2415919103] auto[1] 7 1 T72 1 T331 1 T258 1
auto[2415919104:2550136831] auto[0] 91 1 T15 1 T40 2 T197 1
auto[2415919104:2550136831] auto[1] 8 1 T120 1 T331 3 T229 1
auto[2550136832:2684354559] auto[0] 92 1 T11 1 T4 1 T16 1
auto[2550136832:2684354559] auto[1] 8 1 T120 1 T229 1 T385 1
auto[2684354560:2818572287] auto[0] 88 1 T11 1 T4 2 T40 1
auto[2684354560:2818572287] auto[1] 9 1 T72 3 T120 1 T121 1
auto[2818572288:2952790015] auto[0] 80 1 T3 1 T4 1 T15 2
auto[2818572288:2952790015] auto[1] 11 1 T117 1 T131 1 T331 1
auto[2952790016:3087007743] auto[0] 92 1 T15 1 T40 1 T72 1
auto[2952790016:3087007743] auto[1] 11 1 T131 1 T123 1 T230 1
auto[3087007744:3221225471] auto[0] 93 1 T3 1 T40 1 T48 2
auto[3087007744:3221225471] auto[1] 6 1 T131 1 T172 1 T385 1
auto[3221225472:3355443199] auto[0] 97 1 T3 1 T4 1 T29 1
auto[3221225472:3355443199] auto[1] 8 1 T121 1 T258 1 T273 1
auto[3355443200:3489660927] auto[0] 83 1 T3 1 T29 1 T48 3
auto[3355443200:3489660927] auto[1] 10 1 T117 1 T120 1 T122 2
auto[3489660928:3623878655] auto[0] 82 1 T4 2 T40 2 T193 1
auto[3489660928:3623878655] auto[1] 11 1 T72 1 T119 1 T120 1
auto[3623878656:3758096383] auto[0] 94 1 T4 2 T40 1 T29 1
auto[3623878656:3758096383] auto[1] 10 1 T121 1 T381 1 T398 1
auto[3758096384:3892314111] auto[0] 103 1 T3 1 T38 1 T48 2
auto[3758096384:3892314111] auto[1] 8 1 T120 2 T122 1 T277 1
auto[3892314112:4026531839] auto[0] 78 1 T2 1 T40 1 T56 2
auto[3892314112:4026531839] auto[1] 4 1 T123 1 T408 1 T401 1
auto[4026531840:4160749567] auto[0] 79 1 T11 1 T4 2 T40 1
auto[4026531840:4160749567] auto[1] 12 1 T72 1 T172 1 T229 2
auto[4160749568:4294967295] auto[0] 89 1 T3 1 T113 1 T114 1
auto[4160749568:4294967295] auto[1] 5 1 T72 1 T120 1 T407 1

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