dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1548 1 T2 3 T3 4 T11 1
auto[1] 1763 1 T2 3 T3 12 T11 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 105 1 T4 3 T41 1 T113 1
auto[134217728:268435455] 107 1 T3 1 T72 1 T112 1
auto[268435456:402653183] 90 1 T3 1 T40 3 T193 1
auto[402653184:536870911] 114 1 T4 1 T40 1 T193 1
auto[536870912:671088639] 105 1 T15 2 T40 1 T48 2
auto[671088640:805306367] 111 1 T3 1 T4 2 T40 1
auto[805306368:939524095] 107 1 T11 1 T16 1 T40 1
auto[939524096:1073741823] 114 1 T2 2 T4 2 T40 1
auto[1073741824:1207959551] 115 1 T11 1 T15 1 T40 1
auto[1207959552:1342177279] 103 1 T4 1 T196 1 T114 1
auto[1342177280:1476395007] 117 1 T4 1 T40 1 T29 1
auto[1476395008:1610612735] 108 1 T4 1 T15 1 T46 1
auto[1610612736:1744830463] 89 1 T4 1 T41 1 T112 1
auto[1744830464:1879048191] 110 1 T16 1 T197 1 T48 2
auto[1879048192:2013265919] 105 1 T16 1 T40 1 T41 1
auto[2013265920:2147483647] 112 1 T4 4 T16 1 T40 1
auto[2147483648:2281701375] 93 1 T3 1 T4 2 T15 1
auto[2281701376:2415919103] 96 1 T2 2 T3 2 T4 2
auto[2415919104:2550136831] 102 1 T16 1 T29 1 T46 1
auto[2550136832:2684354559] 92 1 T3 1 T40 2 T193 2
auto[2684354560:2818572287] 99 1 T2 1 T3 1 T4 1
auto[2818572288:2952790015] 101 1 T3 3 T11 1 T48 2
auto[2952790016:3087007743] 94 1 T4 1 T40 2 T38 1
auto[3087007744:3221225471] 114 1 T4 1 T15 1 T29 1
auto[3221225472:3355443199] 110 1 T3 1 T192 1 T193 1
auto[3355443200:3489660927] 107 1 T3 2 T4 2 T15 1
auto[3489660928:3623878655] 85 1 T15 1 T46 1 T56 2
auto[3623878656:3758096383] 98 1 T40 1 T38 1 T48 4
auto[3758096384:3892314111] 110 1 T2 1 T3 1 T4 1
auto[3892314112:4026531839] 97 1 T4 1 T40 1 T29 1
auto[4026531840:4160749567] 107 1 T3 1 T4 1 T40 1
auto[4160749568:4294967295] 94 1 T40 2 T29 1 T41 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 57 1 T4 2 T41 1 T48 1
auto[0:134217727] auto[1] 48 1 T4 1 T113 1 T56 1
auto[134217728:268435455] auto[0] 45 1 T3 1 T112 1 T56 1
auto[134217728:268435455] auto[1] 62 1 T72 1 T113 1 T114 1
auto[268435456:402653183] auto[0] 42 1 T40 1 T193 1 T112 1
auto[268435456:402653183] auto[1] 48 1 T3 1 T40 2 T48 1
auto[402653184:536870911] auto[0] 59 1 T40 1 T114 1 T48 2
auto[402653184:536870911] auto[1] 55 1 T4 1 T193 1 T112 1
auto[536870912:671088639] auto[0] 42 1 T15 1 T48 2 T47 1
auto[536870912:671088639] auto[1] 63 1 T15 1 T40 1 T56 1
auto[671088640:805306367] auto[0] 65 1 T4 2 T29 1 T207 1
auto[671088640:805306367] auto[1] 46 1 T3 1 T40 1 T265 1
auto[805306368:939524095] auto[0] 49 1 T16 1 T54 1 T27 1
auto[805306368:939524095] auto[1] 58 1 T11 1 T40 1 T56 2
auto[939524096:1073741823] auto[0] 45 1 T114 1 T48 3 T62 1
auto[939524096:1073741823] auto[1] 69 1 T2 2 T4 2 T40 1
auto[1073741824:1207959551] auto[0] 51 1 T11 1 T30 1 T197 1
auto[1073741824:1207959551] auto[1] 64 1 T15 1 T40 1 T196 1
auto[1207959552:1342177279] auto[0] 55 1 T196 1 T48 1 T56 1
auto[1207959552:1342177279] auto[1] 48 1 T4 1 T114 1 T54 1
auto[1342177280:1476395007] auto[0] 60 1 T4 1 T40 1 T29 1
auto[1342177280:1476395007] auto[1] 57 1 T197 1 T48 1 T56 1
auto[1476395008:1610612735] auto[0] 45 1 T4 1 T15 1 T46 1
auto[1476395008:1610612735] auto[1] 63 1 T197 1 T38 1 T48 2
auto[1610612736:1744830463] auto[0] 40 1 T4 1 T41 1 T47 2
auto[1610612736:1744830463] auto[1] 49 1 T112 1 T38 1 T50 2
auto[1744830464:1879048191] auto[0] 56 1 T16 1 T48 1 T56 1
auto[1744830464:1879048191] auto[1] 54 1 T197 1 T48 1 T56 1
auto[1879048192:2013265919] auto[0] 43 1 T40 1 T41 1 T48 2
auto[1879048192:2013265919] auto[1] 62 1 T16 1 T112 1 T48 1
auto[2013265920:2147483647] auto[0] 49 1 T4 3 T16 1 T40 1
auto[2013265920:2147483647] auto[1] 63 1 T4 1 T62 1 T24 1
auto[2147483648:2281701375] auto[0] 41 1 T4 1 T15 1 T43 1
auto[2147483648:2281701375] auto[1] 52 1 T3 1 T4 1 T46 1
auto[2281701376:2415919103] auto[0] 43 1 T2 2 T48 1 T56 2
auto[2281701376:2415919103] auto[1] 53 1 T3 2 T4 2 T38 1
auto[2415919104:2550136831] auto[0] 47 1 T29 1 T46 1 T197 1
auto[2415919104:2550136831] auto[1] 55 1 T16 1 T196 1 T38 1
auto[2550136832:2684354559] auto[0] 40 1 T48 2 T54 1 T118 1
auto[2550136832:2684354559] auto[1] 52 1 T3 1 T40 2 T193 2
auto[2684354560:2818572287] auto[0] 42 1 T2 1 T3 1 T4 1
auto[2684354560:2818572287] auto[1] 57 1 T40 1 T72 1 T196 1
auto[2818572288:2952790015] auto[0] 56 1 T3 1 T48 1 T56 2
auto[2818572288:2952790015] auto[1] 45 1 T3 2 T11 1 T48 1
auto[2952790016:3087007743] auto[0] 36 1 T40 1 T38 1 T48 1
auto[2952790016:3087007743] auto[1] 58 1 T4 1 T40 1 T48 1
auto[3087007744:3221225471] auto[0] 66 1 T15 1 T29 1 T192 1
auto[3087007744:3221225471] auto[1] 48 1 T4 1 T48 1 T56 2
auto[3221225472:3355443199] auto[0] 56 1 T193 1 T48 1 T62 1
auto[3221225472:3355443199] auto[1] 54 1 T3 1 T192 1 T265 1
auto[3355443200:3489660927] auto[0] 43 1 T15 1 T29 1 T48 1
auto[3355443200:3489660927] auto[1] 64 1 T3 2 T4 2 T40 1
auto[3489660928:3623878655] auto[0] 40 1 T15 1 T46 1 T62 2
auto[3489660928:3623878655] auto[1] 45 1 T56 2 T249 2 T180 1
auto[3623878656:3758096383] auto[0] 36 1 T48 1 T191 1 T59 1
auto[3623878656:3758096383] auto[1] 62 1 T40 1 T38 1 T48 3
auto[3758096384:3892314111] auto[0] 60 1 T3 1 T40 1 T38 1
auto[3758096384:3892314111] auto[1] 50 1 T2 1 T4 1 T40 2
auto[3892314112:4026531839] auto[0] 43 1 T4 1 T40 1 T29 1
auto[3892314112:4026531839] auto[1] 54 1 T38 1 T56 3 T50 3
auto[4026531840:4160749567] auto[0] 54 1 T4 1 T40 1 T46 2
auto[4026531840:4160749567] auto[1] 53 1 T3 1 T56 1 T50 1
auto[4160749568:4294967295] auto[0] 42 1 T40 2 T29 1 T41 1
auto[4160749568:4294967295] auto[1] 52 1 T113 1 T38 1 T48 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%