Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 98.03 98.66 100.00 99.02 98.41 91.14


Total test records in report: 1089
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T1007 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1796347218 Jul 01 04:30:44 PM PDT 24 Jul 01 04:30:54 PM PDT 24 16861594 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2172056702 Jul 01 04:30:34 PM PDT 24 Jul 01 04:30:48 PM PDT 24 132357082 ps
T1009 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3944643888 Jul 01 04:30:52 PM PDT 24 Jul 01 04:31:00 PM PDT 24 45577643 ps
T1010 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2949098727 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:43 PM PDT 24 88886648 ps
T1011 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4245984623 Jul 01 04:30:39 PM PDT 24 Jul 01 04:30:51 PM PDT 24 237295008 ps
T1012 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1219510687 Jul 01 04:30:36 PM PDT 24 Jul 01 04:30:46 PM PDT 24 66650666 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3788355700 Jul 01 04:30:51 PM PDT 24 Jul 01 04:31:00 PM PDT 24 59706196 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.298080302 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:43 PM PDT 24 14395577 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3183749703 Jul 01 04:30:40 PM PDT 24 Jul 01 04:30:50 PM PDT 24 63737472 ps
T133 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1219167248 Jul 01 04:30:54 PM PDT 24 Jul 01 04:31:05 PM PDT 24 60245202 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3707955620 Jul 01 04:30:44 PM PDT 24 Jul 01 04:30:55 PM PDT 24 384495679 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2033875058 Jul 01 04:31:41 PM PDT 24 Jul 01 04:31:57 PM PDT 24 314947192 ps
T1018 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2842807779 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:11 PM PDT 24 76966321 ps
T1019 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.590938538 Jul 01 04:30:48 PM PDT 24 Jul 01 04:31:12 PM PDT 24 1893612446 ps
T1020 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3518455336 Jul 01 04:30:55 PM PDT 24 Jul 01 04:31:05 PM PDT 24 67407414 ps
T1021 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3260753746 Jul 01 04:30:43 PM PDT 24 Jul 01 04:30:51 PM PDT 24 211195537 ps
T1022 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2589487079 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 7412178 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1446966129 Jul 01 04:30:36 PM PDT 24 Jul 01 04:30:45 PM PDT 24 9235024 ps
T1024 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.968967313 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:44 PM PDT 24 81133093 ps
T1025 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3271429612 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 20228492 ps
T1026 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1284496015 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:59 PM PDT 24 33400585 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3388215053 Jul 01 04:30:25 PM PDT 24 Jul 01 04:30:47 PM PDT 24 189361446 ps
T1028 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1528668445 Jul 01 04:30:28 PM PDT 24 Jul 01 04:30:50 PM PDT 24 434903149 ps
T1029 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3218974497 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:06 PM PDT 24 129373549 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2587028194 Jul 01 04:30:22 PM PDT 24 Jul 01 04:30:38 PM PDT 24 20149889 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1306656136 Jul 01 04:30:45 PM PDT 24 Jul 01 04:30:56 PM PDT 24 108107192 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.28077319 Jul 01 04:30:29 PM PDT 24 Jul 01 04:30:42 PM PDT 24 30507236 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1953102048 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:47 PM PDT 24 140957032 ps
T1034 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.105702417 Jul 01 04:30:42 PM PDT 24 Jul 01 04:30:52 PM PDT 24 25905064 ps
T1035 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2226985533 Jul 01 04:30:48 PM PDT 24 Jul 01 04:30:57 PM PDT 24 71438002 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2041302441 Jul 01 04:30:35 PM PDT 24 Jul 01 04:30:46 PM PDT 24 53918557 ps
T147 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1226070900 Jul 01 04:30:46 PM PDT 24 Jul 01 04:30:57 PM PDT 24 138487015 ps
T1037 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2157067410 Jul 01 04:30:44 PM PDT 24 Jul 01 04:30:54 PM PDT 24 85616105 ps
T1038 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2408009930 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:10 PM PDT 24 17718320 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.982027163 Jul 01 04:30:39 PM PDT 24 Jul 01 04:30:50 PM PDT 24 112584463 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2573201871 Jul 01 04:30:18 PM PDT 24 Jul 01 04:30:44 PM PDT 24 479956874 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1031394229 Jul 01 04:30:19 PM PDT 24 Jul 01 04:30:36 PM PDT 24 75188175 ps
T1042 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1534533804 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 37803196 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4261840694 Jul 01 04:30:41 PM PDT 24 Jul 01 04:30:50 PM PDT 24 78504774 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2126932965 Jul 01 04:30:34 PM PDT 24 Jul 01 04:30:46 PM PDT 24 285425484 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1843334468 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:58 PM PDT 24 1109588830 ps
T1046 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2668680392 Jul 01 04:30:43 PM PDT 24 Jul 01 04:30:55 PM PDT 24 103230654 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2278410880 Jul 01 04:30:42 PM PDT 24 Jul 01 04:30:51 PM PDT 24 166955457 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2987422791 Jul 01 04:30:30 PM PDT 24 Jul 01 04:30:42 PM PDT 24 44111017 ps
T1049 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2760976407 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:08 PM PDT 24 26438931 ps
T1050 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.835541641 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:57 PM PDT 24 10248881 ps
T1051 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.364480934 Jul 01 04:30:36 PM PDT 24 Jul 01 04:30:47 PM PDT 24 58097011 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1385922671 Jul 01 04:30:18 PM PDT 24 Jul 01 04:30:36 PM PDT 24 64288481 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2588641622 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:06 PM PDT 24 13967621 ps
T140 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2200744646 Jul 01 04:30:44 PM PDT 24 Jul 01 04:31:00 PM PDT 24 405260767 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1938867618 Jul 01 04:30:43 PM PDT 24 Jul 01 04:30:53 PM PDT 24 61346184 ps
T1055 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2921823561 Jul 01 04:30:30 PM PDT 24 Jul 01 04:30:48 PM PDT 24 129061369 ps
T1056 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1178656247 Jul 01 04:30:32 PM PDT 24 Jul 01 04:30:44 PM PDT 24 27755174 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4146398006 Jul 01 04:30:31 PM PDT 24 Jul 01 04:30:44 PM PDT 24 48478278 ps
T1058 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2425797431 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:57 PM PDT 24 32012181 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3654635522 Jul 01 04:30:13 PM PDT 24 Jul 01 04:30:33 PM PDT 24 173546794 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2564191292 Jul 01 04:30:27 PM PDT 24 Jul 01 04:30:41 PM PDT 24 58677127 ps
T1061 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1094823425 Jul 01 04:30:49 PM PDT 24 Jul 01 04:31:03 PM PDT 24 2825598493 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4211621565 Jul 01 04:30:23 PM PDT 24 Jul 01 04:30:38 PM PDT 24 36643824 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.18330533 Jul 01 04:30:40 PM PDT 24 Jul 01 04:30:53 PM PDT 24 450369219 ps
T141 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.88198701 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:11 PM PDT 24 195696215 ps
T1064 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.676048069 Jul 01 04:30:45 PM PDT 24 Jul 01 04:30:57 PM PDT 24 81942768 ps
T143 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2917766507 Jul 01 04:30:43 PM PDT 24 Jul 01 04:30:58 PM PDT 24 405666862 ps
T1065 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2795150992 Jul 01 04:30:51 PM PDT 24 Jul 01 04:30:59 PM PDT 24 25326888 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4207454633 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:03 PM PDT 24 10770592 ps
T1067 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.412784318 Jul 01 04:30:37 PM PDT 24 Jul 01 04:30:48 PM PDT 24 140956388 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3127841452 Jul 01 04:30:49 PM PDT 24 Jul 01 04:31:00 PM PDT 24 174306268 ps
T1069 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2558307743 Jul 01 04:30:37 PM PDT 24 Jul 01 04:30:49 PM PDT 24 202422576 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3360171984 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:09 PM PDT 24 211534761 ps
T1071 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1927878057 Jul 01 04:30:40 PM PDT 24 Jul 01 04:31:01 PM PDT 24 372629594 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1633550341 Jul 01 04:30:34 PM PDT 24 Jul 01 04:30:45 PM PDT 24 345533037 ps
T1073 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.829617769 Jul 01 04:30:28 PM PDT 24 Jul 01 04:30:44 PM PDT 24 618443728 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1318093269 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:56 PM PDT 24 77364180 ps
T1075 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3957531998 Jul 01 04:30:54 PM PDT 24 Jul 01 04:31:03 PM PDT 24 17335808 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3002074911 Jul 01 04:30:50 PM PDT 24 Jul 01 04:30:59 PM PDT 24 46733408 ps
T145 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3695925060 Jul 01 04:30:38 PM PDT 24 Jul 01 04:30:53 PM PDT 24 213005587 ps
T1077 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1497207314 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:57 PM PDT 24 30197622 ps
T1078 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1604819035 Jul 01 04:30:43 PM PDT 24 Jul 01 04:31:00 PM PDT 24 808488797 ps
T1079 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3621581478 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 12517109 ps
T1080 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2865141044 Jul 01 04:30:54 PM PDT 24 Jul 01 04:31:02 PM PDT 24 11990662 ps
T1081 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.424726181 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:07 PM PDT 24 132215755 ps
T1082 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3040225792 Jul 01 04:30:53 PM PDT 24 Jul 01 04:31:01 PM PDT 24 18848969 ps
T1083 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.39911123 Jul 01 04:30:49 PM PDT 24 Jul 01 04:30:57 PM PDT 24 65498579 ps
T1084 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1490378866 Jul 01 04:30:45 PM PDT 24 Jul 01 04:30:59 PM PDT 24 208045307 ps
T1085 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1853959090 Jul 01 04:30:35 PM PDT 24 Jul 01 04:30:46 PM PDT 24 30516627 ps
T1086 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1992306283 Jul 01 04:30:30 PM PDT 24 Jul 01 04:30:45 PM PDT 24 564964564 ps
T1087 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1257889595 Jul 01 04:30:23 PM PDT 24 Jul 01 04:30:39 PM PDT 24 24524790 ps
T1088 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1567046076 Jul 01 04:30:28 PM PDT 24 Jul 01 04:30:57 PM PDT 24 1735445755 ps
T1089 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.191531580 Jul 01 04:30:52 PM PDT 24 Jul 01 04:31:02 PM PDT 24 48156160 ps

Test location /workspace/coverage/default/24.keymgr_stress_all.3572831678
Short name T3
Test name
Test status
Simulation time 1513758525 ps
CPU time 30.07 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:10:11 PM PDT 24
Peak memory 222684 kb
Host smart-aa532585-5cee-4050-a584-7bc26b7e3498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572831678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3572831678
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.456518957
Short name T48
Test name
Test status
Simulation time 17535444143 ps
CPU time 58.65 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:11:28 PM PDT 24
Peak memory 222416 kb
Host smart-4f5c62ea-a4d3-45bc-81f1-ad4b9c25acff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456518957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.456518957
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.361515000
Short name T8
Test name
Test status
Simulation time 1279874391 ps
CPU time 9.63 seconds
Started Jul 01 05:07:49 PM PDT 24
Finished Jul 01 05:07:59 PM PDT 24
Peak memory 230564 kb
Host smart-6fa173d4-5c60-4c76-b659-dc2347fb74d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361515000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.361515000
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.874233334
Short name T46
Test name
Test status
Simulation time 267326620 ps
CPU time 11.38 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 222404 kb
Host smart-ccbaa83e-35e3-4b6e-baae-77bad001ea3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874233334 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.874233334
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.751791956
Short name T102
Test name
Test status
Simulation time 445989443 ps
CPU time 5.91 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 219992 kb
Host smart-958c823d-7bde-4742-b1cf-7b2be872832d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751791956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.751791956
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1781177323
Short name T4
Test name
Test status
Simulation time 3482912965 ps
CPU time 29.86 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:09:05 PM PDT 24
Peak memory 215772 kb
Host smart-7ffe07d8-28c6-4bf3-9d11-4c7ed5fd1c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781177323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1781177323
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4168011862
Short name T51
Test name
Test status
Simulation time 4320468181 ps
CPU time 40.49 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:11:20 PM PDT 24
Peak memory 216176 kb
Host smart-b87cef38-1215-4c52-9955-caf186a78770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168011862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4168011862
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4278889508
Short name T42
Test name
Test status
Simulation time 103687254 ps
CPU time 1.99 seconds
Started Jul 01 05:09:59 PM PDT 24
Finished Jul 01 05:10:16 PM PDT 24
Peak memory 214292 kb
Host smart-168542f3-e3b0-4fd3-ae46-80f18859e53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278889508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4278889508
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1224211539
Short name T120
Test name
Test status
Simulation time 2638551437 ps
CPU time 138.56 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:12:11 PM PDT 24
Peak memory 220636 kb
Host smart-7583784c-f994-4c07-b23c-badff3301e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224211539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1224211539
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3733747758
Short name T66
Test name
Test status
Simulation time 509957317 ps
CPU time 9.89 seconds
Started Jul 01 05:08:50 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 222568 kb
Host smart-deb1b9a5-552c-4f74-bd03-c6f2ce3925ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733747758 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3733747758
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3563478264
Short name T7
Test name
Test status
Simulation time 103467656 ps
CPU time 4.49 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 219588 kb
Host smart-1bf5aa03-97fe-4cf3-98bb-a3c2c37e5e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563478264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3563478264
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1339449859
Short name T72
Test name
Test status
Simulation time 2625443323 ps
CPU time 23.3 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:58 PM PDT 24
Peak memory 215000 kb
Host smart-e7ce0d7c-7f73-439e-abb1-05f7b0939039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339449859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1339449859
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3467501474
Short name T35
Test name
Test status
Simulation time 171979433 ps
CPU time 3.74 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 209932 kb
Host smart-f8de5b0d-19f0-4bd9-837d-830a99dbd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467501474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3467501474
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2051610202
Short name T121
Test name
Test status
Simulation time 191341281 ps
CPU time 10.4 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 215796 kb
Host smart-8538a36d-7781-4b2f-adf0-898f5b3584ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051610202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2051610202
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1756308179
Short name T15
Test name
Test status
Simulation time 300180546 ps
CPU time 9.5 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 220260 kb
Host smart-c2ef1f03-fe97-483f-b619-127f0bdf3903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756308179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1756308179
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1001719359
Short name T295
Test name
Test status
Simulation time 535481463 ps
CPU time 27.54 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 214280 kb
Host smart-b162c2f1-ccc6-460f-aa8c-14416e0a58f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001719359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1001719359
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1076447480
Short name T56
Test name
Test status
Simulation time 711019383 ps
CPU time 22.54 seconds
Started Jul 01 05:08:20 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 216380 kb
Host smart-3e8cabf4-3772-4d03-86b4-cffda7115b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076447480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1076447480
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1755153037
Short name T107
Test name
Test status
Simulation time 185661689 ps
CPU time 2.67 seconds
Started Jul 01 04:30:33 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 213940 kb
Host smart-541551d9-52fe-4cfa-b08d-6925df822a2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755153037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1755153037
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1030028408
Short name T19
Test name
Test status
Simulation time 30168079 ps
CPU time 1.34 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 214820 kb
Host smart-1163fa80-87c9-4536-a59a-0ea17ad07146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030028408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1030028408
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4225528244
Short name T229
Test name
Test status
Simulation time 172563998 ps
CPU time 5.03 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:32 PM PDT 24
Peak memory 214428 kb
Host smart-1dfb484f-f851-41e5-9e40-489a914a63ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225528244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4225528244
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1821378399
Short name T345
Test name
Test status
Simulation time 594052041 ps
CPU time 13.37 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 215688 kb
Host smart-29faa5eb-c44b-4ad4-8931-7297c907aa76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821378399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1821378399
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1913278502
Short name T257
Test name
Test status
Simulation time 3181018937 ps
CPU time 29.64 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:11:07 PM PDT 24
Peak memory 222672 kb
Host smart-353ebb08-48bf-4e06-96ef-9dc15c1150ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913278502 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1913278502
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1585226791
Short name T30
Test name
Test status
Simulation time 178080857 ps
CPU time 2.74 seconds
Started Jul 01 05:08:05 PM PDT 24
Finished Jul 01 05:08:09 PM PDT 24
Peak memory 214296 kb
Host smart-f6ba5414-3d9b-4c08-839e-0aeee41ba297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585226791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1585226791
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.202020328
Short name T123
Test name
Test status
Simulation time 241916928 ps
CPU time 6.71 seconds
Started Jul 01 05:10:28 PM PDT 24
Finished Jul 01 05:10:49 PM PDT 24
Peak memory 214392 kb
Host smart-97979f18-2203-4900-8347-2b7539309deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202020328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.202020328
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3063125594
Short name T233
Test name
Test status
Simulation time 1067489467 ps
CPU time 40.56 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 216612 kb
Host smart-0379aec6-4aa1-4e45-bb81-a7e9e30b13d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063125594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3063125594
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1000775536
Short name T158
Test name
Test status
Simulation time 221826799 ps
CPU time 4.19 seconds
Started Jul 01 05:07:57 PM PDT 24
Finished Jul 01 05:08:03 PM PDT 24
Peak memory 218536 kb
Host smart-543ad239-face-4e8c-988b-14a852c6c946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000775536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1000775536
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1066099950
Short name T219
Test name
Test status
Simulation time 849456602 ps
CPU time 6.81 seconds
Started Jul 01 05:10:05 PM PDT 24
Finished Jul 01 05:10:27 PM PDT 24
Peak memory 220112 kb
Host smart-0c5a6212-9990-4683-b7b2-feb1c794a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066099950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1066099950
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2378793091
Short name T132
Test name
Test status
Simulation time 300189245 ps
CPU time 11.02 seconds
Started Jul 01 04:30:28 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 215956 kb
Host smart-e3f8217e-fe92-4df3-a466-9de877a2a0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378793091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2378793091
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1676249525
Short name T398
Test name
Test status
Simulation time 2791854791 ps
CPU time 40.99 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:09:17 PM PDT 24
Peak memory 214592 kb
Host smart-697b4f0d-22a6-45ac-a5c2-1a9da8f29b17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676249525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1676249525
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4053677285
Short name T23
Test name
Test status
Simulation time 259109006 ps
CPU time 3.47 seconds
Started Jul 01 05:10:11 PM PDT 24
Finished Jul 01 05:10:31 PM PDT 24
Peak memory 221576 kb
Host smart-b946adcd-257d-4b53-b9ff-c5342790a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053677285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4053677285
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2917003119
Short name T40
Test name
Test status
Simulation time 495424415 ps
CPU time 12.02 seconds
Started Jul 01 05:09:43 PM PDT 24
Finished Jul 01 05:10:02 PM PDT 24
Peak memory 220852 kb
Host smart-73f6c994-1d99-4dfc-9e7f-91f3647208a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917003119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2917003119
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3138511314
Short name T21
Test name
Test status
Simulation time 101470216 ps
CPU time 1.86 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:21 PM PDT 24
Peak memory 215792 kb
Host smart-57a76ecd-7c65-4336-bae6-762b7c9bb963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138511314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3138511314
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2246382739
Short name T39
Test name
Test status
Simulation time 111615030054 ps
CPU time 276.29 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:13:57 PM PDT 24
Peak memory 215332 kb
Host smart-8e27e0cc-100c-4332-86ef-38a0dde82ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246382739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2246382739
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3810563633
Short name T489
Test name
Test status
Simulation time 11004665 ps
CPU time 0.88 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 206060 kb
Host smart-99e34f68-255d-4057-a0ba-2ce9b0995ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810563633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3810563633
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3788776700
Short name T112
Test name
Test status
Simulation time 38399175 ps
CPU time 2.95 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 214344 kb
Host smart-36d8e060-f8c8-419b-bf8e-b4b00f9b018c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788776700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3788776700
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.954218120
Short name T186
Test name
Test status
Simulation time 2221715052 ps
CPU time 49.11 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:11:08 PM PDT 24
Peak memory 222480 kb
Host smart-28f08916-4da1-48e3-b013-13c3a7967562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954218120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.954218120
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2200744646
Short name T140
Test name
Test status
Simulation time 405260767 ps
CPU time 8.35 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205364 kb
Host smart-36ef5a03-9c7a-4cea-a409-8fc5af94b9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200744646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2200744646
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1123912305
Short name T280
Test name
Test status
Simulation time 48196337 ps
CPU time 2.14 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 214332 kb
Host smart-9a60bf96-3bba-42ee-919f-d5a00d2fada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123912305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1123912305
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3468237906
Short name T228
Test name
Test status
Simulation time 60834022 ps
CPU time 3.74 seconds
Started Jul 01 05:08:11 PM PDT 24
Finished Jul 01 05:08:16 PM PDT 24
Peak memory 214328 kb
Host smart-6a0eca33-cc07-4e12-a7bf-4c8c8a46766d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468237906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3468237906
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.4129505190
Short name T240
Test name
Test status
Simulation time 170977766 ps
CPU time 2.46 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 221844 kb
Host smart-fc0b507f-5787-48d7-8084-cc3d8596cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129505190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4129505190
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.841070343
Short name T258
Test name
Test status
Simulation time 338555188 ps
CPU time 5.66 seconds
Started Jul 01 05:08:50 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 215460 kb
Host smart-94b995f4-c15a-4242-be1e-334cea113d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841070343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.841070343
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3794404079
Short name T320
Test name
Test status
Simulation time 8221351500 ps
CPU time 186.21 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:13:39 PM PDT 24
Peak memory 222500 kb
Host smart-f806b593-b9d0-4d6a-8114-86c0ac516148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794404079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3794404079
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3707923964
Short name T250
Test name
Test status
Simulation time 53661541 ps
CPU time 4.05 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 214480 kb
Host smart-4a7b7d01-735e-4a36-b39a-e4ccd72b4a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707923964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3707923964
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1047861466
Short name T163
Test name
Test status
Simulation time 681245151 ps
CPU time 4.56 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 222720 kb
Host smart-e77d7ebe-cc2c-4779-a9db-76a05a96864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047861466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1047861466
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2583660542
Short name T54
Test name
Test status
Simulation time 4082667287 ps
CPU time 23.45 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:43 PM PDT 24
Peak memory 222768 kb
Host smart-4e7637a9-1d09-40d2-98af-c36e6d588567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583660542 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2583660542
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3711409185
Short name T202
Test name
Test status
Simulation time 1882273637 ps
CPU time 6.62 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:38 PM PDT 24
Peak memory 220772 kb
Host smart-e3decfa4-293a-4265-92b6-7b49745b7d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711409185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3711409185
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1755864216
Short name T84
Test name
Test status
Simulation time 288853211 ps
CPU time 6.91 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:49 PM PDT 24
Peak memory 214352 kb
Host smart-9acd1e42-72fa-4609-a6d1-441c92fd0ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755864216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1755864216
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1981912539
Short name T154
Test name
Test status
Simulation time 52092704 ps
CPU time 2.52 seconds
Started Jul 01 05:10:14 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 222688 kb
Host smart-6f044f3f-98e4-44ed-b3ad-416a01533f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981912539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1981912539
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3672137862
Short name T260
Test name
Test status
Simulation time 39880607 ps
CPU time 2.35 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:42 PM PDT 24
Peak memory 214296 kb
Host smart-768f99fe-802d-40dc-ab6c-500295b40c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672137862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3672137862
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3276819438
Short name T159
Test name
Test status
Simulation time 259949557 ps
CPU time 4.37 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 216912 kb
Host smart-bc8b0040-915b-4110-a01e-95a631fcda47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276819438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3276819438
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.717486792
Short name T160
Test name
Test status
Simulation time 108973494 ps
CPU time 5.29 seconds
Started Jul 01 05:08:18 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 218412 kb
Host smart-ed8c6262-9ca8-43c9-98d0-347046c3f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717486792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.717486792
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1787982816
Short name T296
Test name
Test status
Simulation time 292825532 ps
CPU time 8.06 seconds
Started Jul 01 05:08:55 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 220660 kb
Host smart-9ec0e3fc-e573-4f5b-be8e-ecf9a873a170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787982816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1787982816
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2728766936
Short name T79
Test name
Test status
Simulation time 33026373 ps
CPU time 2.48 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 214312 kb
Host smart-cf997289-01a6-4002-a132-a4ec760fdb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728766936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2728766936
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.770145644
Short name T393
Test name
Test status
Simulation time 1421691349 ps
CPU time 45.33 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:11:23 PM PDT 24
Peak memory 216756 kb
Host smart-e4fa2387-1b75-40b5-848e-e3812c28f762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770145644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.770145644
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.591581563
Short name T285
Test name
Test status
Simulation time 847688979 ps
CPU time 13.12 seconds
Started Jul 01 05:08:18 PM PDT 24
Finished Jul 01 05:08:32 PM PDT 24
Peak memory 214604 kb
Host smart-d2ce7d97-826f-4d6c-87c6-430faa5bbc4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591581563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.591581563
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4176880499
Short name T374
Test name
Test status
Simulation time 536985691 ps
CPU time 10.56 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 216004 kb
Host smart-c031c4cc-912e-4689-8497-06cea64e1464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176880499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4176880499
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3019715748
Short name T137
Test name
Test status
Simulation time 65964432 ps
CPU time 2.68 seconds
Started Jul 01 05:09:47 PM PDT 24
Finished Jul 01 05:09:59 PM PDT 24
Peak memory 210316 kb
Host smart-27add192-a4f1-4700-8e5d-c0582e98a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019715748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3019715748
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1303219224
Short name T144
Test name
Test status
Simulation time 115093848 ps
CPU time 4.68 seconds
Started Jul 01 04:30:29 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 205288 kb
Host smart-88088287-40b6-440d-a98e-294e29d3b3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303219224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1303219224
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1323642361
Short name T162
Test name
Test status
Simulation time 334435970 ps
CPU time 3.67 seconds
Started Jul 01 05:09:59 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 218284 kb
Host smart-e64bdf59-79a3-4f20-b78a-22c10022ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323642361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1323642361
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3457154646
Short name T459
Test name
Test status
Simulation time 97192749 ps
CPU time 3.64 seconds
Started Jul 01 05:08:38 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 208988 kb
Host smart-eee19e1b-6cee-4482-9bea-e7518fa950f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457154646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3457154646
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1304925586
Short name T316
Test name
Test status
Simulation time 31972706 ps
CPU time 2.27 seconds
Started Jul 01 05:08:49 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 222452 kb
Host smart-4eafaff7-43a5-4acd-b86d-5f5f7a17e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304925586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1304925586
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.510668273
Short name T799
Test name
Test status
Simulation time 301332878 ps
CPU time 19.28 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 221592 kb
Host smart-e2974153-12a8-48b5-abdf-3e1635b231ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510668273 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.510668273
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3745851409
Short name T38
Test name
Test status
Simulation time 2594497296 ps
CPU time 25.76 seconds
Started Jul 01 05:08:34 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 222664 kb
Host smart-2d85341b-57a5-4b69-81d1-ebf064475417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745851409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3745851409
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3691575832
Short name T87
Test name
Test status
Simulation time 134557128 ps
CPU time 3.83 seconds
Started Jul 01 05:10:07 PM PDT 24
Finished Jul 01 05:10:26 PM PDT 24
Peak memory 209380 kb
Host smart-7b5fb618-cabf-4791-af1b-6ad9a8e7f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691575832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3691575832
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3985775168
Short name T142
Test name
Test status
Simulation time 97971625 ps
CPU time 3.09 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 210644 kb
Host smart-293ff07c-ce7f-4d95-b3e5-00794b0cba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985775168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3985775168
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1480344473
Short name T164
Test name
Test status
Simulation time 534533109 ps
CPU time 3.37 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:28 PM PDT 24
Peak memory 222620 kb
Host smart-f200885a-c3bc-42e8-900a-192aa04148bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480344473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1480344473
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3499468150
Short name T36
Test name
Test status
Simulation time 550870735 ps
CPU time 8.8 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:08 PM PDT 24
Peak memory 230424 kb
Host smart-a8b9260c-c480-4873-8d04-9d72a7847542
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499468150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3499468150
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2168467356
Short name T157
Test name
Test status
Simulation time 472016005 ps
CPU time 4.85 seconds
Started Jul 01 05:08:18 PM PDT 24
Finished Jul 01 05:08:24 PM PDT 24
Peak memory 218344 kb
Host smart-7f136d47-e883-42b2-b749-ef4c2d3fe17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168467356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2168467356
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3199118338
Short name T397
Test name
Test status
Simulation time 92533722 ps
CPU time 5.19 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:08:03 PM PDT 24
Peak memory 214344 kb
Host smart-c7fd3971-8b55-4162-ba20-c3e190a274b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199118338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3199118338
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.30787124
Short name T277
Test name
Test status
Simulation time 181956160 ps
CPU time 3.44 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 214332 kb
Host smart-825784a0-4158-47a4-b4f9-9717bf3587de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30787124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.30787124
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2123058070
Short name T782
Test name
Test status
Simulation time 2005281668 ps
CPU time 15.27 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:09:09 PM PDT 24
Peak memory 214344 kb
Host smart-34a86b32-3851-44a6-985c-a79599bab9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123058070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2123058070
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1003300470
Short name T818
Test name
Test status
Simulation time 942326888 ps
CPU time 3.42 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 214572 kb
Host smart-4db1ac6c-534e-4e57-a440-bbe818bd48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003300470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1003300470
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1968464065
Short name T337
Test name
Test status
Simulation time 408921780 ps
CPU time 5.32 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:08 PM PDT 24
Peak memory 214284 kb
Host smart-db924124-d109-48da-9151-58e59c594e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968464065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1968464065
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3690091430
Short name T399
Test name
Test status
Simulation time 196941216 ps
CPU time 3.59 seconds
Started Jul 01 05:08:07 PM PDT 24
Finished Jul 01 05:08:12 PM PDT 24
Peak memory 214312 kb
Host smart-dd6e1a80-4099-42ad-a419-ba3750dbf42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690091430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3690091430
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3898903008
Short name T378
Test name
Test status
Simulation time 302179798 ps
CPU time 2.36 seconds
Started Jul 01 05:08:02 PM PDT 24
Finished Jul 01 05:08:06 PM PDT 24
Peak memory 210148 kb
Host smart-2dcd098d-b464-40d8-82e0-c5b81bb59651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898903008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3898903008
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1989436483
Short name T272
Test name
Test status
Simulation time 338991773 ps
CPU time 4 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 208932 kb
Host smart-a4331cb8-428f-402f-93d1-92b6c5beddea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989436483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1989436483
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2869068862
Short name T401
Test name
Test status
Simulation time 67586376 ps
CPU time 3.98 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 214376 kb
Host smart-7cee3339-ed94-4357-b666-ca4fd17917ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869068862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2869068862
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4067174959
Short name T204
Test name
Test status
Simulation time 455040467 ps
CPU time 4.17 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:31 PM PDT 24
Peak memory 214320 kb
Host smart-0f129459-329f-4c23-ba28-ff8fe5c6fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067174959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4067174959
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3903390669
Short name T146
Test name
Test status
Simulation time 326220002 ps
CPU time 5.79 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 213532 kb
Host smart-55b22009-931f-428a-b962-5263c6199d86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903390669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3903390669
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2917766507
Short name T143
Test name
Test status
Simulation time 405666862 ps
CPU time 6.38 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 213528 kb
Host smart-c7435d13-fd8d-4018-a928-bc09f7dc982c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917766507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2917766507
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1219167248
Short name T133
Test name
Test status
Simulation time 60245202 ps
CPU time 3.17 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:05 PM PDT 24
Peak memory 213680 kb
Host smart-d06c37e3-546e-4208-bd17-5fda20d9914e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219167248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1219167248
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3695925060
Short name T145
Test name
Test status
Simulation time 213005587 ps
CPU time 6.03 seconds
Started Jul 01 04:30:38 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 213672 kb
Host smart-b918dacf-5d8a-49f4-ae5d-d74b1740eb4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695925060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3695925060
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1226070900
Short name T147
Test name
Test status
Simulation time 138487015 ps
CPU time 3.36 seconds
Started Jul 01 04:30:46 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213600 kb
Host smart-a55db336-2a5a-4983-ad45-983454a42fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226070900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1226070900
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3570438383
Short name T37
Test name
Test status
Simulation time 1307726966 ps
CPU time 6.48 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:22 PM PDT 24
Peak memory 237352 kb
Host smart-dd9db762-4d01-4732-bcc9-a769da973668
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570438383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3570438383
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1883999597
Short name T181
Test name
Test status
Simulation time 200758114 ps
CPU time 2.57 seconds
Started Jul 01 05:08:38 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 214276 kb
Host smart-5b0bb964-3c2c-4261-b16b-0fe61f9d17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883999597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1883999597
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3276808381
Short name T155
Test name
Test status
Simulation time 156596268 ps
CPU time 3.01 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 218432 kb
Host smart-0880b740-7b40-45f3-aae5-07e2507d7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276808381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3276808381
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2214110191
Short name T216
Test name
Test status
Simulation time 94956458 ps
CPU time 2.61 seconds
Started Jul 01 05:07:50 PM PDT 24
Finished Jul 01 05:07:54 PM PDT 24
Peak memory 207864 kb
Host smart-aa76e0d5-8be5-4458-a7d1-70983f05ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214110191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2214110191
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2990791862
Short name T327
Test name
Test status
Simulation time 86527859 ps
CPU time 3.58 seconds
Started Jul 01 05:07:45 PM PDT 24
Finished Jul 01 05:07:50 PM PDT 24
Peak memory 206984 kb
Host smart-b4783c06-aad6-417d-bb81-0f99f8d3cd98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990791862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2990791862
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1961896400
Short name T206
Test name
Test status
Simulation time 1895783780 ps
CPU time 26.72 seconds
Started Jul 01 05:07:57 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 214432 kb
Host smart-e9d013a6-d2bb-42eb-a409-fd9db1d7b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961896400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1961896400
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.344843479
Short name T217
Test name
Test status
Simulation time 244407537 ps
CPU time 3.02 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 214368 kb
Host smart-68dad52b-a4f1-450b-935d-6381e1d1791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344843479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.344843479
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3668581413
Short name T463
Test name
Test status
Simulation time 228103838 ps
CPU time 2.83 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:48 PM PDT 24
Peak memory 207040 kb
Host smart-2cd9f15f-6aa4-439a-a25d-c28a21fa8da0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668581413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3668581413
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1599599030
Short name T313
Test name
Test status
Simulation time 129849062 ps
CPU time 2.61 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 206092 kb
Host smart-a1027519-4d08-4e3c-86a8-cba7ee03fcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599599030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1599599030
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2429938524
Short name T339
Test name
Test status
Simulation time 63718237 ps
CPU time 2.7 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 214344 kb
Host smart-0fb65f8d-cacc-4778-8580-8f2552117f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429938524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2429938524
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1660933719
Short name T1
Test name
Test status
Simulation time 24995810 ps
CPU time 1.96 seconds
Started Jul 01 05:08:03 PM PDT 24
Finished Jul 01 05:08:07 PM PDT 24
Peak memory 206984 kb
Host smart-0dfe448f-417b-4c2e-8fff-8bed2f29967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660933719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1660933719
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3052660574
Short name T209
Test name
Test status
Simulation time 296468587 ps
CPU time 3.02 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 215664 kb
Host smart-7ef637ca-2ab4-46dc-a5dd-37ef2b6ac82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052660574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3052660574
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3935407985
Short name T205
Test name
Test status
Simulation time 266580367 ps
CPU time 5.57 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 214336 kb
Host smart-6ad324fb-f3dd-4a3f-83f5-5670f79aa96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935407985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3935407985
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2129527726
Short name T210
Test name
Test status
Simulation time 93570400 ps
CPU time 3.61 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 222464 kb
Host smart-47684b81-719b-44ce-95b4-ba0dddff8db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129527726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2129527726
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3723134713
Short name T224
Test name
Test status
Simulation time 280544998 ps
CPU time 3.74 seconds
Started Jul 01 05:09:26 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 208608 kb
Host smart-634e03c1-1216-4a2d-979e-5feb11e39eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723134713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3723134713
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1198896152
Short name T221
Test name
Test status
Simulation time 158374240 ps
CPU time 2.93 seconds
Started Jul 01 05:09:14 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 214352 kb
Host smart-0a2366e4-eb6c-411d-92e7-e1437525d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198896152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1198896152
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2176485008
Short name T909
Test name
Test status
Simulation time 1008584097 ps
CPU time 41.05 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 221560 kb
Host smart-4bb3abd8-3e60-4f69-bc81-3451a4ab7b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176485008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2176485008
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2246371596
Short name T218
Test name
Test status
Simulation time 706669095 ps
CPU time 22.05 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:48 PM PDT 24
Peak memory 221200 kb
Host smart-ff34fd9d-fb71-4ede-b296-4aebe18b1e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246371596 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2246371596
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.360993051
Short name T361
Test name
Test status
Simulation time 98882885 ps
CPU time 3.68 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:27 PM PDT 24
Peak memory 209224 kb
Host smart-773a5655-08e9-4e05-af5f-feae41b9db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360993051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.360993051
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3538567990
Short name T892
Test name
Test status
Simulation time 60565138 ps
CPU time 3.2 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 222388 kb
Host smart-4fae9637-609e-4116-85df-8fa926a6a305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538567990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3538567990
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1685218404
Short name T211
Test name
Test status
Simulation time 3876008255 ps
CPU time 41.61 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:58 PM PDT 24
Peak memory 222500 kb
Host smart-76a52955-7fa2-42ae-985a-335737d1109d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685218404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1685218404
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.267281491
Short name T223
Test name
Test status
Simulation time 307283267 ps
CPU time 20.47 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:48 PM PDT 24
Peak memory 222916 kb
Host smart-526b26df-d120-4a31-903c-a6349965dfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267281491 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.267281491
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3357494232
Short name T161
Test name
Test status
Simulation time 73047318 ps
CPU time 2.99 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 222732 kb
Host smart-6fcd862f-067d-4a5b-8e67-9eeb1db64cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357494232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3357494232
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1028577790
Short name T969
Test name
Test status
Simulation time 875899075 ps
CPU time 5.34 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:43 PM PDT 24
Peak memory 205452 kb
Host smart-acb88b7a-19db-4ac5-8c4d-7a07b46e0e07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028577790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
028577790
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.138588693
Short name T380
Test name
Test status
Simulation time 1964712374 ps
CPU time 8.35 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 205392 kb
Host smart-f13c9608-f290-47ee-ab77-bc37630d95b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138588693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.138588693
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1688541921
Short name T929
Test name
Test status
Simulation time 129154124 ps
CPU time 0.94 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 205280 kb
Host smart-2c38953c-802a-414d-b871-dab645a63860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688541921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
688541921
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2564191292
Short name T1060
Test name
Test status
Simulation time 58677127 ps
CPU time 1.18 seconds
Started Jul 01 04:30:27 PM PDT 24
Finished Jul 01 04:30:41 PM PDT 24
Peak memory 205688 kb
Host smart-b6ff977e-d5ad-495c-b228-758f6deca028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564191292 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2564191292
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4259804478
Short name T987
Test name
Test status
Simulation time 83286227 ps
CPU time 1.19 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:30:31 PM PDT 24
Peak memory 205396 kb
Host smart-f1c0d9c3-7394-4d92-acfb-1dd54526ef70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259804478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4259804478
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.867069959
Short name T952
Test name
Test status
Simulation time 13335681 ps
CPU time 0.74 seconds
Started Jul 01 04:30:19 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 205180 kb
Host smart-de4d5905-92bd-4fd3-8d2d-21b4551a4a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867069959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.867069959
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2869727208
Short name T130
Test name
Test status
Simulation time 504973418 ps
CPU time 2.89 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:40 PM PDT 24
Peak memory 205436 kb
Host smart-1db27f9e-f79d-4872-be55-e9392fca9f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869727208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2869727208
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3654635522
Short name T1059
Test name
Test status
Simulation time 173546794 ps
CPU time 2.57 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 214136 kb
Host smart-c215be44-169f-4f17-b576-ae6f8487fadc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654635522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3654635522
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3388215053
Short name T1027
Test name
Test status
Simulation time 189361446 ps
CPU time 8.79 seconds
Started Jul 01 04:30:25 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 213912 kb
Host smart-002d90e0-cd18-4d93-bc6a-9142754c9e3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388215053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3388215053
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.283843115
Short name T938
Test name
Test status
Simulation time 120696702 ps
CPU time 4.39 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:41 PM PDT 24
Peak memory 213696 kb
Host smart-7444305b-3502-44c2-b7b5-05046b29462c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283843115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.283843115
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2573201871
Short name T1040
Test name
Test status
Simulation time 479956874 ps
CPU time 10.1 seconds
Started Jul 01 04:30:18 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 205628 kb
Host smart-405819ac-1320-4ea0-9a4d-75e51954732e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573201871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
573201871
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2915494719
Short name T953
Test name
Test status
Simulation time 1165575327 ps
CPU time 27.39 seconds
Started Jul 01 04:30:18 PM PDT 24
Finished Jul 01 04:31:02 PM PDT 24
Peak memory 205588 kb
Host smart-8c84521c-ea37-44f5-8ade-d57059dac58f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915494719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
915494719
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.785437311
Short name T1006
Test name
Test status
Simulation time 14561718 ps
CPU time 0.9 seconds
Started Jul 01 04:30:27 PM PDT 24
Finished Jul 01 04:30:40 PM PDT 24
Peak memory 205420 kb
Host smart-367d7323-965e-4214-8945-65f335701192
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785437311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.785437311
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2508413252
Short name T947
Test name
Test status
Simulation time 118815914 ps
CPU time 1.21 seconds
Started Jul 01 04:30:29 PM PDT 24
Finished Jul 01 04:30:42 PM PDT 24
Peak memory 213780 kb
Host smart-5dfc0115-b93e-4d51-9699-dbaa2ea6511c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508413252 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2508413252
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2587028194
Short name T1030
Test name
Test status
Simulation time 20149889 ps
CPU time 1.02 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 205484 kb
Host smart-2c04fa0b-9e2b-4ddc-8e9e-cd1d1327c0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587028194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2587028194
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1031394229
Short name T1041
Test name
Test status
Simulation time 75188175 ps
CPU time 0.81 seconds
Started Jul 01 04:30:19 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 205284 kb
Host smart-ff0d9221-9963-4624-b990-1a28e51b99f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031394229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1031394229
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3131152318
Short name T992
Test name
Test status
Simulation time 263584879 ps
CPU time 1.69 seconds
Started Jul 01 04:30:20 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 205376 kb
Host smart-f396bb18-2aeb-485b-8552-f4bce8cddfc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131152318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3131152318
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1385922671
Short name T1052
Test name
Test status
Simulation time 64288481 ps
CPU time 1.72 seconds
Started Jul 01 04:30:18 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 213988 kb
Host smart-c34d7125-d3a1-4af1-b117-fc8cabd910dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385922671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1385922671
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3809337733
Short name T979
Test name
Test status
Simulation time 367404507 ps
CPU time 4.9 seconds
Started Jul 01 04:30:17 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 220012 kb
Host smart-40389ff9-7d1e-498c-9371-13c29c9a519a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809337733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3809337733
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3719303493
Short name T976
Test name
Test status
Simulation time 171324445 ps
CPU time 2.95 seconds
Started Jul 01 04:30:17 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 213716 kb
Host smart-0d2387c0-faef-410b-8000-4fce3693b1a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719303493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3719303493
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.996306778
Short name T949
Test name
Test status
Simulation time 222598807 ps
CPU time 5.22 seconds
Started Jul 01 04:30:20 PM PDT 24
Finished Jul 01 04:30:41 PM PDT 24
Peak memory 213592 kb
Host smart-86e3d1f0-68da-40b9-a93f-93b4603c994e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996306778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
996306778
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1796347218
Short name T1007
Test name
Test status
Simulation time 16861594 ps
CPU time 1.48 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 213724 kb
Host smart-82eb5d7a-1fc4-4df6-a46c-d68b8d13dd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796347218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1796347218
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3221435846
Short name T923
Test name
Test status
Simulation time 57458780 ps
CPU time 0.93 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:52 PM PDT 24
Peak memory 205260 kb
Host smart-83d24a10-e985-42da-86f4-842005a67151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221435846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3221435846
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4207454633
Short name T1066
Test name
Test status
Simulation time 10770592 ps
CPU time 0.67 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 205172 kb
Host smart-b1cbfa7a-95fc-41e9-a9fd-5ff4cdc54797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207454633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4207454633
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3607193525
Short name T998
Test name
Test status
Simulation time 226348682 ps
CPU time 2.51 seconds
Started Jul 01 04:30:46 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 205064 kb
Host smart-7e140b6d-e087-49d0-b3c4-5cd846404998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607193525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3607193525
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2278410880
Short name T1047
Test name
Test status
Simulation time 166955457 ps
CPU time 1.5 seconds
Started Jul 01 04:30:42 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 213888 kb
Host smart-f9cc6cb5-db5c-4120-a0c5-666f697d2f2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278410880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2278410880
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1973928937
Short name T106
Test name
Test status
Simulation time 606343377 ps
CPU time 6.65 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213924 kb
Host smart-f0f9605c-e51d-4068-947d-f37f6577e605
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973928937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1973928937
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3100042006
Short name T932
Test name
Test status
Simulation time 115093391 ps
CPU time 3.07 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:51 PM PDT 24
Peak memory 215684 kb
Host smart-023a4721-a99e-4fa7-a059-ba3c1489b443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100042006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3100042006
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1604819035
Short name T1078
Test name
Test status
Simulation time 808488797 ps
CPU time 9.65 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 222008 kb
Host smart-729ccefe-c54a-40fe-bb88-b9964ae3e41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604819035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1604819035
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3877251566
Short name T379
Test name
Test status
Simulation time 97825648 ps
CPU time 2 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 213656 kb
Host smart-410c7eb2-4406-4423-a015-8cec177810bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877251566 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3877251566
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2157067410
Short name T1037
Test name
Test status
Simulation time 85616105 ps
CPU time 1.09 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 205328 kb
Host smart-fa3cb3e0-d6dd-4c0e-884e-d0a5819ee3d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157067410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2157067410
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2935856044
Short name T931
Test name
Test status
Simulation time 9342293 ps
CPU time 0.67 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 205244 kb
Host smart-dbc48182-e515-4f09-a118-f0113a4d34d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935856044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2935856044
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1938867618
Short name T1054
Test name
Test status
Simulation time 61346184 ps
CPU time 2.01 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 205416 kb
Host smart-2177a6f4-1b22-4b93-8c5f-e0fa9933b57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938867618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1938867618
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2718894646
Short name T103
Test name
Test status
Simulation time 144730105 ps
CPU time 4 seconds
Started Jul 01 04:30:41 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 213956 kb
Host smart-aab66761-830f-4a83-9a43-986d200175a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718894646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2718894646
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3420341078
Short name T983
Test name
Test status
Simulation time 295136106 ps
CPU time 2.73 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 213692 kb
Host smart-b8e4d17e-a185-46fe-bde0-1d855c25c6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420341078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3420341078
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2149720454
Short name T943
Test name
Test status
Simulation time 108613074 ps
CPU time 2.58 seconds
Started Jul 01 04:30:47 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213496 kb
Host smart-c5d9efc8-71f9-4afd-803c-265d8b75541f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149720454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2149720454
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1526137946
Short name T165
Test name
Test status
Simulation time 479929130 ps
CPU time 1.51 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 213696 kb
Host smart-1efd76f6-c5e9-40c1-afb6-33bb23acf32c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526137946 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1526137946
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3260753746
Short name T1021
Test name
Test status
Simulation time 211195537 ps
CPU time 1.1 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 205560 kb
Host smart-a9a483cd-2faa-4757-81c3-352a03057fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260753746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3260753746
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4261840694
Short name T1043
Test name
Test status
Simulation time 78504774 ps
CPU time 0.79 seconds
Started Jul 01 04:30:41 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 205284 kb
Host smart-f8874a22-887b-4bc6-858a-aea1cee09d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261840694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4261840694
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3727935953
Short name T945
Test name
Test status
Simulation time 66053464 ps
CPU time 2.35 seconds
Started Jul 01 04:30:46 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 205224 kb
Host smart-2f07bb8e-b362-443f-8ff1-dedb7d44a3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727935953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3727935953
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3707955620
Short name T1016
Test name
Test status
Simulation time 384495679 ps
CPU time 3.38 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 213872 kb
Host smart-676b74e5-bb26-40fc-bc14-63e818800b4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707955620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3707955620
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2668680392
Short name T1046
Test name
Test status
Simulation time 103230654 ps
CPU time 3.94 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 213908 kb
Host smart-8b8c0e6b-69cc-4594-87ed-46984eee17dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668680392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2668680392
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.676048069
Short name T1064
Test name
Test status
Simulation time 81942768 ps
CPU time 2.9 seconds
Started Jul 01 04:30:45 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213524 kb
Host smart-4914daaf-5e66-444c-b6cc-eaf52a3e7a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676048069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.676048069
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3236547009
Short name T135
Test name
Test status
Simulation time 296913339 ps
CPU time 4.2 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 213572 kb
Host smart-fee570f9-9f81-472f-9f07-45cc47221f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236547009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3236547009
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3658515900
Short name T991
Test name
Test status
Simulation time 21246140 ps
CPU time 1.28 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:52 PM PDT 24
Peak memory 213620 kb
Host smart-ea04cc28-e65d-4bb8-8470-5c6ff46b283a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658515900 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3658515900
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2702062561
Short name T948
Test name
Test status
Simulation time 147934780 ps
CPU time 1.22 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 205520 kb
Host smart-ead9f032-3397-43fc-b8e3-9b6d53c6adc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702062561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2702062561
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.385573098
Short name T955
Test name
Test status
Simulation time 12473836 ps
CPU time 0.72 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 205288 kb
Host smart-336fae8c-f922-425e-a090-4bbb24d05b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385573098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.385573098
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2506672068
Short name T965
Test name
Test status
Simulation time 468961102 ps
CPU time 3.03 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:56 PM PDT 24
Peak memory 205288 kb
Host smart-78c26384-9a0d-41ff-955c-536eca6c6a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506672068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2506672068
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2981743383
Short name T980
Test name
Test status
Simulation time 2256896408 ps
CPU time 2.94 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 213884 kb
Host smart-38d7827c-219c-4036-b23f-29fea066ef4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981743383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2981743383
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2033875058
Short name T1017
Test name
Test status
Simulation time 314947192 ps
CPU time 4.28 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:57 PM PDT 24
Peak memory 213976 kb
Host smart-eb76a27a-4e7c-4c3d-9bd4-ce2da1dcd743
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033875058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2033875058
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.888907703
Short name T924
Test name
Test status
Simulation time 132373140 ps
CPU time 2.58 seconds
Started Jul 01 04:30:45 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 213696 kb
Host smart-1d19a841-871e-447b-8dec-cadc14174ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888907703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.888907703
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3002074911
Short name T1076
Test name
Test status
Simulation time 46733408 ps
CPU time 1.53 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 205536 kb
Host smart-0abe13be-e6d7-4140-94cc-ebe507258633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002074911 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3002074911
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.39911123
Short name T1083
Test name
Test status
Simulation time 65498579 ps
CPU time 0.93 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205244 kb
Host smart-ad8e4a9c-ba4b-4c37-9791-0cb57f61e6c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.39911123
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.835541641
Short name T1050
Test name
Test status
Simulation time 10248881 ps
CPU time 0.69 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205392 kb
Host smart-ddcc7935-0f5c-40f0-a346-6121eba7584e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835541641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.835541641
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2226985533
Short name T1035
Test name
Test status
Simulation time 71438002 ps
CPU time 2.42 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205496 kb
Host smart-589953e1-b03b-4174-b232-2039030025f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226985533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2226985533
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1306656136
Short name T1031
Test name
Test status
Simulation time 108107192 ps
CPU time 2.42 seconds
Started Jul 01 04:30:45 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 213892 kb
Host smart-ba5e9fe5-c979-4933-a0cf-b247dfd66a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306656136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1306656136
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1337878349
Short name T995
Test name
Test status
Simulation time 525000696 ps
CPU time 15.66 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 213872 kb
Host smart-fb3ae870-25e6-44c9-8f91-7b950c0082d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337878349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1337878349
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3480139809
Short name T927
Test name
Test status
Simulation time 45907358 ps
CPU time 3.12 seconds
Started Jul 01 04:31:39 PM PDT 24
Finished Jul 01 04:31:54 PM PDT 24
Peak memory 213460 kb
Host smart-1f6ca6f3-0963-4d72-bac8-45897bad9859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480139809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3480139809
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2202110949
Short name T981
Test name
Test status
Simulation time 91139443 ps
CPU time 1.72 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 219556 kb
Host smart-4ab8336b-5cc3-488f-8a79-a4cf2d0572b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202110949 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2202110949
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.940073113
Short name T958
Test name
Test status
Simulation time 52069284 ps
CPU time 1.05 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205384 kb
Host smart-b9005e36-1dda-4c54-ba8b-78664a5b5986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940073113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.940073113
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1497207314
Short name T1077
Test name
Test status
Simulation time 30197622 ps
CPU time 0.77 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205312 kb
Host smart-c1cb8c45-a8e9-45ae-9263-ff0c13ef3f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497207314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1497207314
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3204917697
Short name T1005
Test name
Test status
Simulation time 67881939 ps
CPU time 2.07 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 205524 kb
Host smart-ff664f6c-19e0-4bac-8b22-75812985a125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204917697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3204917697
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3422306103
Short name T108
Test name
Test status
Simulation time 314360319 ps
CPU time 1.92 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213876 kb
Host smart-c6780cf3-125a-4b06-acdb-2b4e3fbe33ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422306103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3422306103
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.193275130
Short name T999
Test name
Test status
Simulation time 148267345 ps
CPU time 5.3 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 213972 kb
Host smart-7968e572-3dab-4eae-83f5-f6ae73ce1480
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193275130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.193275130
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.377792437
Short name T926
Test name
Test status
Simulation time 110323052 ps
CPU time 2.64 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:04 PM PDT 24
Peak memory 213728 kb
Host smart-40f53962-ae4d-47aa-87f7-1cbab97edf89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377792437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.377792437
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.88198701
Short name T141
Test name
Test status
Simulation time 195696215 ps
CPU time 2.8 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 205412 kb
Host smart-4456a58a-6274-469c-bcf2-5af26e6517e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88198701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.88198701
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.424726181
Short name T1081
Test name
Test status
Simulation time 132215755 ps
CPU time 1.53 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 213744 kb
Host smart-25cddf8f-b86e-4452-8969-7e168027544e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424726181 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.424726181
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.914989103
Short name T935
Test name
Test status
Simulation time 25050269 ps
CPU time 1.46 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205524 kb
Host smart-b7cb9aea-e482-4498-aaba-e586a06cb05f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914989103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.914989103
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.612599272
Short name T989
Test name
Test status
Simulation time 49018068 ps
CPU time 0.84 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205388 kb
Host smart-066f5bf2-a2fb-4730-84d4-d17687e84ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612599272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.612599272
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3899678333
Short name T127
Test name
Test status
Simulation time 142811927 ps
CPU time 2.58 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 205632 kb
Host smart-ba71d84f-8c04-48a2-9c2e-5bf1cb9dc50c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899678333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3899678333
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2444856159
Short name T104
Test name
Test status
Simulation time 78317016 ps
CPU time 2.39 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 218120 kb
Host smart-8854e6ac-9c81-4749-b207-c9490d426946
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444856159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2444856159
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3360171984
Short name T1070
Test name
Test status
Simulation time 211534761 ps
CPU time 3.62 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 213988 kb
Host smart-a601be16-8178-441c-a58d-ac731a34ffd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360171984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3360171984
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.191531580
Short name T1089
Test name
Test status
Simulation time 48156160 ps
CPU time 3.02 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:02 PM PDT 24
Peak memory 213768 kb
Host smart-41080e9b-1818-441d-b032-48c2435836bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191531580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.191531580
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.257449613
Short name T951
Test name
Test status
Simulation time 139710303 ps
CPU time 5.51 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:04 PM PDT 24
Peak memory 213572 kb
Host smart-84e1bd27-5d24-4955-9489-118d7c6d7d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257449613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.257449613
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.760685974
Short name T919
Test name
Test status
Simulation time 74349361 ps
CPU time 1.24 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 205572 kb
Host smart-cd333e00-f448-413e-90c4-144b6770c6c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760685974 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.760685974
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2588641622
Short name T1053
Test name
Test status
Simulation time 13967621 ps
CPU time 1.11 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 205500 kb
Host smart-f05b4f35-a6cd-4912-b847-841a90ac70a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588641622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2588641622
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1318093269
Short name T1074
Test name
Test status
Simulation time 77364180 ps
CPU time 0.72 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 205288 kb
Host smart-681f8ad7-8adc-42c8-a958-8f26d3d58a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318093269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1318093269
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4200808784
Short name T129
Test name
Test status
Simulation time 469694411 ps
CPU time 3.04 seconds
Started Jul 01 04:30:53 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 205332 kb
Host smart-b6e38d34-9b3b-4e44-ad3f-e444d4a08740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200808784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4200808784
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.701070547
Short name T973
Test name
Test status
Simulation time 180080800 ps
CPU time 2.74 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 213944 kb
Host smart-9f8743b6-b5d2-4577-90e2-e2c34a153ddf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701070547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.701070547
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.590938538
Short name T1019
Test name
Test status
Simulation time 1893612446 ps
CPU time 16.34 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 214168 kb
Host smart-adc5eba8-2a38-4bac-9af4-4a1c188c47c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590938538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.590938538
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1284496015
Short name T1026
Test name
Test status
Simulation time 33400585 ps
CPU time 2.39 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 216672 kb
Host smart-d98d4c8c-51c1-4e96-8b0e-16146d47ecb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284496015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1284496015
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2343910973
Short name T937
Test name
Test status
Simulation time 58964887 ps
CPU time 1.55 seconds
Started Jul 01 04:30:48 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213772 kb
Host smart-90e1556d-52c4-4bb8-b718-7a1d44ce1f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343910973 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2343910973
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3218974497
Short name T1029
Test name
Test status
Simulation time 129373549 ps
CPU time 1.34 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 205400 kb
Host smart-2b8df1b3-d5d4-43fd-9362-b5bb50f07615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218974497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3218974497
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1012147261
Short name T922
Test name
Test status
Simulation time 11676024 ps
CPU time 0.8 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:05 PM PDT 24
Peak memory 205208 kb
Host smart-38e9babb-ad79-4306-9a80-611302c155e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012147261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1012147261
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1071858552
Short name T964
Test name
Test status
Simulation time 152189032 ps
CPU time 2.36 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:01 PM PDT 24
Peak memory 205348 kb
Host smart-a2d64be5-592a-4d7c-b1fe-c2c7ac1be5f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071858552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1071858552
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3771953192
Short name T975
Test name
Test status
Simulation time 402767679 ps
CPU time 2.58 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 213936 kb
Host smart-7ab9cceb-a1af-435e-b0a9-5875348fca7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771953192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3771953192
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3423649388
Short name T960
Test name
Test status
Simulation time 1861607035 ps
CPU time 17.35 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 213920 kb
Host smart-93fe2050-fa7c-433b-92df-44d9907ae161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423649388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3423649388
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1297874917
Short name T928
Test name
Test status
Simulation time 157808337 ps
CPU time 2.61 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 213744 kb
Host smart-8cf9fe35-c16f-446d-b9ac-6bd8970069b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297874917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1297874917
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1094823425
Short name T1061
Test name
Test status
Simulation time 2825598493 ps
CPU time 7.11 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 213904 kb
Host smart-9f7b3a90-b070-4719-ab6b-893c113dd715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094823425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1094823425
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3752033892
Short name T990
Test name
Test status
Simulation time 72862636 ps
CPU time 2.21 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 213668 kb
Host smart-71a20da3-15cb-49c5-a5b6-07daa469f990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752033892 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3752033892
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1898068998
Short name T1003
Test name
Test status
Simulation time 53874912 ps
CPU time 1.19 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 205592 kb
Host smart-56769a47-460f-4268-904e-d1056abdcb0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898068998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1898068998
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.906789900
Short name T934
Test name
Test status
Simulation time 11179993 ps
CPU time 0.84 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 205224 kb
Host smart-7b3a3a9e-82b8-4e2e-8ce3-6b26bab9ff48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906789900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.906789900
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3127841452
Short name T1068
Test name
Test status
Simulation time 174306268 ps
CPU time 3.63 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205400 kb
Host smart-c38bd967-f7bc-446d-8756-3f33a6c1e60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127841452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3127841452
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3788355700
Short name T1013
Test name
Test status
Simulation time 59706196 ps
CPU time 1.44 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 218184 kb
Host smart-e2435a8e-8292-47c3-875c-5f480ffe5cfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788355700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3788355700
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3020902440
Short name T109
Test name
Test status
Simulation time 398214596 ps
CPU time 8.94 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 213836 kb
Host smart-277cbb61-6ef0-4837-b1de-d562867f3689
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020902440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3020902440
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3799706116
Short name T982
Test name
Test status
Simulation time 24326115 ps
CPU time 1.73 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:02 PM PDT 24
Peak memory 213716 kb
Host smart-d1f06490-3f72-446a-8075-c8979b788037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799706116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3799706116
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1916743369
Short name T993
Test name
Test status
Simulation time 189061428 ps
CPU time 4.62 seconds
Started Jul 01 04:30:34 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 205632 kb
Host smart-2c7090d7-ecb0-49cd-af40-e7de166c1496
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916743369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
916743369
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2921823561
Short name T1055
Test name
Test status
Simulation time 129061369 ps
CPU time 6.11 seconds
Started Jul 01 04:30:30 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 205588 kb
Host smart-769819c6-9dbc-4caa-a52c-a7d6bbe56dac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921823561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
921823561
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3720871539
Short name T959
Test name
Test status
Simulation time 265307826 ps
CPU time 0.95 seconds
Started Jul 01 04:30:21 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 205256 kb
Host smart-78a64a92-e8f8-4341-9eb9-530f2f503598
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720871539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
720871539
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.982027163
Short name T1039
Test name
Test status
Simulation time 112584463 ps
CPU time 2.21 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 217980 kb
Host smart-104745fa-1364-48b9-b045-4a2cc8646ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982027163 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.982027163
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2148715467
Short name T124
Test name
Test status
Simulation time 21192101 ps
CPU time 1.29 seconds
Started Jul 01 04:30:33 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 205532 kb
Host smart-8c53b69f-ca83-4641-87a4-85dc63835d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148715467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2148715467
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4211621565
Short name T1062
Test name
Test status
Simulation time 36643824 ps
CPU time 0.74 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 205372 kb
Host smart-bc2d38e1-0fb0-49aa-9dab-0af47ffa7aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211621565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4211621565
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.968967313
Short name T1024
Test name
Test status
Simulation time 81133093 ps
CPU time 1.39 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 205620 kb
Host smart-b0d1adcd-164d-4739-9d7c-7c6ff5a27be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968967313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.968967313
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1953102048
Short name T1033
Test name
Test status
Simulation time 140957032 ps
CPU time 4.14 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 213928 kb
Host smart-673e59c3-5b21-49ae-bb07-5271b667d2cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953102048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1953102048
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1528668445
Short name T1028
Test name
Test status
Simulation time 434903149 ps
CPU time 10.29 seconds
Started Jul 01 04:30:28 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 220972 kb
Host smart-ab25ce54-bedd-4dd1-90cc-43769fe842f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528668445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1528668445
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2727023092
Short name T970
Test name
Test status
Simulation time 90109890 ps
CPU time 2.36 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 213604 kb
Host smart-2e659d3e-605e-4924-8156-b5325e133ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727023092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2727023092
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2795150992
Short name T1065
Test name
Test status
Simulation time 25326888 ps
CPU time 0.83 seconds
Started Jul 01 04:30:51 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 205312 kb
Host smart-4b6ecdfe-51f5-4061-83f9-077f384682b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795150992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2795150992
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3518455336
Short name T1020
Test name
Test status
Simulation time 67407414 ps
CPU time 0.72 seconds
Started Jul 01 04:30:55 PM PDT 24
Finished Jul 01 04:31:05 PM PDT 24
Peak memory 205284 kb
Host smart-afe1e813-e1fa-4913-9830-36c9865c0cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518455336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3518455336
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3040225792
Short name T1082
Test name
Test status
Simulation time 18848969 ps
CPU time 0.74 seconds
Started Jul 01 04:30:53 PM PDT 24
Finished Jul 01 04:31:01 PM PDT 24
Peak memory 205448 kb
Host smart-8baf1aae-9473-4a11-a5b7-c62174f215eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040225792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3040225792
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2408009930
Short name T1038
Test name
Test status
Simulation time 17718320 ps
CPU time 0.7 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:10 PM PDT 24
Peak memory 205288 kb
Host smart-9ad6d32a-0aa4-4b63-82ae-cca7e460092b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408009930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2408009930
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4081846250
Short name T946
Test name
Test status
Simulation time 16167452 ps
CPU time 0.89 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205452 kb
Host smart-36b7c822-8d6f-4b6f-beeb-9842baf05f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081846250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4081846250
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.178170488
Short name T956
Test name
Test status
Simulation time 39819535 ps
CPU time 0.73 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205288 kb
Host smart-22a31346-1f93-4052-a1e1-1dabc2da98ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178170488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.178170488
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3944643888
Short name T1009
Test name
Test status
Simulation time 45577643 ps
CPU time 0.74 seconds
Started Jul 01 04:30:52 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 205288 kb
Host smart-773d53e9-b590-4b2e-91d7-ef0698863038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944643888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3944643888
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3355672964
Short name T920
Test name
Test status
Simulation time 16846539 ps
CPU time 0.84 seconds
Started Jul 01 04:30:50 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 205360 kb
Host smart-3cda1312-d093-41fb-8055-032ac5064395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355672964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3355672964
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2865141044
Short name T1080
Test name
Test status
Simulation time 11990662 ps
CPU time 0.86 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:02 PM PDT 24
Peak memory 205436 kb
Host smart-cff6a6fe-0280-4347-9a50-0f6e5ecde65f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865141044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2865141044
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4090241814
Short name T971
Test name
Test status
Simulation time 44049146 ps
CPU time 0.71 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205388 kb
Host smart-d6d81a0c-c3bd-4deb-9df7-d30422ff5f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090241814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4090241814
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3331337307
Short name T1002
Test name
Test status
Simulation time 536628058 ps
CPU time 7.81 seconds
Started Jul 01 04:30:26 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 205340 kb
Host smart-f294bc10-1d39-491f-8932-d4eb7a62b48c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331337307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
331337307
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1843334468
Short name T1045
Test name
Test status
Simulation time 1109588830 ps
CPU time 15.64 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 205516 kb
Host smart-01414489-1d19-4e73-98da-46508653eeb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843334468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
843334468
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1257889595
Short name T1087
Test name
Test status
Simulation time 24524790 ps
CPU time 1.31 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 205416 kb
Host smart-59d5356b-5a3e-425f-a09e-b067a74045ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257889595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
257889595
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3308085721
Short name T941
Test name
Test status
Simulation time 199121286 ps
CPU time 2.2 seconds
Started Jul 01 04:30:29 PM PDT 24
Finished Jul 01 04:30:43 PM PDT 24
Peak memory 213680 kb
Host smart-5c911e06-291a-4e8a-84b9-3c85df45e72c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308085721 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3308085721
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.367460026
Short name T957
Test name
Test status
Simulation time 52989393 ps
CPU time 1.32 seconds
Started Jul 01 04:30:21 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 205544 kb
Host smart-3cc7646d-7139-4b4f-8a0c-d904ea9ff86e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367460026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.367460026
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2987422791
Short name T1048
Test name
Test status
Simulation time 44111017 ps
CPU time 0.7 seconds
Started Jul 01 04:30:30 PM PDT 24
Finished Jul 01 04:30:42 PM PDT 24
Peak memory 205164 kb
Host smart-93e515b7-bf65-49f0-9b48-994e9760e408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987422791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2987422791
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2041302441
Short name T1036
Test name
Test status
Simulation time 53918557 ps
CPU time 1.75 seconds
Started Jul 01 04:30:35 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 205540 kb
Host smart-7a9bb45c-e122-4411-8af4-114640c7ac23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041302441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2041302441
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1567046076
Short name T1088
Test name
Test status
Simulation time 1735445755 ps
CPU time 16.28 seconds
Started Jul 01 04:30:28 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 213924 kb
Host smart-9911d60c-4dbb-4ca5-95c3-6cd24c26d361
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567046076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1567046076
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.364480934
Short name T1051
Test name
Test status
Simulation time 58097011 ps
CPU time 1.87 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 213736 kb
Host smart-43bc3d38-9135-4a49-8ddc-0c6d339d2ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364480934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.364480934
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2590815589
Short name T376
Test name
Test status
Simulation time 819590942 ps
CPU time 6.32 seconds
Started Jul 01 04:30:24 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 214948 kb
Host smart-5fb01536-bd5d-4c2a-978f-c2e968d3bdf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590815589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2590815589
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2425797431
Short name T1058
Test name
Test status
Simulation time 32012181 ps
CPU time 0.72 seconds
Started Jul 01 04:30:49 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 205436 kb
Host smart-6feb1deb-776f-4e5e-a234-e54d44a10b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425797431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2425797431
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.365265705
Short name T925
Test name
Test status
Simulation time 17965043 ps
CPU time 0.68 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 205284 kb
Host smart-940bd322-794d-49ca-81e3-c83853dbb8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365265705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.365265705
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2736183911
Short name T939
Test name
Test status
Simulation time 64285906 ps
CPU time 0.83 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 205288 kb
Host smart-44439d7d-84f8-4769-8463-40408076e60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736183911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2736183911
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2842807779
Short name T1018
Test name
Test status
Simulation time 76966321 ps
CPU time 0.79 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 205600 kb
Host smart-f6fb19c6-a775-4f94-b16c-d6b8cec8fcf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842807779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2842807779
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1058954905
Short name T961
Test name
Test status
Simulation time 13205350 ps
CPU time 0.87 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 205212 kb
Host smart-1565e6c1-8092-404f-a2a8-94b30ba4ce70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058954905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1058954905
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2589487079
Short name T1022
Test name
Test status
Simulation time 7412178 ps
CPU time 0.78 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 205400 kb
Host smart-f5d759f9-dc1e-4e43-bd95-4ba6fe5727e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589487079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2589487079
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3151701482
Short name T967
Test name
Test status
Simulation time 33843797 ps
CPU time 0.85 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 205516 kb
Host smart-fd9d834c-93b2-4266-8ed2-8b1f5decc0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151701482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3151701482
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2413440647
Short name T962
Test name
Test status
Simulation time 12391922 ps
CPU time 0.7 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 205304 kb
Host smart-a0d640e1-e036-41f8-92f9-e17e90e4e8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413440647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2413440647
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1570218023
Short name T972
Test name
Test status
Simulation time 11039092 ps
CPU time 0.84 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:10 PM PDT 24
Peak memory 205212 kb
Host smart-71417b4a-4de0-4640-923a-909dfdaee44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570218023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1570218023
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2483803299
Short name T984
Test name
Test status
Simulation time 94155323 ps
CPU time 0.71 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 205168 kb
Host smart-903bdce5-7d6b-4bc9-925b-742addfe166f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483803299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2483803299
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2172056702
Short name T1008
Test name
Test status
Simulation time 132357082 ps
CPU time 4.47 seconds
Started Jul 01 04:30:34 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 205372 kb
Host smart-bbb43fa2-ed5c-4af0-8600-795600651693
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172056702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
172056702
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1844794716
Short name T997
Test name
Test status
Simulation time 1622147116 ps
CPU time 6.95 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 205304 kb
Host smart-54bb2a88-943c-4edf-aa67-ff99426052cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844794716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
844794716
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.298080302
Short name T1014
Test name
Test status
Simulation time 14395577 ps
CPU time 0.89 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:43 PM PDT 24
Peak memory 205244 kb
Host smart-9c2437ff-d8ed-45a7-9214-8e36ae716da7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298080302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.298080302
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.471760491
Short name T933
Test name
Test status
Simulation time 28848132 ps
CPU time 1.42 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 205516 kb
Host smart-337ca3b1-9410-409f-b2c4-9db480803ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471760491 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.471760491
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1178656247
Short name T1056
Test name
Test status
Simulation time 27755174 ps
CPU time 1.43 seconds
Started Jul 01 04:30:32 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 205404 kb
Host smart-83adb265-0033-44c4-b949-2172f37782e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178656247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1178656247
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2091024485
Short name T1004
Test name
Test status
Simulation time 17176375 ps
CPU time 0.79 seconds
Started Jul 01 04:30:28 PM PDT 24
Finished Jul 01 04:30:41 PM PDT 24
Peak memory 205288 kb
Host smart-25cd5612-ea62-40e1-8fed-a08b347dc886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091024485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2091024485
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4146398006
Short name T1057
Test name
Test status
Simulation time 48478278 ps
CPU time 2.01 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 205404 kb
Host smart-762b0bde-5be5-4f6d-8b98-354078e18a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146398006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4146398006
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2558307743
Short name T1069
Test name
Test status
Simulation time 202422576 ps
CPU time 3.23 seconds
Started Jul 01 04:30:37 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 213896 kb
Host smart-a4ac0e01-46e1-461d-9b0e-7ebdd675d8bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558307743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2558307743
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4126273691
Short name T101
Test name
Test status
Simulation time 597915766 ps
CPU time 7.89 seconds
Started Jul 01 04:30:33 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 219980 kb
Host smart-c6aa9a1a-1f6c-4e20-9f04-574ec586e708
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126273691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4126273691
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.829617769
Short name T1073
Test name
Test status
Simulation time 618443728 ps
CPU time 3.4 seconds
Started Jul 01 04:30:28 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 215840 kb
Host smart-c5e75472-9a30-4fbb-929d-2224ea9721ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829617769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.829617769
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.230975975
Short name T373
Test name
Test status
Simulation time 1377965142 ps
CPU time 4.38 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 213644 kb
Host smart-a26b5652-afac-4d33-b02c-b0877630ec12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230975975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
230975975
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3271429612
Short name T1025
Test name
Test status
Simulation time 20228492 ps
CPU time 0.69 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 205384 kb
Host smart-7324ba41-6c35-4bb7-8f0b-e3192d592ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271429612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3271429612
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1725577963
Short name T986
Test name
Test status
Simulation time 16373008 ps
CPU time 0.71 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 205212 kb
Host smart-1b51a289-35af-4ded-aa07-56997b2127ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725577963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1725577963
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.326146077
Short name T996
Test name
Test status
Simulation time 52704213 ps
CPU time 0.75 seconds
Started Jul 01 04:31:05 PM PDT 24
Finished Jul 01 04:31:19 PM PDT 24
Peak memory 205212 kb
Host smart-20202f72-f45d-4574-b2b5-a0940eaed619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326146077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.326146077
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2760976407
Short name T1049
Test name
Test status
Simulation time 26438931 ps
CPU time 0.76 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 205256 kb
Host smart-4da99290-4dc1-49ac-ac93-d0dc926c62b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760976407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2760976407
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1534533804
Short name T1042
Test name
Test status
Simulation time 37803196 ps
CPU time 0.8 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 205316 kb
Host smart-6c0045c4-11c5-475c-8bd9-393c1ef325ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534533804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1534533804
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2803061263
Short name T963
Test name
Test status
Simulation time 11964203 ps
CPU time 0.74 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:10 PM PDT 24
Peak memory 205212 kb
Host smart-04e6f152-0f0f-4777-a690-bc2395fd6d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803061263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2803061263
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.870495521
Short name T988
Test name
Test status
Simulation time 33608518 ps
CPU time 0.73 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 205360 kb
Host smart-35d57270-ffe7-4406-a05a-1deac3a27faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870495521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.870495521
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3621581478
Short name T1079
Test name
Test status
Simulation time 12517109 ps
CPU time 0.78 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 205292 kb
Host smart-9de0b22d-27d2-4abd-a2ac-be902b241ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621581478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3621581478
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3957531998
Short name T1075
Test name
Test status
Simulation time 17335808 ps
CPU time 0.9 seconds
Started Jul 01 04:30:54 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 205456 kb
Host smart-ad87d74e-8ced-4ff7-ad18-4e29586155ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957531998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3957531998
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3084589121
Short name T940
Test name
Test status
Simulation time 93373745 ps
CPU time 0.86 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 205248 kb
Host smart-17248ecb-59ec-4100-a916-6ccc393322b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084589121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3084589121
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2963507886
Short name T942
Test name
Test status
Simulation time 36739716 ps
CPU time 2.55 seconds
Started Jul 01 04:30:30 PM PDT 24
Finished Jul 01 04:30:44 PM PDT 24
Peak memory 213924 kb
Host smart-b396f4ca-8caa-42da-88db-c2e6a039fe3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963507886 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2963507886
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2949098727
Short name T1010
Test name
Test status
Simulation time 88886648 ps
CPU time 1.04 seconds
Started Jul 01 04:30:31 PM PDT 24
Finished Jul 01 04:30:43 PM PDT 24
Peak memory 205260 kb
Host smart-2252fa0d-6807-4acf-92f3-0074f76f5d40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949098727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2949098727
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.28077319
Short name T1032
Test name
Test status
Simulation time 30507236 ps
CPU time 0.85 seconds
Started Jul 01 04:30:29 PM PDT 24
Finished Jul 01 04:30:42 PM PDT 24
Peak memory 205168 kb
Host smart-87728073-5ba9-4159-a461-4e717ddcc7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28077319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.28077319
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.271592882
Short name T974
Test name
Test status
Simulation time 399136941 ps
CPU time 1.71 seconds
Started Jul 01 04:30:34 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 205692 kb
Host smart-34fe035a-4e27-4957-8295-63f2cf2fc3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271592882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.271592882
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1992306283
Short name T1086
Test name
Test status
Simulation time 564964564 ps
CPU time 3.16 seconds
Started Jul 01 04:30:30 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 214096 kb
Host smart-c3a19524-1c45-4fd0-8cf6-c315007aeb01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992306283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1992306283
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.759631530
Short name T977
Test name
Test status
Simulation time 178603978 ps
CPU time 6.93 seconds
Started Jul 01 04:30:30 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 213808 kb
Host smart-c7369d91-739f-4a16-b36a-839b2feb5e65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759631530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.759631530
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3244410305
Short name T968
Test name
Test status
Simulation time 194537402 ps
CPU time 2.76 seconds
Started Jul 01 04:30:37 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 213580 kb
Host smart-8cf3895b-f913-4def-bb63-f49419fffbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244410305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3244410305
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.412784318
Short name T1067
Test name
Test status
Simulation time 140956388 ps
CPU time 2.39 seconds
Started Jul 01 04:30:37 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 213728 kb
Host smart-2a622363-aa6d-456e-9c60-dcca36c184e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412784318 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.412784318
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1219510687
Short name T1012
Test name
Test status
Simulation time 66650666 ps
CPU time 0.93 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 205512 kb
Host smart-3aadf189-f8f4-4c2f-93a0-a6113b928855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219510687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1219510687
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1446966129
Short name T1023
Test name
Test status
Simulation time 9235024 ps
CPU time 0.78 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 205388 kb
Host smart-92264204-0915-487b-a990-1c06cdd3fb42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446966129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1446966129
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.105702417
Short name T1034
Test name
Test status
Simulation time 25905064 ps
CPU time 1.7 seconds
Started Jul 01 04:30:42 PM PDT 24
Finished Jul 01 04:30:52 PM PDT 24
Peak memory 205376 kb
Host smart-b5718cec-edc7-4383-a9b5-19ee68a1ed74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105702417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.105702417
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.401635016
Short name T1000
Test name
Test status
Simulation time 1481353903 ps
CPU time 3.06 seconds
Started Jul 01 04:30:35 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 213896 kb
Host smart-3c68cf7f-e0c0-40d8-9cb3-40830205f85c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401635016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.401635016
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3627961846
Short name T105
Test name
Test status
Simulation time 308790326 ps
CPU time 8.72 seconds
Started Jul 01 04:30:36 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 213920 kb
Host smart-768415dd-dcfb-41ba-a5be-589ce925cf72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627961846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3627961846
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4245984623
Short name T1011
Test name
Test status
Simulation time 237295008 ps
CPU time 3.1 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 213616 kb
Host smart-2171744c-a0d3-4b61-8a07-9b9c210e4123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245984623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4245984623
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1681011143
Short name T151
Test name
Test status
Simulation time 197474092 ps
CPU time 2.64 seconds
Started Jul 01 04:30:35 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 205552 kb
Host smart-659a7371-1f63-45c7-9d3a-f3bd54916f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681011143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1681011143
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1853959090
Short name T1085
Test name
Test status
Simulation time 30516627 ps
CPU time 1.78 seconds
Started Jul 01 04:30:35 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 213864 kb
Host smart-aa528962-3754-4251-bd83-bf7c51e69aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853959090 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1853959090
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4250272810
Short name T978
Test name
Test status
Simulation time 22765369 ps
CPU time 1.02 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 205384 kb
Host smart-1459ddc4-aa03-4579-b410-ff007d6bdb5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250272810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4250272810
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2218789977
Short name T944
Test name
Test status
Simulation time 42568085 ps
CPU time 0.81 seconds
Started Jul 01 04:30:38 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 205160 kb
Host smart-1130910d-95fe-46d4-b0f0-261525a307f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218789977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2218789977
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3862739831
Short name T125
Test name
Test status
Simulation time 20972192 ps
CPU time 1.43 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 205476 kb
Host smart-cf15eb12-2d34-4ec6-9c9e-2e826b61a57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862739831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3862739831
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3183749703
Short name T1015
Test name
Test status
Simulation time 63737472 ps
CPU time 1.59 seconds
Started Jul 01 04:30:40 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 214016 kb
Host smart-6edd29bb-69e8-4ecf-9cb5-6be984a11bb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183749703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3183749703
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.18330533
Short name T1063
Test name
Test status
Simulation time 450369219 ps
CPU time 4.42 seconds
Started Jul 01 04:30:40 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 220240 kb
Host smart-65a8077d-c2eb-4344-9391-c2c9344f421c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18330533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_shadow_reg_errors_with_csr_rw.18330533
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2126932965
Short name T1044
Test name
Test status
Simulation time 285425484 ps
CPU time 1.97 seconds
Started Jul 01 04:30:34 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 213636 kb
Host smart-b949f916-9279-4dbe-9130-1f1e17dc706c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126932965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2126932965
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3575689862
Short name T954
Test name
Test status
Simulation time 127070256 ps
CPU time 1.24 seconds
Started Jul 01 04:30:38 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 205628 kb
Host smart-f38764b8-43c7-407c-9fd6-c43163e14f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575689862 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3575689862
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2142408932
Short name T128
Test name
Test status
Simulation time 38468428 ps
CPU time 0.86 seconds
Started Jul 01 04:30:37 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 205436 kb
Host smart-2ee44fdd-68f8-4a89-8ee3-3f14c86e2b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142408932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2142408932
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2522736892
Short name T994
Test name
Test status
Simulation time 22715863 ps
CPU time 0.69 seconds
Started Jul 01 04:30:37 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 205236 kb
Host smart-e8b8a642-04fe-411b-a4ee-688cbfc74042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522736892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2522736892
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2127749674
Short name T966
Test name
Test status
Simulation time 261023954 ps
CPU time 2.41 seconds
Started Jul 01 04:30:39 PM PDT 24
Finished Jul 01 04:30:50 PM PDT 24
Peak memory 205384 kb
Host smart-7a66175e-730c-467a-af57-47ac9558f3ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127749674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2127749674
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1633550341
Short name T1072
Test name
Test status
Simulation time 345533037 ps
CPU time 1.97 seconds
Started Jul 01 04:30:34 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 213896 kb
Host smart-87906c89-956c-4934-b8c4-b044728090ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633550341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1633550341
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1927878057
Short name T1071
Test name
Test status
Simulation time 372629594 ps
CPU time 12.41 seconds
Started Jul 01 04:30:40 PM PDT 24
Finished Jul 01 04:31:01 PM PDT 24
Peak memory 220044 kb
Host smart-05108b8a-f0ed-4df0-803f-ff30ce65ac6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927878057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1927878057
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.214366035
Short name T936
Test name
Test status
Simulation time 81356251 ps
CPU time 1.65 seconds
Started Jul 01 04:30:38 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 213636 kb
Host smart-693b0b55-2b05-4d69-b103-a0b39bebb645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214366035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.214366035
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.480547055
Short name T372
Test name
Test status
Simulation time 431134008 ps
CPU time 12.16 seconds
Started Jul 01 04:30:38 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 205576 kb
Host smart-0b5b09ee-b59d-432a-8ba2-0294ffeb5896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480547055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
480547055
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1438975336
Short name T985
Test name
Test status
Simulation time 28012733 ps
CPU time 1.18 seconds
Started Jul 01 04:30:42 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 205504 kb
Host smart-424a0458-465e-4fac-944f-6c7ea8c88807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438975336 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1438975336
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.217385183
Short name T1001
Test name
Test status
Simulation time 12015156 ps
CPU time 0.83 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:52 PM PDT 24
Peak memory 205360 kb
Host smart-f900fe38-45d6-4f20-975c-70e2ecbf9567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217385183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.217385183
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.950223913
Short name T930
Test name
Test status
Simulation time 18631576 ps
CPU time 0.82 seconds
Started Jul 01 04:30:44 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 205216 kb
Host smart-d9088a5c-30cb-4f0e-b004-9f3d9dc901bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950223913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.950223913
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1764847475
Short name T126
Test name
Test status
Simulation time 247073350 ps
CPU time 2.96 seconds
Started Jul 01 04:30:42 PM PDT 24
Finished Jul 01 04:30:53 PM PDT 24
Peak memory 205608 kb
Host smart-3a1047b7-d101-47d5-9317-f7b6c55252b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764847475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1764847475
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2897272007
Short name T950
Test name
Test status
Simulation time 836867765 ps
CPU time 2.71 seconds
Started Jul 01 04:31:42 PM PDT 24
Finished Jul 01 04:31:57 PM PDT 24
Peak memory 213144 kb
Host smart-b9d45eea-8fa7-48bb-8ffd-4f29898eef95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897272007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2897272007
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1490378866
Short name T1084
Test name
Test status
Simulation time 208045307 ps
CPU time 6.06 seconds
Started Jul 01 04:30:45 PM PDT 24
Finished Jul 01 04:30:59 PM PDT 24
Peak memory 213932 kb
Host smart-7102d871-5b18-48c7-ba6f-1659d615a305
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490378866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1490378866
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3815142040
Short name T921
Test name
Test status
Simulation time 145363432 ps
CPU time 3.42 seconds
Started Jul 01 04:30:43 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 213604 kb
Host smart-8befb627-96a5-4054-a490-cd556566e6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815142040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3815142040
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.667352401
Short name T847
Test name
Test status
Simulation time 13921127 ps
CPU time 0.75 seconds
Started Jul 01 05:07:51 PM PDT 24
Finished Jul 01 05:07:53 PM PDT 24
Peak memory 206068 kb
Host smart-8ccc1ddf-d8fa-4c8a-8900-21ba88ad1a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667352401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.667352401
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.448944940
Short name T131
Test name
Test status
Simulation time 105682184 ps
CPU time 4.04 seconds
Started Jul 01 05:07:48 PM PDT 24
Finished Jul 01 05:07:53 PM PDT 24
Peak memory 214380 kb
Host smart-2b3ba23b-4943-4a78-a614-5e5e0f2dce1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448944940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.448944940
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1716402003
Short name T18
Test name
Test status
Simulation time 260245424 ps
CPU time 8.94 seconds
Started Jul 01 05:07:53 PM PDT 24
Finished Jul 01 05:08:03 PM PDT 24
Peak memory 210144 kb
Host smart-19b8f207-2aa5-4e78-b17c-e72403971356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716402003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1716402003
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3762870474
Short name T492
Test name
Test status
Simulation time 103495928 ps
CPU time 2.45 seconds
Started Jul 01 05:07:51 PM PDT 24
Finished Jul 01 05:07:54 PM PDT 24
Peak memory 218416 kb
Host smart-70090815-11ff-49ba-801f-432af88d9e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762870474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3762870474
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1498508221
Short name T238
Test name
Test status
Simulation time 109438489 ps
CPU time 2.72 seconds
Started Jul 01 05:07:52 PM PDT 24
Finished Jul 01 05:07:56 PM PDT 24
Peak memory 214372 kb
Host smart-57dea6e6-a3e0-4af3-a8ed-a30eb31ecc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498508221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1498508221
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3849335446
Short name T874
Test name
Test status
Simulation time 72740763 ps
CPU time 2.53 seconds
Started Jul 01 05:07:50 PM PDT 24
Finished Jul 01 05:07:53 PM PDT 24
Peak memory 222440 kb
Host smart-d6b842ff-88d1-4a49-9158-27d5a7e3b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849335446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3849335446
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.3164977013
Short name T870
Test name
Test status
Simulation time 1819946363 ps
CPU time 20.99 seconds
Started Jul 01 05:07:47 PM PDT 24
Finished Jul 01 05:08:09 PM PDT 24
Peak memory 209700 kb
Host smart-37e6792e-6a5d-4ece-ab9b-32aac9da1a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164977013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3164977013
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.724712379
Short name T182
Test name
Test status
Simulation time 145439176 ps
CPU time 3.7 seconds
Started Jul 01 05:07:45 PM PDT 24
Finished Jul 01 05:07:50 PM PDT 24
Peak memory 208924 kb
Host smart-56858fe4-04b5-4840-890f-7b522e7405cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724712379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.724712379
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1617756694
Short name T427
Test name
Test status
Simulation time 144790108 ps
CPU time 2.22 seconds
Started Jul 01 05:07:45 PM PDT 24
Finished Jul 01 05:07:49 PM PDT 24
Peak memory 206856 kb
Host smart-34a88bb7-1d21-451b-9c60-82572ba9d381
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617756694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1617756694
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2213326059
Short name T825
Test name
Test status
Simulation time 124112440 ps
CPU time 2.4 seconds
Started Jul 01 05:07:48 PM PDT 24
Finished Jul 01 05:07:51 PM PDT 24
Peak memory 206964 kb
Host smart-055e44ac-e0c3-4b3d-b0a8-b00311972e35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213326059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2213326059
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1807777193
Short name T633
Test name
Test status
Simulation time 30539345 ps
CPU time 2.14 seconds
Started Jul 01 05:07:50 PM PDT 24
Finished Jul 01 05:07:53 PM PDT 24
Peak memory 210148 kb
Host smart-6459d9d4-97d6-416a-aa34-26a6be089693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807777193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1807777193
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2940784600
Short name T518
Test name
Test status
Simulation time 19839173 ps
CPU time 1.71 seconds
Started Jul 01 05:07:44 PM PDT 24
Finished Jul 01 05:07:47 PM PDT 24
Peak memory 206852 kb
Host smart-7235c2dc-08d5-4755-9113-610d2e805ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940784600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2940784600
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3285112834
Short name T349
Test name
Test status
Simulation time 616791506 ps
CPU time 24.54 seconds
Started Jul 01 05:07:52 PM PDT 24
Finished Jul 01 05:08:17 PM PDT 24
Peak memory 222324 kb
Host smart-61f1251f-b7f5-47cb-a596-e1ff75c329d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285112834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3285112834
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.957232821
Short name T134
Test name
Test status
Simulation time 211716877 ps
CPU time 13.95 seconds
Started Jul 01 05:07:52 PM PDT 24
Finished Jul 01 05:08:06 PM PDT 24
Peak memory 220468 kb
Host smart-6d50dada-26b4-41b2-9bd1-1def7c275418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957232821 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.957232821
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.633148683
Short name T249
Test name
Test status
Simulation time 136267991 ps
CPU time 5.58 seconds
Started Jul 01 05:07:51 PM PDT 24
Finished Jul 01 05:07:58 PM PDT 24
Peak memory 210016 kb
Host smart-ca940975-b977-4901-a907-547e26d87960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633148683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.633148683
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.702779640
Short name T394
Test name
Test status
Simulation time 173267457 ps
CPU time 1.68 seconds
Started Jul 01 05:07:48 PM PDT 24
Finished Jul 01 05:07:51 PM PDT 24
Peak memory 210088 kb
Host smart-40ca4f23-b54a-4c8a-a79e-cf1c925df376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702779640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.702779640
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.456281339
Short name T820
Test name
Test status
Simulation time 41318517 ps
CPU time 0.71 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:07:58 PM PDT 24
Peak memory 206084 kb
Host smart-850d7e07-5b23-4fa1-82ab-cfdf088667aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456281339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.456281339
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.36498953
Short name T788
Test name
Test status
Simulation time 1280144841 ps
CPU time 11.97 seconds
Started Jul 01 05:07:54 PM PDT 24
Finished Jul 01 05:08:07 PM PDT 24
Peak memory 209272 kb
Host smart-5a758771-1c39-4e13-8cd7-afa380e4c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36498953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.36498953
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4260247367
Short name T83
Test name
Test status
Simulation time 376633310 ps
CPU time 8.41 seconds
Started Jul 01 05:07:57 PM PDT 24
Finished Jul 01 05:08:07 PM PDT 24
Peak memory 214264 kb
Host smart-47c1fc59-edbc-4a11-9142-c250da344c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260247367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4260247367
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1757623492
Short name T41
Test name
Test status
Simulation time 74879220 ps
CPU time 2.58 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:07:59 PM PDT 24
Peak memory 214284 kb
Host smart-583e2634-9130-40ba-9d4c-6503d15ae0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757623492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1757623492
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.1425979129
Short name T827
Test name
Test status
Simulation time 69110845 ps
CPU time 3.09 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:02 PM PDT 24
Peak memory 207908 kb
Host smart-00734c92-7df0-4511-9b1a-1b2713557209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425979129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1425979129
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.150008883
Short name T639
Test name
Test status
Simulation time 770742077 ps
CPU time 8.32 seconds
Started Jul 01 05:07:50 PM PDT 24
Finished Jul 01 05:07:59 PM PDT 24
Peak memory 208788 kb
Host smart-f39f0315-9ecb-412c-80b9-fd00156e5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150008883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.150008883
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3802527983
Short name T765
Test name
Test status
Simulation time 1393971867 ps
CPU time 26.36 seconds
Started Jul 01 05:07:55 PM PDT 24
Finished Jul 01 05:08:22 PM PDT 24
Peak memory 207916 kb
Host smart-34d01b3b-fa96-4452-94c5-e0ce24b70e3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802527983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3802527983
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3343093813
Short name T645
Test name
Test status
Simulation time 68235809 ps
CPU time 2.92 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:08:00 PM PDT 24
Peak memory 206980 kb
Host smart-3c0746f5-1d1f-43df-a29c-2c9b9d55b380
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343093813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3343093813
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.752362294
Short name T531
Test name
Test status
Simulation time 237350732 ps
CPU time 5.02 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:08:02 PM PDT 24
Peak memory 208492 kb
Host smart-b62eb52d-51e9-4705-bdf4-02d706543173
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752362294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.752362294
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1194769446
Short name T596
Test name
Test status
Simulation time 40759394 ps
CPU time 1.79 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:01 PM PDT 24
Peak memory 215372 kb
Host smart-61d7ce37-505c-4370-b6e6-0b812b907a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194769446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1194769446
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3978267613
Short name T490
Test name
Test status
Simulation time 386776144 ps
CPU time 2.3 seconds
Started Jul 01 05:07:49 PM PDT 24
Finished Jul 01 05:07:52 PM PDT 24
Peak memory 207312 kb
Host smart-685ded76-4888-4410-9d84-60a0485429e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978267613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3978267613
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2428106568
Short name T70
Test name
Test status
Simulation time 13070877788 ps
CPU time 93.87 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 216892 kb
Host smart-c5dc8e1c-77b6-4be5-8e06-6bb7815622c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428106568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2428106568
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3013070897
Short name T67
Test name
Test status
Simulation time 1065553900 ps
CPU time 11.52 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:11 PM PDT 24
Peak memory 222632 kb
Host smart-53f5441f-b657-4877-8d48-95348f54039c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013070897 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3013070897
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.847759629
Short name T355
Test name
Test status
Simulation time 448815562 ps
CPU time 5.31 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:04 PM PDT 24
Peak memory 218244 kb
Host smart-5ee62dc6-0933-4eaa-8f2e-28fb777b314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847759629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.847759629
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1814790304
Short name T681
Test name
Test status
Simulation time 88618089 ps
CPU time 2.8 seconds
Started Jul 01 05:07:55 PM PDT 24
Finished Jul 01 05:07:59 PM PDT 24
Peak memory 211080 kb
Host smart-52bf94cd-ad33-409c-8aba-a11827ea47e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814790304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1814790304
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.350424523
Short name T558
Test name
Test status
Simulation time 38600169 ps
CPU time 0.89 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 206064 kb
Host smart-55791467-6c53-40d9-bd04-8730f3e2fbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350424523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.350424523
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.550481040
Short name T400
Test name
Test status
Simulation time 62572409 ps
CPU time 3.47 seconds
Started Jul 01 05:08:37 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 214340 kb
Host smart-d423daff-c291-43da-829a-728ac488bb2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550481040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.550481040
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3624312328
Short name T335
Test name
Test status
Simulation time 770422398 ps
CPU time 9.91 seconds
Started Jul 01 05:08:40 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 214336 kb
Host smart-d373e5a4-c155-4baa-8ffb-a427322d892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624312328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3624312328
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.102166953
Short name T856
Test name
Test status
Simulation time 128999365 ps
CPU time 6.21 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 220956 kb
Host smart-0c2790de-f35e-45d7-9f20-7071c05c52a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102166953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.102166953
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.486885159
Short name T729
Test name
Test status
Simulation time 57055837 ps
CPU time 2.33 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 220572 kb
Host smart-3e4d1d59-7c40-4009-8c77-acff1afc1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486885159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.486885159
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.1860926436
Short name T689
Test name
Test status
Simulation time 138270131 ps
CPU time 2.75 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 208584 kb
Host smart-af1eb87e-47e9-47e8-9c20-3148965c5e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860926436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1860926436
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1474342143
Short name T713
Test name
Test status
Simulation time 197385899 ps
CPU time 4.06 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 207028 kb
Host smart-fa4b62e3-9ff7-49c1-990c-3a3374face75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474342143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1474342143
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.664010615
Short name T444
Test name
Test status
Simulation time 63665710 ps
CPU time 3.44 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:49 PM PDT 24
Peak memory 207284 kb
Host smart-62cce26f-6fec-4cfe-b342-0c6be5565836
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664010615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.664010615
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1855652425
Short name T906
Test name
Test status
Simulation time 119628482 ps
CPU time 4.47 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:08:46 PM PDT 24
Peak memory 206896 kb
Host smart-c2b088fe-4c98-485c-bdd0-506639cdadde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855652425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1855652425
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2598489639
Short name T435
Test name
Test status
Simulation time 106700647 ps
CPU time 2.16 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 209992 kb
Host smart-04262573-a292-4f35-9314-ad8f15b22008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598489639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2598489639
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1981357776
Short name T474
Test name
Test status
Simulation time 583331625 ps
CPU time 2.73 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 206784 kb
Host smart-b4540df1-398a-4878-b602-dd7220eda581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981357776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1981357776
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1812716063
Short name T6
Test name
Test status
Simulation time 19573031302 ps
CPU time 114.05 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 216636 kb
Host smart-1d03c691-859c-4439-aadb-339be2c495a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812716063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1812716063
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3304080951
Short name T661
Test name
Test status
Simulation time 1161394527 ps
CPU time 12.84 seconds
Started Jul 01 05:08:38 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 214332 kb
Host smart-7b5d8b92-0f2f-4d99-a329-17d193c78e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304080951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3304080951
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4036058865
Short name T677
Test name
Test status
Simulation time 139794972 ps
CPU time 3.51 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 210096 kb
Host smart-2e3293ff-0fe0-4ce5-bdbd-8d391837f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036058865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4036058865
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3138780455
Short name T514
Test name
Test status
Simulation time 21576856 ps
CPU time 0.81 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 206024 kb
Host smart-c4b05334-7db0-48fb-a60e-fadc92e49b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138780455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3138780455
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1096944832
Short name T695
Test name
Test status
Simulation time 44840606 ps
CPU time 3.17 seconds
Started Jul 01 05:08:43 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 215728 kb
Host smart-ddde6482-4001-4728-a69e-da5f341947da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096944832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1096944832
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3237434374
Short name T894
Test name
Test status
Simulation time 200474383 ps
CPU time 2.24 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 217188 kb
Host smart-84055809-8ebc-4ca9-b033-3bd93eee7bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237434374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3237434374
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4020594957
Short name T312
Test name
Test status
Simulation time 153474035 ps
CPU time 2.37 seconds
Started Jul 01 05:08:40 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 207080 kb
Host smart-c1735934-6318-4149-b15a-e4f41b01c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020594957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4020594957
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2977815852
Short name T82
Test name
Test status
Simulation time 134972557 ps
CPU time 4.43 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 220260 kb
Host smart-43771d3c-c785-42f5-aee5-db5c86e2c66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977815852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2977815852
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2183653857
Short name T588
Test name
Test status
Simulation time 354372461 ps
CPU time 3.45 seconds
Started Jul 01 05:08:47 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 222344 kb
Host smart-13989e2d-7080-49db-8922-65b66b45522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183653857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2183653857
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.981851098
Short name T549
Test name
Test status
Simulation time 384690272 ps
CPU time 2.36 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 214392 kb
Host smart-bd59339f-ea38-47eb-8014-ae629f6a1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981851098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.981851098
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1156855229
Short name T309
Test name
Test status
Simulation time 89601125 ps
CPU time 4.64 seconds
Started Jul 01 05:08:40 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 209916 kb
Host smart-768ddc91-ebe1-4892-8c79-1afa4c7a8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156855229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1156855229
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1998098287
Short name T560
Test name
Test status
Simulation time 113320123 ps
CPU time 4.13 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 207000 kb
Host smart-fcacc8a2-0d7b-4bb1-9230-d98a59961b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998098287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1998098287
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1666828095
Short name T709
Test name
Test status
Simulation time 46150301 ps
CPU time 2.18 seconds
Started Jul 01 05:08:38 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 208612 kb
Host smart-afd5ed9e-22d1-4d4b-a863-9722e5d583c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666828095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1666828095
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1661211834
Short name T826
Test name
Test status
Simulation time 1599814695 ps
CPU time 7.81 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 207156 kb
Host smart-46e31e25-7ad7-4820-9f79-4b300dcb64b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661211834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1661211834
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.108195089
Short name T544
Test name
Test status
Simulation time 98904391 ps
CPU time 2.02 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 214340 kb
Host smart-075e74e3-0e98-4282-a6ab-101ba49bcb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108195089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.108195089
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2391932349
Short name T195
Test name
Test status
Simulation time 188464294 ps
CPU time 4.97 seconds
Started Jul 01 05:08:39 PM PDT 24
Finished Jul 01 05:08:46 PM PDT 24
Peak memory 208440 kb
Host smart-1b2b89a8-5fa2-4e29-94f4-a1a6d20b9ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391932349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2391932349
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.969020839
Short name T722
Test name
Test status
Simulation time 292066386 ps
CPU time 8.12 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 219872 kb
Host smart-a5be79d9-0627-4080-932c-17e926573198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969020839 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.969020839
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1706912089
Short name T95
Test name
Test status
Simulation time 179851212 ps
CPU time 5.79 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 214364 kb
Host smart-8bc60970-df7a-4b32-ab62-49b44567b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706912089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1706912089
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3562463894
Short name T467
Test name
Test status
Simulation time 260206116 ps
CPU time 3.17 seconds
Started Jul 01 05:08:47 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 210052 kb
Host smart-6403b540-7420-4098-bad4-5a3970b02fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562463894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3562463894
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3336006130
Short name T731
Test name
Test status
Simulation time 10030105 ps
CPU time 0.73 seconds
Started Jul 01 05:08:47 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 206192 kb
Host smart-cdc52f72-6896-42ee-8e72-5ae077a745fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336006130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3336006130
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3173430228
Short name T885
Test name
Test status
Simulation time 108515110 ps
CPU time 2.92 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 214684 kb
Host smart-664395a0-d210-4f8a-9a1f-5bf20c89532c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173430228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3173430228
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1973069255
Short name T241
Test name
Test status
Simulation time 30852457 ps
CPU time 2.47 seconds
Started Jul 01 05:08:48 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 214336 kb
Host smart-61a4bcd2-1c76-4b28-b5c5-62bcd2ea1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973069255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1973069255
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1282654992
Short name T876
Test name
Test status
Simulation time 189918362 ps
CPU time 6.17 seconds
Started Jul 01 05:08:55 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 214044 kb
Host smart-7ce615ae-2a8e-4a93-a6e7-f8e66a616ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282654992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1282654992
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3324006055
Short name T220
Test name
Test status
Simulation time 826705398 ps
CPU time 26.43 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 214368 kb
Host smart-36be9f88-6eb2-4b21-bf7b-92b44e92c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324006055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3324006055
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1369973357
Short name T175
Test name
Test status
Simulation time 125255667 ps
CPU time 6.26 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 207496 kb
Host smart-a8e16151-acf4-4ea8-9086-4640ed0fca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369973357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1369973357
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1082868734
Short name T534
Test name
Test status
Simulation time 173260969 ps
CPU time 4.63 seconds
Started Jul 01 05:08:43 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 207924 kb
Host smart-001b772c-adbf-43ba-9809-3f98090109a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082868734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1082868734
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3501347787
Short name T487
Test name
Test status
Simulation time 245612937 ps
CPU time 5.78 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 208024 kb
Host smart-82199116-3e74-4d6c-8ff1-deda2c0a1ba6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501347787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3501347787
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3511758271
Short name T787
Test name
Test status
Simulation time 154290054 ps
CPU time 4.37 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 208732 kb
Host smart-ca1570ee-81c2-4d24-b9e4-50bf8ce085dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511758271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3511758271
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2472574924
Short name T791
Test name
Test status
Simulation time 86047526 ps
CPU time 3.73 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 207024 kb
Host smart-6afc63d5-242a-4dfa-9f30-be00b2c3ad9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472574924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2472574924
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1869177500
Short name T615
Test name
Test status
Simulation time 93707696 ps
CPU time 1.98 seconds
Started Jul 01 05:08:43 PM PDT 24
Finished Jul 01 05:08:48 PM PDT 24
Peak memory 210136 kb
Host smart-2886cc53-a0aa-4b87-aa57-dcda0ff0c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869177500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1869177500
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.547768916
Short name T859
Test name
Test status
Simulation time 36286317 ps
CPU time 2.23 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 208392 kb
Host smart-1eedaac6-c35c-4a2d-877c-7431dab18952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547768916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.547768916
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.10722303
Short name T110
Test name
Test status
Simulation time 1609273085 ps
CPU time 13.03 seconds
Started Jul 01 05:08:55 PM PDT 24
Finished Jul 01 05:09:08 PM PDT 24
Peak memory 222528 kb
Host smart-3e8d4b6d-f7dd-49f4-a17e-c299818c71c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722303 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.10722303
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1773266341
Short name T774
Test name
Test status
Simulation time 11687272951 ps
CPU time 36.81 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 214392 kb
Host smart-e6c6b83d-1e88-4fc8-80f2-de1f6ec7aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773266341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1773266341
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1520689396
Short name T614
Test name
Test status
Simulation time 154783520 ps
CPU time 1.48 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:49 PM PDT 24
Peak memory 210060 kb
Host smart-e7867f8f-9269-4465-93ec-60ae5638870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520689396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1520689396
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2710167944
Short name T598
Test name
Test status
Simulation time 20726458 ps
CPU time 0.87 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:04 PM PDT 24
Peak memory 205868 kb
Host smart-e93e46a8-ef06-4ca3-bd35-1372602f8bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710167944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2710167944
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3609532031
Short name T411
Test name
Test status
Simulation time 128579271 ps
CPU time 3.14 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 214328 kb
Host smart-d7b90623-dc41-482e-b93e-a8ab0d9a0090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609532031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3609532031
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3067208211
Short name T539
Test name
Test status
Simulation time 43091883 ps
CPU time 2.06 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:55 PM PDT 24
Peak memory 214296 kb
Host smart-fff3d7d9-4809-43c3-8abd-940471bc6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067208211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3067208211
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1482340444
Short name T740
Test name
Test status
Simulation time 4095573083 ps
CPU time 20.63 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:09:10 PM PDT 24
Peak memory 209320 kb
Host smart-2f5ce34f-09a2-4c55-8394-ddf8ac6acaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482340444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1482340444
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.474448820
Short name T571
Test name
Test status
Simulation time 142539225 ps
CPU time 2.76 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 214344 kb
Host smart-790707c4-1ebd-432c-80fe-12c16df00ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474448820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.474448820
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3359372311
Short name T745
Test name
Test status
Simulation time 437766138 ps
CPU time 3.55 seconds
Started Jul 01 05:08:50 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 214264 kb
Host smart-137c29a2-aa4b-461f-9c45-e7ad5cb9475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359372311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3359372311
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2710268573
Short name T579
Test name
Test status
Simulation time 42748183 ps
CPU time 1.86 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:49 PM PDT 24
Peak memory 209132 kb
Host smart-e402b340-eeaa-4c18-8b88-59e6448a3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710268573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2710268573
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1294741642
Short name T757
Test name
Test status
Simulation time 186935285 ps
CPU time 3.81 seconds
Started Jul 01 05:08:43 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 214356 kb
Host smart-e4fe3243-2bd4-4086-a16b-06a58f7b7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294741642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1294741642
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.4034259405
Short name T281
Test name
Test status
Simulation time 4911424449 ps
CPU time 17.99 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 208940 kb
Host smart-7ee30eec-06c5-4381-9e68-9335d88356c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034259405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4034259405
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.375379071
Short name T499
Test name
Test status
Simulation time 53194195 ps
CPU time 2.8 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 207052 kb
Host smart-b740c5b9-2033-4098-8ee7-1147b487e26f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375379071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.375379071
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1605617993
Short name T744
Test name
Test status
Simulation time 142498271 ps
CPU time 2.62 seconds
Started Jul 01 05:08:46 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 208916 kb
Host smart-40843b6b-d3ad-43c7-a0a3-80c203af35e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605617993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1605617993
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4157399093
Short name T653
Test name
Test status
Simulation time 492483633 ps
CPU time 14.59 seconds
Started Jul 01 05:08:43 PM PDT 24
Finished Jul 01 05:09:00 PM PDT 24
Peak memory 208704 kb
Host smart-4d4f7642-7837-4748-be79-cbb9fa2a3e9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157399093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4157399093
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.363905317
Short name T904
Test name
Test status
Simulation time 1018729483 ps
CPU time 10.11 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 210396 kb
Host smart-59e422a7-b937-4bc4-b051-0aed91c5542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363905317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.363905317
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2058905671
Short name T446
Test name
Test status
Simulation time 111285948 ps
CPU time 3.33 seconds
Started Jul 01 05:08:44 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 207760 kb
Host smart-083f383f-00bc-4bc0-bf38-0edb05bd0872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058905671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2058905671
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4071007992
Short name T863
Test name
Test status
Simulation time 554513594 ps
CPU time 3.23 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 214344 kb
Host smart-0c568977-bdb6-485d-a491-36c7806d426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071007992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4071007992
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.820412583
Short name T138
Test name
Test status
Simulation time 104592338 ps
CPU time 2.94 seconds
Started Jul 01 05:08:56 PM PDT 24
Finished Jul 01 05:09:00 PM PDT 24
Peak memory 210284 kb
Host smart-3afaca30-6c51-49fa-ae01-33026543a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820412583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.820412583
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1968847974
Short name T769
Test name
Test status
Simulation time 14316095 ps
CPU time 0.85 seconds
Started Jul 01 05:08:53 PM PDT 24
Finished Jul 01 05:08:55 PM PDT 24
Peak memory 206080 kb
Host smart-532e78e2-4d21-44f0-959f-642e46f11753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968847974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1968847974
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2863361431
Short name T405
Test name
Test status
Simulation time 57630732 ps
CPU time 3.58 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 214920 kb
Host smart-6560d0db-f2f0-426d-9be1-e4e69870cd49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863361431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2863361431
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2459411649
Short name T63
Test name
Test status
Simulation time 75184592 ps
CPU time 2.83 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 218124 kb
Host smart-206eb4ca-ca36-4e41-800b-12e30206d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459411649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2459411649
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3219288083
Short name T804
Test name
Test status
Simulation time 234735434 ps
CPU time 2.49 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:05 PM PDT 24
Peak memory 206996 kb
Host smart-2fa2d801-c983-444a-bfe2-89edcd6e74ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219288083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3219288083
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.300043037
Short name T482
Test name
Test status
Simulation time 56453302 ps
CPU time 1.99 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 214928 kb
Host smart-b44dbaef-b844-4ebd-a888-169a54927ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300043037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.300043037
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3150930430
Short name T748
Test name
Test status
Simulation time 610833843 ps
CPU time 7.56 seconds
Started Jul 01 05:08:50 PM PDT 24
Finished Jul 01 05:08:59 PM PDT 24
Peak memory 214300 kb
Host smart-ce527d7b-a808-4202-8abc-fecb9362362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150930430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3150930430
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1068361072
Short name T913
Test name
Test status
Simulation time 94071834 ps
CPU time 2.75 seconds
Started Jul 01 05:08:55 PM PDT 24
Finished Jul 01 05:08:58 PM PDT 24
Peak memory 208528 kb
Host smart-c2a40b44-85d0-4169-bf50-3c8d4e1d9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068361072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1068361072
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.867760223
Short name T763
Test name
Test status
Simulation time 139190171 ps
CPU time 2.55 seconds
Started Jul 01 05:08:54 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 206832 kb
Host smart-6cc09dfd-3922-4823-91d8-eb75558ed4d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867760223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.867760223
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1038090792
Short name T344
Test name
Test status
Simulation time 68248831 ps
CPU time 3.29 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 208832 kb
Host smart-b4247235-b569-4eb5-9f39-35082d124748
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038090792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1038090792
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2519665159
Short name T543
Test name
Test status
Simulation time 320639430 ps
CPU time 4.06 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 208884 kb
Host smart-1795c151-d741-436a-a3d9-204c797257c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519665159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2519665159
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.576496050
Short name T606
Test name
Test status
Simulation time 154195676 ps
CPU time 2.79 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 216028 kb
Host smart-b6b207e2-8aa2-4b65-a34d-711106784aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576496050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.576496050
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.4268503879
Short name T416
Test name
Test status
Simulation time 265080536 ps
CPU time 2.37 seconds
Started Jul 01 05:08:49 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 208532 kb
Host smart-8c36e973-31b5-437b-9d35-8c06005917ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268503879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.4268503879
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4078240639
Short name T60
Test name
Test status
Simulation time 1366011248 ps
CPU time 9.53 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:08 PM PDT 24
Peak memory 220048 kb
Host smart-b674d003-aa6c-4de5-96b6-58171201d8c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078240639 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4078240639
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3542886774
Short name T461
Test name
Test status
Simulation time 268966368 ps
CPU time 3.47 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:57 PM PDT 24
Peak memory 207700 kb
Host smart-984c484e-67d6-427a-8b80-552882401b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542886774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3542886774
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3245069805
Short name T776
Test name
Test status
Simulation time 41190474 ps
CPU time 2.22 seconds
Started Jul 01 05:08:49 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 209816 kb
Host smart-82469604-e273-426c-a92e-c7deeef8941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245069805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3245069805
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3492669556
Short name T697
Test name
Test status
Simulation time 31550713 ps
CPU time 0.83 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 206232 kb
Host smart-4639ef53-f779-43b1-9084-123c03b4f87b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492669556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3492669556
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4071149324
Short name T61
Test name
Test status
Simulation time 132840932 ps
CPU time 4.16 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 218608 kb
Host smart-b30203dd-67fa-4c6f-9c15-a375651e9f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071149324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4071149324
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3828000674
Short name T403
Test name
Test status
Simulation time 330515132 ps
CPU time 2.49 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 209868 kb
Host smart-0a85037c-fa86-400f-821d-cfbab5549fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828000674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3828000674
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1155703135
Short name T551
Test name
Test status
Simulation time 100385839 ps
CPU time 2.24 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 214344 kb
Host smart-fc18ef22-a95b-4415-8031-9e7fa098eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155703135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1155703135
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.69933962
Short name T208
Test name
Test status
Simulation time 381203673 ps
CPU time 3.63 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 215312 kb
Host smart-14eaa143-8268-473d-b5ea-633ab97e73e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69933962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.69933962
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4261015779
Short name T363
Test name
Test status
Simulation time 907781845 ps
CPU time 6.37 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:59 PM PDT 24
Peak memory 218068 kb
Host smart-9df6e575-9743-4701-8f47-d5c99a5e627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261015779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4261015779
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4253723228
Short name T737
Test name
Test status
Simulation time 452704869 ps
CPU time 3.5 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 206744 kb
Host smart-da78ddd4-ad64-4710-b17a-13dc094fa764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253723228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4253723228
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2940099814
Short name T703
Test name
Test status
Simulation time 41104812 ps
CPU time 1.92 seconds
Started Jul 01 05:08:51 PM PDT 24
Finished Jul 01 05:08:55 PM PDT 24
Peak memory 207180 kb
Host smart-aee82d1b-6b95-411a-81dd-ad0ed19db450
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940099814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2940099814
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.373640443
Short name T846
Test name
Test status
Simulation time 74002112 ps
CPU time 1.89 seconds
Started Jul 01 05:08:54 PM PDT 24
Finished Jul 01 05:08:56 PM PDT 24
Peak memory 207484 kb
Host smart-2abb0898-901e-4b41-afde-0a82d8277ac1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373640443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.373640443
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1604791998
Short name T201
Test name
Test status
Simulation time 286843043 ps
CPU time 7.57 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:10 PM PDT 24
Peak memory 208872 kb
Host smart-8fda697b-7acb-494d-99ae-d7f2a3cd3fbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604791998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1604791998
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1485255544
Short name T711
Test name
Test status
Simulation time 96684978 ps
CPU time 2.43 seconds
Started Jul 01 05:08:56 PM PDT 24
Finished Jul 01 05:09:00 PM PDT 24
Peak memory 209220 kb
Host smart-63582ed8-129b-47db-bb67-46d96ad28de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485255544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1485255544
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.319381264
Short name T783
Test name
Test status
Simulation time 428803514 ps
CPU time 8.11 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:11 PM PDT 24
Peak memory 208328 kb
Host smart-e83e28e0-548d-42d2-a83f-e6cdcfe83ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319381264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.319381264
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2160692419
Short name T536
Test name
Test status
Simulation time 2084927374 ps
CPU time 18.7 seconds
Started Jul 01 05:09:01 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 208496 kb
Host smart-8235456c-39cc-4b04-a446-87e7e5118d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160692419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2160692419
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2418338950
Short name T111
Test name
Test status
Simulation time 327676445 ps
CPU time 12.25 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:12 PM PDT 24
Peak memory 222604 kb
Host smart-634f538f-9c66-4c33-a899-1ab67f1051c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418338950 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2418338950
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.781239425
Short name T322
Test name
Test status
Simulation time 3518851332 ps
CPU time 20.86 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 219816 kb
Host smart-5adf29b7-eff3-484e-a12c-ab5bee3eaa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781239425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.781239425
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.287856227
Short name T96
Test name
Test status
Simulation time 29198277 ps
CPU time 1.61 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 208784 kb
Host smart-06187c91-015c-470f-aa2a-fd8ee82ac12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287856227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.287856227
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2851106328
Short name T535
Test name
Test status
Simulation time 26136336 ps
CPU time 0.95 seconds
Started Jul 01 05:09:01 PM PDT 24
Finished Jul 01 05:09:04 PM PDT 24
Peak memory 206064 kb
Host smart-170a57df-ed8f-4232-bf8d-f903e31f7483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851106328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2851106328
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1610471018
Short name T384
Test name
Test status
Simulation time 35507418 ps
CPU time 3.01 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 214348 kb
Host smart-37a6518d-79e3-4f09-9dbb-96a7b6dd3715
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610471018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1610471018
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3776068687
Short name T699
Test name
Test status
Simulation time 200364341 ps
CPU time 2.91 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 209168 kb
Host smart-34bf3457-72b1-4214-b25e-55d899abd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776068687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3776068687
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3701137326
Short name T278
Test name
Test status
Simulation time 293010930 ps
CPU time 3.5 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:05 PM PDT 24
Peak memory 214332 kb
Host smart-115dbd93-9f99-48ac-8fc9-ef7a3e157a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701137326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3701137326
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.606072236
Short name T292
Test name
Test status
Simulation time 43657747 ps
CPU time 2.6 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:04 PM PDT 24
Peak memory 214456 kb
Host smart-9d2cdc83-6222-4343-b5df-e9413c0f84ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606072236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.606072236
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.500039503
Short name T822
Test name
Test status
Simulation time 103893631 ps
CPU time 3.3 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 210276 kb
Host smart-0ad245f6-c0ce-442d-b548-d03e763e4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500039503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.500039503
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2473612144
Short name T502
Test name
Test status
Simulation time 810315191 ps
CPU time 6.56 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 218400 kb
Host smart-3ac5670e-e233-4fca-abbc-28c349b5f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473612144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2473612144
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2020519698
Short name T356
Test name
Test status
Simulation time 92176801 ps
CPU time 4.03 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 208564 kb
Host smart-2ca88871-5da8-4763-9e4b-f1db66e126de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020519698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2020519698
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3842776991
Short name T575
Test name
Test status
Simulation time 187535717 ps
CPU time 7.4 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:09 PM PDT 24
Peak memory 208400 kb
Host smart-a0b650fe-5287-4078-9035-826d825f43fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842776991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3842776991
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3143486809
Short name T451
Test name
Test status
Simulation time 651655510 ps
CPU time 16.21 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 209060 kb
Host smart-b4b600e1-d9ed-49ab-86d7-74c2eb70e2d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143486809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3143486809
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2402559830
Short name T718
Test name
Test status
Simulation time 123315438 ps
CPU time 5.6 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 208188 kb
Host smart-3aaee6f0-72c0-4b81-b02d-e93ecbdde150
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402559830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2402559830
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4054663729
Short name T391
Test name
Test status
Simulation time 33422649 ps
CPU time 1.97 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 208040 kb
Host smart-1aaaf3f9-16f6-4b7b-aec7-f9a7b678df4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054663729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4054663729
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4272502466
Short name T486
Test name
Test status
Simulation time 482013237 ps
CPU time 5.6 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:08 PM PDT 24
Peak memory 206852 kb
Host smart-4b972e64-e0fc-48a7-8038-8f164d43315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272502466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4272502466
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1505690725
Short name T564
Test name
Test status
Simulation time 219852563 ps
CPU time 5.98 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 218216 kb
Host smart-603aab80-b2aa-419d-80db-391b9f6b5d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505690725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1505690725
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1377237449
Short name T44
Test name
Test status
Simulation time 2766749386 ps
CPU time 23.5 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 222688 kb
Host smart-d3a9f822-99e5-49f4-b8e4-e2189fd33de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377237449 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1377237449
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3211823779
Short name T113
Test name
Test status
Simulation time 123688766 ps
CPU time 4.37 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 208504 kb
Host smart-b0e30e81-0f18-44a7-9e40-c0dced7e594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211823779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3211823779
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2979811612
Short name T49
Test name
Test status
Simulation time 173706083 ps
CPU time 2.07 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:00 PM PDT 24
Peak memory 209788 kb
Host smart-1996b945-5c9e-4c02-9879-e523e1ac038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979811612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2979811612
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2990254691
Short name T851
Test name
Test status
Simulation time 17795944 ps
CPU time 1.03 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 206200 kb
Host smart-a98728b0-a2b6-4f3f-9720-70c99d06122c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990254691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2990254691
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1736300211
Short name T409
Test name
Test status
Simulation time 39530962 ps
CPU time 3.12 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 214684 kb
Host smart-94b512e9-b644-43cd-8f02-27c703cfe5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736300211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1736300211
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2019196092
Short name T26
Test name
Test status
Simulation time 455333841 ps
CPU time 3.46 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 222828 kb
Host smart-d0b9e453-4bb8-4b4a-bc7f-da8e95ec44aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019196092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2019196092
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3582608814
Short name T693
Test name
Test status
Simulation time 85903801 ps
CPU time 3.98 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 214340 kb
Host smart-af55a63d-e9b8-408e-9781-12430e78be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582608814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3582608814
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3549499354
Short name T237
Test name
Test status
Simulation time 215907163 ps
CPU time 2.67 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:04 PM PDT 24
Peak memory 214336 kb
Host smart-ca2c799c-624e-428b-85f0-43894164c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549499354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3549499354
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3772143481
Short name T496
Test name
Test status
Simulation time 1190187021 ps
CPU time 4.3 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 209956 kb
Host smart-8c724757-069f-428d-9ebc-a87782996147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772143481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3772143481
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1272424583
Short name T97
Test name
Test status
Simulation time 1609120569 ps
CPU time 5.52 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 207116 kb
Host smart-c6413049-395f-461e-927e-e4f43922d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272424583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1272424583
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.370438664
Short name T432
Test name
Test status
Simulation time 179939428 ps
CPU time 5.9 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 208020 kb
Host smart-1bf996c2-5b06-46a7-bcb8-6dd47c77154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370438664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.370438664
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2542056274
Short name T900
Test name
Test status
Simulation time 167941978 ps
CPU time 3.61 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 208748 kb
Host smart-5fc0894b-4659-4dd3-8760-a888c6854e19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542056274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2542056274
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3776331014
Short name T608
Test name
Test status
Simulation time 106348879 ps
CPU time 4.57 seconds
Started Jul 01 05:08:59 PM PDT 24
Finished Jul 01 05:09:07 PM PDT 24
Peak memory 208748 kb
Host smart-ac981b24-292d-442f-9f69-bd64760f3174
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776331014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3776331014
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2862965469
Short name T200
Test name
Test status
Simulation time 87160117 ps
CPU time 1.86 seconds
Started Jul 01 05:08:58 PM PDT 24
Finished Jul 01 05:09:03 PM PDT 24
Peak memory 207580 kb
Host smart-b87dbe92-7a8b-4279-b4bd-e6b7d525d563
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862965469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2862965469
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3031940208
Short name T562
Test name
Test status
Simulation time 107682115 ps
CPU time 3.39 seconds
Started Jul 01 05:09:00 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 208728 kb
Host smart-acb7dd76-69de-4ab4-af8d-37ddaa59b7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031940208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3031940208
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.259931040
Short name T880
Test name
Test status
Simulation time 162767820 ps
CPU time 1.84 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:01 PM PDT 24
Peak memory 208620 kb
Host smart-0d44d87c-f52b-469d-84d1-3c105bfb989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259931040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.259931040
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1180817215
Short name T324
Test name
Test status
Simulation time 896766618 ps
CPU time 27.79 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 222428 kb
Host smart-c127ac0c-38b7-4ace-bf8f-ebb4eb51bce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180817215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1180817215
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1521705797
Short name T59
Test name
Test status
Simulation time 266246541 ps
CPU time 5.09 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 222720 kb
Host smart-88dc3719-aa0a-49aa-8809-23cd6370fb51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521705797 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1521705797
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2426456514
Short name T433
Test name
Test status
Simulation time 225767817 ps
CPU time 6 seconds
Started Jul 01 05:08:57 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 214360 kb
Host smart-f6592cda-c178-40fe-b3dc-900815caa3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426456514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2426456514
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1911879089
Short name T914
Test name
Test status
Simulation time 96151799 ps
CPU time 3.43 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 210680 kb
Host smart-e28f00b0-010c-4ce6-be49-aa3fb7a49965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911879089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1911879089
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4188941777
Short name T758
Test name
Test status
Simulation time 39413355 ps
CPU time 0.89 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:09 PM PDT 24
Peak memory 206120 kb
Host smart-8aa0dc86-be20-4365-a319-82755ef821f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188941777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4188941777
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2868331409
Short name T382
Test name
Test status
Simulation time 163213362 ps
CPU time 3.18 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 214340 kb
Host smart-a3bccb9b-0a9e-4715-9f59-cd95a1c1ed23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868331409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2868331409
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1835329860
Short name T751
Test name
Test status
Simulation time 203614107 ps
CPU time 3.02 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 209760 kb
Host smart-61402d76-871e-4949-aee2-f6881091e776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835329860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1835329860
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3115364874
Short name T85
Test name
Test status
Simulation time 199129018 ps
CPU time 2.87 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:12 PM PDT 24
Peak memory 209508 kb
Host smart-5d87b35d-d703-4701-b77d-84123d08c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115364874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3115364874
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4250432851
Short name T916
Test name
Test status
Simulation time 33430813 ps
CPU time 2.61 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 216968 kb
Host smart-620d3c1f-a8e2-4779-b827-d6be53ab716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250432851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4250432851
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2944132068
Short name T270
Test name
Test status
Simulation time 153698191 ps
CPU time 3.75 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 214424 kb
Host smart-b9cc25d1-5c39-4df5-b6d9-e603b4bd99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944132068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2944132068
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.459348279
Short name T895
Test name
Test status
Simulation time 245487239 ps
CPU time 4.6 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 208208 kb
Host smart-22d7395d-7ab1-4577-8ef7-9e69e5ea17d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459348279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.459348279
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2415054554
Short name T525
Test name
Test status
Simulation time 115623217 ps
CPU time 3.34 seconds
Started Jul 01 05:09:06 PM PDT 24
Finished Jul 01 05:09:10 PM PDT 24
Peak memory 206880 kb
Host smart-b7ba480b-d988-4950-85f6-a50588a4269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415054554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2415054554
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3636838752
Short name T613
Test name
Test status
Simulation time 201597154 ps
CPU time 2.93 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 208828 kb
Host smart-b5ba2583-0492-47d4-85c7-814549cf634a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636838752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3636838752
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.778181628
Short name T509
Test name
Test status
Simulation time 643968248 ps
CPU time 4.9 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 208492 kb
Host smart-c06fc36f-218f-4284-a4d3-96f1094f18a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778181628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.778181628
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.638019248
Short name T622
Test name
Test status
Simulation time 440492882 ps
CPU time 5.32 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:25 PM PDT 24
Peak memory 208400 kb
Host smart-4013b730-ae2c-4183-9fbd-f4e610111fdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638019248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.638019248
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.381602883
Short name T810
Test name
Test status
Simulation time 1111080857 ps
CPU time 3.06 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:12 PM PDT 24
Peak memory 208592 kb
Host smart-7231ab4c-9dbe-4c3e-95b7-bf2f19b65e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381602883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.381602883
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2972666371
Short name T569
Test name
Test status
Simulation time 19416008 ps
CPU time 1.68 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:09 PM PDT 24
Peak memory 206708 kb
Host smart-ed5b4681-bd93-44e9-8823-3bf2500b7cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972666371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2972666371
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1305169477
Short name T768
Test name
Test status
Simulation time 3882278510 ps
CPU time 30.34 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:51 PM PDT 24
Peak memory 222524 kb
Host smart-142080a4-4f07-4c64-9748-92cf773523d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305169477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1305169477
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2058437881
Short name T873
Test name
Test status
Simulation time 124669782 ps
CPU time 7.62 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 222816 kb
Host smart-6279fbeb-818f-4657-8f00-bdf2de0df0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058437881 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2058437881
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.275435222
Short name T850
Test name
Test status
Simulation time 54696120 ps
CPU time 3.15 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 207728 kb
Host smart-21cf2184-863a-440b-9bcc-08f56697b1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275435222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.275435222
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3392243701
Short name T369
Test name
Test status
Simulation time 158332039 ps
CPU time 3.54 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 210448 kb
Host smart-1470a92e-ee74-46d7-9570-1f7cbeb07f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392243701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3392243701
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1080303204
Short name T172
Test name
Test status
Simulation time 47456650 ps
CPU time 3.46 seconds
Started Jul 01 05:09:12 PM PDT 24
Finished Jul 01 05:09:17 PM PDT 24
Peak memory 215288 kb
Host smart-b60aae30-c972-4637-a4ef-b221163ae5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080303204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1080303204
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1782686162
Short name T20
Test name
Test status
Simulation time 274257487 ps
CPU time 2.97 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 221320 kb
Host smart-029f8486-c70d-4a54-a66e-4aefa07a55e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782686162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1782686162
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1133643782
Short name T503
Test name
Test status
Simulation time 212569500 ps
CPU time 4.94 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 207752 kb
Host smart-95f1f19a-36de-4222-a7d2-e40277bc1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133643782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1133643782
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.712994544
Short name T801
Test name
Test status
Simulation time 58362546 ps
CPU time 3.28 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:12 PM PDT 24
Peak memory 214312 kb
Host smart-8ebe3448-d5ea-451b-b50b-669e69209cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712994544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.712994544
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1428878304
Short name T868
Test name
Test status
Simulation time 247675440 ps
CPU time 1.78 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:12 PM PDT 24
Peak memory 214496 kb
Host smart-68bc4058-fd3c-45bf-83d9-1639c94f775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428878304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1428878304
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3854493020
Short name T353
Test name
Test status
Simulation time 1193691183 ps
CPU time 8.98 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:17 PM PDT 24
Peak memory 208220 kb
Host smart-603e9342-cb9a-4384-a8f5-1d69441ce7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854493020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3854493020
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1262251069
Short name T896
Test name
Test status
Simulation time 187349491 ps
CPU time 4.94 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 208468 kb
Host smart-989ab426-7266-440c-87a2-2ab719954f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262251069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1262251069
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3879775578
Short name T577
Test name
Test status
Simulation time 75863074 ps
CPU time 3.72 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 208900 kb
Host smart-03640aef-5488-4cf3-b7da-fab45075c100
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879775578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3879775578
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3157354526
Short name T912
Test name
Test status
Simulation time 714239367 ps
CPU time 6.15 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 208832 kb
Host smart-77f42bb4-0a15-4065-828d-c992a841abd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157354526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3157354526
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3136254164
Short name T849
Test name
Test status
Simulation time 124734991 ps
CPU time 3.16 seconds
Started Jul 01 05:09:07 PM PDT 24
Finished Jul 01 05:09:11 PM PDT 24
Peak memory 206984 kb
Host smart-bcfb0399-0c0e-410d-a1b7-8355237d30f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136254164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3136254164
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2522722783
Short name T192
Test name
Test status
Simulation time 150326171 ps
CPU time 2.7 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 209936 kb
Host smart-2dbb4342-87d1-42ce-beb9-cd9631af7829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522722783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2522722783
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3023891681
Short name T890
Test name
Test status
Simulation time 56744305 ps
CPU time 2.47 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:15 PM PDT 24
Peak memory 206808 kb
Host smart-79a91ddd-54cf-4fc4-8ab5-51de7079ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023891681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3023891681
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2688344251
Short name T330
Test name
Test status
Simulation time 1354580404 ps
CPU time 34.04 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 222432 kb
Host smart-ba6f82ae-93aa-4184-8da1-70e4159e68ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688344251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2688344251
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.358190716
Short name T453
Test name
Test status
Simulation time 778449132 ps
CPU time 20.61 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 209900 kb
Host smart-ee2d86b9-c62a-4d78-8cf7-8e48332f9cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358190716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.358190716
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.474329277
Short name T728
Test name
Test status
Simulation time 280871733 ps
CPU time 1.96 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 210380 kb
Host smart-c3fbfe7d-2b75-4b6a-ac3f-7c8129753aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474329277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.474329277
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3219800171
Short name T719
Test name
Test status
Simulation time 71757386 ps
CPU time 0.78 seconds
Started Jul 01 05:08:04 PM PDT 24
Finished Jul 01 05:08:06 PM PDT 24
Peak memory 206056 kb
Host smart-ea2fccbf-5da0-40cc-a396-1ce0509876dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219800171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3219800171
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3890634570
Short name T529
Test name
Test status
Simulation time 18811565 ps
CPU time 1.3 seconds
Started Jul 01 05:08:03 PM PDT 24
Finished Jul 01 05:08:05 PM PDT 24
Peak memory 207496 kb
Host smart-998926bf-1760-4422-a574-8f0c502ef2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890634570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3890634570
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2970749550
Short name T80
Test name
Test status
Simulation time 3312319396 ps
CPU time 6.16 seconds
Started Jul 01 05:08:02 PM PDT 24
Finished Jul 01 05:08:10 PM PDT 24
Peak memory 209028 kb
Host smart-f8bf558e-4a63-403f-93de-05e6d1e2590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970749550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2970749550
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2721132221
Short name T666
Test name
Test status
Simulation time 57956521 ps
CPU time 3 seconds
Started Jul 01 05:08:03 PM PDT 24
Finished Jul 01 05:08:08 PM PDT 24
Peak memory 214340 kb
Host smart-fe5e4432-c29a-430f-bbc4-8c4ded817965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721132221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2721132221
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1410363005
Short name T183
Test name
Test status
Simulation time 89117233 ps
CPU time 3.01 seconds
Started Jul 01 05:08:04 PM PDT 24
Finished Jul 01 05:08:09 PM PDT 24
Peak memory 210352 kb
Host smart-eb2286a0-853b-4321-9043-caf0327872a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410363005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1410363005
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2512092699
Short name T727
Test name
Test status
Simulation time 113472403 ps
CPU time 4.83 seconds
Started Jul 01 05:08:08 PM PDT 24
Finished Jul 01 05:08:14 PM PDT 24
Peak memory 210332 kb
Host smart-965c9cd7-91ac-4107-9047-d9e7a67cfc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512092699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2512092699
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2936359778
Short name T9
Test name
Test status
Simulation time 281537434 ps
CPU time 9.59 seconds
Started Jul 01 05:08:03 PM PDT 24
Finished Jul 01 05:08:14 PM PDT 24
Peak memory 234208 kb
Host smart-e9e3513d-7fa4-4686-a4a3-3ed7b53e1a4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936359778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2936359778
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3072298882
Short name T898
Test name
Test status
Simulation time 100061454 ps
CPU time 3.07 seconds
Started Jul 01 05:07:58 PM PDT 24
Finished Jul 01 05:08:02 PM PDT 24
Peak memory 206832 kb
Host smart-7aa41d52-11fd-418b-9232-ead4df44bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072298882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3072298882
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3346008543
Short name T537
Test name
Test status
Simulation time 1516143555 ps
CPU time 46.36 seconds
Started Jul 01 05:08:05 PM PDT 24
Finished Jul 01 05:08:52 PM PDT 24
Peak memory 208280 kb
Host smart-039574f2-e34c-495f-a20b-c192c00df412
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346008543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3346008543
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.794977559
Short name T816
Test name
Test status
Simulation time 269082735 ps
CPU time 3.42 seconds
Started Jul 01 05:08:07 PM PDT 24
Finished Jul 01 05:08:11 PM PDT 24
Peak memory 208540 kb
Host smart-6651d853-0a3a-4262-b12e-4b3cf0d565be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794977559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.794977559
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2087043239
Short name T841
Test name
Test status
Simulation time 302077690 ps
CPU time 3.17 seconds
Started Jul 01 05:08:04 PM PDT 24
Finished Jul 01 05:08:09 PM PDT 24
Peak memory 207036 kb
Host smart-545fb30e-a3c6-40bd-81b7-cfcf9879967b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087043239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2087043239
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2568166154
Short name T581
Test name
Test status
Simulation time 461203277 ps
CPU time 3.03 seconds
Started Jul 01 05:07:56 PM PDT 24
Finished Jul 01 05:08:00 PM PDT 24
Peak memory 206800 kb
Host smart-524de9e2-3d66-4ea6-a620-162ae03191a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568166154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2568166154
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1722593628
Short name T790
Test name
Test status
Simulation time 393790719 ps
CPU time 16.02 seconds
Started Jul 01 05:08:02 PM PDT 24
Finished Jul 01 05:08:20 PM PDT 24
Peak memory 216144 kb
Host smart-beb1fdf3-53a4-4ddb-a2f0-4139dfa89aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722593628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1722593628
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2525235267
Short name T167
Test name
Test status
Simulation time 1117469224 ps
CPU time 12.67 seconds
Started Jul 01 05:08:02 PM PDT 24
Finished Jul 01 05:08:16 PM PDT 24
Peak memory 222704 kb
Host smart-a006075c-3f0c-4774-8bc1-9ed1066172f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525235267 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2525235267
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3113991821
Short name T854
Test name
Test status
Simulation time 650097141 ps
CPU time 9.24 seconds
Started Jul 01 05:08:03 PM PDT 24
Finished Jul 01 05:08:14 PM PDT 24
Peak memory 207844 kb
Host smart-07793389-c777-4a7b-acde-558e78d9689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113991821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3113991821
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.176174317
Short name T557
Test name
Test status
Simulation time 12520165 ps
CPU time 0.91 seconds
Started Jul 01 05:09:11 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 206080 kb
Host smart-b9d058ff-6a1f-4646-8b02-b3a8aa85f9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176174317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.176174317
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3181250677
Short name T117
Test name
Test status
Simulation time 918163692 ps
CPU time 12.82 seconds
Started Jul 01 05:09:11 PM PDT 24
Finished Jul 01 05:09:26 PM PDT 24
Peak memory 214356 kb
Host smart-a7851dc3-a3f8-4e2f-9c42-c1b95ff2ebfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181250677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3181250677
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.829997293
Short name T69
Test name
Test status
Simulation time 441657899 ps
CPU time 14.57 seconds
Started Jul 01 05:09:12 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 209728 kb
Host smart-876df25e-793b-411e-9d5e-0835c3a14de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829997293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.829997293
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.365144072
Short name T91
Test name
Test status
Simulation time 122273554 ps
CPU time 2.95 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 222380 kb
Host smart-403823d7-f60a-4781-b65d-793897230322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365144072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.365144072
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.1776550105
Short name T116
Test name
Test status
Simulation time 681196318 ps
CPU time 9.56 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:20 PM PDT 24
Peak memory 218340 kb
Host smart-40adb648-136e-43a5-9fd9-acda4a292a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776550105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1776550105
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2898059257
Short name T641
Test name
Test status
Simulation time 592241669 ps
CPU time 7.65 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 209108 kb
Host smart-89287aa3-e951-473a-8da3-2e495e4cca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898059257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2898059257
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1727855480
Short name T305
Test name
Test status
Simulation time 595467441 ps
CPU time 5.71 seconds
Started Jul 01 05:09:11 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 206792 kb
Host smart-81c83547-46ca-47ef-ba34-a91402cd1d94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727855480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1727855480
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2827094102
Short name T199
Test name
Test status
Simulation time 212174195 ps
CPU time 2.96 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 206992 kb
Host smart-d4fbdab2-a2a9-49cb-9029-4498edb153ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827094102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2827094102
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1123828891
Short name T590
Test name
Test status
Simulation time 360743469 ps
CPU time 3.26 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:16 PM PDT 24
Peak memory 206980 kb
Host smart-0fcf0add-0e62-490e-968f-d4b4f2836b19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123828891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1123828891
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2850407059
Short name T619
Test name
Test status
Simulation time 61926059 ps
CPU time 1.59 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 207808 kb
Host smart-c3928ed3-01de-46d5-8a1e-410185396706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850407059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2850407059
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3191179936
Short name T568
Test name
Test status
Simulation time 301182583 ps
CPU time 8.66 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 208416 kb
Host smart-2746d3b2-7dd6-4a4b-ae83-7b3bc66ce70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191179936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3191179936
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4234607730
Short name T785
Test name
Test status
Simulation time 1028173811 ps
CPU time 13.79 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:25 PM PDT 24
Peak memory 216712 kb
Host smart-101b702d-b342-4d81-89a2-b5053dbb4746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234607730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4234607730
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1055187714
Short name T170
Test name
Test status
Simulation time 1432895506 ps
CPU time 7.46 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 222624 kb
Host smart-8e043092-d901-4396-9d8e-23d408c66c56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055187714 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1055187714
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4270979352
Short name T193
Test name
Test status
Simulation time 1266928643 ps
CPU time 30.33 seconds
Started Jul 01 05:09:09 PM PDT 24
Finished Jul 01 05:09:42 PM PDT 24
Peak memory 209316 kb
Host smart-9ab15b5a-c140-4263-a127-0b18902265be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270979352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4270979352
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.16744538
Short name T907
Test name
Test status
Simulation time 126918426 ps
CPU time 2.46 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 209864 kb
Host smart-ecd86009-1ef4-4f06-af6d-bc7f4c164953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16744538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.16744538
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3831186381
Short name T750
Test name
Test status
Simulation time 64761554 ps
CPU time 0.88 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 206068 kb
Host smart-810025df-cfe8-44cf-81a9-7003dec6b892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831186381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3831186381
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4011974822
Short name T351
Test name
Test status
Simulation time 216009866 ps
CPU time 4.11 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 214976 kb
Host smart-09034aee-c295-4693-b335-44eff7de8565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011974822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4011974822
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.44973476
Short name T301
Test name
Test status
Simulation time 154001856 ps
CPU time 5.18 seconds
Started Jul 01 05:09:10 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 207560 kb
Host smart-60b64be5-9beb-4150-a039-48eb1d11c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44973476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.44973476
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2961846632
Short name T321
Test name
Test status
Simulation time 77181030 ps
CPU time 3.39 seconds
Started Jul 01 05:09:14 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 218492 kb
Host smart-444cca03-8ddd-4f50-9ae5-e7353a4bf33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961846632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2961846632
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.206126598
Short name T43
Test name
Test status
Simulation time 504034882 ps
CPU time 2.79 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 206896 kb
Host smart-62be33d0-fb59-42d2-9c01-b9f80e4bd805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206126598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.206126598
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.2890950656
Short name T307
Test name
Test status
Simulation time 9016538110 ps
CPU time 43.53 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 214472 kb
Host smart-84572fef-41d3-4772-84ba-f3d6a88e4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890950656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2890950656
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3901576762
Short name T275
Test name
Test status
Simulation time 4497190282 ps
CPU time 27.17 seconds
Started Jul 01 05:09:11 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 208856 kb
Host smart-63d53bc0-6dd6-425d-991d-671ecde15e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901576762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3901576762
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2178414397
Short name T616
Test name
Test status
Simulation time 103630811 ps
CPU time 2.8 seconds
Started Jul 01 05:09:12 PM PDT 24
Finished Jul 01 05:09:17 PM PDT 24
Peak memory 208532 kb
Host smart-59bf01a4-9819-428f-9540-4ca69f30a37e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178414397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2178414397
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3406843524
Short name T674
Test name
Test status
Simulation time 125695107 ps
CPU time 4.17 seconds
Started Jul 01 05:09:13 PM PDT 24
Finished Jul 01 05:09:19 PM PDT 24
Peak memory 208932 kb
Host smart-182b2dbb-8f0a-49e8-aee7-69fb33d5a10d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406843524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3406843524
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.565869762
Short name T180
Test name
Test status
Simulation time 200149120 ps
CPU time 1.69 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 207692 kb
Host smart-18b2a9d6-76a8-4193-b4b1-e7c512cf8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565869762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.565869762
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3606256405
Short name T585
Test name
Test status
Simulation time 22870435 ps
CPU time 1.77 seconds
Started Jul 01 05:09:08 PM PDT 24
Finished Jul 01 05:09:11 PM PDT 24
Peak memory 208788 kb
Host smart-81438f9f-b622-40d7-a307-803add329b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606256405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3606256405
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3132752836
Short name T796
Test name
Test status
Simulation time 1023394502 ps
CPU time 6.21 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 209200 kb
Host smart-142208f9-5efc-4584-8f1a-f46aa0749dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132752836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3132752836
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1227075597
Short name T371
Test name
Test status
Simulation time 371754673 ps
CPU time 3.02 seconds
Started Jul 01 05:09:14 PM PDT 24
Finished Jul 01 05:09:20 PM PDT 24
Peak memory 209976 kb
Host smart-5edb0b05-8da5-4063-ac4b-1630a3999c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227075597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1227075597
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2807218855
Short name T521
Test name
Test status
Simulation time 54869868 ps
CPU time 0.85 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:20 PM PDT 24
Peak memory 206176 kb
Host smart-0cbd0606-1b14-408e-93c6-a68d69a70526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807218855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2807218855
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.208116761
Short name T611
Test name
Test status
Simulation time 144598789 ps
CPU time 3.13 seconds
Started Jul 01 05:09:26 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 209756 kb
Host smart-9b8be852-5e6b-435d-9788-e3b8ed190993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208116761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.208116761
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.190131752
Short name T455
Test name
Test status
Simulation time 254058755 ps
CPU time 3.46 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 209036 kb
Host smart-14c41884-0180-41c6-9486-acece18d1412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190131752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.190131752
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2406799841
Short name T573
Test name
Test status
Simulation time 112250056 ps
CPU time 2.8 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 222532 kb
Host smart-fe3911fd-02f0-4a5b-aca1-63c0f64e73fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406799841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2406799841
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.4205452948
Short name T701
Test name
Test status
Simulation time 52208230 ps
CPU time 3.36 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 208224 kb
Host smart-3809b93c-d238-405a-86d0-9beb9499aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205452948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4205452948
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.963711312
Short name T555
Test name
Test status
Simulation time 21749722 ps
CPU time 1.7 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 207112 kb
Host smart-bcc379b6-329c-4d0e-a507-9d3bd9166be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963711312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.963711312
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.388802664
Short name T742
Test name
Test status
Simulation time 76910282 ps
CPU time 3.29 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 208300 kb
Host smart-2632a7fd-9945-4ece-adb8-3fa570cdad80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388802664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.388802664
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1488539431
Short name T838
Test name
Test status
Simulation time 208087274 ps
CPU time 3.18 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 207760 kb
Host smart-fc65b5c1-5122-4a69-b916-ce862f2d2ada
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488539431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1488539431
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1254231335
Short name T893
Test name
Test status
Simulation time 3204636037 ps
CPU time 6.69 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 208720 kb
Host smart-8c32fa42-4d18-4035-a491-373d5a1392ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254231335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1254231335
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3949459961
Short name T174
Test name
Test status
Simulation time 30663627 ps
CPU time 1.95 seconds
Started Jul 01 05:09:17 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 214352 kb
Host smart-75c5425d-3381-4a80-aff3-caa36e9dbc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949459961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3949459961
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2316327344
Short name T724
Test name
Test status
Simulation time 150773414 ps
CPU time 2 seconds
Started Jul 01 05:09:18 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 206828 kb
Host smart-5ca5077e-5baf-4f6e-97f5-63f52c7bf673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316327344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2316327344
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1599896722
Short name T651
Test name
Test status
Simulation time 1045080431 ps
CPU time 12.16 seconds
Started Jul 01 05:09:25 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 216540 kb
Host smart-e27e0399-c921-40e6-886f-6d8017244d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599896722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1599896722
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2962296898
Short name T759
Test name
Test status
Simulation time 1530602364 ps
CPU time 25.35 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 208564 kb
Host smart-7685e1d7-0d06-4707-9947-0ddd569f3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962296898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2962296898
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.815960376
Short name T593
Test name
Test status
Simulation time 1506242846 ps
CPU time 4.39 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 211116 kb
Host smart-3b52378b-a807-41c8-b787-9e2e65d13c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815960376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.815960376
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.685404804
Short name T599
Test name
Test status
Simulation time 16458124 ps
CPU time 0.89 seconds
Started Jul 01 05:09:18 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 206132 kb
Host smart-39bc76ce-31b3-47a3-97bf-40c24561ee2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685404804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.685404804
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3892256375
Short name T230
Test name
Test status
Simulation time 66280860 ps
CPU time 2.74 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 215004 kb
Host smart-1748fc32-892d-4c5a-9607-235ff25dce11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892256375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3892256375
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3671804152
Short name T780
Test name
Test status
Simulation time 45238202 ps
CPU time 1.91 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 209092 kb
Host smart-66e0e3d9-689c-413b-a10b-b8055f1a8416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671804152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3671804152
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.726322413
Short name T390
Test name
Test status
Simulation time 33617951 ps
CPU time 1.87 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:21 PM PDT 24
Peak memory 214420 kb
Host smart-7b1192bc-9bc9-4253-bbb0-afacb5bd5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726322413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.726322413
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.793339765
Short name T659
Test name
Test status
Simulation time 280078927 ps
CPU time 6.06 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 214280 kb
Host smart-1d654438-d54f-41ec-aa70-c0dd0a586fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793339765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.793339765
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4013713173
Short name T239
Test name
Test status
Simulation time 75266692 ps
CPU time 3.18 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 214280 kb
Host smart-fb805e6d-cb52-4042-ba06-8c758b407a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013713173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4013713173
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2268106869
Short name T470
Test name
Test status
Simulation time 96504328 ps
CPU time 3.13 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:23 PM PDT 24
Peak memory 215316 kb
Host smart-cb301dea-4aa5-4f2a-9144-a951b60a56b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268106869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2268106869
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.686472477
Short name T672
Test name
Test status
Simulation time 298311840 ps
CPU time 4.44 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:25 PM PDT 24
Peak memory 209088 kb
Host smart-d252cd83-e1a3-469d-aa01-65146bcf9711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686472477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.686472477
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2220959433
Short name T478
Test name
Test status
Simulation time 184231143 ps
CPU time 2.97 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 208604 kb
Host smart-8defed6d-1c9f-4795-995e-63a00569a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220959433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2220959433
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3612356504
Short name T328
Test name
Test status
Simulation time 20018813 ps
CPU time 1.88 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:21 PM PDT 24
Peak memory 207048 kb
Host smart-4ce0d3ac-bb72-4019-865b-b2f041df9d07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612356504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3612356504
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.224313171
Short name T626
Test name
Test status
Simulation time 148085059 ps
CPU time 3.63 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 208596 kb
Host smart-877d0125-bbac-4eb0-b847-817838b4d675
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224313171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.224313171
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3657971449
Short name T294
Test name
Test status
Simulation time 28601972 ps
CPU time 2.15 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:22 PM PDT 24
Peak memory 208588 kb
Host smart-a22341af-cb9b-4ce2-93a0-b1b3f7a00e14
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657971449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3657971449
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4102665857
Short name T772
Test name
Test status
Simulation time 84144114 ps
CPU time 1.74 seconds
Started Jul 01 05:09:18 PM PDT 24
Finished Jul 01 05:09:24 PM PDT 24
Peak memory 214380 kb
Host smart-515898f2-676c-42b9-b135-98b3f128e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102665857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4102665857
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4129432657
Short name T471
Test name
Test status
Simulation time 98583606 ps
CPU time 2.58 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 206720 kb
Host smart-55074906-22b0-4cfb-aad4-b9b6411a0c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129432657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4129432657
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3998081682
Short name T171
Test name
Test status
Simulation time 1001735136 ps
CPU time 17.36 seconds
Started Jul 01 05:09:16 PM PDT 24
Finished Jul 01 05:09:37 PM PDT 24
Peak memory 220740 kb
Host smart-a93beff4-c094-4a42-8fc4-d02a33f671e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998081682 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3998081682
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1220976754
Short name T741
Test name
Test status
Simulation time 444419984 ps
CPU time 11.82 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:34 PM PDT 24
Peak memory 214324 kb
Host smart-d6786471-50e5-44c6-987c-3b987ef9d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220976754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1220976754
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.511759609
Short name T793
Test name
Test status
Simulation time 211114674 ps
CPU time 2.51 seconds
Started Jul 01 05:09:14 PM PDT 24
Finished Jul 01 05:09:20 PM PDT 24
Peak memory 209848 kb
Host smart-7b3446c8-9686-47f1-8cf2-c49c0195fc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511759609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.511759609
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3192836108
Short name T522
Test name
Test status
Simulation time 41097978 ps
CPU time 0.73 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 206008 kb
Host smart-2ece25f5-b7d1-4ab5-b8c9-1378b2a10cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192836108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3192836108
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4044150123
Short name T402
Test name
Test status
Simulation time 112506061 ps
CPU time 6.36 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 215672 kb
Host smart-a112f2fd-2f95-4c8e-9f7c-a88278096dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044150123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4044150123
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.168723076
Short name T17
Test name
Test status
Simulation time 76116264 ps
CPU time 3.32 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 219784 kb
Host smart-3eb38bf0-a7cd-43a2-a974-ea38f104db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168723076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.168723076
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2613727292
Short name T720
Test name
Test status
Simulation time 90907021 ps
CPU time 2.72 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:21 PM PDT 24
Peak memory 208116 kb
Host smart-345915e3-8d06-4578-88f5-10d85dfcd597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613727292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2613727292
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1127755669
Short name T81
Test name
Test status
Simulation time 2311889148 ps
CPU time 72.27 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 209644 kb
Host smart-52e33853-691a-49b1-9a46-6c46d3420657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127755669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1127755669
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3101072003
Short name T340
Test name
Test status
Simulation time 90508967 ps
CPU time 1.88 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:21 PM PDT 24
Peak memory 214292 kb
Host smart-9c6fd38e-d8cb-4587-8d6f-ac05f21511bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101072003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3101072003
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2470403041
Short name T546
Test name
Test status
Simulation time 387074824 ps
CPU time 3.64 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 214204 kb
Host smart-ed897f71-3533-4c03-9a73-ee7a65ccb153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470403041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2470403041
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4115411047
Short name T673
Test name
Test status
Simulation time 838292513 ps
CPU time 5.22 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 207580 kb
Host smart-1451edae-cb08-4fb2-a005-5ec8ee1b4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115411047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4115411047
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.520962652
Short name T632
Test name
Test status
Simulation time 125727575 ps
CPU time 4.57 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 207996 kb
Host smart-61f542e6-1366-4499-90b7-18f51f7ec76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520962652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.520962652
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1796314117
Short name T513
Test name
Test status
Simulation time 543563205 ps
CPU time 4.79 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 206956 kb
Host smart-2233f70b-9d47-482f-960d-bccc6e85b6ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796314117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1796314117
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3243579715
Short name T242
Test name
Test status
Simulation time 143663997 ps
CPU time 4.61 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:27 PM PDT 24
Peak memory 208764 kb
Host smart-c5d7ea5f-98a5-4b2e-9c6b-8485999badf4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243579715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3243579715
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1130302441
Short name T676
Test name
Test status
Simulation time 837025519 ps
CPU time 19.62 seconds
Started Jul 01 05:09:15 PM PDT 24
Finished Jul 01 05:09:38 PM PDT 24
Peak memory 208908 kb
Host smart-632948ae-b143-4a01-b1e1-d6a1c5c0f1ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130302441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1130302441
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1302668085
Short name T469
Test name
Test status
Simulation time 16158134 ps
CPU time 1.5 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 207972 kb
Host smart-9864f9e8-4dc0-45e7-9e62-a39e76601a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302668085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1302668085
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4174709094
Short name T443
Test name
Test status
Simulation time 47084762 ps
CPU time 2.32 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 206864 kb
Host smart-302f4d9a-7380-4549-92ea-6b967ce40a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174709094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4174709094
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4046804783
Short name T840
Test name
Test status
Simulation time 3211588958 ps
CPU time 6.7 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 209256 kb
Host smart-8deab91d-90fd-4390-b671-39de3569f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046804783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4046804783
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3309513164
Short name T643
Test name
Test status
Simulation time 67757385 ps
CPU time 2.75 seconds
Started Jul 01 05:09:18 PM PDT 24
Finished Jul 01 05:09:25 PM PDT 24
Peak memory 209900 kb
Host smart-e21cb6e7-e149-4b9f-bdd5-edf41c00e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309513164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3309513164
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1058487448
Short name T434
Test name
Test status
Simulation time 32925933 ps
CPU time 0.94 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:27 PM PDT 24
Peak memory 206124 kb
Host smart-cf1b3931-a73b-41d5-b8bc-f4880c1cc798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058487448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1058487448
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3167291749
Short name T269
Test name
Test status
Simulation time 64875175 ps
CPU time 4.75 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 222604 kb
Host smart-cd376c0b-87c4-4269-a009-059dc2dce935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167291749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3167291749
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.4240610165
Short name T628
Test name
Test status
Simulation time 265320146 ps
CPU time 2.61 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 215940 kb
Host smart-cd85e873-2434-407b-95ab-393742d8969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240610165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.4240610165
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.326319141
Short name T366
Test name
Test status
Simulation time 413440077 ps
CPU time 3.93 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 207964 kb
Host smart-90675bd6-725b-400d-809c-f5ba475c2fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326319141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.326319141
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4206271745
Short name T99
Test name
Test status
Simulation time 69006562 ps
CPU time 2.67 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 214436 kb
Host smart-dd60b333-0c85-4d56-b867-b6bd9be2dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206271745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4206271745
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2509074802
Short name T207
Test name
Test status
Simulation time 201089329 ps
CPU time 2.6 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:34 PM PDT 24
Peak memory 215020 kb
Host smart-18ae4b94-7f51-49a8-9f8a-ca9301bdcb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509074802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2509074802
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2747750406
Short name T832
Test name
Test status
Simulation time 1126662762 ps
CPU time 7.66 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 208032 kb
Host smart-2b9569f6-399d-45f0-b23a-166969494ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747750406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2747750406
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2343885489
Short name T395
Test name
Test status
Simulation time 107531600 ps
CPU time 1.9 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 207312 kb
Host smart-7758ce89-1264-4dda-bf82-5f56646b4fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343885489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2343885489
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.501868999
Short name T814
Test name
Test status
Simulation time 170929085 ps
CPU time 5.04 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 208964 kb
Host smart-da9e1e28-d1d9-4339-9aa8-32c43a6e52b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501868999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.501868999
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3549010180
Short name T739
Test name
Test status
Simulation time 65247569 ps
CPU time 3.41 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:27 PM PDT 24
Peak memory 208652 kb
Host smart-b190c198-9dba-4a9d-9e91-276744b4dbc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549010180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3549010180
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3684872200
Short name T738
Test name
Test status
Simulation time 1619911538 ps
CPU time 6.73 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 208024 kb
Host smart-e54df28e-5d4a-49b5-b118-d0b97d0e5b67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684872200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3684872200
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3529992478
Short name T668
Test name
Test status
Simulation time 228598323 ps
CPU time 6.83 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 207052 kb
Host smart-54c3839a-7bd2-40b2-af98-bac0615db580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529992478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3529992478
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1258723014
Short name T362
Test name
Test status
Simulation time 1208629792 ps
CPU time 16.37 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 219692 kb
Host smart-ce341d56-6df5-4fb3-9de0-58dc89ceab70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258723014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1258723014
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.283020125
Short name T450
Test name
Test status
Simulation time 1415122849 ps
CPU time 13.73 seconds
Started Jul 01 05:09:24 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 214296 kb
Host smart-0bdf0c89-ebe3-4188-9155-1732a3dac96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283020125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.283020125
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3154911925
Short name T735
Test name
Test status
Simulation time 58798475 ps
CPU time 2.68 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 210016 kb
Host smart-3140d4c6-1835-4834-b940-d8430190865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154911925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3154911925
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4082178939
Short name T770
Test name
Test status
Simulation time 25621224 ps
CPU time 0.98 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:26 PM PDT 24
Peak memory 206112 kb
Host smart-61f486a5-ec5f-4b5a-8017-361273df6b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082178939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4082178939
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.180813309
Short name T396
Test name
Test status
Simulation time 61659705 ps
CPU time 3.45 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 214492 kb
Host smart-8c439533-a313-4a82-8d71-dfa88ada18c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180813309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.180813309
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.838161768
Short name T25
Test name
Test status
Simulation time 63589937 ps
CPU time 3.13 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:28 PM PDT 24
Peak memory 222912 kb
Host smart-899fa36e-f1c0-4f8e-b1c7-306a1d139630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838161768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.838161768
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2195445498
Short name T623
Test name
Test status
Simulation time 557088856 ps
CPU time 2.81 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 207200 kb
Host smart-77e47bcb-7a7d-4faf-b3c1-8606e4b2c56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195445498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2195445498
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4087611182
Short name T78
Test name
Test status
Simulation time 4411294853 ps
CPU time 31.13 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 214564 kb
Host smart-7a22fbfd-44e8-49d9-8508-8c762ff08b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087611182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4087611182
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3686974394
Short name T118
Test name
Test status
Simulation time 155289616 ps
CPU time 5.56 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 216064 kb
Host smart-884a55ab-7ccd-4f68-ac77-a27c4fd4f91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686974394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3686974394
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2630156143
Short name T561
Test name
Test status
Simulation time 855498759 ps
CPU time 5.34 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 222400 kb
Host smart-de861790-0e2f-494c-adfd-5fadd3cdc725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630156143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2630156143
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1638068195
Short name T286
Test name
Test status
Simulation time 609948582 ps
CPU time 15.28 seconds
Started Jul 01 05:09:19 PM PDT 24
Finished Jul 01 05:09:38 PM PDT 24
Peak memory 207748 kb
Host smart-e6cf5dae-5163-4b27-b90d-c21af0e4ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638068195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1638068195
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2725044679
Short name T688
Test name
Test status
Simulation time 1880603608 ps
CPU time 4.68 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:09:35 PM PDT 24
Peak memory 208640 kb
Host smart-82f5ab06-1dcf-49ad-aeb4-afe6830d5cce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725044679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2725044679
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1230309423
Short name T283
Test name
Test status
Simulation time 147832097 ps
CPU time 4.86 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 208204 kb
Host smart-188b85c9-0c47-424d-8f91-a90449f08d17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230309423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1230309423
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3354544957
Short name T694
Test name
Test status
Simulation time 62911834 ps
CPU time 2.72 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 207348 kb
Host smart-84fb98e3-bcb7-45b4-8373-41aa579c61bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354544957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3354544957
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4097185075
Short name T428
Test name
Test status
Simulation time 80635193 ps
CPU time 2.01 seconds
Started Jul 01 05:09:23 PM PDT 24
Finished Jul 01 05:09:29 PM PDT 24
Peak memory 207664 kb
Host smart-bbccf47a-0098-4e72-8895-4bf38707a6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097185075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4097185075
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1745778042
Short name T438
Test name
Test status
Simulation time 172632580 ps
CPU time 4.27 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 208340 kb
Host smart-844487ae-2748-43dd-89e0-56c84a2da3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745778042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1745778042
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1967927082
Short name T300
Test name
Test status
Simulation time 9163599042 ps
CPU time 69.21 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:10:34 PM PDT 24
Peak memory 216028 kb
Host smart-5b66557d-58e0-44d5-a8fe-b27493fe0485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967927082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1967927082
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3057907232
Short name T271
Test name
Test status
Simulation time 106028204 ps
CPU time 4.8 seconds
Started Jul 01 05:09:22 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 208812 kb
Host smart-842c1ce0-bd13-4d58-9920-c29352f80877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057907232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3057907232
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3398613358
Short name T690
Test name
Test status
Simulation time 168838561 ps
CPU time 2.25 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:26 PM PDT 24
Peak memory 210240 kb
Host smart-68fccc36-cf21-43c5-a820-060652981f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398613358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3398613358
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3004415351
Short name T618
Test name
Test status
Simulation time 30827697 ps
CPU time 0.88 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:34 PM PDT 24
Peak memory 206040 kb
Host smart-c22e4726-ff8f-4fbb-bdd2-847aec541bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004415351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3004415351
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4177675419
Short name T702
Test name
Test status
Simulation time 284569409 ps
CPU time 2.29 seconds
Started Jul 01 05:09:35 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 214692 kb
Host smart-515e744b-72f8-4b6a-b8f5-6b19972b3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177675419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4177675419
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2900683791
Short name T675
Test name
Test status
Simulation time 136556616 ps
CPU time 2.15 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 207916 kb
Host smart-295d28e0-5a88-4068-b27d-d388ea195747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900683791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2900683791
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3677715210
Short name T236
Test name
Test status
Simulation time 89071586 ps
CPU time 1.61 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 214308 kb
Host smart-7b4f5341-ef26-4bed-bd61-183aa455ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677715210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3677715210
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1495567993
Short name T62
Test name
Test status
Simulation time 4248565538 ps
CPU time 20.45 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 214340 kb
Host smart-b35ffabc-4599-4ae3-8fca-b0eaed524d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495567993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1495567993
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3370217864
Short name T624
Test name
Test status
Simulation time 1270996731 ps
CPU time 6.46 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 210184 kb
Host smart-e83ee354-93f4-476c-a1c8-bdf4ae0b68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370217864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3370217864
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2152472750
Short name T245
Test name
Test status
Simulation time 526500015 ps
CPU time 5.17 seconds
Started Jul 01 05:09:21 PM PDT 24
Finished Jul 01 05:09:31 PM PDT 24
Peak memory 208528 kb
Host smart-e78b4227-24a7-450e-a8d0-efdfa8aef78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152472750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2152472750
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3697437613
Short name T716
Test name
Test status
Simulation time 694310476 ps
CPU time 7.33 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 208608 kb
Host smart-faaefd2c-180d-4828-b3f2-dfef3b090eb0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697437613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3697437613
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1282647005
Short name T457
Test name
Test status
Simulation time 1811705573 ps
CPU time 31.72 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:10:04 PM PDT 24
Peak memory 208992 kb
Host smart-80edd36a-f298-4841-87d6-72d7b101ebb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282647005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1282647005
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3977376003
Short name T14
Test name
Test status
Simulation time 350124615 ps
CPU time 5.2 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 208432 kb
Host smart-4c3af55d-015f-4ad6-8c91-b7cfe4325a36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977376003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3977376003
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2806140469
Short name T319
Test name
Test status
Simulation time 509229794 ps
CPU time 8.55 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 209108 kb
Host smart-c2db10a5-4da8-4ddd-bc1f-b1d5e4318eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806140469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2806140469
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.15486125
Short name T835
Test name
Test status
Simulation time 840112699 ps
CPU time 6.01 seconds
Started Jul 01 05:09:20 PM PDT 24
Finished Jul 01 05:09:30 PM PDT 24
Peak memory 208332 kb
Host smart-6ec993dc-09b5-4f5f-a1ef-b8c4222ab599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15486125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.15486125
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2921277589
Short name T323
Test name
Test status
Simulation time 26878491078 ps
CPU time 260.36 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:13:56 PM PDT 24
Peak memory 217016 kb
Host smart-3c299a85-bbb5-4921-bc6b-170b444c62d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921277589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2921277589
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4064306317
Short name T808
Test name
Test status
Simulation time 900188933 ps
CPU time 9.57 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 208680 kb
Host smart-b843ab43-65e2-448b-a692-b64388c4ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064306317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4064306317
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1715529591
Short name T90
Test name
Test status
Simulation time 26669521 ps
CPU time 0.76 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:32 PM PDT 24
Peak memory 206112 kb
Host smart-739ceb90-cbea-4c42-b348-1ab0862db58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715529591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1715529591
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4174575255
Short name T53
Test name
Test status
Simulation time 71009309 ps
CPU time 2.64 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:35 PM PDT 24
Peak memory 208580 kb
Host smart-121f8bae-a92d-4ace-8e73-f654f8406f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174575255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4174575255
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4288070858
Short name T318
Test name
Test status
Simulation time 190295709 ps
CPU time 2.74 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:09:38 PM PDT 24
Peak memory 209768 kb
Host smart-1d8a6ee9-8900-4ed4-9e2c-d4d05f7f5815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288070858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4288070858
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2079578423
Short name T767
Test name
Test status
Simulation time 91628026 ps
CPU time 1.91 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:37 PM PDT 24
Peak memory 214456 kb
Host smart-125261c4-f5fd-437b-b462-ca0db411711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079578423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2079578423
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2789682027
Short name T500
Test name
Test status
Simulation time 176571262 ps
CPU time 3.31 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:42 PM PDT 24
Peak memory 207368 kb
Host smart-70e37402-b090-463c-a241-cd46c2b06fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789682027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2789682027
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.210002743
Short name T152
Test name
Test status
Simulation time 29361008 ps
CPU time 2.38 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 220192 kb
Host smart-5a60b49b-26fe-4a7c-b2d0-010879414af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210002743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.210002743
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2882463625
Short name T311
Test name
Test status
Simulation time 4369208078 ps
CPU time 55.02 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 210468 kb
Host smart-e9903772-1203-4f9e-aa00-6f29671cd1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882463625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2882463625
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2965458393
Short name T664
Test name
Test status
Simulation time 66857995 ps
CPU time 3.2 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 208892 kb
Host smart-cd1fa9fd-ae0d-4ea3-a38b-65e1578ab998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965458393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2965458393
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.355642543
Short name T692
Test name
Test status
Simulation time 572705549 ps
CPU time 6.82 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 208324 kb
Host smart-a7497b8c-1c06-4f5e-bc8c-4c1dd46779a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355642543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.355642543
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1288356340
Short name T268
Test name
Test status
Simulation time 133383503 ps
CPU time 4.22 seconds
Started Jul 01 05:09:38 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 208372 kb
Host smart-cbc74cfe-3abf-4653-b3c9-31713c769756
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288356340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1288356340
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1503223204
Short name T495
Test name
Test status
Simulation time 1181632260 ps
CPU time 30.35 seconds
Started Jul 01 05:09:27 PM PDT 24
Finished Jul 01 05:10:00 PM PDT 24
Peak memory 208732 kb
Host smart-493e3e74-c476-482d-ba94-a7a31463f92e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503223204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1503223204
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.812683986
Short name T610
Test name
Test status
Simulation time 39351840 ps
CPU time 2.39 seconds
Started Jul 01 05:09:38 PM PDT 24
Finished Jul 01 05:09:49 PM PDT 24
Peak memory 209860 kb
Host smart-cc726929-d2f4-4fe7-9bf0-13d797f32d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812683986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.812683986
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.265689071
Short name T538
Test name
Test status
Simulation time 168199033 ps
CPU time 3.58 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 207868 kb
Host smart-fbfa8cac-d02d-408e-99f5-e113530fe489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265689071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.265689071
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.4045584147
Short name T2
Test name
Test status
Simulation time 355467226 ps
CPU time 13.67 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 222548 kb
Host smart-8d8d013c-80a2-44e0-9f99-78ddc6d54114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045584147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.4045584147
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2147741826
Short name T819
Test name
Test status
Simulation time 1744037150 ps
CPU time 37.64 seconds
Started Jul 01 05:09:38 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 208568 kb
Host smart-bf890cec-b57e-4527-9a23-22ee6f7511ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147741826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2147741826
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.304307277
Short name T377
Test name
Test status
Simulation time 534366495 ps
CPU time 3.23 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:42 PM PDT 24
Peak memory 210316 kb
Host smart-c2e5a74d-edcc-4dbf-9be7-7fed6ad26f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304307277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.304307277
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.222040666
Short name T762
Test name
Test status
Simulation time 51738740 ps
CPU time 0.77 seconds
Started Jul 01 05:09:36 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 206080 kb
Host smart-00f92d9a-cf88-4100-a50e-e9be9fb1b202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222040666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.222040666
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4211489684
Short name T297
Test name
Test status
Simulation time 219732592 ps
CPU time 4.13 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:36 PM PDT 24
Peak memory 214936 kb
Host smart-a47239ae-4801-4627-9234-64f2c9e89bb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211489684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4211489684
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.516278804
Short name T16
Test name
Test status
Simulation time 71498669 ps
CPU time 5.04 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 214444 kb
Host smart-55b11740-f9a1-43a9-a051-ef47067ea64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516278804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.516278804
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.388019091
Short name T777
Test name
Test status
Simulation time 37688375 ps
CPU time 1.76 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:09:48 PM PDT 24
Peak memory 214332 kb
Host smart-112ffa29-d47f-4193-876c-5b6033e7300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388019091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.388019091
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2831492708
Short name T293
Test name
Test status
Simulation time 236851188 ps
CPU time 2.69 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 214372 kb
Host smart-ffea1f98-050d-4f82-8c0d-f7517dbb871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831492708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2831492708
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3879188786
Short name T47
Test name
Test status
Simulation time 1360693750 ps
CPU time 5.19 seconds
Started Jul 01 05:09:43 PM PDT 24
Finished Jul 01 05:09:56 PM PDT 24
Peak memory 222420 kb
Host smart-b37cf768-d68f-49a2-9128-3ed6642caf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879188786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3879188786
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2349367315
Short name T636
Test name
Test status
Simulation time 61800280 ps
CPU time 2.87 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:37 PM PDT 24
Peak memory 209624 kb
Host smart-8ed55232-39c8-4d7b-8730-7f8cd34cce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349367315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2349367315
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2544834730
Short name T231
Test name
Test status
Simulation time 272232013 ps
CPU time 4.21 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 207992 kb
Host smart-059b4cb3-0a48-4f26-84bc-8fbf72ae139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544834730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2544834730
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2362884280
Short name T654
Test name
Test status
Simulation time 145232788 ps
CPU time 4.19 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:09:51 PM PDT 24
Peak memory 208516 kb
Host smart-1063986b-bd39-4d32-b9bd-99b5e8f750fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362884280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2362884280
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1234938597
Short name T746
Test name
Test status
Simulation time 86640636 ps
CPU time 1.89 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:35 PM PDT 24
Peak memory 207628 kb
Host smart-62a5e05e-1636-484c-9975-873d9361d201
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234938597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1234938597
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1326879266
Short name T910
Test name
Test status
Simulation time 5882400810 ps
CPU time 34.76 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 209040 kb
Host smart-6befe3ce-48f7-45b2-9f6a-504577d53e44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326879266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1326879266
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3938340454
Short name T184
Test name
Test status
Simulation time 263725986 ps
CPU time 3.32 seconds
Started Jul 01 05:09:29 PM PDT 24
Finished Jul 01 05:09:37 PM PDT 24
Peak memory 208640 kb
Host smart-2a1bd789-0680-47e2-8fd9-6e0a5b641430
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938340454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3938340454
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3232781971
Short name T530
Test name
Test status
Simulation time 38288122 ps
CPU time 1.78 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 208184 kb
Host smart-d09bd7b9-80bb-4365-b1e6-70d56584991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232781971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3232781971
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3842230055
Short name T683
Test name
Test status
Simulation time 722440725 ps
CPU time 3.92 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 207940 kb
Host smart-5cdddafc-319a-4f53-9550-ca484a1e050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842230055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3842230055
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3214950489
Short name T187
Test name
Test status
Simulation time 10741815410 ps
CPU time 208.24 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:13:08 PM PDT 24
Peak memory 222484 kb
Host smart-a24fbfe8-6654-4bb5-ba01-b469520ad1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214950489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3214950489
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2415630545
Short name T454
Test name
Test status
Simulation time 604867752 ps
CPU time 7.3 seconds
Started Jul 01 05:09:28 PM PDT 24
Finished Jul 01 05:09:39 PM PDT 24
Peak memory 208748 kb
Host smart-1bcbe4f7-5e00-46b3-bd1d-dea29c06fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415630545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2415630545
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.949546836
Short name T173
Test name
Test status
Simulation time 179928674 ps
CPU time 2.64 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 210464 kb
Host smart-16f1f064-d2fe-4ccc-8664-430023af1e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949546836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.949546836
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4219412174
Short name T511
Test name
Test status
Simulation time 15082510 ps
CPU time 0.83 seconds
Started Jul 01 05:08:12 PM PDT 24
Finished Jul 01 05:08:15 PM PDT 24
Peak memory 206032 kb
Host smart-f2b6fc73-6211-4a13-8eae-d2f931f1911e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219412174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4219412174
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2682266257
Short name T64
Test name
Test status
Simulation time 166193092 ps
CPU time 6.02 seconds
Started Jul 01 05:08:16 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 221528 kb
Host smart-91742ad3-e0c6-433f-9d21-9f23471346c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682266257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2682266257
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2676956307
Short name T700
Test name
Test status
Simulation time 151067461 ps
CPU time 2.03 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:17 PM PDT 24
Peak memory 208796 kb
Host smart-517c4999-08ee-4343-95c6-7fa2bafadd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676956307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2676956307
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.874942096
Short name T290
Test name
Test status
Simulation time 149943303 ps
CPU time 2.15 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:17 PM PDT 24
Peak memory 214512 kb
Host smart-99918671-4dea-46df-a8d6-6000aa5a67ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874942096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.874942096
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3842705693
Short name T519
Test name
Test status
Simulation time 249440190 ps
CPU time 3.8 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:19 PM PDT 24
Peak memory 214292 kb
Host smart-6205812d-c163-4d9f-8a22-c7351b0764a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842705693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3842705693
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1242154798
Short name T879
Test name
Test status
Simulation time 190675633 ps
CPU time 4.6 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:20 PM PDT 24
Peak memory 214896 kb
Host smart-827a96e5-72c4-4864-901d-f87a71a1481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242154798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1242154798
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.410406979
Short name T754
Test name
Test status
Simulation time 750929561 ps
CPU time 8.86 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 214332 kb
Host smart-52c86f3d-3afb-4895-81c9-efff1739445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410406979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.410406979
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1615901585
Short name T10
Test name
Test status
Simulation time 273829327 ps
CPU time 6.28 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:21 PM PDT 24
Peak memory 233496 kb
Host smart-7f05dbf7-cf83-4770-82c2-bb1fa531cd5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615901585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1615901585
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2278207135
Short name T12
Test name
Test status
Simulation time 82807956 ps
CPU time 2.34 seconds
Started Jul 01 05:08:04 PM PDT 24
Finished Jul 01 05:08:07 PM PDT 24
Peak memory 208260 kb
Host smart-8c14e290-da24-4dc5-8912-be3ff283f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278207135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2278207135
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3712088244
Short name T635
Test name
Test status
Simulation time 230536517 ps
CPU time 2.86 seconds
Started Jul 01 05:08:04 PM PDT 24
Finished Jul 01 05:08:09 PM PDT 24
Peak memory 207000 kb
Host smart-80c7e0fa-194a-4361-9e39-426392354f3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712088244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3712088244
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2632634914
Short name T232
Test name
Test status
Simulation time 528312057 ps
CPU time 4.16 seconds
Started Jul 01 05:08:07 PM PDT 24
Finished Jul 01 05:08:12 PM PDT 24
Peak memory 206924 kb
Host smart-b77a4414-016d-463a-ac39-0490a589376e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632634914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2632634914
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.853756060
Short name T862
Test name
Test status
Simulation time 3612287446 ps
CPU time 40.03 seconds
Started Jul 01 05:08:12 PM PDT 24
Finished Jul 01 05:08:54 PM PDT 24
Peak memory 209292 kb
Host smart-e1aba1a4-dc92-4aa6-9855-2f56f0c683f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853756060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.853756060
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4167205001
Short name T196
Test name
Test status
Simulation time 1071395939 ps
CPU time 3.96 seconds
Started Jul 01 05:08:11 PM PDT 24
Finished Jul 01 05:08:16 PM PDT 24
Peak memory 209188 kb
Host smart-872f0844-9ef6-4957-a25a-39079ae01c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167205001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4167205001
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1263024702
Short name T480
Test name
Test status
Simulation time 155406795 ps
CPU time 1.71 seconds
Started Jul 01 05:08:05 PM PDT 24
Finished Jul 01 05:08:08 PM PDT 24
Peak memory 206868 kb
Host smart-487e7b09-78a9-4497-8563-1521487bb411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263024702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1263024702
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2286337313
Short name T244
Test name
Test status
Simulation time 232682301 ps
CPU time 6.84 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:22 PM PDT 24
Peak memory 219848 kb
Host smart-515dcce9-4a0b-46b4-9d6b-7665567c20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286337313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2286337313
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.384418689
Short name T572
Test name
Test status
Simulation time 270317737 ps
CPU time 3.2 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:17 PM PDT 24
Peak memory 210828 kb
Host smart-274da29e-0ffc-4092-9207-7deaec6ae636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384418689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.384418689
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3161832116
Short name T178
Test name
Test status
Simulation time 22210314 ps
CPU time 1.03 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 206184 kb
Host smart-dbd916fa-1dc4-4f30-bf3b-59c59e5788f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161832116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3161832116
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1845279821
Short name T385
Test name
Test status
Simulation time 340535353 ps
CPU time 5.42 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 215504 kb
Host smart-71111559-ff24-4045-a719-2b86802eff96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845279821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1845279821
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3637170879
Short name T71
Test name
Test status
Simulation time 191282259 ps
CPU time 2.47 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 214344 kb
Host smart-05db14fa-408a-4db8-bcbe-d9826e397cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637170879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3637170879
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2437447814
Short name T279
Test name
Test status
Simulation time 26603234 ps
CPU time 1.76 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:44 PM PDT 24
Peak memory 214292 kb
Host smart-4553b0c3-e1ba-4d7e-9fe0-0eddbce1494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437447814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2437447814
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.287614163
Short name T261
Test name
Test status
Simulation time 108498389 ps
CPU time 1.94 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:43 PM PDT 24
Peak memory 222376 kb
Host smart-7dcc8781-b6bf-48a1-96c2-dd7b9cbd0405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287614163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.287614163
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1870951087
Short name T215
Test name
Test status
Simulation time 153375933 ps
CPU time 2.46 seconds
Started Jul 01 05:09:35 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 214352 kb
Host smart-58261223-76a3-4a6b-91c9-4bceca337252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870951087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1870951087
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2065284916
Short name T597
Test name
Test status
Simulation time 750695372 ps
CPU time 8.64 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:48 PM PDT 24
Peak memory 206968 kb
Host smart-3e83aaf2-40ab-4015-b9aa-48deff443539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065284916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2065284916
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.423034225
Short name T156
Test name
Test status
Simulation time 216458341 ps
CPU time 4.53 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:45 PM PDT 24
Peak memory 208604 kb
Host smart-d4253db6-55a7-40d4-95fd-11450b95973a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423034225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.423034225
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2777461923
Short name T574
Test name
Test status
Simulation time 204865706 ps
CPU time 2.92 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:51 PM PDT 24
Peak memory 206964 kb
Host smart-836fcfe4-2706-4b9b-aead-2f2acf7fbb0f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777461923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2777461923
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2010316580
Short name T662
Test name
Test status
Simulation time 258229981 ps
CPU time 5.6 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:47 PM PDT 24
Peak memory 208656 kb
Host smart-0b6d2c24-7685-47d6-b4dc-f381ffec3e55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010316580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2010316580
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3328708970
Short name T706
Test name
Test status
Simulation time 972033836 ps
CPU time 23.69 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 208268 kb
Host smart-82846f2a-89b6-4abf-b41a-8bbba2f7e663
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328708970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3328708970
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2504195563
Short name T485
Test name
Test status
Simulation time 133785825 ps
CPU time 2.38 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:43 PM PDT 24
Peak memory 222580 kb
Host smart-52aa70b0-cf3b-431f-a46e-e28618e42a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504195563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2504195563
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.308402385
Short name T430
Test name
Test status
Simulation time 35857914 ps
CPU time 2.33 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:09:43 PM PDT 24
Peak memory 208468 kb
Host smart-71b0eb31-d57f-4357-9e63-c2ef4860d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308402385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.308402385
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2931849279
Short name T341
Test name
Test status
Simulation time 5026385031 ps
CPU time 38.19 seconds
Started Jul 01 05:09:34 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 222500 kb
Host smart-0b3bd40a-1b61-4351-b2ec-700984fd1f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931849279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2931849279
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1534968911
Short name T592
Test name
Test status
Simulation time 138171636 ps
CPU time 6.41 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:48 PM PDT 24
Peak memory 208352 kb
Host smart-30d0b63f-46bc-498c-b9f5-cbd11a0f94e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534968911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1534968911
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2514586541
Short name T591
Test name
Test status
Simulation time 138285159 ps
CPU time 4.23 seconds
Started Jul 01 05:09:30 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 211064 kb
Host smart-80b76a0c-f635-40d5-9442-30fd7cca804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514586541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2514586541
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3764186482
Short name T88
Test name
Test status
Simulation time 10715266 ps
CPU time 0.75 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:09:40 PM PDT 24
Peak memory 206064 kb
Host smart-1c0d5cec-bf3b-45e0-8f82-3136a43e8c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764186482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3764186482
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.817179734
Short name T387
Test name
Test status
Simulation time 120143920 ps
CPU time 2.69 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:09:49 PM PDT 24
Peak memory 214400 kb
Host smart-e6225ebc-ef92-491a-b60e-518d2a28e162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817179734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.817179734
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2245745845
Short name T213
Test name
Test status
Simulation time 840262368 ps
CPU time 5.52 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 221184 kb
Host smart-021f6a8c-f5da-4ac9-8d8f-16848b4c491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245745845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2245745845
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.452889131
Short name T684
Test name
Test status
Simulation time 143427822 ps
CPU time 4.93 seconds
Started Jul 01 05:09:31 PM PDT 24
Finished Jul 01 05:09:43 PM PDT 24
Peak memory 208404 kb
Host smart-f071fcb7-8be9-407c-8c4f-5faffa3d00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452889131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.452889131
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3712796302
Short name T343
Test name
Test status
Simulation time 7189650337 ps
CPU time 34.05 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:10:21 PM PDT 24
Peak memory 214284 kb
Host smart-bd4329bd-a5f6-49ec-89d0-64c2a9bff909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712796302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3712796302
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1689485873
Short name T704
Test name
Test status
Simulation time 162337229 ps
CPU time 3.34 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 214284 kb
Host smart-ba3285de-5537-4080-bb6f-7f088e1a0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689485873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1689485873
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3203349342
Short name T476
Test name
Test status
Simulation time 1090199291 ps
CPU time 5.18 seconds
Started Jul 01 05:09:37 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 209304 kb
Host smart-8830e881-8f36-4539-a339-8e9f99b9e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203349342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3203349342
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2258194383
Short name T329
Test name
Test status
Simulation time 4531604070 ps
CPU time 29.77 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 209984 kb
Host smart-32d15f42-cf7b-4b6d-ad94-08db96cc057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258194383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2258194383
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.460126966
Short name T276
Test name
Test status
Simulation time 78827175 ps
CPU time 2.94 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:42 PM PDT 24
Peak memory 206900 kb
Host smart-30480ffd-72ed-4a03-ac30-826a982b28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460126966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.460126966
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.281733665
Short name T526
Test name
Test status
Simulation time 77443335 ps
CPU time 1.77 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 207060 kb
Host smart-d516d1f1-7ed1-493c-a601-38158eb0bd08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281733665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.281733665
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.642468778
Short name T465
Test name
Test status
Simulation time 1514701171 ps
CPU time 19.02 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 208268 kb
Host smart-e1f0d49e-d855-4de6-998f-e93a77c8f2eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642468778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.642468778
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1226311837
Short name T491
Test name
Test status
Simulation time 398145506 ps
CPU time 5.66 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 207976 kb
Host smart-86948b36-4740-4cac-8a2a-a03ddbc8e1b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226311837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1226311837
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3553759532
Short name T100
Test name
Test status
Simulation time 76669772 ps
CPU time 1.58 seconds
Started Jul 01 05:09:32 PM PDT 24
Finished Jul 01 05:09:41 PM PDT 24
Peak memory 215776 kb
Host smart-3a16b05d-84e1-4d43-b437-92e9ad79b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553759532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3553759532
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.155674276
Short name T524
Test name
Test status
Simulation time 739342085 ps
CPU time 13.51 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:10:02 PM PDT 24
Peak memory 208536 kb
Host smart-9ff72da1-c84e-4f38-9ce4-f83c528f681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155674276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.155674276
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2908009734
Short name T68
Test name
Test status
Simulation time 3285879032 ps
CPU time 32.39 seconds
Started Jul 01 05:09:33 PM PDT 24
Finished Jul 01 05:10:13 PM PDT 24
Peak memory 215716 kb
Host smart-22a23159-a412-41d1-a813-3ddb1f21c81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908009734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2908009734
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1584875793
Short name T646
Test name
Test status
Simulation time 242577538 ps
CPU time 6.66 seconds
Started Jul 01 05:09:36 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 222520 kb
Host smart-0eaae153-a12d-48d0-969f-291e37f45847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584875793 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1584875793
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4270577990
Short name T542
Test name
Test status
Simulation time 38610544 ps
CPU time 2.9 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:56 PM PDT 24
Peak memory 207932 kb
Host smart-325c2b88-34f2-4758-8b0e-fb7c416b701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270577990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4270577990
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3419819573
Short name T370
Test name
Test status
Simulation time 126540149 ps
CPU time 3.48 seconds
Started Jul 01 05:09:35 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 210180 kb
Host smart-48166911-25fd-4b2a-bc24-72fe896b4fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419819573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3419819573
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2432852066
Short name T554
Test name
Test status
Simulation time 21002099 ps
CPU time 0.83 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 206028 kb
Host smart-a3f0e51f-7aa6-4ae9-98d6-6ac0cd9a1a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432852066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2432852066
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1585635002
Short name T407
Test name
Test status
Simulation time 2770007529 ps
CPU time 38.58 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 215896 kb
Host smart-9b7e2a56-0896-4dd8-8d7b-1be565acc857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585635002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1585635002
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.198588976
Short name T33
Test name
Test status
Simulation time 716831024 ps
CPU time 3.89 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 218048 kb
Host smart-5bdb5ee6-37b4-47b7-83a0-5a89cc510db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198588976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.198588976
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3654122955
Short name T638
Test name
Test status
Simulation time 46573158 ps
CPU time 2.59 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 210400 kb
Host smart-2044faa4-b65f-41b8-9c78-03ada71dc3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654122955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3654122955
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3149488978
Short name T878
Test name
Test status
Simulation time 302930489 ps
CPU time 3.94 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 214336 kb
Host smart-581d20f7-3db9-472c-b50a-16f057caafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149488978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3149488978
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.483757790
Short name T291
Test name
Test status
Simulation time 214245632 ps
CPU time 3.67 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 214284 kb
Host smart-6ef569cb-0502-49e4-ba19-ce2f280c4bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483757790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.483757790
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2895813219
Short name T429
Test name
Test status
Simulation time 87842516 ps
CPU time 3.58 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 210088 kb
Host smart-99217a2e-db94-4f2c-b79c-edd22f2dc94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895813219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2895813219
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.580805268
Short name T565
Test name
Test status
Simulation time 2032801131 ps
CPU time 26.54 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:10:16 PM PDT 24
Peak memory 208992 kb
Host smart-6be91986-6b9c-4609-9bcf-af159633e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580805268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.580805268
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2680834320
Short name T556
Test name
Test status
Simulation time 266406423 ps
CPU time 3.21 seconds
Started Jul 01 05:09:35 PM PDT 24
Finished Jul 01 05:09:46 PM PDT 24
Peak memory 206752 kb
Host smart-6011b6a2-cce3-403e-9a53-4f58a9de0bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680834320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2680834320
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4188512754
Short name T449
Test name
Test status
Simulation time 22938013 ps
CPU time 1.94 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:03 PM PDT 24
Peak memory 207328 kb
Host smart-1f5e31e4-88f5-4134-9e94-4c4d03d83c1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188512754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4188512754
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3029281867
Short name T855
Test name
Test status
Simulation time 465972225 ps
CPU time 11.51 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:10:01 PM PDT 24
Peak memory 208852 kb
Host smart-9ff1c525-a6a9-4006-8c5f-f3d5b934d518
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029281867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3029281867
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3038869310
Short name T247
Test name
Test status
Simulation time 419330500 ps
CPU time 3.61 seconds
Started Jul 01 05:09:40 PM PDT 24
Finished Jul 01 05:09:51 PM PDT 24
Peak memory 208968 kb
Host smart-ef22cdaf-39c1-4cbf-8fb9-d8a0b7b966d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038869310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3038869310
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2546002059
Short name T911
Test name
Test status
Simulation time 76101692 ps
CPU time 2.21 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 209252 kb
Host smart-bd8a2fd3-91b5-4058-8776-e35e24b29836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546002059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2546002059
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.493810780
Short name T414
Test name
Test status
Simulation time 22118403 ps
CPU time 1.71 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 206756 kb
Host smart-96a8919d-36d0-44eb-bf01-526e49ac1dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493810780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.493810780
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1629086460
Short name T901
Test name
Test status
Simulation time 277891031 ps
CPU time 5.42 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:05 PM PDT 24
Peak memory 214340 kb
Host smart-85babb9d-bbeb-481f-a1b1-be435d11fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629086460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1629086460
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2772198934
Short name T58
Test name
Test status
Simulation time 375464101 ps
CPU time 3.35 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 210212 kb
Host smart-3560021b-7718-43f6-bd8e-c9965abed0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772198934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2772198934
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1781380345
Short name T89
Test name
Test status
Simulation time 12028589 ps
CPU time 0.86 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 206048 kb
Host smart-ca27e588-8a80-40c9-9ddb-05608367a5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781380345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1781380345
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4007756293
Short name T392
Test name
Test status
Simulation time 39075571 ps
CPU time 2.55 seconds
Started Jul 01 05:09:48 PM PDT 24
Finished Jul 01 05:10:01 PM PDT 24
Peak memory 207440 kb
Host smart-aa618c08-daf0-4350-9098-ebd4e9df87a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007756293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4007756293
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1061442987
Short name T830
Test name
Test status
Simulation time 196112057 ps
CPU time 2.42 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 214548 kb
Host smart-d4de50ce-122b-44fd-a625-bf206b3476d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061442987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1061442987
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.561181156
Short name T803
Test name
Test status
Simulation time 625186159 ps
CPU time 4.29 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:59 PM PDT 24
Peak memory 215192 kb
Host smart-7e894a92-2325-459c-abb5-197f37e3be5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561181156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.561181156
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1674149534
Short name T45
Test name
Test status
Simulation time 69471824 ps
CPU time 2.25 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 214980 kb
Host smart-f0165792-acb8-46a0-9c87-752071cdc971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674149534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1674149534
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.12581616
Short name T691
Test name
Test status
Simulation time 192716416 ps
CPU time 4.23 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 207728 kb
Host smart-bd52c2cd-d086-498f-8b90-baf3d5646921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12581616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.12581616
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2176023636
Short name T872
Test name
Test status
Simulation time 106523391 ps
CPU time 2.84 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 207012 kb
Host smart-c56fee8d-a638-4e27-a4cf-61b3f76cda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176023636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2176023636
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3914771575
Short name T176
Test name
Test status
Simulation time 928610702 ps
CPU time 7.29 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 208676 kb
Host smart-1f8b8487-7b65-4fcd-b204-df40e26cde48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914771575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3914771575
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4014153046
Short name T766
Test name
Test status
Simulation time 257485909 ps
CPU time 4.03 seconds
Started Jul 01 05:09:48 PM PDT 24
Finished Jul 01 05:10:03 PM PDT 24
Peak memory 208680 kb
Host smart-57785ff0-4d08-418e-8748-3099a8aa6229
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014153046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4014153046
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.556765705
Short name T806
Test name
Test status
Simulation time 926249014 ps
CPU time 3.44 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 208596 kb
Host smart-af147900-b05a-44da-afd9-6c82b18f87e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556765705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.556765705
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1137956136
Short name T601
Test name
Test status
Simulation time 285030144 ps
CPU time 3.15 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:53 PM PDT 24
Peak memory 210056 kb
Host smart-466ba85d-755d-4a9b-bbac-a9aba036dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137956136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1137956136
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1224643786
Short name T510
Test name
Test status
Simulation time 98126620 ps
CPU time 3.34 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 208576 kb
Host smart-6fb02260-1e40-4020-bf2e-0bd6996bca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224643786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1224643786
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1408913344
Short name T848
Test name
Test status
Simulation time 724534967 ps
CPU time 18.79 seconds
Started Jul 01 05:09:41 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 215864 kb
Host smart-0c087efd-0577-43ff-8c4a-66c1a7a85c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408913344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1408913344
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2022021535
Short name T545
Test name
Test status
Simulation time 200326757 ps
CPU time 4.85 seconds
Started Jul 01 05:09:42 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 214488 kb
Host smart-c9354083-26e3-412b-9a35-9dd66f2dd01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022021535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2022021535
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1737367039
Short name T431
Test name
Test status
Simulation time 49720940 ps
CPU time 1.76 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 210108 kb
Host smart-c869c037-a41b-4136-b659-0c81aac4dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737367039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1737367039
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1206457718
Short name T460
Test name
Test status
Simulation time 27737873 ps
CPU time 0.73 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:07 PM PDT 24
Peak memory 206048 kb
Host smart-c489970b-cc80-478a-8c3c-e99ec1cf6135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206457718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1206457718
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.590478380
Short name T331
Test name
Test status
Simulation time 262619895 ps
CPU time 14.2 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 214532 kb
Host smart-a22e9901-1446-4a6b-90ea-f008831406d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590478380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.590478380
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2345455833
Short name T413
Test name
Test status
Simulation time 155433579 ps
CPU time 1.34 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 208996 kb
Host smart-9b2379b5-f9f5-4ffc-b83c-80178a78cc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345455833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2345455833
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1906043694
Short name T843
Test name
Test status
Simulation time 61586200 ps
CPU time 1.98 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:03 PM PDT 24
Peak memory 209148 kb
Host smart-99c2412e-c00a-4acf-abe1-0314cfe79621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906043694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1906043694
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3906815625
Short name T203
Test name
Test status
Simulation time 88127918 ps
CPU time 4.14 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:59 PM PDT 24
Peak memory 209420 kb
Host smart-b2e12dc7-db1a-4e04-8b3b-73556f2caa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906815625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3906815625
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3688032628
Short name T76
Test name
Test status
Simulation time 105461207 ps
CPU time 2.19 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:03 PM PDT 24
Peak memory 205628 kb
Host smart-45074460-0c82-40d4-9aa6-0aafdf9e993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688032628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3688032628
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3513162499
Short name T92
Test name
Test status
Simulation time 192576714 ps
CPU time 3.24 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 209204 kb
Host smart-4c363733-aaf6-4d0e-9ab3-54165c8e7ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513162499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3513162499
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3700673595
Short name T705
Test name
Test status
Simulation time 1426016881 ps
CPU time 5.52 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 207372 kb
Host smart-122f122f-55b4-4cf3-9a0e-b5d771a729c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700673595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3700673595
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2544245025
Short name T629
Test name
Test status
Simulation time 108424858 ps
CPU time 3.7 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:06 PM PDT 24
Peak memory 206888 kb
Host smart-cc733a7e-5910-4846-add6-943d377cd312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544245025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2544245025
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1057560699
Short name T775
Test name
Test status
Simulation time 97525260 ps
CPU time 4.3 seconds
Started Jul 01 05:09:44 PM PDT 24
Finished Jul 01 05:09:56 PM PDT 24
Peak memory 206976 kb
Host smart-084a004e-d78f-4c9a-a30b-cae719ca27bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057560699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1057560699
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4036090061
Short name T726
Test name
Test status
Simulation time 832103326 ps
CPU time 8.74 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 208676 kb
Host smart-d8b02953-414b-477e-95fd-fe8d1f3bfdbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036090061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4036090061
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3376212397
Short name T304
Test name
Test status
Simulation time 1868781283 ps
CPU time 12.17 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 208092 kb
Host smart-b9e9ee19-5e65-4778-9679-9b29f00f416a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376212397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3376212397
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4107347571
Short name T456
Test name
Test status
Simulation time 193292305 ps
CPU time 2.8 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 207856 kb
Host smart-70f4bcd6-9910-4ab2-84a7-8f262fa45edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107347571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4107347571
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3808769143
Short name T708
Test name
Test status
Simulation time 45934337 ps
CPU time 2.47 seconds
Started Jul 01 05:09:39 PM PDT 24
Finished Jul 01 05:09:50 PM PDT 24
Peak memory 208384 kb
Host smart-b2fb0bcc-455b-45bd-acb0-01f270692577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808769143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3808769143
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3262111243
Short name T326
Test name
Test status
Simulation time 476297784 ps
CPU time 22.28 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 221396 kb
Host smart-30edd6c1-996e-42c7-a82a-976cbd991f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262111243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3262111243
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1640600266
Short name T284
Test name
Test status
Simulation time 421316043 ps
CPU time 5.17 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 214060 kb
Host smart-cc596af2-e502-4b04-82b8-1fc2459ece37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640600266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1640600266
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.834200904
Short name T586
Test name
Test status
Simulation time 42883471 ps
CPU time 0.86 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:54 PM PDT 24
Peak memory 206024 kb
Host smart-a4aa6404-7848-4cc3-955a-e55924f80182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834200904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.834200904
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1031116914
Short name T408
Test name
Test status
Simulation time 34776142 ps
CPU time 2.66 seconds
Started Jul 01 05:09:48 PM PDT 24
Finished Jul 01 05:10:02 PM PDT 24
Peak memory 214304 kb
Host smart-bbc97176-44fe-49c4-9c1b-70b18f6febca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031116914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1031116914
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.120276328
Short name T679
Test name
Test status
Simulation time 664004149 ps
CPU time 5.25 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:13 PM PDT 24
Peak memory 208848 kb
Host smart-495434fa-3945-4655-a8bc-96d3ccbc62d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120276328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.120276328
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2271109584
Short name T828
Test name
Test status
Simulation time 85463050 ps
CPU time 3.32 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:59 PM PDT 24
Peak memory 209436 kb
Host smart-809075f8-b4cc-4d91-8be2-f92bb08691b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271109584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2271109584
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1509446128
Short name T582
Test name
Test status
Simulation time 52997155 ps
CPU time 2.87 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 214220 kb
Host smart-2208c4e2-562f-4211-8460-14d16ec328f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509446128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1509446128
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.164740728
Short name T317
Test name
Test status
Simulation time 33182128 ps
CPU time 1.88 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 214144 kb
Host smart-b131504a-515f-41f6-8066-cd18904432d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164740728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.164740728
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4138750859
Short name T214
Test name
Test status
Simulation time 54795166 ps
CPU time 2.11 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:04 PM PDT 24
Peak memory 209436 kb
Host smart-5d8c741f-1c86-4adf-9a30-d8e795df64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138750859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4138750859
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2680354807
Short name T306
Test name
Test status
Simulation time 102125485 ps
CPU time 4.3 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 208572 kb
Host smart-d8e19cde-a2ad-431c-8367-2f4dc02bf15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680354807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2680354807
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2240508644
Short name T604
Test name
Test status
Simulation time 1645113445 ps
CPU time 6.85 seconds
Started Jul 01 05:09:47 PM PDT 24
Finished Jul 01 05:10:04 PM PDT 24
Peak memory 208368 kb
Host smart-43c23f37-c3fb-48bc-b8c2-da724969b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240508644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2240508644
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2095974820
Short name T686
Test name
Test status
Simulation time 209331791 ps
CPU time 2.77 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 206636 kb
Host smart-68dc6c62-99e5-4a9c-901c-2ae4f21e8a0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095974820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2095974820
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.769708296
Short name T595
Test name
Test status
Simulation time 188832230 ps
CPU time 2.77 seconds
Started Jul 01 05:09:47 PM PDT 24
Finished Jul 01 05:10:00 PM PDT 24
Peak memory 206952 kb
Host smart-3c1b1c6e-3eb9-4f84-9bf5-80fffb23c72f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769708296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.769708296
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1050103648
Short name T548
Test name
Test status
Simulation time 154169435 ps
CPU time 3.68 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:59 PM PDT 24
Peak memory 208792 kb
Host smart-6763444c-da4b-4d76-a71e-f306846c5880
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050103648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1050103648
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1144298796
Short name T603
Test name
Test status
Simulation time 196475593 ps
CPU time 2.54 seconds
Started Jul 01 05:09:45 PM PDT 24
Finished Jul 01 05:09:57 PM PDT 24
Peak memory 209236 kb
Host smart-f409cf1a-fca5-4731-997f-41bf6305c629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144298796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1144298796
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3364576383
Short name T649
Test name
Test status
Simulation time 324996918 ps
CPU time 5.06 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:06 PM PDT 24
Peak memory 208616 kb
Host smart-397dc6b3-62ce-4f01-a0b9-2e5adfe754f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364576383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3364576383
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1870375130
Short name T357
Test name
Test status
Simulation time 862059948 ps
CPU time 34.36 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 215108 kb
Host smart-f611069b-7332-414f-8661-2400ccf4fd79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870375130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1870375130
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3633901149
Short name T550
Test name
Test status
Simulation time 424698442 ps
CPU time 6.18 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 208836 kb
Host smart-e727aa55-e4f9-4999-8439-9654fe11056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633901149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3633901149
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2109585549
Short name T797
Test name
Test status
Simulation time 164220099 ps
CPU time 2.18 seconds
Started Jul 01 05:09:50 PM PDT 24
Finished Jul 01 05:10:04 PM PDT 24
Peak memory 210128 kb
Host smart-b7f3afe0-7736-4e8b-9664-2bb4271e54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109585549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2109585549
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3590427541
Short name T883
Test name
Test status
Simulation time 42221038 ps
CPU time 0.75 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:07 PM PDT 24
Peak memory 206044 kb
Host smart-b6a4a9ce-bf05-4e05-9ea0-cbf67c2f752e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590427541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3590427541
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.197596000
Short name T253
Test name
Test status
Simulation time 372128101 ps
CPU time 3.53 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 214492 kb
Host smart-972ec3f5-d148-4ca6-9f0d-ba5ec30be0df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=197596000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.197596000
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2535541553
Short name T881
Test name
Test status
Simulation time 229882590 ps
CPU time 6.26 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 208820 kb
Host smart-b9b42c83-fba1-47ed-869b-c893b13b8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535541553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2535541553
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1564610021
Short name T756
Test name
Test status
Simulation time 361579053 ps
CPU time 4.97 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 222428 kb
Host smart-b244ed38-d13e-4aac-ac1c-bbebb9b7f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564610021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1564610021
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3244089836
Short name T888
Test name
Test status
Simulation time 55562736 ps
CPU time 3.12 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 214284 kb
Host smart-aaf60937-1ecf-4518-b59b-64f55fe661bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244089836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3244089836
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.802711024
Short name T332
Test name
Test status
Simulation time 304953337 ps
CPU time 4.26 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 214144 kb
Host smart-05f72b22-02a3-4db1-a713-f371063b0cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802711024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.802711024
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3702664244
Short name T98
Test name
Test status
Simulation time 145247350 ps
CPU time 4.24 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:05 PM PDT 24
Peak memory 221888 kb
Host smart-bff731de-3bac-436a-98cc-0ab5ff4e6194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702664244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3702664244
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.710740406
Short name T899
Test name
Test status
Simulation time 59234909 ps
CPU time 3.05 seconds
Started Jul 01 05:09:46 PM PDT 24
Finished Jul 01 05:09:58 PM PDT 24
Peak memory 208712 kb
Host smart-7a6c6e5e-5221-491a-9548-69ca162db0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710740406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.710740406
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2076068606
Short name T436
Test name
Test status
Simulation time 68097734 ps
CPU time 2.44 seconds
Started Jul 01 05:09:49 PM PDT 24
Finished Jul 01 05:10:02 PM PDT 24
Peak memory 206912 kb
Host smart-4a533ae2-25c9-4eaf-a9e6-f7d6d6f7105b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076068606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2076068606
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3436786995
Short name T512
Test name
Test status
Simulation time 441458898 ps
CPU time 5.6 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:13 PM PDT 24
Peak memory 208628 kb
Host smart-6dbe5f3e-ad83-4076-8087-fd874ef142f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436786995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3436786995
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1146270579
Short name T365
Test name
Test status
Simulation time 751317863 ps
CPU time 7.02 seconds
Started Jul 01 05:09:47 PM PDT 24
Finished Jul 01 05:10:04 PM PDT 24
Peak memory 207904 kb
Host smart-b0d02e84-8a54-4d26-8222-6af10e33de9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146270579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1146270579
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1946401945
Short name T11
Test name
Test status
Simulation time 1099795782 ps
CPU time 24.8 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 209376 kb
Host smart-c71cc1fe-c92b-4945-a80b-96bacc527c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946401945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1946401945
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3687267970
Short name T834
Test name
Test status
Simulation time 126456754 ps
CPU time 3.34 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 206892 kb
Host smart-639c8079-c600-49eb-8898-3ef1b9be1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687267970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3687267970
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2943006804
Short name T153
Test name
Test status
Simulation time 473225348 ps
CPU time 23.51 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 214964 kb
Host smart-60eae4ef-545c-4137-b200-2e2141a0968c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943006804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2943006804
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3137696066
Short name T197
Test name
Test status
Simulation time 308850121 ps
CPU time 6.83 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:26 PM PDT 24
Peak memory 209044 kb
Host smart-e21916b8-c600-4748-9972-0b5488189557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137696066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3137696066
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1810182159
Short name T375
Test name
Test status
Simulation time 89350599 ps
CPU time 3.41 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:13 PM PDT 24
Peak memory 210344 kb
Host smart-b64e10ea-db95-4195-8535-a1eacb4f7ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810182159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1810182159
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2607223643
Short name T917
Test name
Test status
Simulation time 48880409 ps
CPU time 0.85 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:06 PM PDT 24
Peak memory 206076 kb
Host smart-c6c7a774-6321-4d90-8a38-301b41a74f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607223643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2607223643
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4192946212
Short name T310
Test name
Test status
Simulation time 92778043 ps
CPU time 3.35 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 214768 kb
Host smart-9503fdae-067b-45ef-ac54-d865ed577fc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192946212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4192946212
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3374582789
Short name T27
Test name
Test status
Simulation time 169475425 ps
CPU time 2.81 seconds
Started Jul 01 05:09:55 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 218476 kb
Host smart-20d287e0-3c80-471d-a49e-e7b39b1950f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374582789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3374582789
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1162026530
Short name T685
Test name
Test status
Simulation time 205041746 ps
CPU time 1.78 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 207940 kb
Host smart-1f7d80f3-2047-460b-8ff5-a74187b947bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162026530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1162026530
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2923894263
Short name T22
Test name
Test status
Simulation time 303059535 ps
CPU time 4.45 seconds
Started Jul 01 05:09:51 PM PDT 24
Finished Jul 01 05:10:08 PM PDT 24
Peak memory 208580 kb
Host smart-2f768811-aa79-4d71-81da-49f244c4bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923894263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2923894263
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1670218243
Short name T652
Test name
Test status
Simulation time 618685346 ps
CPU time 5.42 seconds
Started Jul 01 05:09:55 PM PDT 24
Finished Jul 01 05:10:15 PM PDT 24
Peak memory 215160 kb
Host smart-d3efb163-5ebc-4126-a00c-edc714658119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670218243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1670218243
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4035299100
Short name T342
Test name
Test status
Simulation time 48901362 ps
CPU time 3.31 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 222604 kb
Host smart-fd8b3970-98de-44c1-8c36-0556a67f0fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035299100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4035299100
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2223672713
Short name T243
Test name
Test status
Simulation time 102427992 ps
CPU time 3.9 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 218144 kb
Host smart-7c2002ca-b3d1-4c06-b9df-9fbc571f2505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223672713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2223672713
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1954856502
Short name T497
Test name
Test status
Simulation time 121859052 ps
CPU time 2.52 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 206756 kb
Host smart-0626f288-652b-454b-b99c-feab6e9515c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954856502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1954856502
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3027568159
Short name T813
Test name
Test status
Simulation time 378294499 ps
CPU time 3.52 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 206952 kb
Host smart-8ee2317d-955c-43b5-8db1-13ec8ce274be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027568159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3027568159
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3127269680
Short name T784
Test name
Test status
Simulation time 49417546 ps
CPU time 2.85 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 206808 kb
Host smart-20f3c5e6-f3cf-419e-ac61-320af751bb69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127269680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3127269680
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4154728539
Short name T867
Test name
Test status
Simulation time 80132950 ps
CPU time 1.75 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:11 PM PDT 24
Peak memory 206800 kb
Host smart-a9de8a77-dfcd-4193-98eb-6e2b6b86d424
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154728539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4154728539
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3128129505
Short name T678
Test name
Test status
Simulation time 168278428 ps
CPU time 2.29 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:10 PM PDT 24
Peak memory 215912 kb
Host smart-c8e17f47-4ad8-47a9-8564-402487f31c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128129505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3128129505
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1791719781
Short name T415
Test name
Test status
Simulation time 4328523478 ps
CPU time 14.98 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 208948 kb
Host smart-dbd4de37-8368-43d0-affe-b0714cd7b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791719781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1791719781
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2189464439
Short name T836
Test name
Test status
Simulation time 692446631 ps
CPU time 10.21 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 216260 kb
Host smart-592a624e-2210-4279-ba80-9f7f396aa127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189464439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2189464439
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.313631224
Short name T715
Test name
Test status
Simulation time 1183002910 ps
CPU time 13.3 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 222700 kb
Host smart-1f50c7b1-53ec-4281-8a93-9cbe8ba60a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313631224 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.313631224
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4170756781
Short name T779
Test name
Test status
Simulation time 927976874 ps
CPU time 5.48 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:15 PM PDT 24
Peak memory 214336 kb
Host smart-fc98157b-20fd-4c1c-b181-b2a7d92e7414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170756781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4170756781
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1002779543
Short name T148
Test name
Test status
Simulation time 129575082 ps
CPU time 2.03 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 209792 kb
Host smart-d063ee85-6dda-4364-9b98-8fe80d3e536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002779543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1002779543
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2356450901
Short name T93
Test name
Test status
Simulation time 19184941 ps
CPU time 0.72 seconds
Started Jul 01 05:10:05 PM PDT 24
Finished Jul 01 05:10:21 PM PDT 24
Peak memory 206056 kb
Host smart-2c651eb6-917f-4d38-abbd-05fd3c70f8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356450901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2356450901
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.975146444
Short name T298
Test name
Test status
Simulation time 63540309 ps
CPU time 2.92 seconds
Started Jul 01 05:09:51 PM PDT 24
Finished Jul 01 05:10:06 PM PDT 24
Peak memory 215200 kb
Host smart-f1ac1ec6-c49e-4b11-a323-073126bd6caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975146444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.975146444
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.396990885
Short name T589
Test name
Test status
Simulation time 194646421 ps
CPU time 3.05 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:07 PM PDT 24
Peak memory 208544 kb
Host smart-a35dc649-8703-47b7-9fa9-195668247ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396990885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.396990885
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.646196352
Short name T86
Test name
Test status
Simulation time 958135500 ps
CPU time 8.48 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 214416 kb
Host smart-8650afc1-cd27-46da-86e4-87fddff674d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646196352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.646196352
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3679643159
Short name T315
Test name
Test status
Simulation time 63331060 ps
CPU time 2.4 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 214292 kb
Host smart-2003a596-0c0e-4864-a47b-d32d2afe121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679643159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3679643159
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2246341537
Short name T665
Test name
Test status
Simulation time 45981700 ps
CPU time 2.9 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:11 PM PDT 24
Peak memory 210244 kb
Host smart-495210b1-9e7c-4de9-980f-9d44bc0082b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246341537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2246341537
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2177620040
Short name T440
Test name
Test status
Simulation time 313877087 ps
CPU time 3.82 seconds
Started Jul 01 05:09:52 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 209004 kb
Host smart-7b421f72-b0d0-496c-bd59-37bddafa92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177620040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2177620040
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3971042317
Short name T755
Test name
Test status
Simulation time 263865859 ps
CPU time 2.9 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:22 PM PDT 24
Peak memory 206768 kb
Host smart-a292aa13-0518-4fbe-8c13-e09c64cb9ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971042317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3971042317
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1519741038
Short name T794
Test name
Test status
Simulation time 33463097 ps
CPU time 2.41 seconds
Started Jul 01 05:09:55 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 208852 kb
Host smart-588468a3-b763-4082-b273-292d7b07d8e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519741038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1519741038
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3278347189
Short name T256
Test name
Test status
Simulation time 606079145 ps
CPU time 16.55 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:36 PM PDT 24
Peak memory 207908 kb
Host smart-1d334cc0-bccb-4ea7-ba06-7037e2c232ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278347189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3278347189
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1601532760
Short name T795
Test name
Test status
Simulation time 485810483 ps
CPU time 7.11 seconds
Started Jul 01 05:09:54 PM PDT 24
Finished Jul 01 05:10:17 PM PDT 24
Peak memory 208644 kb
Host smart-8716eb44-700e-4641-a61d-a4ba07bfca71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601532760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1601532760
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2344725758
Short name T448
Test name
Test status
Simulation time 145993292 ps
CPU time 1.81 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:19 PM PDT 24
Peak memory 214380 kb
Host smart-a7d624bb-9922-440e-bcf2-829f6e0d1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344725758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2344725758
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.27041434
Short name T717
Test name
Test status
Simulation time 90057678 ps
CPU time 2.35 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:09 PM PDT 24
Peak memory 206972 kb
Host smart-8cea1755-2a78-498c-b9a3-6125f2ea8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27041434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.27041434
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2553662378
Short name T212
Test name
Test status
Simulation time 4082863258 ps
CPU time 28.16 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 215144 kb
Host smart-c2cf29cc-c40d-4b4e-822e-df3353d3e2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553662378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2553662378
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2208846961
Short name T671
Test name
Test status
Simulation time 119856390 ps
CPU time 4.04 seconds
Started Jul 01 05:09:53 PM PDT 24
Finished Jul 01 05:10:12 PM PDT 24
Peak memory 207704 kb
Host smart-ea80d8c9-b1f3-466c-ac06-5cb002e7c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208846961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2208846961
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4121161733
Short name T760
Test name
Test status
Simulation time 89881655 ps
CPU time 3.33 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 210552 kb
Host smart-7393efb1-d7db-49d6-a37e-64d599305eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121161733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4121161733
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1228562261
Short name T845
Test name
Test status
Simulation time 40298511 ps
CPU time 0.71 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:16 PM PDT 24
Peak memory 206052 kb
Host smart-ccef9bd1-cae2-4813-a1b2-410d9f361aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228562261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1228562261
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.339216883
Short name T119
Test name
Test status
Simulation time 29877818 ps
CPU time 2.4 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 214316 kb
Host smart-277e13f9-3667-47cf-ad56-9520dfb5bbff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339216883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.339216883
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1707420205
Short name T824
Test name
Test status
Simulation time 42820282 ps
CPU time 2.71 seconds
Started Jul 01 05:10:05 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 214332 kb
Host smart-d8de2c8a-ec8c-421f-b060-204585192c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707420205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1707420205
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1737502991
Short name T262
Test name
Test status
Simulation time 27276588 ps
CPU time 1.8 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:19 PM PDT 24
Peak memory 214324 kb
Host smart-d92c77a2-76b6-446b-ba09-8026ff822a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737502991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1737502991
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4258529228
Short name T747
Test name
Test status
Simulation time 331450132 ps
CPU time 4.4 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 218788 kb
Host smart-311660cb-3ed0-4e0a-a80f-cd687b5e36b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258529228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4258529228
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2052690293
Short name T251
Test name
Test status
Simulation time 175287888 ps
CPU time 5.58 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:26 PM PDT 24
Peak memory 208604 kb
Host smart-435f900b-28e3-498a-80dc-a7336805b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052690293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2052690293
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4169001149
Short name T501
Test name
Test status
Simulation time 107031206 ps
CPU time 3.61 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 206820 kb
Host smart-60d9bfd2-bf46-4bfd-962e-c70135d692be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169001149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4169001149
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2901179130
Short name T807
Test name
Test status
Simulation time 31240250 ps
CPU time 2.11 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:20 PM PDT 24
Peak memory 206968 kb
Host smart-536bb3fc-55f2-43e9-986a-c5e3baa444c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901179130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2901179130
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2182667463
Short name T13
Test name
Test status
Simulation time 249789710 ps
CPU time 3.35 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:19 PM PDT 24
Peak memory 209128 kb
Host smart-52db7a11-0461-460e-a40a-822ed7103b11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182667463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2182667463
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.245262751
Short name T567
Test name
Test status
Simulation time 811887477 ps
CPU time 23.72 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 208604 kb
Host smart-ce4e5ad6-7c80-4218-9614-8a3972a9c9f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245262751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.245262751
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3475254974
Short name T473
Test name
Test status
Simulation time 1125692997 ps
CPU time 3.7 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 209528 kb
Host smart-52c84164-19c1-4677-b224-a8be1da8d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475254974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3475254974
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1902280245
Short name T723
Test name
Test status
Simulation time 2109162779 ps
CPU time 8.35 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 207784 kb
Host smart-d800011f-df31-4fef-b6c1-2541bb6181a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902280245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1902280245
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2180630753
Short name T282
Test name
Test status
Simulation time 5398349357 ps
CPU time 121.55 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:12:22 PM PDT 24
Peak memory 217112 kb
Host smart-bb0943c3-3553-453f-b39a-e79b46f7804c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180630753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2180630753
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1671210208
Short name T50
Test name
Test status
Simulation time 200611099 ps
CPU time 12.38 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 222524 kb
Host smart-c95da31e-84e8-41a5-80e8-ce599f2b278d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671210208 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1671210208
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1062301865
Short name T875
Test name
Test status
Simulation time 221894388 ps
CPU time 6.02 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:25 PM PDT 24
Peak memory 207460 kb
Host smart-32b329f0-4999-4347-9408-dcc40570d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062301865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1062301865
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2393261261
Short name T426
Test name
Test status
Simulation time 720779705 ps
CPU time 17.08 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 211040 kb
Host smart-cd1060b8-a1cd-47a6-8ea1-37c2e5d38777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393261261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2393261261
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2660553790
Short name T508
Test name
Test status
Simulation time 65397416 ps
CPU time 0.89 seconds
Started Jul 01 05:08:21 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 206064 kb
Host smart-ce69c8d0-6fc8-464c-bf19-74f7e91563d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660553790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2660553790
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2035408048
Short name T857
Test name
Test status
Simulation time 447281925 ps
CPU time 4.35 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:19 PM PDT 24
Peak memory 219748 kb
Host smart-f1f55552-e769-49b6-ade4-3719b867091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035408048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2035408048
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.73518906
Short name T65
Test name
Test status
Simulation time 44891009 ps
CPU time 1.94 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:18 PM PDT 24
Peak memory 208096 kb
Host smart-bfd68d33-70c2-4d2c-8023-dada2876b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73518906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.73518906
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1499318653
Short name T858
Test name
Test status
Simulation time 438343057 ps
CPU time 5.22 seconds
Started Jul 01 05:08:11 PM PDT 24
Finished Jul 01 05:08:17 PM PDT 24
Peak memory 222428 kb
Host smart-61ab81db-ef9e-4f78-bc95-3fb439caf1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499318653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1499318653
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3514331855
Short name T833
Test name
Test status
Simulation time 486002252 ps
CPU time 3.31 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:18 PM PDT 24
Peak memory 221076 kb
Host smart-677cd70e-b649-4da2-a5ab-c85022158838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514331855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3514331855
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.45111445
Short name T540
Test name
Test status
Simulation time 90246838 ps
CPU time 2.21 seconds
Started Jul 01 05:08:11 PM PDT 24
Finished Jul 01 05:08:14 PM PDT 24
Peak memory 214532 kb
Host smart-11e20db2-2962-4e78-8f4a-6600740cd9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45111445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.45111445
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3984538027
Short name T419
Test name
Test status
Simulation time 319656643 ps
CPU time 8.67 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 209524 kb
Host smart-d8c0698b-d031-4109-abf2-29a5ca762651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984538027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3984538027
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1783993580
Short name T771
Test name
Test status
Simulation time 167914070 ps
CPU time 4.91 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:21 PM PDT 24
Peak memory 206784 kb
Host smart-cdd17e1b-a19c-4436-945c-6093f7613137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783993580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1783993580
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2854683867
Short name T798
Test name
Test status
Simulation time 877396605 ps
CPU time 7.06 seconds
Started Jul 01 05:08:15 PM PDT 24
Finished Jul 01 05:08:24 PM PDT 24
Peak memory 208528 kb
Host smart-db81dcbd-8942-444b-9776-29ce6f9875a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854683867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2854683867
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.601149525
Short name T749
Test name
Test status
Simulation time 152842370 ps
CPU time 3.12 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:19 PM PDT 24
Peak memory 206848 kb
Host smart-a323e775-72b5-4548-85be-1837e4bce07b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601149525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.601149525
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.912101366
Short name T877
Test name
Test status
Simulation time 1669754232 ps
CPU time 12.5 seconds
Started Jul 01 05:08:15 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 207924 kb
Host smart-924a576c-89c0-4ff9-af8c-d991cd17057e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912101366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.912101366
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.604874689
Short name T515
Test name
Test status
Simulation time 202440605 ps
CPU time 4.34 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:19 PM PDT 24
Peak memory 209316 kb
Host smart-2615c683-d12f-4d1a-9289-309f4c91a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604874689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.604874689
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4211107351
Short name T617
Test name
Test status
Simulation time 1825509551 ps
CPU time 15.08 seconds
Started Jul 01 05:08:12 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 208060 kb
Host smart-aec0c75f-4716-4ea9-b4b2-a993eb1acc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211107351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4211107351
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2061635310
Short name T226
Test name
Test status
Simulation time 231550212 ps
CPU time 11.6 seconds
Started Jul 01 05:08:13 PM PDT 24
Finished Jul 01 05:08:26 PM PDT 24
Peak memory 215760 kb
Host smart-e42ae062-886a-46ad-9219-285d0fae3906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061635310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2061635310
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3796808964
Short name T169
Test name
Test status
Simulation time 349715794 ps
CPU time 9.1 seconds
Started Jul 01 05:08:12 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 222604 kb
Host smart-d41ea707-a8e4-44f2-a524-5e897bc7e8b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796808964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3796808964
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2315460288
Short name T325
Test name
Test status
Simulation time 118055691 ps
CPU time 3.3 seconds
Started Jul 01 05:08:14 PM PDT 24
Finished Jul 01 05:08:19 PM PDT 24
Peak memory 214328 kb
Host smart-33a799be-b054-4bac-941f-7c4770307e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315460288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2315460288
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1566997362
Short name T781
Test name
Test status
Simulation time 82328410 ps
CPU time 2.74 seconds
Started Jul 01 05:08:12 PM PDT 24
Finished Jul 01 05:08:15 PM PDT 24
Peak memory 210620 kb
Host smart-5bb2fa4d-4b6f-4ce8-bd5a-137596b11748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566997362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1566997362
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.109745624
Short name T479
Test name
Test status
Simulation time 45964939 ps
CPU time 0.78 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 205948 kb
Host smart-4a10d3e8-6bfc-4c18-8903-c12c51315e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109745624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.109745624
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.626378083
Short name T122
Test name
Test status
Simulation time 341832129 ps
CPU time 5.4 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:21 PM PDT 24
Peak memory 214256 kb
Host smart-efa525e4-2d34-4257-9646-3f5ce07c0054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626378083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.626378083
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.194374510
Short name T837
Test name
Test status
Simulation time 48160538 ps
CPU time 2.08 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:22 PM PDT 24
Peak memory 219876 kb
Host smart-654d4f79-b11f-4d54-a5b7-6095b0e876f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194374510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.194374510
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2841315236
Short name T865
Test name
Test status
Simulation time 64829275 ps
CPU time 2.74 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 208948 kb
Host smart-2d5b3b8c-b05b-4220-97a6-1f62bd2c39b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841315236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2841315236
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3503562532
Short name T517
Test name
Test status
Simulation time 555027645 ps
CPU time 18.01 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 214340 kb
Host smart-f4b0f05e-4e36-49d9-9f66-3c4c14377016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503562532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3503562532
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1071372511
Short name T288
Test name
Test status
Simulation time 46008464 ps
CPU time 1.68 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:17 PM PDT 24
Peak memory 214348 kb
Host smart-f8d88432-7e57-43c4-9bf8-75140baf3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071372511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1071372511
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.4102831320
Short name T55
Test name
Test status
Simulation time 478830522 ps
CPU time 6.56 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:22 PM PDT 24
Peak memory 214348 kb
Host smart-f9ee4cf4-b9c5-46bc-94bd-c48a303f515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102831320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.4102831320
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2438902463
Short name T680
Test name
Test status
Simulation time 166524919 ps
CPU time 3.83 seconds
Started Jul 01 05:10:02 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 209736 kb
Host smart-d7d1caa8-09fa-4810-bf70-7d435774817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438902463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2438902463
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1181582820
Short name T903
Test name
Test status
Simulation time 201055011 ps
CPU time 2.93 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 207608 kb
Host smart-b8429fcc-88df-452a-b91e-cc9b824f9c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181582820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1181582820
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1458282103
Short name T884
Test name
Test status
Simulation time 102445315 ps
CPU time 3.82 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:19 PM PDT 24
Peak memory 208472 kb
Host smart-af033e7f-50c2-4187-b9f6-0351d9191a8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458282103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1458282103
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2156928253
Short name T346
Test name
Test status
Simulation time 50005679 ps
CPU time 2.5 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 208044 kb
Host smart-8458b89a-c3a2-43fe-8871-c2a06f95f198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156928253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2156928253
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3474649509
Short name T547
Test name
Test status
Simulation time 73771702 ps
CPU time 3.29 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 208864 kb
Host smart-782120ed-2d9b-4ecc-a31f-6d46ed0fd20f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474649509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3474649509
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3339320198
Short name T631
Test name
Test status
Simulation time 345495031 ps
CPU time 2.53 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:19 PM PDT 24
Peak memory 207644 kb
Host smart-734b5543-51ba-4466-aa4a-323ba6d46f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339320198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3339320198
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1937020970
Short name T805
Test name
Test status
Simulation time 43677757 ps
CPU time 2.08 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 206880 kb
Host smart-eee58879-30ac-4ca7-9ceb-1d03bc722eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937020970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1937020970
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.12011540
Short name T809
Test name
Test status
Simulation time 343111592 ps
CPU time 4.84 seconds
Started Jul 01 05:10:01 PM PDT 24
Finished Jul 01 05:10:21 PM PDT 24
Peak memory 207636 kb
Host smart-e0965bbc-70d1-4816-a8b5-93b9f8388097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12011540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.12011540
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4213537627
Short name T576
Test name
Test status
Simulation time 1321260782 ps
CPU time 11.02 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:31 PM PDT 24
Peak memory 210532 kb
Host smart-ee206abd-6edf-4a47-8b2b-d74c6356c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213537627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4213537627
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1473424627
Short name T422
Test name
Test status
Simulation time 53027432 ps
CPU time 0.92 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:25 PM PDT 24
Peak memory 206184 kb
Host smart-e834f1da-6731-4228-b03f-16fab0e9807d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473424627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1473424627
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1601814602
Short name T386
Test name
Test status
Simulation time 194692682 ps
CPU time 3.8 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 214356 kb
Host smart-42cf679b-45da-4d4c-8f72-17db1ded7004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601814602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1601814602
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1778201645
Short name T630
Test name
Test status
Simulation time 174867878 ps
CPU time 5.53 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 217816 kb
Host smart-01183090-dc08-4c93-9592-6dcc7bf55b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778201645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1778201645
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.970326173
Short name T612
Test name
Test status
Simulation time 90025459 ps
CPU time 2.65 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 214332 kb
Host smart-07fb51dc-f700-46ec-9c1f-7f09a4119ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970326173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.970326173
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1070157604
Short name T620
Test name
Test status
Simulation time 46518207 ps
CPU time 1.71 seconds
Started Jul 01 05:10:12 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 214424 kb
Host smart-2b909672-1b4d-4013-9562-9b5c25dbe8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070157604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1070157604
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.36651556
Short name T367
Test name
Test status
Simulation time 66028345 ps
CPU time 2.61 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:28 PM PDT 24
Peak memory 222460 kb
Host smart-7957d3e1-c0f4-4622-8d53-5cca5bc178fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36651556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.36651556
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.56882977
Short name T222
Test name
Test status
Simulation time 92403576 ps
CPU time 3.18 seconds
Started Jul 01 05:10:11 PM PDT 24
Finished Jul 01 05:10:31 PM PDT 24
Peak memory 209292 kb
Host smart-2489c1e9-a6b2-48d3-b9fc-accf5d1ddf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56882977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.56882977
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.4033776041
Short name T368
Test name
Test status
Simulation time 441961666 ps
CPU time 5.91 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 208228 kb
Host smart-4104474a-4631-4748-bb4a-a2509056b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033776041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.4033776041
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.5738677
Short name T778
Test name
Test status
Simulation time 57607670 ps
CPU time 3.13 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:17 PM PDT 24
Peak memory 208016 kb
Host smart-8442a6cd-5c47-4942-980c-fa1b0d2900d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5738677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.5738677
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1902059676
Short name T358
Test name
Test status
Simulation time 35789707 ps
CPU time 2.51 seconds
Started Jul 01 05:09:59 PM PDT 24
Finished Jul 01 05:10:15 PM PDT 24
Peak memory 207760 kb
Host smart-eb58a7ee-b93f-49ac-b6c7-4301bd348c65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902059676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1902059676
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.547140219
Short name T264
Test name
Test status
Simulation time 347337141 ps
CPU time 3.52 seconds
Started Jul 01 05:10:03 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 208572 kb
Host smart-caa3e86c-9c72-4c0b-b7c0-4e1dbb9a116c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547140219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.547140219
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2639558699
Short name T505
Test name
Test status
Simulation time 390224615 ps
CPU time 7.16 seconds
Started Jul 01 05:10:04 PM PDT 24
Finished Jul 01 05:10:28 PM PDT 24
Peak memory 208908 kb
Host smart-6dfe46f4-977d-423f-a37b-707ba2a468a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639558699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2639558699
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4037298506
Short name T710
Test name
Test status
Simulation time 963792945 ps
CPU time 18.41 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:52 PM PDT 24
Peak memory 210144 kb
Host smart-eee7e321-f88f-4524-874c-b3e8676bfec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037298506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4037298506
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.269042133
Short name T869
Test name
Test status
Simulation time 38627611 ps
CPU time 2.17 seconds
Started Jul 01 05:10:00 PM PDT 24
Finished Jul 01 05:10:17 PM PDT 24
Peak memory 206984 kb
Host smart-97730132-da0d-4374-823d-df43f8aa4019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269042133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.269042133
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4220468302
Short name T667
Test name
Test status
Simulation time 530210157 ps
CPU time 15.02 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:57 PM PDT 24
Peak memory 222600 kb
Host smart-3c4a65aa-e00b-4bdf-9349-27683c831b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220468302 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4220468302
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3670164741
Short name T266
Test name
Test status
Simulation time 408309835 ps
CPU time 6.91 seconds
Started Jul 01 05:10:08 PM PDT 24
Finished Jul 01 05:10:31 PM PDT 24
Peak memory 210240 kb
Host smart-bd98b8f6-06af-422d-8919-4d6f1226d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670164741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3670164741
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1037835943
Short name T552
Test name
Test status
Simulation time 707702976 ps
CPU time 4.45 seconds
Started Jul 01 05:10:08 PM PDT 24
Finished Jul 01 05:10:29 PM PDT 24
Peak memory 210068 kb
Host smart-04fc0c43-6980-4d6e-a5c7-ccd3a4e785e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037835943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1037835943
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3589460929
Short name T523
Test name
Test status
Simulation time 87904310 ps
CPU time 0.87 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 206108 kb
Host smart-d650e646-feee-4850-a593-7331c155950f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589460929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3589460929
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1871449880
Short name T812
Test name
Test status
Simulation time 105152378 ps
CPU time 2.99 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:27 PM PDT 24
Peak memory 210144 kb
Host smart-f98e6a7b-c4ad-4f2a-be5c-11037db81b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871449880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1871449880
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2041902374
Short name T188
Test name
Test status
Simulation time 41816158 ps
CPU time 1.53 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:26 PM PDT 24
Peak memory 206836 kb
Host smart-ff9c45ef-0862-4629-8a81-b24d3e4e3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041902374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2041902374
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2294592245
Short name T889
Test name
Test status
Simulation time 95211022 ps
CPU time 3.8 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:10:34 PM PDT 24
Peak memory 214280 kb
Host smart-e3915e9c-a5fa-4c7d-b5c5-8a933c88b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294592245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2294592245
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4186567744
Short name T580
Test name
Test status
Simulation time 373128107 ps
CPU time 2.52 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:29 PM PDT 24
Peak memory 218836 kb
Host smart-03ea1853-17f6-41bb-9da7-e88a82698800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186567744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4186567744
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1807971374
Short name T637
Test name
Test status
Simulation time 192730898 ps
CPU time 4.88 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:29 PM PDT 24
Peak memory 207924 kb
Host smart-f143634f-5d0e-4a61-9d5a-8ff40091b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807971374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1807971374
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.656028614
Short name T477
Test name
Test status
Simulation time 411268579 ps
CPU time 9.93 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:46 PM PDT 24
Peak memory 208596 kb
Host smart-95006daa-6226-48f3-af96-55c54ecf94bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656028614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.656028614
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.307931776
Short name T424
Test name
Test status
Simulation time 57957884 ps
CPU time 2.78 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 208620 kb
Host smart-02e26dad-1ec5-4ded-80b5-88e9b64e458f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307931776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.307931776
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2507100964
Short name T475
Test name
Test status
Simulation time 153375237 ps
CPU time 2.53 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:28 PM PDT 24
Peak memory 206988 kb
Host smart-4e8a77d1-9729-43f1-8b2a-edfd4706fc00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507100964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2507100964
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3631921059
Short name T516
Test name
Test status
Simulation time 214063898 ps
CPU time 2.96 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 207492 kb
Host smart-06003d34-0214-4e88-83a0-4322e7092489
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631921059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3631921059
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.157521674
Short name T852
Test name
Test status
Simulation time 639628887 ps
CPU time 7.62 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 208152 kb
Host smart-6f98c380-6c49-42f6-b05f-d1b2f52ffcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157521674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.157521674
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1290501652
Short name T423
Test name
Test status
Simulation time 94359235 ps
CPU time 2.12 seconds
Started Jul 01 05:10:06 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 206992 kb
Host smart-840e00e3-508a-4b00-9661-39f5a45a5234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290501652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1290501652
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2144118925
Short name T553
Test name
Test status
Simulation time 772500969 ps
CPU time 27.52 seconds
Started Jul 01 05:10:08 PM PDT 24
Finished Jul 01 05:10:52 PM PDT 24
Peak memory 219720 kb
Host smart-f3a4f08f-ec5d-4279-abb4-8a452dada25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144118925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2144118925
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3107545960
Short name T860
Test name
Test status
Simulation time 615405393 ps
CPU time 24.2 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:50 PM PDT 24
Peak memory 222648 kb
Host smart-40598fa8-47a7-4c56-bf65-8735c963a08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107545960 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3107545960
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2233820528
Short name T802
Test name
Test status
Simulation time 103329022 ps
CPU time 4.61 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 209144 kb
Host smart-2c28c378-521f-4c4c-b2d8-77f953aef39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233820528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2233820528
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2548032254
Short name T625
Test name
Test status
Simulation time 1311641362 ps
CPU time 7.63 seconds
Started Jul 01 05:10:08 PM PDT 24
Finished Jul 01 05:10:32 PM PDT 24
Peak memory 210816 kb
Host smart-8e0acf09-cd33-443d-a76b-debe91dbdbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548032254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2548032254
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1301689650
Short name T94
Test name
Test status
Simulation time 11724886 ps
CPU time 0.83 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:25 PM PDT 24
Peak memory 206060 kb
Host smart-d71ab606-af38-4404-a641-096f748c4ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301689650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1301689650
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.739091835
Short name T406
Test name
Test status
Simulation time 107847950 ps
CPU time 6.36 seconds
Started Jul 01 05:10:12 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 214560 kb
Host smart-43ba8378-99b4-43c1-946e-7189f43ffcba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739091835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.739091835
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3366164021
Short name T528
Test name
Test status
Simulation time 35582078 ps
CPU time 2.56 seconds
Started Jul 01 05:10:11 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 210076 kb
Host smart-816b6f8c-d162-4dbd-86a5-541f41ae053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366164021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3366164021
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.512030903
Short name T29
Test name
Test status
Simulation time 1106010197 ps
CPU time 11.8 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 222312 kb
Host smart-2895717e-3e3b-4b5f-b402-5fb25a1ef696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512030903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.512030903
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4048639848
Short name T657
Test name
Test status
Simulation time 414274784 ps
CPU time 1.88 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 216284 kb
Host smart-7350af44-4cde-4500-9ec6-3d26e7725bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048639848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4048639848
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3444088963
Short name T287
Test name
Test status
Simulation time 310358195 ps
CPU time 7.67 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 208196 kb
Host smart-2e10c315-16de-4c3a-a475-89dedb2a46ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444088963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3444088963
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2583650599
Short name T821
Test name
Test status
Simulation time 568382787 ps
CPU time 20.32 seconds
Started Jul 01 05:10:07 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 209064 kb
Host smart-74be2f09-b729-4cd3-976c-ebdc6c0457b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583650599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2583650599
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2356328613
Short name T504
Test name
Test status
Simulation time 29418838 ps
CPU time 2.11 seconds
Started Jul 01 05:10:19 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 206944 kb
Host smart-02df3ca6-0cdc-4938-921c-f680f57a61bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356328613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2356328613
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.500796958
Short name T655
Test name
Test status
Simulation time 141197482 ps
CPU time 2.6 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 208868 kb
Host smart-9aacf04f-7931-4a5c-bf80-e4eb1d76e020
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500796958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.500796958
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.54447204
Short name T605
Test name
Test status
Simulation time 63225001 ps
CPU time 3 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:27 PM PDT 24
Peak memory 206820 kb
Host smart-7deee124-3abb-492a-ae31-f417e32984ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54447204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.54447204
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.561632464
Short name T866
Test name
Test status
Simulation time 213388679 ps
CPU time 5.04 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:38 PM PDT 24
Peak memory 209776 kb
Host smart-04b42e09-fd5f-449d-b2bb-9ebdbe812344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561632464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.561632464
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3396802694
Short name T915
Test name
Test status
Simulation time 60134247 ps
CPU time 2.46 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 206696 kb
Host smart-564a7709-c13f-46f0-9881-d4619ea70cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396802694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3396802694
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.687374392
Short name T527
Test name
Test status
Simulation time 283452489 ps
CPU time 3.62 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:38 PM PDT 24
Peak memory 207892 kb
Host smart-747c6929-be3e-42b8-8108-2a3414f56b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687374392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.687374392
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3623585043
Short name T149
Test name
Test status
Simulation time 90283164 ps
CPU time 3.04 seconds
Started Jul 01 05:10:11 PM PDT 24
Finished Jul 01 05:10:30 PM PDT 24
Peak memory 210252 kb
Host smart-38535ad7-e00c-47c6-8597-4a897c7437d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623585043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3623585043
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3749556360
Short name T462
Test name
Test status
Simulation time 26328310 ps
CPU time 0.9 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 206168 kb
Host smart-30998ef1-e021-48fd-8e5b-fbce0923ca67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749556360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3749556360
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1677678313
Short name T383
Test name
Test status
Simulation time 34514669 ps
CPU time 2.6 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 215100 kb
Host smart-585bf037-820a-456d-8f3b-2a9e68394533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677678313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1677678313
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.705455410
Short name T24
Test name
Test status
Simulation time 236150532 ps
CPU time 4.66 seconds
Started Jul 01 05:10:14 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 222892 kb
Host smart-0b0ca050-dea0-49b3-a674-9787886ad2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705455410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.705455410
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3033481706
Short name T578
Test name
Test status
Simulation time 369589387 ps
CPU time 2.85 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 208940 kb
Host smart-4e646785-94d8-411b-8a02-25fc9efe44bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033481706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3033481706
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4079244762
Short name T815
Test name
Test status
Simulation time 169133787 ps
CPU time 2.06 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 214472 kb
Host smart-96db096f-1bfd-45aa-b380-1334a2929957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079244762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4079244762
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.506580645
Short name T602
Test name
Test status
Simulation time 177700350 ps
CPU time 3.15 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:36 PM PDT 24
Peak memory 214284 kb
Host smart-23a3df2a-86ab-4aae-ab2f-4d372fa7b238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506580645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.506580645
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3850038788
Short name T5
Test name
Test status
Simulation time 124857959 ps
CPU time 2.6 seconds
Started Jul 01 05:10:23 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 209376 kb
Host smart-1ea71ab2-88ee-4ce3-85fb-39388bf06532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850038788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3850038788
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2564462051
Short name T359
Test name
Test status
Simulation time 486811074 ps
CPU time 5.57 seconds
Started Jul 01 05:10:06 PM PDT 24
Finished Jul 01 05:10:27 PM PDT 24
Peak memory 222412 kb
Host smart-1ffa0b34-c5fd-40ce-96ff-5693870bebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564462051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2564462051
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1715585221
Short name T194
Test name
Test status
Simulation time 92268784 ps
CPU time 3.1 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 206792 kb
Host smart-f542a223-547e-4e3e-8f71-6b6da23363d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715585221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1715585221
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2628838092
Short name T267
Test name
Test status
Simulation time 217754312 ps
CPU time 3.05 seconds
Started Jul 01 05:10:09 PM PDT 24
Finished Jul 01 05:10:27 PM PDT 24
Peak memory 207664 kb
Host smart-6a0e8840-66f1-4474-b3a1-80cbf78c2f1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628838092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2628838092
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3530629668
Short name T458
Test name
Test status
Simulation time 607927964 ps
CPU time 7.12 seconds
Started Jul 01 05:10:10 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 208252 kb
Host smart-9ad263d1-1a8a-44ac-82ed-593943056583
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530629668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3530629668
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3164442471
Short name T714
Test name
Test status
Simulation time 56998733 ps
CPU time 3.04 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:36 PM PDT 24
Peak memory 208740 kb
Host smart-58033122-2b06-43a0-9c86-5b52e7ad7674
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164442471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3164442471
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3614213440
Short name T302
Test name
Test status
Simulation time 542739868 ps
CPU time 4.14 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 214304 kb
Host smart-9b8de83f-844a-4103-ad16-890bfc1d70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614213440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3614213440
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3738798682
Short name T420
Test name
Test status
Simulation time 489017630 ps
CPU time 3.58 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:10:33 PM PDT 24
Peak memory 208288 kb
Host smart-1dff81f6-e95f-4eda-b70e-c9ce11ef4700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738798682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3738798682
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2567270836
Short name T263
Test name
Test status
Simulation time 1376088422 ps
CPU time 9.24 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 216424 kb
Host smart-621c1709-5c1b-4af7-a44a-dcd6d1fa943c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567270836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2567270836
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3606637306
Short name T254
Test name
Test status
Simulation time 1583117997 ps
CPU time 20.91 seconds
Started Jul 01 05:10:12 PM PDT 24
Finished Jul 01 05:10:49 PM PDT 24
Peak memory 220528 kb
Host smart-59f8fc53-302d-4b4f-95fc-71c8c6d2c408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606637306 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3606637306
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.952679258
Short name T439
Test name
Test status
Simulation time 546187404 ps
CPU time 5.17 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 214336 kb
Host smart-4149d7e6-ed8c-43c5-ab18-a5691f7b70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952679258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.952679258
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.641703294
Short name T179
Test name
Test status
Simulation time 183454943 ps
CPU time 2.87 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 210308 kb
Host smart-a83dc19f-d161-4ee2-8313-977d51075dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641703294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.641703294
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1486087232
Short name T842
Test name
Test status
Simulation time 21590871 ps
CPU time 1 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 206176 kb
Host smart-1b465b1e-0e90-4006-b75f-bdc5a32f16fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486087232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1486087232
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.435011559
Short name T404
Test name
Test status
Simulation time 638959034 ps
CPU time 8.58 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 215084 kb
Host smart-fd787d59-3fa7-4449-be48-a376b043b572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435011559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.435011559
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.165544418
Short name T886
Test name
Test status
Simulation time 100234183 ps
CPU time 2.55 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 207280 kb
Host smart-582662c4-aab3-4482-9f7f-d5395eaef52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165544418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.165544418
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1793846069
Short name T289
Test name
Test status
Simulation time 222170947 ps
CPU time 3.59 seconds
Started Jul 01 05:10:17 PM PDT 24
Finished Jul 01 05:10:38 PM PDT 24
Peak memory 214280 kb
Host smart-5f0cb98c-5fad-4fe9-a368-1bf9f11ccb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793846069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1793846069
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2309144161
Short name T494
Test name
Test status
Simulation time 286650113 ps
CPU time 2.67 seconds
Started Jul 01 05:10:18 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 209548 kb
Host smart-d29930c2-0007-45f8-ba39-68497fbdbb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309144161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2309144161
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2151222443
Short name T663
Test name
Test status
Simulation time 614835434 ps
CPU time 10.48 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:47 PM PDT 24
Peak memory 209128 kb
Host smart-3f2a36dd-ec23-4eff-902e-d12ee9f3ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151222443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2151222443
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1164388507
Short name T468
Test name
Test status
Simulation time 129243462 ps
CPU time 3.95 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 208488 kb
Host smart-48c610e6-c682-4cb4-a3b9-59d4858a6a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164388507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1164388507
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1840696668
Short name T447
Test name
Test status
Simulation time 2945607750 ps
CPU time 34.76 seconds
Started Jul 01 05:10:16 PM PDT 24
Finished Jul 01 05:11:08 PM PDT 24
Peak memory 208256 kb
Host smart-0a9077fe-6e69-4409-ab14-8b65947d186b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840696668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1840696668
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.612754714
Short name T303
Test name
Test status
Simulation time 58810986 ps
CPU time 2.99 seconds
Started Jul 01 05:10:14 PM PDT 24
Finished Jul 01 05:10:34 PM PDT 24
Peak memory 207956 kb
Host smart-19a4586e-af61-4768-a564-c2754b23f3c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612754714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.612754714
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.574542961
Short name T493
Test name
Test status
Simulation time 72513536 ps
CPU time 2.9 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:35 PM PDT 24
Peak memory 206824 kb
Host smart-c172f232-e439-43a3-8fb0-8c40a2a9ae83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574542961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.574542961
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2319854880
Short name T864
Test name
Test status
Simulation time 64201700 ps
CPU time 2.27 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:42 PM PDT 24
Peak memory 218012 kb
Host smart-a05ab932-3f9b-45fc-a036-bde66e36623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319854880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2319854880
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3066836641
Short name T115
Test name
Test status
Simulation time 373856049 ps
CPU time 4.53 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 207928 kb
Host smart-fd50ffe1-3380-4806-8b45-4d06aed3acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066836641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3066836641
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4045016739
Short name T299
Test name
Test status
Simulation time 877159478 ps
CPU time 31.7 seconds
Started Jul 01 05:10:19 PM PDT 24
Finished Jul 01 05:11:07 PM PDT 24
Peak memory 222524 kb
Host smart-bd87b301-a53e-478c-8f23-a10ead77af82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045016739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4045016739
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1644288649
Short name T607
Test name
Test status
Simulation time 226847870 ps
CPU time 9.45 seconds
Started Jul 01 05:10:13 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 219692 kb
Host smart-1957a5d7-e4cc-4171-b6f6-2298d5dd2a4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644288649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1644288649
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.8953074
Short name T334
Test name
Test status
Simulation time 2555637729 ps
CPU time 6.43 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 207892 kb
Host smart-f0b11903-7972-43ea-9b4b-6907294b935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8953074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.8953074
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3698459785
Short name T150
Test name
Test status
Simulation time 48690502 ps
CPU time 1.9 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 209908 kb
Host smart-de79d0b7-55a0-4291-b8fb-becd66f9585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698459785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3698459785
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3873251792
Short name T733
Test name
Test status
Simulation time 30873349 ps
CPU time 0.95 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:38 PM PDT 24
Peak memory 206196 kb
Host smart-90c941bc-4f4e-4c1c-bc17-3414505313bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873251792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3873251792
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1394570821
Short name T410
Test name
Test status
Simulation time 170654043 ps
CPU time 3.48 seconds
Started Jul 01 05:10:14 PM PDT 24
Finished Jul 01 05:10:34 PM PDT 24
Peak memory 215420 kb
Host smart-a9eabc61-a012-448f-989c-0cc99cf9c55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394570821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1394570821
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3753849365
Short name T28
Test name
Test status
Simulation time 89823350 ps
CPU time 4.32 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 214408 kb
Host smart-01bfd8d2-fe0b-4d57-9aac-dc2c02be409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753849365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3753849365
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2424697526
Short name T734
Test name
Test status
Simulation time 59918119 ps
CPU time 2.15 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 210000 kb
Host smart-a0650d86-b9ed-4661-8dfd-cc5e9da2a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424697526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2424697526
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3794022422
Short name T786
Test name
Test status
Simulation time 33008397 ps
CPU time 2.54 seconds
Started Jul 01 05:10:28 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 214268 kb
Host smart-9f009fa7-ab19-459a-be6e-9f080e6378f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794022422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3794022422
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3080228818
Short name T225
Test name
Test status
Simulation time 100567928 ps
CPU time 3.35 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 219988 kb
Host smart-fbdac129-5edc-4bee-9d5e-8e212b1ff5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080228818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3080228818
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2853230875
Short name T246
Test name
Test status
Simulation time 184681643 ps
CPU time 5.32 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 214320 kb
Host smart-73355f49-f6e6-491b-a46a-f1fa47941704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853230875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2853230875
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.7998240
Short name T352
Test name
Test status
Simulation time 1567631205 ps
CPU time 36.39 seconds
Started Jul 01 05:10:14 PM PDT 24
Finished Jul 01 05:11:07 PM PDT 24
Peak memory 208028 kb
Host smart-bcf165ca-e6a0-4b8c-80f8-e6871ac10829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7998240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.7998240
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2854123733
Short name T333
Test name
Test status
Simulation time 640541265 ps
CPU time 14.85 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:55 PM PDT 24
Peak memory 207876 kb
Host smart-abbb2b59-d386-40a3-8e42-ca8e42bd3d48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854123733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2854123733
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1693851011
Short name T594
Test name
Test status
Simulation time 528710050 ps
CPU time 12.01 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:48 PM PDT 24
Peak memory 208680 kb
Host smart-ab065012-b9c3-4b83-817c-99f9b7b91113
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693851011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1693851011
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3051799420
Short name T442
Test name
Test status
Simulation time 1757330772 ps
CPU time 37.39 seconds
Started Jul 01 05:10:15 PM PDT 24
Finished Jul 01 05:11:10 PM PDT 24
Peak memory 208792 kb
Host smart-3454a38f-5a84-448d-8bb6-92d683be2a52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051799420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3051799420
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2085443487
Short name T445
Test name
Test status
Simulation time 15724900 ps
CPU time 1.46 seconds
Started Jul 01 05:10:19 PM PDT 24
Finished Jul 01 05:10:36 PM PDT 24
Peak memory 208392 kb
Host smart-09fa4e82-3621-4217-bd22-9a46d1d96896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085443487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2085443487
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2048371902
Short name T464
Test name
Test status
Simulation time 4455974661 ps
CPU time 6.06 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 208436 kb
Host smart-8d75eb50-ed7d-497e-8127-db50b91f1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048371902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2048371902
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3285038105
Short name T265
Test name
Test status
Simulation time 467537088 ps
CPU time 5.03 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 218288 kb
Host smart-09587aba-9144-441b-9687-23316dab220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285038105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3285038105
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2240609246
Short name T52
Test name
Test status
Simulation time 138656002 ps
CPU time 1.78 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 210312 kb
Host smart-04de41e1-42ae-4c03-866c-5777c2e16597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240609246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2240609246
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2665375422
Short name T753
Test name
Test status
Simulation time 25732297 ps
CPU time 0.7 seconds
Started Jul 01 05:10:26 PM PDT 24
Finished Jul 01 05:10:42 PM PDT 24
Peak memory 206076 kb
Host smart-4155f1fc-0259-4b36-8093-9417f9b00258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665375422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2665375422
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.757318724
Short name T600
Test name
Test status
Simulation time 109590241 ps
CPU time 4.49 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 209500 kb
Host smart-c083cf60-aa57-47bf-b8d7-0708df664e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757318724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.757318724
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1515909564
Short name T817
Test name
Test status
Simulation time 259148492 ps
CPU time 3.96 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:46 PM PDT 24
Peak memory 209808 kb
Host smart-81d3ac76-f19e-4817-b567-d40c29def20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515909564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1515909564
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1201979324
Short name T75
Test name
Test status
Simulation time 51495972 ps
CPU time 2.17 seconds
Started Jul 01 05:10:26 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 214520 kb
Host smart-92885af2-e87e-4400-b6ee-1983332670b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201979324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1201979324
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3001534653
Short name T743
Test name
Test status
Simulation time 271239188 ps
CPU time 3.4 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:42 PM PDT 24
Peak memory 214312 kb
Host smart-7ea189a7-63f5-4c0a-8dc3-51ca4ea0fea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001534653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3001534653
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3048532830
Short name T481
Test name
Test status
Simulation time 232913563 ps
CPU time 2.49 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:37 PM PDT 24
Peak memory 215076 kb
Host smart-1afa00de-d531-476f-9550-e83ffcdb1243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048532830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3048532830
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3658966355
Short name T563
Test name
Test status
Simulation time 1261882928 ps
CPU time 8.48 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 208780 kb
Host smart-2fa1bbb9-72a1-4084-a39a-6f6c0f0463bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658966355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3658966355
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3307897413
Short name T640
Test name
Test status
Simulation time 35405644 ps
CPU time 2.31 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:38 PM PDT 24
Peak memory 206928 kb
Host smart-6f472a6c-1c99-48be-821b-6debdccafcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307897413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3307897413
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.227118469
Short name T248
Test name
Test status
Simulation time 259720061 ps
CPU time 3.35 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 209196 kb
Host smart-602ad64e-897f-4dca-9bf7-1b823f3fd6e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227118469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.227118469
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1763819791
Short name T736
Test name
Test status
Simulation time 34386360 ps
CPU time 1.71 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 207192 kb
Host smart-c56a8b3d-b09c-4e00-8674-3811bfcb9176
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763819791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1763819791
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1555144533
Short name T800
Test name
Test status
Simulation time 342921774 ps
CPU time 5.94 seconds
Started Jul 01 05:10:23 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 209044 kb
Host smart-e3bc94ca-b614-4de1-8dfc-896757c9e4db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555144533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1555144533
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3482317601
Short name T792
Test name
Test status
Simulation time 71532632 ps
CPU time 3.53 seconds
Started Jul 01 05:10:20 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 209352 kb
Host smart-c42f8dd1-b0dd-4bb2-90e0-6e98243cd224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482317601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3482317601
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2599928749
Short name T687
Test name
Test status
Simulation time 8905480995 ps
CPU time 20.61 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:58 PM PDT 24
Peak memory 207968 kb
Host smart-083b5e62-fb62-419a-bcd8-4aeabd456159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599928749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2599928749
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2229129864
Short name T227
Test name
Test status
Simulation time 1961145093 ps
CPU time 23.74 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:11:03 PM PDT 24
Peak memory 222648 kb
Host smart-5bd24d53-8512-4ebe-a4df-a410c3c0c051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229129864 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2229129864
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4184219431
Short name T648
Test name
Test status
Simulation time 42369231 ps
CPU time 2.46 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 209780 kb
Host smart-e1821bb2-444b-4a44-9b74-01d15ce87de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184219431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4184219431
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2001043458
Short name T57
Test name
Test status
Simulation time 1852659656 ps
CPU time 14.96 seconds
Started Jul 01 05:10:19 PM PDT 24
Finished Jul 01 05:10:50 PM PDT 24
Peak memory 211124 kb
Host smart-6fc035a5-f703-4480-8aba-0a950f889831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001043458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2001043458
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1286953480
Short name T773
Test name
Test status
Simulation time 24712785 ps
CPU time 0.73 seconds
Started Jul 01 05:10:23 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 206076 kb
Host smart-23abc8c4-3034-4c6c-9669-120ec6d897c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286953480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1286953480
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1165264213
Short name T381
Test name
Test status
Simulation time 143672945 ps
CPU time 3.3 seconds
Started Jul 01 05:10:26 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 215188 kb
Host smart-fad9b6c2-45d6-4892-92be-7762069bfa2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165264213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1165264213
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3200656446
Short name T682
Test name
Test status
Simulation time 153059241 ps
CPU time 4.42 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 209632 kb
Host smart-94d4a8b8-1456-47ad-8e19-37447c543e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200656446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3200656446
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2737815079
Short name T670
Test name
Test status
Simulation time 234438364 ps
CPU time 2.27 seconds
Started Jul 01 05:10:22 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 209376 kb
Host smart-71ffe072-7f02-489c-83dd-55d4f7755d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737815079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2737815079
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.945365282
Short name T74
Test name
Test status
Simulation time 2993220339 ps
CPU time 17.76 seconds
Started Jul 01 05:10:23 PM PDT 24
Finished Jul 01 05:10:56 PM PDT 24
Peak memory 209940 kb
Host smart-6331a7f5-7485-4beb-a7a2-0ea854236bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945365282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.945365282
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4073059575
Short name T336
Test name
Test status
Simulation time 88697470 ps
CPU time 3.68 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 214304 kb
Host smart-b362837d-e5c8-409b-80fc-5c9f053c7db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073059575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4073059575
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2432549898
Short name T732
Test name
Test status
Simulation time 97901345 ps
CPU time 2.74 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 219664 kb
Host smart-67a90d83-ccfb-45bb-8245-a319110cd067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432549898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2432549898
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1883010853
Short name T853
Test name
Test status
Simulation time 517221579 ps
CPU time 6.11 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:42 PM PDT 24
Peak memory 208592 kb
Host smart-08746dd4-8f71-4814-a3ff-744dec2be20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883010853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1883010853
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.861560881
Short name T712
Test name
Test status
Simulation time 142483605 ps
CPU time 4.42 seconds
Started Jul 01 05:10:19 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 208256 kb
Host smart-6a754867-d0b5-40f8-bf90-710dea563291
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861560881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.861560881
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4110318303
Short name T844
Test name
Test status
Simulation time 853443406 ps
CPU time 6.13 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 208516 kb
Host smart-d733b49d-e516-4057-baf2-8d2ffa964003
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110318303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4110318303
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3863534437
Short name T417
Test name
Test status
Simulation time 58928476 ps
CPU time 2.91 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:39 PM PDT 24
Peak memory 207064 kb
Host smart-095e812c-7c90-46cb-9a6d-0d636c02f728
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863534437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3863534437
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1283244088
Short name T559
Test name
Test status
Simulation time 316404959 ps
CPU time 4.37 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:46 PM PDT 24
Peak memory 214316 kb
Host smart-e7f6612e-bd51-4991-8bcc-b08e5bcff59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283244088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1283244088
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2085689901
Short name T189
Test name
Test status
Simulation time 109533608 ps
CPU time 3.38 seconds
Started Jul 01 05:10:25 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 206904 kb
Host smart-c7d3eda9-1e82-4281-bd84-f2f3130a70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085689901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2085689901
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2862962605
Short name T789
Test name
Test status
Simulation time 1033404401 ps
CPU time 26.95 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:11:09 PM PDT 24
Peak memory 219820 kb
Host smart-a7acf776-ab84-4dae-814a-aa1a21b22c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862962605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2862962605
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3276774198
Short name T752
Test name
Test status
Simulation time 578597159 ps
CPU time 7.13 seconds
Started Jul 01 05:10:23 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 208108 kb
Host smart-9fb6e2dc-b926-4cf9-b3a7-b5ae1abf5777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276774198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3276774198
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.425276358
Short name T139
Test name
Test status
Simulation time 43716787 ps
CPU time 2.08 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:41 PM PDT 24
Peak memory 210340 kb
Host smart-84d2b964-5897-4eb5-93b4-8db7bd976f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425276358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.425276358
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.467453653
Short name T609
Test name
Test status
Simulation time 17842237 ps
CPU time 0.97 seconds
Started Jul 01 05:10:33 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 206184 kb
Host smart-8ce30e08-bd64-466a-97a5-03bbe5f40dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467453653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.467453653
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.817970908
Short name T658
Test name
Test status
Simulation time 107406819 ps
CPU time 1.65 seconds
Started Jul 01 05:10:28 PM PDT 24
Finished Jul 01 05:10:44 PM PDT 24
Peak memory 209608 kb
Host smart-677f5008-bef9-4657-bf50-68e20a7fb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817970908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.817970908
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1084051014
Short name T259
Test name
Test status
Simulation time 227403213 ps
CPU time 1.88 seconds
Started Jul 01 05:10:32 PM PDT 24
Finished Jul 01 05:10:46 PM PDT 24
Peak memory 206968 kb
Host smart-4b7dbbf6-00f2-4e65-a6f8-96f8b8a2ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084051014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1084051014
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2071189999
Short name T360
Test name
Test status
Simulation time 112563200 ps
CPU time 2.39 seconds
Started Jul 01 05:10:39 PM PDT 24
Finished Jul 01 05:10:50 PM PDT 24
Peak memory 208632 kb
Host smart-9f06846f-73ef-47c9-be19-80a9f3454c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071189999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2071189999
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.741840016
Short name T887
Test name
Test status
Simulation time 260320628 ps
CPU time 2.48 seconds
Started Jul 01 05:10:30 PM PDT 24
Finished Jul 01 05:10:46 PM PDT 24
Peak memory 214276 kb
Host smart-a040508a-c12b-488e-b924-d0997a86d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741840016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.741840016
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3001216729
Short name T650
Test name
Test status
Simulation time 83507041 ps
CPU time 1.67 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:43 PM PDT 24
Peak memory 214764 kb
Host smart-c5a390d6-906b-4e53-8f0e-36e946b15df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001216729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3001216729
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3228012338
Short name T114
Test name
Test status
Simulation time 461756658 ps
CPU time 3.63 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:45 PM PDT 24
Peak memory 207632 kb
Host smart-bfe3cde9-de9a-4356-85f4-fe2723f3f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228012338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3228012338
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3971913517
Short name T308
Test name
Test status
Simulation time 2581973837 ps
CPU time 40.9 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:11:17 PM PDT 24
Peak memory 208972 kb
Host smart-d6a2871f-d132-4a52-9e19-ba09c24a5251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971913517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3971913517
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1057270941
Short name T764
Test name
Test status
Simulation time 49651496 ps
CPU time 1.83 seconds
Started Jul 01 05:10:36 PM PDT 24
Finished Jul 01 05:10:49 PM PDT 24
Peak memory 207072 kb
Host smart-b73d328c-4196-4d97-b930-fd1cc376ca54
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057270941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1057270941
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3416482227
Short name T908
Test name
Test status
Simulation time 668790830 ps
CPU time 17.5 seconds
Started Jul 01 05:10:24 PM PDT 24
Finished Jul 01 05:10:57 PM PDT 24
Peak memory 208824 kb
Host smart-b39235b7-7beb-45ed-9802-da19b7f8dd87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416482227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3416482227
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3448222732
Short name T421
Test name
Test status
Simulation time 892450700 ps
CPU time 6.91 seconds
Started Jul 01 05:10:28 PM PDT 24
Finished Jul 01 05:10:49 PM PDT 24
Peak memory 208972 kb
Host smart-5bd307d8-117d-4f45-b848-3bd98f04f9d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448222732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3448222732
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3735414891
Short name T347
Test name
Test status
Simulation time 162032144 ps
CPU time 3.81 seconds
Started Jul 01 05:10:41 PM PDT 24
Finished Jul 01 05:10:52 PM PDT 24
Peak memory 218216 kb
Host smart-884d8a9f-eaa1-4b1e-8fb4-2b9c6e1476f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735414891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3735414891
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4199092449
Short name T644
Test name
Test status
Simulation time 257839197 ps
CPU time 3.51 seconds
Started Jul 01 05:10:21 PM PDT 24
Finished Jul 01 05:10:40 PM PDT 24
Peak memory 208536 kb
Host smart-f7e5b9eb-d5ce-45c7-b939-a5d45a4a82b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199092449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4199092449
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1281556103
Short name T730
Test name
Test status
Simulation time 374700991 ps
CPU time 12.97 seconds
Started Jul 01 05:10:30 PM PDT 24
Finished Jul 01 05:10:56 PM PDT 24
Peak memory 222424 kb
Host smart-1a513aad-3e5e-45e7-8eef-4f7cfaa65465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281556103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1281556103
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3684380222
Short name T354
Test name
Test status
Simulation time 1508238985 ps
CPU time 8.74 seconds
Started Jul 01 05:10:36 PM PDT 24
Finished Jul 01 05:10:55 PM PDT 24
Peak memory 222632 kb
Host smart-18833dd9-a0d3-440d-872e-5dc660f68e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684380222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3684380222
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2972842009
Short name T364
Test name
Test status
Simulation time 234695388 ps
CPU time 5.35 seconds
Started Jul 01 05:10:27 PM PDT 24
Finished Jul 01 05:10:47 PM PDT 24
Peak memory 210148 kb
Host smart-8c390ed7-0592-4400-8bdc-c5fc6664962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972842009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2972842009
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4210727021
Short name T532
Test name
Test status
Simulation time 17092148 ps
CPU time 0.9 seconds
Started Jul 01 05:08:21 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 206064 kb
Host smart-23610cb8-709b-40e1-9026-5c7b7ab6664c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210727021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4210727021
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2532449046
Short name T273
Test name
Test status
Simulation time 203775237 ps
CPU time 3.69 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 214356 kb
Host smart-8022ad44-239e-4c38-9add-3983be2fd8bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532449046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2532449046
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4228907542
Short name T918
Test name
Test status
Simulation time 203650398 ps
CPU time 2.79 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:30 PM PDT 24
Peak memory 218548 kb
Host smart-e80ccfc9-4a2a-4d13-86ec-7e743c7d5c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228907542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4228907542
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3461644120
Short name T627
Test name
Test status
Simulation time 235948533 ps
CPU time 3.5 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:24 PM PDT 24
Peak memory 209824 kb
Host smart-cdc507ba-4494-451f-9fb0-9b8b33c08bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461644120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3461644120
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3768071800
Short name T274
Test name
Test status
Simulation time 105864717 ps
CPU time 4.55 seconds
Started Jul 01 05:08:22 PM PDT 24
Finished Jul 01 05:08:28 PM PDT 24
Peak memory 210640 kb
Host smart-003f10f1-bcae-469b-bb5b-158919d7d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768071800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3768071800
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2284392901
Short name T634
Test name
Test status
Simulation time 1563681272 ps
CPU time 15.36 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:36 PM PDT 24
Peak memory 208172 kb
Host smart-8f0acb81-45bc-496f-99f1-9e24f3273b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284392901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2284392901
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.313886190
Short name T177
Test name
Test status
Simulation time 166895995 ps
CPU time 2.54 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 208560 kb
Host smart-b44cf961-a166-4f2b-8dd8-f4983c46dcb8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313886190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.313886190
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3458835590
Short name T861
Test name
Test status
Simulation time 145819796 ps
CPU time 2.64 seconds
Started Jul 01 05:08:21 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 206820 kb
Host smart-19f94634-9559-453a-8235-265b6be54806
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458835590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3458835590
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.64573056
Short name T484
Test name
Test status
Simulation time 59225078 ps
CPU time 2.45 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 206968 kb
Host smart-6c9f1122-4723-4468-bebb-493157c311f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64573056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.64573056
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.929238966
Short name T570
Test name
Test status
Simulation time 72923520 ps
CPU time 3.49 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:24 PM PDT 24
Peak memory 214280 kb
Host smart-a386de11-447a-4ea8-a00f-f940f7008f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929238966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.929238966
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3741622928
Short name T811
Test name
Test status
Simulation time 143898400 ps
CPU time 3.65 seconds
Started Jul 01 05:08:20 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 207032 kb
Host smart-75d7ec8d-dd74-4c42-a18c-9df7a3942b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741622928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3741622928
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.228168224
Short name T234
Test name
Test status
Simulation time 1871685093 ps
CPU time 46.34 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:09:14 PM PDT 24
Peak memory 222548 kb
Host smart-c2cc4f2e-dcb6-4b45-bc81-fdfad007f21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228168224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.228168224
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2604505607
Short name T166
Test name
Test status
Simulation time 939053947 ps
CPU time 6.01 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:26 PM PDT 24
Peak memory 222632 kb
Host smart-59b05490-c27d-4af0-a46a-afba4d798901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604505607 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2604505607
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3050350824
Short name T388
Test name
Test status
Simulation time 72463079 ps
CPU time 2.66 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 206928 kb
Host smart-9b589413-ba7e-429b-b72b-4d610f91af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050350824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3050350824
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1283197895
Short name T136
Test name
Test status
Simulation time 437853024 ps
CPU time 3.42 seconds
Started Jul 01 05:08:22 PM PDT 24
Finished Jul 01 05:08:27 PM PDT 24
Peak memory 210464 kb
Host smart-eab07084-0ca5-4f93-af14-5acddf92272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283197895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1283197895
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1239278547
Short name T498
Test name
Test status
Simulation time 9491057 ps
CPU time 0.83 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:33 PM PDT 24
Peak memory 206028 kb
Host smart-244cfa88-f5f7-4e47-a2c7-cde7080059b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239278547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1239278547
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.601329757
Short name T235
Test name
Test status
Simulation time 1100507108 ps
CPU time 18.38 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 219668 kb
Host smart-34ceb3c3-735f-4cc8-be7f-77e3d3ffc7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601329757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.601329757
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.508685740
Short name T73
Test name
Test status
Simulation time 362989885 ps
CPU time 2.9 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 222380 kb
Host smart-56733c0e-d326-4d49-bfec-40ac1b6a4403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508685740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.508685740
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1781034097
Short name T338
Test name
Test status
Simulation time 44067917 ps
CPU time 2.47 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 214176 kb
Host smart-a32652ee-4a71-411b-8163-d5693cadad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781034097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1781034097
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.124385540
Short name T761
Test name
Test status
Simulation time 291557229 ps
CPU time 3.46 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:24 PM PDT 24
Peak memory 209660 kb
Host smart-ebf18eda-44b3-40d2-a63a-7021c340f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124385540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.124385540
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.704320640
Short name T725
Test name
Test status
Simulation time 349670256 ps
CPU time 5.45 seconds
Started Jul 01 05:08:22 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 214484 kb
Host smart-f62858e0-3348-4d20-bebf-f7461dabac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704320640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.704320640
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3808618485
Short name T533
Test name
Test status
Simulation time 173654749 ps
CPU time 2.38 seconds
Started Jul 01 05:08:19 PM PDT 24
Finished Jul 01 05:08:23 PM PDT 24
Peak memory 207228 kb
Host smart-a4f43f2a-ea64-4731-9c33-650426a57327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808618485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3808618485
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1281510000
Short name T425
Test name
Test status
Simulation time 98992366 ps
CPU time 2.42 seconds
Started Jul 01 05:08:22 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 207040 kb
Host smart-9be48eca-60fc-4983-b07d-e4ff4e540c42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281510000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1281510000
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2779076641
Short name T721
Test name
Test status
Simulation time 34629988 ps
CPU time 2.12 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:28 PM PDT 24
Peak memory 206888 kb
Host smart-f27c4d76-4bbf-47e4-8f43-d4f3bad50d2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779076641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2779076641
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2195020228
Short name T472
Test name
Test status
Simulation time 145015144 ps
CPU time 5.49 seconds
Started Jul 01 05:08:20 PM PDT 24
Finished Jul 01 05:08:27 PM PDT 24
Peak memory 208688 kb
Host smart-621dd14c-445f-4b44-a033-f20813ecac9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195020228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2195020228
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3206912438
Short name T621
Test name
Test status
Simulation time 55317229 ps
CPU time 2.82 seconds
Started Jul 01 05:08:18 PM PDT 24
Finished Jul 01 05:08:22 PM PDT 24
Peak memory 208560 kb
Host smart-60bda26a-97a6-42ce-8e85-d30c71bc0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206912438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3206912438
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3815218997
Short name T418
Test name
Test status
Simulation time 853757577 ps
CPU time 21.77 seconds
Started Jul 01 05:08:21 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 208632 kb
Host smart-382bd5c6-3764-40e1-9bea-d76bf70b418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815218997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3815218997
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2320638501
Short name T707
Test name
Test status
Simulation time 91257093 ps
CPU time 3.32 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:30 PM PDT 24
Peak memory 207456 kb
Host smart-b92f00e7-c655-4041-a30e-3faa6d4dde9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320638501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2320638501
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.986682133
Short name T441
Test name
Test status
Simulation time 2071824703 ps
CPU time 3.4 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:30 PM PDT 24
Peak memory 210056 kb
Host smart-0fab27f5-7363-4bdf-83c3-b9cdcffbecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986682133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.986682133
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1526897755
Short name T905
Test name
Test status
Simulation time 43134262 ps
CPU time 0.91 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:36 PM PDT 24
Peak memory 206024 kb
Host smart-76446121-39cd-4da0-a2f0-203e1796f408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526897755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1526897755
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.356641930
Short name T488
Test name
Test status
Simulation time 87491285 ps
CPU time 2.24 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:34 PM PDT 24
Peak memory 208456 kb
Host smart-39a5e173-8238-4048-823b-e9a2bb46eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356641930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.356641930
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.298661029
Short name T897
Test name
Test status
Simulation time 314041183 ps
CPU time 2.42 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 214416 kb
Host smart-6cc43549-2c59-4f88-9450-786a72b6f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298661029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.298661029
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2083156879
Short name T77
Test name
Test status
Simulation time 109736478 ps
CPU time 4.97 seconds
Started Jul 01 05:08:24 PM PDT 24
Finished Jul 01 05:08:30 PM PDT 24
Peak memory 214336 kb
Host smart-fbb3bc52-f130-4aa6-9eae-12afcae80b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083156879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2083156879
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1682496258
Short name T587
Test name
Test status
Simulation time 93180016 ps
CPU time 2.23 seconds
Started Jul 01 05:08:27 PM PDT 24
Finished Jul 01 05:08:31 PM PDT 24
Peak memory 214276 kb
Host smart-b9440c38-7136-46ab-9bf5-846903c90fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682496258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1682496258
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3196657390
Short name T839
Test name
Test status
Simulation time 73378255 ps
CPU time 3.69 seconds
Started Jul 01 05:08:27 PM PDT 24
Finished Jul 01 05:08:32 PM PDT 24
Peak memory 214428 kb
Host smart-32f8a8e3-da2f-45c0-8467-3089ea2a2b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196657390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3196657390
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4285488229
Short name T831
Test name
Test status
Simulation time 129280172 ps
CPU time 2.54 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:28 PM PDT 24
Peak memory 208288 kb
Host smart-b183b260-812b-4b6d-8d93-329ef2c19707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285488229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4285488229
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3073547350
Short name T902
Test name
Test status
Simulation time 91033009 ps
CPU time 3.12 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 206892 kb
Host smart-72b94e71-9329-4509-b338-1f6ea1ce263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073547350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3073547350
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.166384471
Short name T541
Test name
Test status
Simulation time 26178902 ps
CPU time 2.05 seconds
Started Jul 01 05:08:26 PM PDT 24
Finished Jul 01 05:08:29 PM PDT 24
Peak memory 208868 kb
Host smart-dbc5b03a-3156-44c5-a47f-212ffb3cf395
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166384471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.166384471
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.896514429
Short name T669
Test name
Test status
Simulation time 333377159 ps
CPU time 8.11 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 208752 kb
Host smart-4b47aa2e-cd5d-4cf2-9a03-2e9a63c3b8bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896514429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.896514429
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1069309271
Short name T829
Test name
Test status
Simulation time 357925937 ps
CPU time 4.43 seconds
Started Jul 01 05:08:29 PM PDT 24
Finished Jul 01 05:08:34 PM PDT 24
Peak memory 208172 kb
Host smart-f653e822-a3fd-4744-8392-0c6ddc4659d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069309271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1069309271
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.874502123
Short name T452
Test name
Test status
Simulation time 64210288 ps
CPU time 2.67 seconds
Started Jul 01 05:08:28 PM PDT 24
Finished Jul 01 05:08:32 PM PDT 24
Peak memory 214344 kb
Host smart-6ab80fa4-0b61-4893-9929-8024ce877628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874502123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.874502123
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1718534618
Short name T696
Test name
Test status
Simulation time 218601476 ps
CPU time 4.68 seconds
Started Jul 01 05:08:25 PM PDT 24
Finished Jul 01 05:08:31 PM PDT 24
Peak memory 207292 kb
Host smart-e369e2ce-0984-4c40-ba28-f7729f4f7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718534618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1718534618
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2446286505
Short name T168
Test name
Test status
Simulation time 464093624 ps
CPU time 8.58 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 220440 kb
Host smart-53b982a7-57fb-4f1b-9c04-38c9e342f192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446286505 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2446286505
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1625243142
Short name T348
Test name
Test status
Simulation time 421146649 ps
CPU time 5.69 seconds
Started Jul 01 05:08:28 PM PDT 24
Finished Jul 01 05:08:35 PM PDT 24
Peak memory 208948 kb
Host smart-46d2d710-7bbb-4526-bf0c-cdf0bcf57970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625243142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1625243142
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4119258091
Short name T507
Test name
Test status
Simulation time 77824257 ps
CPU time 2.65 seconds
Started Jul 01 05:08:27 PM PDT 24
Finished Jul 01 05:08:30 PM PDT 24
Peak memory 210668 kb
Host smart-3dd9bf8b-c06e-4553-b477-fd39dcab2d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119258091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4119258091
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1837589203
Short name T871
Test name
Test status
Simulation time 42715814 ps
CPU time 0.74 seconds
Started Jul 01 05:08:35 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 206064 kb
Host smart-db890c1d-df2a-4692-bccb-2492bf9e684c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837589203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1837589203
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.477758315
Short name T34
Test name
Test status
Simulation time 192598315 ps
CPU time 5.65 seconds
Started Jul 01 05:08:35 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 220996 kb
Host smart-a809d5d5-5946-4989-b6e9-0f376aa99d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477758315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.477758315
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2343640676
Short name T566
Test name
Test status
Simulation time 318233620 ps
CPU time 2.95 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 208376 kb
Host smart-a0a853cc-fd32-436b-9a39-16a972476129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343640676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2343640676
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2756548480
Short name T698
Test name
Test status
Simulation time 302263399 ps
CPU time 2.9 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:47 PM PDT 24
Peak memory 214500 kb
Host smart-626a375b-6eb7-4972-97a6-6a32b09225c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756548480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2756548480
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.65841946
Short name T314
Test name
Test status
Simulation time 92049160 ps
CPU time 3.75 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 214684 kb
Host smart-ffbb1436-32a0-41e9-8252-7b1577393d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65841946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.65841946
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4148801694
Short name T660
Test name
Test status
Simulation time 286113176 ps
CPU time 2.47 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:34 PM PDT 24
Peak memory 220264 kb
Host smart-ad53fe28-ab85-45e7-a778-1038bf445ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148801694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4148801694
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1999639381
Short name T350
Test name
Test status
Simulation time 876054514 ps
CPU time 6.97 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 208864 kb
Host smart-fd7484df-4347-4917-8aa0-1dff817706d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999639381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1999639381
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3584883187
Short name T891
Test name
Test status
Simulation time 53008761 ps
CPU time 2.56 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:34 PM PDT 24
Peak memory 206148 kb
Host smart-29779807-5636-403f-8df1-4dc2f0e629df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584883187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3584883187
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3896481817
Short name T190
Test name
Test status
Simulation time 126859833 ps
CPU time 3.31 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 206964 kb
Host smart-52226798-6543-48a7-89ef-c77f6323fa65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896481817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3896481817
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.546847994
Short name T483
Test name
Test status
Simulation time 210379015 ps
CPU time 2.66 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:38 PM PDT 24
Peak memory 208232 kb
Host smart-701fe3c5-5417-45c7-8db9-6e595c961ea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546847994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.546847994
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.370207037
Short name T437
Test name
Test status
Simulation time 193506030 ps
CPU time 2.9 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 207132 kb
Host smart-8405d197-d982-417e-98bf-8dab0074d873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370207037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.370207037
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.601639630
Short name T412
Test name
Test status
Simulation time 1160127732 ps
CPU time 4.43 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 216208 kb
Host smart-fe8c51cd-5230-4add-b1cc-e0b892170104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601639630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.601639630
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3759421818
Short name T584
Test name
Test status
Simulation time 28233341 ps
CPU time 1.97 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:37 PM PDT 24
Peak memory 206968 kb
Host smart-3f523d68-30b7-42d5-8d87-07ed426fbbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759421818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3759421818
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2617626559
Short name T191
Test name
Test status
Simulation time 1309497913 ps
CPU time 8.93 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:53 PM PDT 24
Peak memory 209352 kb
Host smart-6f3b0884-35c3-44cc-b979-be183d679a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617626559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2617626559
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.667011164
Short name T32
Test name
Test status
Simulation time 671880872 ps
CPU time 6.63 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:42 PM PDT 24
Peak memory 210976 kb
Host smart-9547d5ef-2527-4117-bef9-6c7a5d144ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667011164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.667011164
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.168862955
Short name T583
Test name
Test status
Simulation time 30725766 ps
CPU time 0.81 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 206080 kb
Host smart-371c745e-2312-4d16-952b-524ba8073193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168862955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.168862955
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.317912276
Short name T506
Test name
Test status
Simulation time 87214971 ps
CPU time 4.09 seconds
Started Jul 01 05:08:41 PM PDT 24
Finished Jul 01 05:08:48 PM PDT 24
Peak memory 214352 kb
Host smart-eb6946d6-4585-406a-9bb5-f97caa592b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317912276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.317912276
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3292482739
Short name T185
Test name
Test status
Simulation time 198913634 ps
CPU time 2.18 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:35 PM PDT 24
Peak memory 207948 kb
Host smart-488e3763-8bdd-40bf-8234-bec92badf74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292482739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3292482739
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3567554900
Short name T882
Test name
Test status
Simulation time 127000607 ps
CPU time 4.36 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:49 PM PDT 24
Peak memory 214320 kb
Host smart-7be0ddc2-88a8-4026-945e-777d16a0e7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567554900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3567554900
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2878864356
Short name T466
Test name
Test status
Simulation time 90092652 ps
CPU time 4.3 seconds
Started Jul 01 05:08:32 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 209560 kb
Host smart-e9d5464c-7e7c-4cc8-9286-083cf99485ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878864356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2878864356
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2634039672
Short name T656
Test name
Test status
Simulation time 256263669 ps
CPU time 8.81 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:44 PM PDT 24
Peak memory 208460 kb
Host smart-914500d8-6d3f-4da0-971a-6406c430d4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634039672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2634039672
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1854544696
Short name T642
Test name
Test status
Simulation time 6109103697 ps
CPU time 42.92 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:09:18 PM PDT 24
Peak memory 208132 kb
Host smart-78d5f3c5-9031-470a-952b-0a36257dc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854544696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1854544696
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3944392296
Short name T647
Test name
Test status
Simulation time 141515481 ps
CPU time 4.25 seconds
Started Jul 01 05:08:31 PM PDT 24
Finished Jul 01 05:08:36 PM PDT 24
Peak memory 208508 kb
Host smart-3b91afbf-b73d-4077-9699-fc8361653651
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944392296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3944392296
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3995964148
Short name T252
Test name
Test status
Simulation time 154099480 ps
CPU time 4.92 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:49 PM PDT 24
Peak memory 208044 kb
Host smart-41db6eea-02f9-4a19-aba5-5dd044837a23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995964148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3995964148
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1317108541
Short name T389
Test name
Test status
Simulation time 716059692 ps
CPU time 4.71 seconds
Started Jul 01 05:08:35 PM PDT 24
Finished Jul 01 05:08:42 PM PDT 24
Peak memory 208720 kb
Host smart-0b930263-846e-4fb8-b9cb-9c67f50e2dda
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317108541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1317108541
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2179569139
Short name T255
Test name
Test status
Simulation time 349170091 ps
CPU time 4.64 seconds
Started Jul 01 05:08:38 PM PDT 24
Finished Jul 01 05:08:45 PM PDT 24
Peak memory 208076 kb
Host smart-e6f941c3-8fc5-4194-a2c3-6b06360b3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179569139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2179569139
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1816496859
Short name T198
Test name
Test status
Simulation time 204809943 ps
CPU time 3.94 seconds
Started Jul 01 05:08:33 PM PDT 24
Finished Jul 01 05:08:39 PM PDT 24
Peak memory 208712 kb
Host smart-5b67ae5f-b91e-4892-9238-23c999e16983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816496859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1816496859
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.282504576
Short name T520
Test name
Test status
Simulation time 1071782437 ps
CPU time 20.03 seconds
Started Jul 01 05:08:40 PM PDT 24
Finished Jul 01 05:09:02 PM PDT 24
Peak memory 215128 kb
Host smart-89827dd1-345e-4f12-809c-cc601404aa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282504576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.282504576
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.405099216
Short name T823
Test name
Test status
Simulation time 632310825 ps
CPU time 5.8 seconds
Started Jul 01 05:08:42 PM PDT 24
Finished Jul 01 05:08:50 PM PDT 24
Peak memory 208932 kb
Host smart-4633d3c1-8df4-4e00-a3c6-c3de2823be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405099216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.405099216
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.129430002
Short name T31
Test name
Test status
Simulation time 33519230 ps
CPU time 1.91 seconds
Started Jul 01 05:08:45 PM PDT 24
Finished Jul 01 05:08:51 PM PDT 24
Peak memory 209740 kb
Host smart-b64cd538-7e0a-499c-93bc-72213be839c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129430002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.129430002
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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