Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
57863 |
1 |
|
|
T1 |
47 |
|
T2 |
27 |
|
T3 |
615 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
33842 |
1 |
|
|
T1 |
14 |
|
T2 |
27 |
|
T3 |
372 |
auto[1] |
24021 |
1 |
|
|
T1 |
33 |
|
T3 |
243 |
|
T12 |
6 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28758 |
1 |
|
|
T1 |
24 |
|
T2 |
1 |
|
T3 |
351 |
auto[1] |
29105 |
1 |
|
|
T1 |
23 |
|
T2 |
26 |
|
T3 |
264 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16680 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
191 |
all_values[0] |
auto[0] |
auto[1] |
17162 |
1 |
|
|
T1 |
7 |
|
T2 |
26 |
|
T3 |
181 |
all_values[0] |
auto[1] |
auto[0] |
12078 |
1 |
|
|
T1 |
17 |
|
T3 |
160 |
|
T15 |
25 |
all_values[0] |
auto[1] |
auto[1] |
11943 |
1 |
|
|
T1 |
16 |
|
T3 |
83 |
|
T12 |
6 |