Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4981

1

T1

11

T2

3

T3

29

auto[1]

526

1

T3

2

T15

1

T81

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4981

1

T1

11

T2

3

T3

29

auto[1]

526

1

T3

2

T15

1

T81

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4939

1

T1

11

T2

2

T3

24

auto[1]

568

1

T2

1

T3

7

T24

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4939

1

T1

11

T2

2

T3

24

auto[1]

568

1

T2

1

T3

7

T24

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	422	1			T2	1		T3	1		T11	1
auto[OpGenId]	1234	1			T2	1		T3	8		T11	1
auto[OpGenSwOut]	1182	1			T2	1		T3	10		T11	1
auto[OpGenHwOut]	2584	1			T1	11		T3	11		T11	6
auto[OpDisable]	85	1			T3	1		T44	1		T42	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	422	1			T2	1		T3	1		T11	1
auto[OpGenId]	1234	1			T2	1		T3	8		T11	1
auto[OpGenSwOut]	1182	1			T2	1		T3	10		T11	1
auto[OpGenHwOut]	2584	1			T1	11		T3	11		T11	6
auto[OpDisable]	85	1			T3	1		T44	1		T42	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4952

1

T1

8

T2

2

T3

31

auto[1]

555

1

T1

3

T2

1

T13

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4952

1

T1

8

T2

2

T3

31

auto[1]

555

1

T1

3

T2

1

T13

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5146

1

T1

11

T2

3

T3

31

auto[1]

361

1

T115

21

T116

9

T77

9

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1876	1			T1	2		T2	2		T3	10
auto[1]	711	1			T1	2		T2	1		T3	4
auto[2]	732	1			T3	6		T33	1		T44	1
auto[3]	705	1			T1	2		T3	5		T11	4
auto[4]	367	1			T3	2		T11	2		T13	1
auto[5]	376	1			T1	2		T11	1		T15	1
auto[6]	363	1			T1	1		T3	1		T15	1
auto[7]	377	1			T1	2		T3	3		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1483	1			T1	5		T3	6		T11	3
clear_one[1]	711	1			T1	2		T2	1		T3	4
clear_one[2]	732	1			T3	6		T33	1		T44	1
clear_one[3]	705	1			T1	2		T3	5		T11	4
clear_none	1876	1			T1	2		T2	2		T3	10

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1008	1			T1	3		T2	1		T3	9
auto[StInit]	678	1			T1	1		T2	1		T3	2
auto[StCreatorRootKey]	568	1			T1	1		T3	3		T15	1
auto[StOwnerIntKey]	511	1			T1	1		T3	3		T11	1
auto[StOwnerKey]	513	1			T1	1		T3	2		T11	1
auto[StDisabled]	1937	1			T1	4		T2	1		T3	12
auto[StInvalid]	292	1			T35	3		T36	2		T45	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1008	1			T1	3		T2	1		T3	9
auto[StInit]	678	1			T1	1		T2	1		T3	2
auto[StCreatorRootKey]	568	1			T1	1		T3	3		T15	1
auto[StOwnerIntKey]	511	1			T1	1		T3	3		T11	1
auto[StOwnerKey]	513	1			T1	1		T3	2		T11	1
auto[StDisabled]	1937	1			T1	4		T2	1		T3	12
auto[StInvalid]	292	1			T35	3		T36	2		T45	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[4] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[4] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T225	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	176	1			T2	1		T3	3		T81	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	148	1			T3	1		T15	1		T25	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	271	1			T1	1		T3	1		T11	1
auto[0]	auto[StInit]	auto[OpAdvance]	47	1			T5	1		T116	1		T226	1
auto[0]	auto[StInit]	auto[OpGenId]	105	1			T12	1		T81	1		T44	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	91	1			T2	1		T115	1		T5	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	181	1			T3	1		T14	1		T24	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T77	1		T131	2		T141	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	44	1			T33	1		T50	2		T189	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T3	1		T81	1		T188	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	76	1			T191	1		T116	1		T56	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T226	1		T227	1		T228	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T81	1		T229	1		T230	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	27	1			T3	1		T50	1		T87	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T5	2		T59	1		T76	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T231	1		T232	1		T221	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	22	1			T33	1		T208	1		T233	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T13	1		T5	2		T116	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T116	1		T195	1		T199	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T115	5		T42	1		T234	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T115	6		T56	1		T235	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T3	2		T13	1		T15	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	176	1			T1	1		T123	1		T5	4
auto[0]	auto[StDisabled]	auto[OpDisable]	25	1			T50	1		T51	1		T233	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	15	1			T52	1		T236	1		T237	1
auto[0]	auto[StInvalid]	auto[OpGenId]	32	1			T35	2		T52	1		T82	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T36	1		T238	1		T85	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	28	1			T239	1		T83	1		T240	1
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T11	1		T76	1		T66	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T5	1		T17	2		T67	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T3	2		T199	1		T79	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T129	1		T241	1		T242	1
auto[1]	auto[StInit]	auto[OpGenId]	7	1			T20	1		T122	1		T27	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T81	1		T243	1		T244	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T199	1		T74	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T132	2		T58	1		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T208	1		T58	1		T247	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T5	1		T50	1		T129	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T5	1		T195	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T14	1		T59	1		T229	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T249	1		T250	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T81	1		T129	1		T196	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T1	1		T191	1		T195	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T252	1		T130	1		T58	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T42	1		T246	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T59	1		T229	1		T246	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T254	1		T255	1		T229	2
auto[1]	auto[StDisabled]	auto[OpAdvance]	33	1			T2	1		T5	2		T116	1
auto[1]	auto[StDisabled]	auto[OpGenId]	67	1			T3	2		T13	1		T59	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	46	1			T56	1		T80	1		T42	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T1	1		T5	2		T193	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T44	1		T256	1		T257	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T45	1		T85	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T259	1		T260	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T52	1		T238	2		T262	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T83	2		T262	2		T258	1
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T42	1		T263	1		T264	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	23	1			T124	1		T79	1		T42	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T74	1		T36	1		T265	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T20	1		T72	1		T88	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T59	1		T50	1		T73	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	17	1			T3	1		T234	1		T263	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T5	1		T192	1		T254	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T116	2		T266	1		T204	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	22	1			T124	1		T56	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T265	1		T50	1		T243	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T3	1		T199	1		T42	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T3	1		T123	1		T247	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T44	1		T116	2		T42	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T268	1		T269	1		T184	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T192	1		T270	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T87	1		T63	1		T121	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T5	1		T79	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	27	1			T3	1		T265	1		T120	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T56	1		T273	1		T208	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T274	1		T58	1		T122	1
auto[2]	auto[StDisabled]	auto[OpGenId]	63	1			T3	1		T5	1		T75	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T33	1		T5	4		T75	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T193	1		T194	1		T191	1
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T3	1		T54	1		T275	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T276	1		T86	1		T277	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T82	1		T278	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T36	1		T85	1		T262	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T262	1		T240	1		T279	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T280	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	13	1			T42	1		T39	1		T220	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T208	1		T72	1		T97	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T11	1		T192	1		T76	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T76	1		T130	1		T280	1
auto[3]	auto[StInit]	auto[OpGenId]	15	1			T42	1		T121	1		T281	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	9	1			T268	1		T55	1		T209	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T11	1		T282	1		T104	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T226	1		T253	1		T72	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T115	3		T283	1		T196	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T126	1		T284	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T1	1		T192	1		T74	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T120	1		T264	1		T286	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T81	1		T79	1		T122	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T130	1		T287	1		T122	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T3	1		T11	1		T265	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T288	1		T289	1		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	19	1			T5	1		T196	1		T130	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T58	1		T249	1		T72	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T1	1		T193	1		T191	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T77	1		T268	1		T290	1
auto[3]	auto[StDisabled]	auto[OpGenId]	54	1			T24	1		T5	1		T42	3
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T3	2		T56	1		T80	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	141	1			T3	2		T11	1		T15	1
auto[3]	auto[StDisabled]	auto[OpDisable]	15	1			T42	1		T55	1		T291	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T259	1		T292	1		T293	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T45	1		T238	1		T85	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T82	1		T239	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T35	1		T238	1		T294	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T3	1		T280	1		T294	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T55	1		T184	1		T185	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T254	1		T55	1		T288	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T295	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T290	1		T264	1		T247	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T58	1		T296	1		T184	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T255	1		T297	1		T287	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T63	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T20	1		T183	1		T280	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T58	1		T298	1		T217	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T3	1		T59	1		T282	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T299	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T122	1		T97	1		T184	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T33	1		T58	1		T247	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T194	1		T199	1		T300	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T121	1		T301	1		T302	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T42	1		T303	1		T304	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T5	1		T84	1		T184	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T11	1		T5	1		T74	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T77	3		T80	2		T129	2
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T13	1		T59	1		T265	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T11	1		T81	1		T197	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T33	1		T193	1		T192	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T67	1		T58	1		T182	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	7	1			T259	1		T262	1		T305	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T237	1		T306	1		T307	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T306	1		T294	1		T308	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T45	1		T22	1		T294	1
auto[5]	auto[StReset]	auto[OpGenId]	14	1			T5	1		T51	1		T309	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T92	1		T310	1		T311	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T1	1		T81	1		T5	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T312	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T66	1		T21	1		T256	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T52	1		T88	1		T201	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T1	1		T195	1		T248	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T77	1		T247	1		T225	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T244	1		T201	1		T222	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T44	1		T5	1		T274	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T270	1		T313	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T129	1		T315	1		T185	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T198	1		T121	1		T55	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T18	1		T316	1		T317	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T115	1		T193	1		T318	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T15	1		T78	1		T208	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	11	1			T61	1		T208	1		T122	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T77	4		T250	1		T204	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T192	1		T129	1		T190	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	18	1			T11	1		T5	1		T76	1
auto[5]	auto[StDisabled]	auto[OpGenId]	31	1			T59	1		T129	1		T196	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T5	1		T56	1		T50	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T5	1		T50	1		T270	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T50	1		T319	1		T320	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T321	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T240	1		T293	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T45	1		T261	1		T323	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T324	1		T325	2		T326	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T52	1		T214	1		T327	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T45	1		T42	1		T72	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	31	1			T1	1		T126	1		T74	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T309	1		T145	1		T327	1
auto[6]	auto[StInit]	auto[OpGenId]	1	1			T328	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	9	1			T283	1		T50	1		T30	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T5	1		T43	1		T310	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T56	1		T329	1		T330	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T5	1		T58	1		T184	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T56	1		T30	1		T296	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T24	1		T193	1		T254	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T331	1		T299	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T75	1		T208	1		T244	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T5	1		T184	1		T332	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	9	1			T333	1		T334	1		T335	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T115	1		T336	1		T337	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T291	1		T319	1		T338	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T234	1		T230	1		T183	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T248	1		T339	1		T318	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T75	1		T336	1		T103	1
auto[6]	auto[StDisabled]	auto[OpGenId]	34	1			T15	1		T50	1		T340	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T3	1		T33	1		T50	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T192	1		T74	1		T254	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T71	1		T185	1		T341	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T86	1		T342	1		T343	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T82	1		T93	1		T323	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T236	1		T278	1		T276	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T45	1		T278	1		T343	1
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T81	1		T43	1		T30	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T64	1		T185	1		T344	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	18	1			T3	1		T195	1		T74	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T264	1		T345	1		T346	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T265	1		T88	1		T347	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T190	1		T110	1		T348	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T122	1		T206	1		T349	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T58	1		T122	1		T251	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T81	1		T42	1		T55	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T15	1		T194	1		T339	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T310	1		T241	2		T328	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T73	1		T184	1		T241	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T56	1		T50	1		T232	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T56	1		T350	1		T339	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T115	3		T76	1		T247	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T3	1		T5	1		T290	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T209	1		T310	1		T351	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T194	1		T352	1		T353	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T58	1		T310	1		T48	1
auto[7]	auto[StDisabled]	auto[OpGenId]	35	1			T59	1		T340	1		T229	3
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T115	3		T274	1		T300	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T1	2		T3	1		T115	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T61	1		T66	1		T354	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T355	1		T356	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T236	1		T260	1		T279	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T278	1		T357	1		T358	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T82	1		T359	1		T360	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1483

1

T1

5

T3

6

T11

3

clear_one[1]

auto[0]

auto[0]

auto[0]

402

1

T3

3

T11

1

T13

1

clear_one[1]

auto[0]

auto[0]

auto[1]

121

1

T1

2

T59

1

T195

4

clear_one[1]

auto[0]

auto[1]

auto[0]

136

1

T3

1

T5

2

T193

1

clear_one[1]

auto[0]

auto[1]

auto[1]

52

1

T2

1

T5

2

T116

1

clear_one[2]

auto[0]

auto[0]

auto[0]

442

1

T3

5

T33

1

T44

1

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T116

4

T199

3

T87

2

clear_one[2]

auto[1]

auto[0]

auto[0]

128

1

T3

1

T5

1

T191

1

clear_one[2]

auto[1]

auto[0]

auto[1]

35

1

T284

1

T312

2

T208

1

clear_one[3]

auto[0]

auto[0]

auto[0]

418

1

T1

2

T3

1

T11

4

clear_one[3]

auto[0]

auto[1]

auto[0]

126

1

T3

3

T24

1

T5

1

clear_one[3]

auto[1]

auto[0]

auto[0]

131

1

T3

1

T15

1

T81

1

clear_one[3]

auto[1]

auto[1]

auto[0]

30

1

T283

1

T196

1

T290

1

clear_none

auto[0]

auto[0]

auto[0]

1359

1

T1

1

T2

2

T3

7

clear_none

auto[0]

auto[0]

auto[1]

139

1

T1

1

T13

1

T116

2

clear_none

auto[0]

auto[1]

auto[0]

133

1

T3

3

T123

1

T5

1

clear_none

auto[0]

auto[1]

auto[1]

43

1

T197

1

T116

3

T42

1

clear_none

auto[1]

auto[0]

auto[0]

134

1

T115

1

T5

1

T191

1

clear_none

auto[1]

auto[0]

auto[1]

20

1

T50

1

T229

1

T247

1

clear_none

auto[1]

auto[1]

auto[0]

30

1

T115

2

T5

2

T361

1

clear_none

auto[1]

auto[1]

auto[1]

18

1

T5

2

T116

1

T284

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1370	1			T1	5		T3	6		T11	3
clear_all	auto[1]	113	1			T115	6		T77	7		T80	1
clear_one[1]	auto[0]	652	1			T1	2		T2	1		T3	4
clear_one[1]	auto[1]	59	1			T80	1		T129	2		T130	2
clear_one[2]	auto[0]	680	1			T3	6		T33	1		T44	1
clear_one[2]	auto[1]	52	1			T116	3		T80	1		T336	1
clear_one[3]	auto[0]	663	1			T1	2		T3	5		T11	4
clear_one[3]	auto[1]	42	1			T115	2		T130	6		T250	3
clear_none	auto[0]	1781	1			T1	2		T2	2		T3	10
clear_none	auto[1]	95	1			T115	13		T116	6		T77	2