Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11041

1

T1

10

T2

18

T3

125

auto[Attestation]

7729

1

T1

5

T2

3

T3

68

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2720	1			T2	1		T3	25		T4	3
auto[Aes]	3317	1			T2	6		T3	35		T11	7
auto[Kmac]	3425	1			T2	6		T3	39		T4	3
auto[Otbn]	3398	1			T1	15		T2	3		T3	25

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7660	1			T1	8		T2	5		T3	61
auto[OpGenId]	5910	1			T2	5		T3	69		T4	1
auto[OpGenSwOut]	5832	1			T2	12		T3	67		T4	2
auto[OpGenHwOut]	7028	1			T1	15		T2	4		T3	57
auto[OpDisable]	158	1			T3	1		T44	1		T5	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10717

1

T1

8

T2

16

T3

75

auto[OpDoneFail]

15871

1

T1

15

T2

10

T3

180

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6413	1			T1	8		T2	8		T3	97
auto[StInit]	3760	1			T1	2		T2	4		T3	22
auto[StCreatorRootKey]	3184	1			T1	2		T2	5		T3	27
auto[StOwnerIntKey]	2791	1			T1	2		T2	6		T3	15
auto[StOwnerKey]	2485	1			T1	2		T2	3		T3	16
auto[StDisabled]	7955	1			T1	7		T3	78		T11	12

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	332	1			T3	6		T25	2		T124	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T3	1		T5	2		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T3	1		T81	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	78	1			T2	1		T15	1		T5	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T3	1		T5	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	197	1			T3	1		T11	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	300	1			T3	8		T34	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	89	1			T2	1		T59	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	84	1			T3	1		T28	1		T187	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	69	1			T2	2		T33	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	52	1			T5	1		T116	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	220	1			T3	1		T5	3		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	315	1			T2	3		T3	3		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T3	1		T33	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T2	1		T3	3		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T11	1		T5	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T81	1		T125	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	205	1			T3	3		T33	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	311	1			T2	1		T3	7		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	113	1			T2	1		T15	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T3	1		T11	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T3	1		T34	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T34	1		T5	2		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	232	1			T3	4		T5	2		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T3	1		T33	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	114	1			T3	2		T5	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T3	1		T34	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	79	1			T4	2		T15	1		T81	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T13	1		T123	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	207	1			T3	2		T11	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	78	1			T33	1		T5	2		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T2	1		T15	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T3	1		T11	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T11	1		T44	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T24	1		T5	2		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T3	5		T11	1		T33	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T3	2		T5	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	99	1			T33	1		T34	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T125	1		T28	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T2	1		T3	1		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	69	1			T3	1		T24	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	239	1			T3	5		T13	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T3	2		T81	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T81	1		T5	1		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T81	1		T5	1		T59	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T15	1		T81	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T123	1		T5	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	204	1			T3	1		T24	1		T123	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	267	1			T3	3		T11	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	80	1			T3	1		T24	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	92	1			T5	1		T56	2		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T34	1		T5	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T181	1		T84	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	189	1			T3	2		T13	1		T123	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	510	1			T3	8		T11	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	95	1			T3	1		T115	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T3	1		T11	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T3	1		T191	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T2	2		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	265	1			T3	1		T33	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	472	1			T3	7		T11	3		T124	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T4	1		T123	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T126	1		T193	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T2	1		T11	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	102	1			T3	1		T5	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	276	1			T3	1		T33	1		T115	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	437	1			T1	7		T3	3		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	133	1			T1	1		T13	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T24	1		T195	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T195	1		T42	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	286	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T3	1		T81	3		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T11	1		T5	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T3	1		T126	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	76	1			T11	1		T87	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T4	1		T197	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	178	1			T3	1		T123	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T3	1		T33	1		T81	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T3	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	106	1			T3	1		T5	2		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T5	2		T50	1		T179	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T5	1		T50	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	267	1			T3	3		T15	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T3	3		T81	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T3	3		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T3	2		T24	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T115	1		T193	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	101	1			T4	1		T24	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	289	1			T3	3		T15	1		T123	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T3	2		T59	1		T56	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T81	1		T24	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T13	1		T15	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T1	1		T3	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	98	1			T1	1		T3	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T1	3		T3	1		T11	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	203	1			T2	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	636	1			T3	9		T11	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	192	1			T2	2		T3	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	622	1			T2	1		T3	9		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T2	1		T3	3		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	635	1			T2	3		T3	7		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T3	2		T11	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	668	1			T2	2		T3	11		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T4	2		T13	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	405	1			T3	6		T11	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	210	1			T3	1		T11	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	401	1			T2	1		T3	5		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	206	1			T2	1		T3	2		T11	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	423	1			T3	7		T13	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T15	1		T81	2		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	405	1			T3	3		T81	3		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T34	1		T5	2		T56	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	548	1			T3	6		T11	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	281	1			T2	2		T3	3		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	882	1			T3	10		T11	4		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T2	1		T3	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	881	1			T3	8		T4	1		T11	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	877	1			T1	9		T3	4		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T3	1		T4	1		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	361	1			T3	2		T11	1		T81	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	275	1			T3	1		T5	4		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	454	1			T3	5		T12	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	304	1			T3	2		T4	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	496	1			T3	9		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T1	2		T3	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	478	1			T1	3		T3	3		T11	3