Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32796

1

T1

28

T2

31

T3

286

auto[1]

360

1

T115

16

T116

9

T77

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32808	1			T1	28		T2	31		T3	286
auto[134217728:268435455]	13	1			T115	2		T129	1		T131	1
auto[268435456:402653183]	11	1			T116	1		T229	2		T336	1
auto[402653184:536870911]	5	1			T374	1		T280	1		T394	1
auto[536870912:671088639]	8	1			T116	2		T229	1		T336	1
auto[671088640:805306367]	9	1			T116	1		T77	1		T374	2
auto[805306368:939524095]	14	1			T77	1		T229	1		T272	1
auto[939524096:1073741823]	9	1			T77	1		T131	1		T229	1
auto[1073741824:1207959551]	17	1			T116	1		T77	2		T80	1
auto[1207959552:1342177279]	10	1			T116	1		T130	1		T229	1
auto[1342177280:1476395007]	14	1			T115	1		T77	1		T129	1
auto[1476395008:1610612735]	15	1			T130	1		T131	1		T229	1
auto[1610612736:1744830463]	12	1			T129	1		T132	1		T336	3
auto[1744830464:1879048191]	7	1			T115	2		T336	1		T272	1
auto[1879048192:2013265919]	15	1			T116	1		T272	1		T315	1
auto[2013265920:2147483647]	10	1			T116	1		T246	1		T394	1
auto[2147483648:2281701375]	13	1			T115	1		T129	1		T229	1
auto[2281701376:2415919103]	8	1			T115	1		T229	2		T315	1
auto[2415919104:2550136831]	12	1			T115	2		T132	1		T336	1
auto[2550136832:2684354559]	12	1			T115	1		T131	1		T374	1
auto[2684354560:2818572287]	6	1			T129	1		T375	1		T395	1
auto[2818572288:2952790015]	11	1			T116	1		T130	1		T229	2
auto[2952790016:3087007743]	16	1			T77	1		T130	1		T272	3
auto[3087007744:3221225471]	12	1			T115	1		T80	1		T129	2
auto[3221225472:3355443199]	9	1			T129	2		T132	1		T272	2
auto[3355443200:3489660927]	17	1			T115	1		T132	1		T374	1
auto[3489660928:3623878655]	14	1			T115	1		T80	1		T132	1
auto[3623878656:3758096383]	14	1			T130	1		T336	1		T280	1
auto[3758096384:3892314111]	5	1			T131	1		T132	1		T396	2
auto[3892314112:4026531839]	15	1			T115	1		T129	1		T130	2
auto[4026531840:4160749567]	8	1			T115	1		T129	1		T371	1
auto[4160749568:4294967295]	7	1			T80	1		T272	1		T286	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32796	1			T1	28		T2	31		T3	286
auto[0:134217727]	auto[1]	12	1			T115	1		T77	2		T131	1
auto[134217728:268435455]	auto[1]	13	1			T115	2		T129	1		T131	1
auto[268435456:402653183]	auto[1]	11	1			T116	1		T229	2		T336	1
auto[402653184:536870911]	auto[1]	5	1			T374	1		T280	1		T394	1
auto[536870912:671088639]	auto[1]	8	1			T116	2		T229	1		T336	1
auto[671088640:805306367]	auto[1]	9	1			T116	1		T77	1		T374	2
auto[805306368:939524095]	auto[1]	14	1			T77	1		T229	1		T272	1
auto[939524096:1073741823]	auto[1]	9	1			T77	1		T131	1		T229	1
auto[1073741824:1207959551]	auto[1]	17	1			T116	1		T77	2		T80	1
auto[1207959552:1342177279]	auto[1]	10	1			T116	1		T130	1		T229	1
auto[1342177280:1476395007]	auto[1]	14	1			T115	1		T77	1		T129	1
auto[1476395008:1610612735]	auto[1]	15	1			T130	1		T131	1		T229	1
auto[1610612736:1744830463]	auto[1]	12	1			T129	1		T132	1		T336	3
auto[1744830464:1879048191]	auto[1]	7	1			T115	2		T336	1		T272	1
auto[1879048192:2013265919]	auto[1]	15	1			T116	1		T272	1		T315	1
auto[2013265920:2147483647]	auto[1]	10	1			T116	1		T246	1		T394	1
auto[2147483648:2281701375]	auto[1]	13	1			T115	1		T129	1		T229	1
auto[2281701376:2415919103]	auto[1]	8	1			T115	1		T229	2		T315	1
auto[2415919104:2550136831]	auto[1]	12	1			T115	2		T132	1		T336	1
auto[2550136832:2684354559]	auto[1]	12	1			T115	1		T131	1		T374	1
auto[2684354560:2818572287]	auto[1]	6	1			T129	1		T375	1		T395	1
auto[2818572288:2952790015]	auto[1]	11	1			T116	1		T130	1		T229	2
auto[2952790016:3087007743]	auto[1]	16	1			T77	1		T130	1		T272	3
auto[3087007744:3221225471]	auto[1]	12	1			T115	1		T80	1		T129	2
auto[3221225472:3355443199]	auto[1]	9	1			T129	2		T132	1		T272	2
auto[3355443200:3489660927]	auto[1]	17	1			T115	1		T132	1		T374	1
auto[3489660928:3623878655]	auto[1]	14	1			T115	1		T80	1		T132	1
auto[3623878656:3758096383]	auto[1]	14	1			T130	1		T336	1		T280	1
auto[3758096384:3892314111]	auto[1]	5	1			T131	1		T132	1		T396	2
auto[3892314112:4026531839]	auto[1]	15	1			T115	1		T129	1		T130	2
auto[4026531840:4160749567]	auto[1]	8	1			T115	1		T129	1		T371	1
auto[4160749568:4294967295]	auto[1]	7	1			T80	1		T272	1		T286	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1622

1

T2

2

T3

26

T11

1

auto[1]

1768

1

T2

2

T3

11

T11

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T3	2		T25	1		T126	1
auto[134217728:268435455]	101	1			T12	1		T35	1		T56	1
auto[268435456:402653183]	110	1			T3	2		T11	1		T25	1
auto[402653184:536870911]	109	1			T24	1		T25	1		T35	1
auto[536870912:671088639]	99	1			T3	3		T115	1		T5	1
auto[671088640:805306367]	94	1			T2	1		T5	1		T35	1
auto[805306368:939524095]	106	1			T115	2		T5	2		T35	1
auto[939524096:1073741823]	105	1			T3	1		T81	1		T5	2
auto[1073741824:1207959551]	89	1			T3	1		T44	1		T116	1
auto[1207959552:1342177279]	103	1			T3	2		T81	1		T123	1
auto[1342177280:1476395007]	107	1			T11	1		T28	1		T5	1
auto[1476395008:1610612735]	108	1			T3	1		T15	2		T81	1
auto[1610612736:1744830463]	112	1			T3	1		T81	1		T24	1
auto[1744830464:1879048191]	123	1			T3	2		T44	1		T5	1
auto[1879048192:2013265919]	99	1			T3	1		T124	1		T28	1
auto[2013265920:2147483647]	93	1			T3	1		T81	1		T123	1
auto[2147483648:2281701375]	111	1			T3	1		T59	1		T76	1
auto[2281701376:2415919103]	108	1			T2	1		T3	3		T12	1
auto[2415919104:2550136831]	104	1			T3	2		T124	1		T115	1
auto[2550136832:2684354559]	114	1			T11	1		T25	1		T44	1
auto[2684354560:2818572287]	106	1			T15	1		T81	1		T126	1
auto[2818572288:2952790015]	112	1			T11	1		T81	1		T24	1
auto[2952790016:3087007743]	113	1			T3	1		T5	1		T77	1
auto[3087007744:3221225471]	109	1			T3	1		T12	1		T123	2
auto[3221225472:3355443199]	123	1			T15	1		T42	3		T50	2
auto[3355443200:3489660927]	92	1			T3	1		T14	1		T24	1
auto[3489660928:3623878655]	94	1			T3	2		T116	1		T56	1
auto[3623878656:3758096383]	96	1			T2	1		T3	2		T5	2
auto[3758096384:3892314111]	106	1			T2	1		T3	2		T14	1
auto[3892314112:4026531839]	118	1			T3	2		T81	1		T5	1
auto[4026531840:4160749567]	101	1			T3	3		T11	1		T115	1
auto[4160749568:4294967295]	108	1			T81	1		T5	1		T87	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	61	1			T3	2		T25	1		T126	1
auto[0:134217727]	auto[1]	56	1			T5	1		T76	1		T50	2
auto[134217728:268435455]	auto[0]	43	1			T12	1		T35	1		T75	1
auto[134217728:268435455]	auto[1]	58	1			T56	1		T129	1		T87	1
auto[268435456:402653183]	auto[0]	52	1			T25	1		T115	1		T5	2
auto[268435456:402653183]	auto[1]	58	1			T3	2		T11	1		T5	2
auto[402653184:536870911]	auto[0]	60	1			T24	1		T25	1		T35	1
auto[402653184:536870911]	auto[1]	49	1			T79	1		T120	1		T290	1
auto[536870912:671088639]	auto[0]	47	1			T3	2		T115	1		T234	1
auto[536870912:671088639]	auto[1]	52	1			T3	1		T5	1		T52	1
auto[671088640:805306367]	auto[0]	50	1			T2	1		T5	1		T35	1
auto[671088640:805306367]	auto[1]	44	1			T56	1		T50	1		T196	1
auto[805306368:939524095]	auto[0]	51	1			T36	1		T42	1		T43	1
auto[805306368:939524095]	auto[1]	55	1			T115	2		T5	2		T35	1
auto[939524096:1073741823]	auto[0]	50	1			T3	1		T116	1		T36	1
auto[939524096:1073741823]	auto[1]	55	1			T81	1		T5	2		T56	2
auto[1073741824:1207959551]	auto[0]	41	1			T190	1		T54	1		T230	1
auto[1073741824:1207959551]	auto[1]	48	1			T3	1		T44	1		T116	1
auto[1207959552:1342177279]	auto[0]	40	1			T3	2		T243	1		T181	1
auto[1207959552:1342177279]	auto[1]	63	1			T81	1		T123	1		T197	2
auto[1342177280:1476395007]	auto[0]	56	1			T28	1		T79	1		T80	1
auto[1342177280:1476395007]	auto[1]	51	1			T11	1		T5	1		T50	1
auto[1476395008:1610612735]	auto[0]	51	1			T3	1		T25	1		T5	1
auto[1476395008:1610612735]	auto[1]	57	1			T15	2		T81	1		T5	1
auto[1610612736:1744830463]	auto[0]	58	1			T126	1		T42	2		T284	1
auto[1610612736:1744830463]	auto[1]	54	1			T3	1		T81	1		T24	1
auto[1744830464:1879048191]	auto[0]	64	1			T3	1		T44	1		T5	1
auto[1744830464:1879048191]	auto[1]	59	1			T3	1		T42	1		T49	1
auto[1879048192:2013265919]	auto[0]	45	1			T50	1		T397	1		T121	1
auto[1879048192:2013265919]	auto[1]	54	1			T3	1		T124	1		T28	1
auto[2013265920:2147483647]	auto[0]	37	1			T3	1		T268	1		T208	1
auto[2013265920:2147483647]	auto[1]	56	1			T81	1		T123	1		T234	1
auto[2147483648:2281701375]	auto[0]	55	1			T3	1		T59	1		T76	1
auto[2147483648:2281701375]	auto[1]	56	1			T42	1		T50	1		T120	1
auto[2281701376:2415919103]	auto[0]	50	1			T3	3		T59	1		T80	1
auto[2281701376:2415919103]	auto[1]	58	1			T2	1		T12	1		T24	1
auto[2415919104:2550136831]	auto[0]	54	1			T3	2		T124	1		T5	1
auto[2415919104:2550136831]	auto[1]	50	1			T115	1		T5	1		T116	1
auto[2550136832:2684354559]	auto[0]	49	1			T11	1		T25	1		T197	1
auto[2550136832:2684354559]	auto[1]	65	1			T44	1		T59	1		T42	1
auto[2684354560:2818572287]	auto[0]	50	1			T81	1		T126	1		T56	1
auto[2684354560:2818572287]	auto[1]	56	1			T15	1		T5	2		T76	1
auto[2818572288:2952790015]	auto[0]	52	1			T116	1		T59	2		T340	1
auto[2818572288:2952790015]	auto[1]	60	1			T11	1		T81	1		T24	1
auto[2952790016:3087007743]	auto[0]	51	1			T5	1		T52	1		T46	1
auto[2952790016:3087007743]	auto[1]	62	1			T3	1		T77	1		T50	1
auto[3087007744:3221225471]	auto[0]	45	1			T3	1		T123	2		T5	1
auto[3087007744:3221225471]	auto[1]	64	1			T12	1		T5	1		T50	1
auto[3221225472:3355443199]	auto[0]	62	1			T42	3		T50	1		T196	1
auto[3221225472:3355443199]	auto[1]	61	1			T15	1		T50	1		T340	1
auto[3355443200:3489660927]	auto[0]	52	1			T3	1		T59	1		T198	1
auto[3355443200:3489660927]	auto[1]	40	1			T14	1		T24	1		T5	2
auto[3489660928:3623878655]	auto[0]	51	1			T3	1		T76	1		T45	1
auto[3489660928:3623878655]	auto[1]	43	1			T3	1		T116	1		T56	1
auto[3623878656:3758096383]	auto[0]	50	1			T2	1		T3	1		T243	1
auto[3623878656:3758096383]	auto[1]	46	1			T3	1		T5	2		T78	1
auto[3758096384:3892314111]	auto[0]	53	1			T3	1		T126	1		T5	2
auto[3758096384:3892314111]	auto[1]	53	1			T2	1		T3	1		T14	1
auto[3892314112:4026531839]	auto[0]	47	1			T3	2		T81	1		T35	1
auto[3892314112:4026531839]	auto[1]	71	1			T5	1		T59	1		T77	1
auto[4026531840:4160749567]	auto[0]	43	1			T3	3		T115	1		T5	1
auto[4026531840:4160749567]	auto[1]	58	1			T11	1		T79	1		T340	1
auto[4160749568:4294967295]	auto[0]	52	1			T81	1		T181	1		T398	1
auto[4160749568:4294967295]	auto[1]	56	1			T5	1		T87	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1607

1

T2

2

T3

22

T11

2

auto[1]

1784

1

T2

2

T3

15

T11

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T3	2		T5	2		T50	3
auto[134217728:268435455]	125	1			T3	2		T11	1		T25	1
auto[268435456:402653183]	116	1			T3	1		T11	1		T15	1
auto[402653184:536870911]	100	1			T3	3		T15	1		T81	1
auto[536870912:671088639]	107	1			T5	1		T59	1		T42	1
auto[671088640:805306367]	108	1			T3	2		T14	1		T81	1
auto[805306368:939524095]	98	1			T59	1		T77	1		T79	1
auto[939524096:1073741823]	109	1			T3	2		T44	1		T123	1
auto[1073741824:1207959551]	95	1			T3	1		T115	2		T28	1
auto[1207959552:1342177279]	107	1			T3	2		T11	2		T81	1
auto[1342177280:1476395007]	108	1			T3	4		T11	1		T15	1
auto[1476395008:1610612735]	109	1			T15	1		T5	2		T59	1
auto[1610612736:1744830463]	121	1			T3	1		T24	1		T25	1
auto[1744830464:1879048191]	113	1			T115	1		T126	1		T5	1
auto[1879048192:2013265919]	94	1			T44	1		T5	2		T197	1
auto[2013265920:2147483647]	101	1			T5	1		T59	1		T56	2
auto[2147483648:2281701375]	99	1			T12	1		T56	2		T79	1
auto[2281701376:2415919103]	103	1			T2	1		T3	1		T5	1
auto[2415919104:2550136831]	103	1			T81	1		T25	1		T124	1
auto[2550136832:2684354559]	98	1			T3	1		T25	1		T5	1
auto[2684354560:2818572287]	110	1			T2	1		T5	1		T76	1
auto[2818572288:2952790015]	104	1			T3	2		T12	1		T81	1
auto[2952790016:3087007743]	101	1			T24	1		T126	1		T28	1
auto[3087007744:3221225471]	119	1			T3	1		T81	1		T5	1
auto[3221225472:3355443199]	91	1			T3	2		T123	1		T5	1
auto[3355443200:3489660927]	108	1			T81	1		T35	2		T45	1
auto[3489660928:3623878655]	84	1			T3	1		T81	1		T24	1
auto[3623878656:3758096383]	116	1			T2	1		T3	2		T44	1
auto[3758096384:3892314111]	112	1			T3	1		T12	1		T14	1
auto[3892314112:4026531839]	115	1			T2	1		T3	2		T5	3
auto[4026531840:4160749567]	108	1			T3	2		T25	1		T50	2
auto[4160749568:4294967295]	106	1			T3	2		T44	1		T123	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T3	1		T43	1		T21	1
auto[0:134217727]	auto[1]	60	1			T3	1		T5	2		T50	3
auto[134217728:268435455]	auto[0]	58	1			T25	1		T5	1		T284	1
auto[134217728:268435455]	auto[1]	67	1			T3	2		T11	1		T5	2
auto[268435456:402653183]	auto[0]	50	1			T3	1		T5	2		T50	1
auto[268435456:402653183]	auto[1]	66	1			T11	1		T15	1		T81	1
auto[402653184:536870911]	auto[0]	49	1			T3	2		T123	1		T76	1
auto[402653184:536870911]	auto[1]	51	1			T3	1		T15	1		T81	1
auto[536870912:671088639]	auto[0]	57	1			T120	1		T82	1		T68	1
auto[536870912:671088639]	auto[1]	50	1			T5	1		T59	1		T42	1
auto[671088640:805306367]	auto[0]	35	1			T3	2		T126	1		T5	1
auto[671088640:805306367]	auto[1]	73	1			T14	1		T81	1		T5	1
auto[805306368:939524095]	auto[0]	46	1			T42	2		T62	1		T236	1
auto[805306368:939524095]	auto[1]	52	1			T59	1		T77	1		T79	1
auto[939524096:1073741823]	auto[0]	61	1			T5	1		T197	1		T59	1
auto[939524096:1073741823]	auto[1]	48	1			T3	2		T44	1		T123	1
auto[1073741824:1207959551]	auto[0]	54	1			T3	1		T36	1		T42	1
auto[1073741824:1207959551]	auto[1]	41	1			T115	2		T28	1		T116	1
auto[1207959552:1342177279]	auto[0]	42	1			T3	1		T11	1		T5	1
auto[1207959552:1342177279]	auto[1]	65	1			T3	1		T11	1		T81	1
auto[1342177280:1476395007]	auto[0]	54	1			T3	3		T11	1		T124	1
auto[1342177280:1476395007]	auto[1]	54	1			T3	1		T15	1		T5	1
auto[1476395008:1610612735]	auto[0]	55	1			T36	1		T75	1		T42	2
auto[1476395008:1610612735]	auto[1]	54	1			T15	1		T5	2		T59	1
auto[1610612736:1744830463]	auto[0]	49	1			T3	1		T25	1		T126	1
auto[1610612736:1744830463]	auto[1]	72	1			T24	1		T115	2		T75	1
auto[1744830464:1879048191]	auto[0]	54	1			T126	1		T5	1		T230	1
auto[1744830464:1879048191]	auto[1]	59	1			T115	1		T59	1		T42	1
auto[1879048192:2013265919]	auto[0]	51	1			T44	1		T5	2		T59	1
auto[1879048192:2013265919]	auto[1]	43	1			T197	1		T50	1		T239	1
auto[2013265920:2147483647]	auto[0]	42	1			T59	1		T78	1		T42	2
auto[2013265920:2147483647]	auto[1]	59	1			T5	1		T56	2		T76	1
auto[2147483648:2281701375]	auto[0]	44	1			T12	1		T56	1		T79	1
auto[2147483648:2281701375]	auto[1]	55	1			T56	1		T190	1		T58	2
auto[2281701376:2415919103]	auto[0]	49	1			T5	1		T116	1		T36	1
auto[2281701376:2415919103]	auto[1]	54	1			T2	1		T3	1		T56	1
auto[2415919104:2550136831]	auto[0]	49	1			T81	1		T25	1		T124	1
auto[2415919104:2550136831]	auto[1]	54	1			T5	2		T116	1		T50	1
auto[2550136832:2684354559]	auto[0]	49	1			T3	1		T25	1		T5	1
auto[2550136832:2684354559]	auto[1]	49	1			T36	1		T179	1		T252	1
auto[2684354560:2818572287]	auto[0]	50	1			T50	1		T7	1		T46	1
auto[2684354560:2818572287]	auto[1]	60	1			T2	1		T5	1		T76	1
auto[2818572288:2952790015]	auto[0]	56	1			T3	1		T12	1		T81	1
auto[2818572288:2952790015]	auto[1]	48	1			T3	1		T24	2		T5	2
auto[2952790016:3087007743]	auto[0]	43	1			T126	1		T28	1		T59	1
auto[2952790016:3087007743]	auto[1]	58	1			T24	1		T129	1		T131	1
auto[3087007744:3221225471]	auto[0]	56	1			T81	1		T116	1		T42	1
auto[3087007744:3221225471]	auto[1]	63	1			T3	1		T5	1		T197	1
auto[3221225472:3355443199]	auto[0]	44	1			T3	1		T123	1		T59	1
auto[3221225472:3355443199]	auto[1]	47	1			T3	1		T5	1		T77	1
auto[3355443200:3489660927]	auto[0]	45	1			T35	1		T45	1		T61	1
auto[3355443200:3489660927]	auto[1]	63	1			T81	1		T35	1		T50	1
auto[3489660928:3623878655]	auto[0]	48	1			T3	1		T24	1		T59	1
auto[3489660928:3623878655]	auto[1]	36	1			T81	1		T56	1		T80	1
auto[3623878656:3758096383]	auto[0]	55	1			T2	1		T3	1		T77	1
auto[3623878656:3758096383]	auto[1]	61	1			T3	1		T44	1		T115	1
auto[3758096384:3892314111]	auto[0]	49	1			T5	1		T50	1		T340	1
auto[3758096384:3892314111]	auto[1]	63	1			T3	1		T12	1		T14	1
auto[3892314112:4026531839]	auto[0]	55	1			T2	1		T3	1		T5	1
auto[3892314112:4026531839]	auto[1]	60	1			T3	1		T5	2		T59	1
auto[4026531840:4160749567]	auto[0]	59	1			T3	2		T25	1		T196	1
auto[4026531840:4160749567]	auto[1]	49	1			T50	2		T129	1		T63	1
auto[4160749568:4294967295]	auto[0]	56	1			T3	2		T44	1		T197	1
auto[4160749568:4294967295]	auto[1]	50	1			T123	1		T76	1		T63	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T2

2

T3

25

T11

2

auto[1]

1787

1

T2

2

T3

12

T11

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T14	1		T81	1		T197	1
auto[134217728:268435455]	105	1			T3	2		T115	1		T5	2
auto[268435456:402653183]	96	1			T2	1		T3	1		T24	1
auto[402653184:536870911]	88	1			T14	1		T24	1		T25	1
auto[536870912:671088639]	111	1			T28	1		T5	2		T197	1
auto[671088640:805306367]	98	1			T24	1		T25	1		T80	1
auto[805306368:939524095]	97	1			T3	3		T5	2		T50	1
auto[939524096:1073741823]	125	1			T3	1		T11	1		T15	1
auto[1073741824:1207959551]	100	1			T11	1		T24	1		T5	3
auto[1207959552:1342177279]	95	1			T2	1		T5	2		T76	1
auto[1342177280:1476395007]	101	1			T5	1		T59	1		T36	1
auto[1476395008:1610612735]	108	1			T3	1		T12	1		T81	2
auto[1610612736:1744830463]	117	1			T3	1		T81	1		T126	1
auto[1744830464:1879048191]	100	1			T123	1		T5	2		T78	1
auto[1879048192:2013265919]	109	1			T2	1		T44	1		T28	1
auto[2013265920:2147483647]	97	1			T115	1		T116	1		T45	1
auto[2147483648:2281701375]	93	1			T3	2		T81	1		T126	1
auto[2281701376:2415919103]	107	1			T3	4		T123	1		T5	2
auto[2415919104:2550136831]	104	1			T3	1		T11	1		T15	1
auto[2550136832:2684354559]	110	1			T3	1		T25	1		T126	1
auto[2684354560:2818572287]	109	1			T3	2		T81	1		T44	1
auto[2818572288:2952790015]	98	1			T3	2		T11	1		T81	1
auto[2952790016:3087007743]	104	1			T2	1		T3	1		T5	1
auto[3087007744:3221225471]	94	1			T3	1		T12	1		T115	1
auto[3221225472:3355443199]	121	1			T3	2		T11	1		T81	1
auto[3355443200:3489660927]	116	1			T3	3		T5	1		T197	1
auto[3489660928:3623878655]	111	1			T3	3		T25	1		T5	2
auto[3623878656:3758096383]	119	1			T12	1		T15	1		T81	1
auto[3758096384:3892314111]	110	1			T3	1		T123	1		T115	1
auto[3892314112:4026531839]	101	1			T126	1		T59	1		T50	1
auto[4026531840:4160749567]	115	1			T3	3		T44	1		T5	2
auto[4160749568:4294967295]	123	1			T3	2		T15	1		T5	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T81	1		T197	1		T59	1
auto[0:134217727]	auto[1]	56	1			T14	1		T50	2		T84	1
auto[134217728:268435455]	auto[0]	51	1			T3	1		T115	1		T5	1
auto[134217728:268435455]	auto[1]	54	1			T3	1		T5	1		T59	1
auto[268435456:402653183]	auto[0]	49	1			T124	1		T56	1		T198	1
auto[268435456:402653183]	auto[1]	47	1			T2	1		T3	1		T24	1
auto[402653184:536870911]	auto[0]	37	1			T25	1		T58	1		T22	1
auto[402653184:536870911]	auto[1]	51	1			T14	1		T24	1		T116	1
auto[536870912:671088639]	auto[0]	57	1			T197	1		T36	1		T45	1
auto[536870912:671088639]	auto[1]	54	1			T28	1		T5	2		T6	1
auto[671088640:805306367]	auto[0]	55	1			T24	1		T25	1		T80	1
auto[671088640:805306367]	auto[1]	43	1			T42	1		T50	1		T120	1
auto[805306368:939524095]	auto[0]	42	1			T3	3		T5	1		T196	1
auto[805306368:939524095]	auto[1]	55	1			T5	1		T50	1		T243	1
auto[939524096:1073741823]	auto[0]	61	1			T3	1		T11	1		T35	2
auto[939524096:1073741823]	auto[1]	64	1			T15	1		T115	1		T5	1
auto[1073741824:1207959551]	auto[0]	44	1			T5	1		T129	1		T284	1
auto[1073741824:1207959551]	auto[1]	56	1			T11	1		T24	1		T5	2
auto[1207959552:1342177279]	auto[0]	45	1			T5	2		T50	1		T21	1
auto[1207959552:1342177279]	auto[1]	50	1			T2	1		T76	1		T42	1
auto[1342177280:1476395007]	auto[0]	54	1			T5	1		T59	1		T36	1
auto[1342177280:1476395007]	auto[1]	47	1			T50	1		T196	1		T340	1
auto[1476395008:1610612735]	auto[0]	55	1			T3	1		T12	1		T5	1
auto[1476395008:1610612735]	auto[1]	53	1			T81	2		T59	1		T42	1
auto[1610612736:1744830463]	auto[0]	66	1			T3	1		T126	1		T35	1
auto[1610612736:1744830463]	auto[1]	51	1			T81	1		T5	1		T59	1
auto[1744830464:1879048191]	auto[0]	39	1			T123	1		T5	1		T42	1
auto[1744830464:1879048191]	auto[1]	61	1			T5	1		T78	1		T50	1
auto[1879048192:2013265919]	auto[0]	50	1			T2	1		T28	1		T284	1
auto[1879048192:2013265919]	auto[1]	59	1			T44	1		T5	2		T78	1
auto[2013265920:2147483647]	auto[0]	41	1			T116	1		T45	1		T42	2
auto[2013265920:2147483647]	auto[1]	56	1			T115	1		T50	1		T63	1
auto[2147483648:2281701375]	auto[0]	57	1			T3	2		T59	1		T129	1
auto[2147483648:2281701375]	auto[1]	36	1			T81	1		T126	1		T5	1
auto[2281701376:2415919103]	auto[0]	54	1			T3	2		T5	1		T42	1
auto[2281701376:2415919103]	auto[1]	53	1			T3	2		T123	1		T5	1
auto[2415919104:2550136831]	auto[0]	49	1			T3	1		T5	1		T243	1
auto[2415919104:2550136831]	auto[1]	55	1			T11	1		T15	1		T197	1
auto[2550136832:2684354559]	auto[0]	55	1			T3	1		T25	1		T126	1
auto[2550136832:2684354559]	auto[1]	55	1			T28	1		T78	1		T46	1
auto[2684354560:2818572287]	auto[0]	48	1			T3	1		T55	1		T47	1
auto[2684354560:2818572287]	auto[1]	61	1			T3	1		T81	1		T44	1
auto[2818572288:2952790015]	auto[0]	40	1			T11	1		T25	1		T397	1
auto[2818572288:2952790015]	auto[1]	58	1			T3	2		T81	1		T5	1
auto[2952790016:3087007743]	auto[0]	55	1			T2	1		T3	1		T5	1
auto[2952790016:3087007743]	auto[1]	49	1			T78	1		T181	1		T84	1
auto[3087007744:3221225471]	auto[0]	42	1			T3	1		T5	1		T52	1
auto[3087007744:3221225471]	auto[1]	52	1			T12	1		T115	1		T5	1
auto[3221225472:3355443199]	auto[0]	59	1			T81	1		T5	1		T59	2
auto[3221225472:3355443199]	auto[1]	62	1			T3	2		T11	1		T36	1
auto[3355443200:3489660927]	auto[0]	53	1			T3	2		T5	1		T116	1
auto[3355443200:3489660927]	auto[1]	63	1			T3	1		T197	1		T59	1
auto[3489660928:3623878655]	auto[0]	38	1			T3	2		T25	1		T7	1
auto[3489660928:3623878655]	auto[1]	73	1			T3	1		T5	2		T75	1
auto[3623878656:3758096383]	auto[0]	55	1			T12	1		T81	1		T24	1
auto[3623878656:3758096383]	auto[1]	64	1			T15	1		T44	1		T123	1
auto[3758096384:3892314111]	auto[0]	47	1			T3	1		T123	1		T115	1
auto[3758096384:3892314111]	auto[1]	63	1			T56	1		T50	1		T234	1
auto[3892314112:4026531839]	auto[0]	46	1			T126	1		T59	1		T340	1
auto[3892314112:4026531839]	auto[1]	55	1			T50	1		T120	1		T51	1
auto[4026531840:4160749567]	auto[0]	56	1			T3	3		T44	1		T35	1
auto[4026531840:4160749567]	auto[1]	59	1			T5	2		T42	1		T50	1
auto[4160749568:4294967295]	auto[0]	51	1			T3	1		T59	1		T76	1
auto[4160749568:4294967295]	auto[1]	72	1			T3	1		T15	1		T5	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T2

2

T3

24

T11

2

auto[1]

1787

1

T2

2

T3

13

T11

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T44	1		T115	1
auto[134217728:268435455]	109	1			T11	1		T44	1		T5	3
auto[268435456:402653183]	102	1			T5	3		T36	2		T77	1
auto[402653184:536870911]	112	1			T5	4		T35	1		T56	2
auto[536870912:671088639]	104	1			T2	1		T3	1		T15	1
auto[671088640:805306367]	100	1			T3	2		T11	1		T15	1
auto[805306368:939524095]	113	1			T3	1		T81	1		T25	1
auto[939524096:1073741823]	100	1			T3	1		T124	1		T126	1
auto[1073741824:1207959551]	117	1			T3	1		T124	1		T5	2
auto[1207959552:1342177279]	105	1			T2	1		T3	1		T81	1
auto[1342177280:1476395007]	89	1			T3	1		T81	1		T28	2
auto[1476395008:1610612735]	118	1			T3	2		T5	2		T59	1
auto[1610612736:1744830463]	106	1			T3	3		T5	2		T77	1
auto[1744830464:1879048191]	101	1			T3	1		T12	1		T5	1
auto[1879048192:2013265919]	103	1			T3	1		T14	1		T81	1
auto[2013265920:2147483647]	94	1			T3	1		T116	1		T75	1
auto[2147483648:2281701375]	102	1			T3	2		T81	1		T115	1
auto[2281701376:2415919103]	112	1			T3	2		T11	1		T81	1
auto[2415919104:2550136831]	85	1			T50	1		T87	1		T49	1
auto[2550136832:2684354559]	108	1			T3	1		T5	2		T79	1
auto[2684354560:2818572287]	113	1			T44	2		T123	1		T5	1
auto[2818572288:2952790015]	105	1			T3	1		T14	1		T15	1
auto[2952790016:3087007743]	111	1			T3	2		T126	1		T5	1
auto[3087007744:3221225471]	111	1			T2	1		T3	1		T24	1
auto[3221225472:3355443199]	119	1			T3	4		T11	1		T25	1
auto[3355443200:3489660927]	119	1			T3	2		T15	1		T5	2
auto[3489660928:3623878655]	103	1			T2	1		T3	1		T12	1
auto[3623878656:3758096383]	118	1			T11	1		T24	1		T59	1
auto[3758096384:3892314111]	107	1			T3	1		T12	1		T24	1
auto[3892314112:4026531839]	90	1			T3	1		T81	2		T5	2
auto[4026531840:4160749567]	101	1			T3	1		T35	1		T42	1
auto[4160749568:4294967295]	101	1			T3	1		T81	1		T115	1