Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2968

1

T2

4

T3

23

T11

5

auto[1]

348

1

T115

12

T116

6

T77

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T3	1		T115	1		T76	1
auto[134217728:268435455]	103	1			T3	2		T81	1		T25	1
auto[268435456:402653183]	95	1			T11	1		T25	1		T115	1
auto[402653184:536870911]	105	1			T3	1		T25	1		T115	1
auto[536870912:671088639]	98	1			T3	2		T59	1		T78	1
auto[671088640:805306367]	111	1			T3	1		T12	1		T24	1
auto[805306368:939524095]	103	1			T2	1		T5	2		T56	1
auto[939524096:1073741823]	107	1			T11	1		T59	1		T56	2
auto[1073741824:1207959551]	104	1			T2	1		T15	1		T81	1
auto[1207959552:1342177279]	110	1			T5	1		T59	1		T36	1
auto[1342177280:1476395007]	111	1			T11	1		T124	1		T115	2
auto[1476395008:1610612735]	97	1			T2	1		T3	1		T81	1
auto[1610612736:1744830463]	98	1			T3	2		T24	1		T44	1
auto[1744830464:1879048191]	89	1			T11	1		T81	1		T115	1
auto[1879048192:2013265919]	87	1			T14	1		T81	1		T116	1
auto[2013265920:2147483647]	113	1			T3	1		T5	1		T116	1
auto[2147483648:2281701375]	101	1			T3	1		T116	1		T59	1
auto[2281701376:2415919103]	93	1			T2	1		T3	2		T115	1
auto[2415919104:2550136831]	110	1			T81	1		T24	1		T115	1
auto[2550136832:2684354559]	112	1			T3	1		T5	2		T116	2
auto[2684354560:2818572287]	104	1			T24	1		T44	1		T28	1
auto[2818572288:2952790015]	107	1			T123	1		T5	2		T197	1
auto[2952790016:3087007743]	85	1			T15	1		T115	1		T5	1
auto[3087007744:3221225471]	96	1			T81	1		T123	1		T115	1
auto[3221225472:3355443199]	119	1			T3	2		T15	1		T81	1
auto[3355443200:3489660927]	101	1			T3	1		T115	1		T116	1
auto[3489660928:3623878655]	91	1			T3	1		T24	1		T115	1
auto[3623878656:3758096383]	118	1			T81	1		T44	1		T28	1
auto[3758096384:3892314111]	112	1			T25	1		T124	1		T5	2
auto[3892314112:4026531839]	99	1			T3	2		T11	1		T44	1
auto[4026531840:4160749567]	112	1			T12	1		T115	1		T5	1
auto[4160749568:4294967295]	111	1			T3	2		T15	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T3	1		T76	1		T50	2
auto[0:134217727]	auto[1]	17	1			T115	1		T131	1		T246	1
auto[134217728:268435455]	auto[0]	90	1			T3	2		T81	1		T25	1
auto[134217728:268435455]	auto[1]	13	1			T80	1		T229	1		T336	1
auto[268435456:402653183]	auto[0]	80	1			T11	1		T25	1		T115	1
auto[268435456:402653183]	auto[1]	15	1			T77	1		T129	1		T130	1
auto[402653184:536870911]	auto[0]	92	1			T3	1		T25	1		T35	1
auto[402653184:536870911]	auto[1]	13	1			T115	1		T130	1		T229	1
auto[536870912:671088639]	auto[0]	90	1			T3	2		T59	1		T78	1
auto[536870912:671088639]	auto[1]	8	1			T129	1		T131	1		T229	1
auto[671088640:805306367]	auto[0]	102	1			T3	1		T12	1		T24	1
auto[671088640:805306367]	auto[1]	9	1			T116	1		T130	1		T336	1
auto[805306368:939524095]	auto[0]	97	1			T2	1		T5	2		T56	1
auto[805306368:939524095]	auto[1]	6	1			T77	1		T129	1		T336	1
auto[939524096:1073741823]	auto[0]	97	1			T11	1		T59	1		T56	2
auto[939524096:1073741823]	auto[1]	10	1			T80	1		T272	1		T315	1
auto[1073741824:1207959551]	auto[0]	93	1			T2	1		T15	1		T81	1
auto[1073741824:1207959551]	auto[1]	11	1			T115	1		T130	1		T132	1
auto[1207959552:1342177279]	auto[0]	102	1			T5	1		T59	1		T36	1
auto[1207959552:1342177279]	auto[1]	8	1			T77	1		T336	1		T329	1
auto[1342177280:1476395007]	auto[0]	100	1			T11	1		T124	1		T5	1
auto[1342177280:1476395007]	auto[1]	11	1			T115	2		T371	1		T280	1
auto[1476395008:1610612735]	auto[0]	90	1			T2	1		T3	1		T81	1
auto[1476395008:1610612735]	auto[1]	7	1			T115	1		T80	1		T374	1
auto[1610612736:1744830463]	auto[0]	84	1			T3	2		T24	1		T44	1
auto[1610612736:1744830463]	auto[1]	14	1			T115	1		T80	1		T129	1
auto[1744830464:1879048191]	auto[0]	77	1			T11	1		T81	1		T126	1
auto[1744830464:1879048191]	auto[1]	12	1			T115	1		T80	1		T130	1
auto[1879048192:2013265919]	auto[0]	73	1			T14	1		T81	1		T59	1
auto[1879048192:2013265919]	auto[1]	14	1			T116	1		T132	2		T250	1
auto[2013265920:2147483647]	auto[0]	99	1			T3	1		T5	1		T116	1
auto[2013265920:2147483647]	auto[1]	14	1			T132	1		T246	1		T315	1
auto[2147483648:2281701375]	auto[0]	88	1			T3	1		T116	1		T59	1
auto[2147483648:2281701375]	auto[1]	13	1			T336	2		T286	2		T375	1
auto[2281701376:2415919103]	auto[0]	88	1			T2	1		T3	2		T115	1
auto[2281701376:2415919103]	auto[1]	5	1			T77	1		T396	1		T406	1
auto[2415919104:2550136831]	auto[0]	106	1			T81	1		T24	1		T115	1
auto[2415919104:2550136831]	auto[1]	4	1			T129	1		T336	1		T250	1
auto[2550136832:2684354559]	auto[0]	100	1			T3	1		T5	2		T59	1
auto[2550136832:2684354559]	auto[1]	12	1			T116	2		T131	1		T280	1
auto[2684354560:2818572287]	auto[0]	92	1			T24	1		T44	1		T28	1
auto[2684354560:2818572287]	auto[1]	12	1			T77	1		T336	1		T272	1
auto[2818572288:2952790015]	auto[0]	101	1			T123	1		T5	2		T197	1
auto[2818572288:2952790015]	auto[1]	6	1			T116	1		T229	1		T246	1
auto[2952790016:3087007743]	auto[0]	75	1			T15	1		T5	1		T78	2
auto[2952790016:3087007743]	auto[1]	10	1			T115	1		T77	1		T129	1
auto[3087007744:3221225471]	auto[0]	91	1			T81	1		T123	1		T115	1
auto[3087007744:3221225471]	auto[1]	5	1			T315	1		T394	1		T403	1
auto[3221225472:3355443199]	auto[0]	107	1			T3	2		T15	1		T81	1
auto[3221225472:3355443199]	auto[1]	12	1			T115	1		T116	1		T229	1
auto[3355443200:3489660927]	auto[0]	87	1			T3	1		T116	1		T78	1
auto[3355443200:3489660927]	auto[1]	14	1			T115	1		T129	1		T130	1
auto[3489660928:3623878655]	auto[0]	77	1			T3	1		T24	1		T77	1
auto[3489660928:3623878655]	auto[1]	14	1			T115	1		T336	1		T280	1
auto[3623878656:3758096383]	auto[0]	104	1			T81	1		T44	1		T28	1
auto[3623878656:3758096383]	auto[1]	14	1			T130	1		T229	1		T374	3
auto[3758096384:3892314111]	auto[0]	99	1			T25	1		T124	1		T5	2
auto[3758096384:3892314111]	auto[1]	13	1			T229	1		T246	1		T336	2
auto[3892314112:4026531839]	auto[0]	91	1			T3	2		T11	1		T44	1
auto[3892314112:4026531839]	auto[1]	8	1			T286	1		T394	1		T378	1
auto[4026531840:4160749567]	auto[0]	97	1			T12	1		T115	1		T5	1
auto[4026531840:4160749567]	auto[1]	15	1			T130	1		T229	1		T246	2
auto[4160749568:4294967295]	auto[0]	102	1			T3	2		T15	1		T5	1
auto[4160749568:4294967295]	auto[1]	9	1			T77	1		T129	1		T131	1