Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T2

2

T3

24

T11

1

auto[1]

1780

1

T2

2

T3

13

T11

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T2	1		T3	1		T123	1
auto[134217728:268435455]	102	1			T12	1		T115	1		T28	1
auto[268435456:402653183]	113	1			T2	1		T126	1		T5	1
auto[402653184:536870911]	110	1			T3	1		T81	1		T35	1
auto[536870912:671088639]	95	1			T3	2		T81	1		T44	1
auto[671088640:805306367]	115	1			T3	3		T5	1		T35	1
auto[805306368:939524095]	97	1			T3	2		T14	1		T123	1
auto[939524096:1073741823]	95	1			T3	1		T124	1		T126	1
auto[1073741824:1207959551]	109	1			T3	1		T81	1		T25	1
auto[1207959552:1342177279]	110	1			T3	1		T25	1		T59	1
auto[1342177280:1476395007]	97	1			T3	3		T81	1		T24	1
auto[1476395008:1610612735]	99	1			T24	1		T5	3		T197	1
auto[1610612736:1744830463]	109	1			T3	3		T35	1		T76	1
auto[1744830464:1879048191]	114	1			T3	2		T11	1		T81	1
auto[1879048192:2013265919]	104	1			T3	2		T115	1		T5	1
auto[2013265920:2147483647]	109	1			T3	3		T28	1		T56	1
auto[2147483648:2281701375]	102	1			T3	1		T5	1		T59	1
auto[2281701376:2415919103]	101	1			T3	2		T5	3		T35	1
auto[2415919104:2550136831]	122	1			T3	1		T11	1		T14	1
auto[2550136832:2684354559]	132	1			T12	1		T123	1		T5	1
auto[2684354560:2818572287]	102	1			T81	1		T123	1		T5	2
auto[2818572288:2952790015]	98	1			T15	1		T25	1		T56	1
auto[2952790016:3087007743]	101	1			T3	2		T11	1		T42	1
auto[3087007744:3221225471]	116	1			T3	1		T81	1		T5	1
auto[3221225472:3355443199]	97	1			T2	1		T11	1		T24	1
auto[3355443200:3489660927]	103	1			T3	1		T15	1		T5	1
auto[3489660928:3623878655]	90	1			T12	1		T5	3		T59	1
auto[3623878656:3758096383]	107	1			T2	1		T116	1		T36	1
auto[3758096384:3892314111]	93	1			T3	1		T81	1		T115	1
auto[3892314112:4026531839]	100	1			T3	2		T11	1		T15	1
auto[4026531840:4160749567]	119	1			T3	1		T24	1		T44	1
auto[4160749568:4294967295]	116	1			T15	1		T44	1		T124	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T115	1		T5	1		T45	1
auto[0:134217727]	auto[1]	65	1			T2	1		T3	1		T123	1
auto[134217728:268435455]	auto[0]	48	1			T12	1		T28	1		T234	1
auto[134217728:268435455]	auto[1]	54	1			T115	1		T5	1		T239	1
auto[268435456:402653183]	auto[0]	58	1			T2	1		T126	1		T5	1
auto[268435456:402653183]	auto[1]	55	1			T59	1		T56	1		T63	1
auto[402653184:536870911]	auto[0]	40	1			T3	1		T35	1		T56	1
auto[402653184:536870911]	auto[1]	70	1			T81	1		T79	1		T42	1
auto[536870912:671088639]	auto[0]	40	1			T3	2		T81	1		T5	2
auto[536870912:671088639]	auto[1]	55	1			T44	1		T28	1		T50	2
auto[671088640:805306367]	auto[0]	58	1			T3	2		T35	1		T36	1
auto[671088640:805306367]	auto[1]	57	1			T3	1		T5	1		T21	1
auto[805306368:939524095]	auto[0]	36	1			T234	1		T243	1		T46	1
auto[805306368:939524095]	auto[1]	61	1			T3	2		T14	1		T123	1
auto[939524096:1073741823]	auto[0]	38	1			T3	1		T124	1		T126	1
auto[939524096:1073741823]	auto[1]	57	1			T5	2		T79	1		T42	1
auto[1073741824:1207959551]	auto[0]	50	1			T3	1		T25	1		T5	1
auto[1073741824:1207959551]	auto[1]	59	1			T81	1		T44	1		T115	1
auto[1207959552:1342177279]	auto[0]	46	1			T3	1		T25	1		T77	1
auto[1207959552:1342177279]	auto[1]	64	1			T59	1		T77	1		T78	1
auto[1342177280:1476395007]	auto[0]	53	1			T3	1		T78	1		T42	2
auto[1342177280:1476395007]	auto[1]	44	1			T3	2		T81	1		T24	1
auto[1476395008:1610612735]	auto[0]	53	1			T5	1		T50	1		T20	1
auto[1476395008:1610612735]	auto[1]	46	1			T24	1		T5	2		T197	1
auto[1610612736:1744830463]	auto[0]	44	1			T3	1		T35	1		T42	1
auto[1610612736:1744830463]	auto[1]	65	1			T3	2		T76	1		T50	1
auto[1744830464:1879048191]	auto[0]	51	1			T3	1		T81	1		T25	1
auto[1744830464:1879048191]	auto[1]	63	1			T3	1		T11	1		T59	1
auto[1879048192:2013265919]	auto[0]	48	1			T3	1		T115	1		T59	2
auto[1879048192:2013265919]	auto[1]	56	1			T3	1		T5	1		T59	1
auto[2013265920:2147483647]	auto[0]	46	1			T3	2		T243	1		T20	1
auto[2013265920:2147483647]	auto[1]	63	1			T3	1		T28	1		T56	1
auto[2147483648:2281701375]	auto[0]	47	1			T5	1		T59	1		T236	1
auto[2147483648:2281701375]	auto[1]	55	1			T3	1		T75	1		T121	1
auto[2281701376:2415919103]	auto[0]	48	1			T3	2		T5	1		T35	1
auto[2281701376:2415919103]	auto[1]	53	1			T5	2		T50	1		T87	2
auto[2415919104:2550136831]	auto[0]	63	1			T3	1		T11	1		T24	1
auto[2415919104:2550136831]	auto[1]	59	1			T14	1		T115	1		T116	1
auto[2550136832:2684354559]	auto[0]	73	1			T123	1		T56	1		T36	1
auto[2550136832:2684354559]	auto[1]	59	1			T12	1		T5	1		T116	1
auto[2684354560:2818572287]	auto[0]	51	1			T5	1		T56	1		T80	1
auto[2684354560:2818572287]	auto[1]	51	1			T81	1		T123	1		T5	1
auto[2818572288:2952790015]	auto[0]	53	1			T25	1		T42	1		T7	1
auto[2818572288:2952790015]	auto[1]	45	1			T15	1		T56	1		T42	1
auto[2952790016:3087007743]	auto[0]	51	1			T3	1		T42	1		T129	1
auto[2952790016:3087007743]	auto[1]	50	1			T3	1		T11	1		T37	1
auto[3087007744:3221225471]	auto[0]	54	1			T3	1		T5	1		T197	1
auto[3087007744:3221225471]	auto[1]	62	1			T81	1		T50	1		T234	1
auto[3221225472:3355443199]	auto[0]	40	1			T25	1		T5	2		T59	1
auto[3221225472:3355443199]	auto[1]	57	1			T2	1		T11	1		T24	1
auto[3355443200:3489660927]	auto[0]	57	1			T3	1		T5	1		T80	1
auto[3355443200:3489660927]	auto[1]	46	1			T15	1		T56	1		T76	2
auto[3489660928:3623878655]	auto[0]	42	1			T12	1		T5	1		T59	1
auto[3489660928:3623878655]	auto[1]	48	1			T5	2		T50	1		T54	1
auto[3623878656:3758096383]	auto[0]	67	1			T2	1		T116	1		T36	1
auto[3623878656:3758096383]	auto[1]	40	1			T6	1		T340	1		T62	1
auto[3758096384:3892314111]	auto[0]	49	1			T3	1		T115	1		T5	1
auto[3758096384:3892314111]	auto[1]	44	1			T81	1		T116	1		T42	1
auto[3892314112:4026531839]	auto[0]	44	1			T3	2		T42	2		T54	1
auto[3892314112:4026531839]	auto[1]	56	1			T11	1		T15	1		T81	1
auto[4026531840:4160749567]	auto[0]	69	1			T3	1		T126	1		T5	1
auto[4026531840:4160749567]	auto[1]	50	1			T24	1		T44	1		T79	1
auto[4160749568:4294967295]	auto[0]	45	1			T59	1		T243	1		T268	1
auto[4160749568:4294967295]	auto[1]	71	1			T15	1		T44	1		T124	1