Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4508

1

T2

4

T3

48

T11

8

auto[1]

2272

1

T2

4

T3

26

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	194	1			T3	6		T11	2		T116	2
auto[134217728:268435455]	214	1			T3	2		T59	2		T78	2
auto[268435456:402653183]	216	1			T3	2		T81	2		T44	2
auto[402653184:536870911]	244	1			T3	2		T11	2		T56	2
auto[536870912:671088639]	230	1			T2	2		T3	2		T12	2
auto[671088640:805306367]	232	1			T2	2		T3	6		T11	2
auto[805306368:939524095]	204	1			T3	4		T12	2		T81	2
auto[939524096:1073741823]	222	1			T3	2		T12	2		T14	2
auto[1073741824:1207959551]	224	1			T5	6		T76	2		T42	2
auto[1207959552:1342177279]	198	1			T25	2		T5	2		T36	2
auto[1342177280:1476395007]	186	1			T3	4		T25	2		T59	2
auto[1476395008:1610612735]	188	1			T3	2		T5	2		T52	2
auto[1610612736:1744830463]	194	1			T3	2		T11	2		T28	2
auto[1744830464:1879048191]	228	1			T3	2		T81	2		T24	2
auto[1879048192:2013265919]	200	1			T3	2		T5	6		T35	2
auto[2013265920:2147483647]	230	1			T3	4		T124	2		T59	4
auto[2147483648:2281701375]	212	1			T15	2		T5	2		T77	2
auto[2281701376:2415919103]	200	1			T3	2		T15	2		T115	2
auto[2415919104:2550136831]	188	1			T3	2		T123	4		T5	8
auto[2550136832:2684354559]	158	1			T3	4		T123	2		T124	2
auto[2684354560:2818572287]	194	1			T3	2		T24	2		T25	2
auto[2818572288:2952790015]	230	1			T24	2		T115	2		T28	2
auto[2952790016:3087007743]	170	1			T81	4		T44	2		T59	4
auto[3087007744:3221225471]	178	1			T123	2		T115	2		T126	2
auto[3221225472:3355443199]	230	1			T3	2		T24	2		T115	2
auto[3355443200:3489660927]	204	1			T3	4		T81	2		T5	4
auto[3489660928:3623878655]	258	1			T3	2		T197	2		T116	2
auto[3623878656:3758096383]	194	1			T3	2		T44	2		T77	2
auto[3758096384:3892314111]	230	1			T2	2		T3	2		T115	2
auto[3892314112:4026531839]	218	1			T3	2		T5	6		T116	2
auto[4026531840:4160749567]	240	1			T2	2		T3	2		T11	2
auto[4160749568:4294967295]	272	1			T3	6		T14	2		T81	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	134	1			T3	4		T11	2		T116	2
auto[0:134217727]	auto[1]	60	1			T3	2		T239	2		T208	2
auto[134217728:268435455]	auto[0]	146	1			T129	2		T340	2		T61	2
auto[134217728:268435455]	auto[1]	68	1			T3	2		T59	2		T78	2
auto[268435456:402653183]	auto[0]	134	1			T3	2		T81	2		T5	4
auto[268435456:402653183]	auto[1]	82	1			T44	2		T50	2		T190	2
auto[402653184:536870911]	auto[0]	154	1			T3	2		T11	2		T50	2
auto[402653184:536870911]	auto[1]	90	1			T56	2		T52	2		T208	2
auto[536870912:671088639]	auto[0]	150	1			T2	2		T12	2		T79	2
auto[536870912:671088639]	auto[1]	80	1			T3	2		T36	2		T46	2
auto[671088640:805306367]	auto[0]	150	1			T3	4		T11	2		T81	2
auto[671088640:805306367]	auto[1]	82	1			T2	2		T3	2		T15	2
auto[805306368:939524095]	auto[0]	138	1			T3	2		T12	2		T116	2
auto[805306368:939524095]	auto[1]	66	1			T3	2		T81	2		T5	2
auto[939524096:1073741823]	auto[0]	156	1			T12	2		T15	2		T5	4
auto[939524096:1073741823]	auto[1]	66	1			T3	2		T14	2		T56	2
auto[1073741824:1207959551]	auto[0]	152	1			T5	2		T76	2		T196	2
auto[1073741824:1207959551]	auto[1]	72	1			T5	4		T42	2		T6	2
auto[1207959552:1342177279]	auto[0]	144	1			T25	2		T5	2		T36	2
auto[1207959552:1342177279]	auto[1]	54	1			T6	2		T62	2		T264	2
auto[1342177280:1476395007]	auto[0]	124	1			T3	2		T25	2		T59	2
auto[1342177280:1476395007]	auto[1]	62	1			T3	2		T76	2		T58	2
auto[1476395008:1610612735]	auto[0]	124	1			T3	2		T5	2		T340	2
auto[1476395008:1610612735]	auto[1]	64	1			T52	2		T263	2		T233	2
auto[1610612736:1744830463]	auto[0]	126	1			T3	2		T28	2		T129	2
auto[1610612736:1744830463]	auto[1]	68	1			T11	2		T5	2		T50	2
auto[1744830464:1879048191]	auto[0]	156	1			T3	2		T24	2		T44	2
auto[1744830464:1879048191]	auto[1]	72	1			T81	2		T52	2		T62	2
auto[1879048192:2013265919]	auto[0]	132	1			T3	2		T5	6		T35	2
auto[1879048192:2013265919]	auto[1]	68	1			T56	6		T290	2		T398	2
auto[2013265920:2147483647]	auto[0]	150	1			T3	2		T124	2		T59	2
auto[2013265920:2147483647]	auto[1]	80	1			T3	2		T59	2		T77	2
auto[2147483648:2281701375]	auto[0]	146	1			T15	2		T5	2		T77	2
auto[2147483648:2281701375]	auto[1]	66	1			T42	2		T120	2		T312	2
auto[2281701376:2415919103]	auto[0]	124	1			T15	2		T126	2		T5	2
auto[2281701376:2415919103]	auto[1]	76	1			T3	2		T115	2		T42	2
auto[2415919104:2550136831]	auto[0]	114	1			T3	2		T123	4		T5	6
auto[2415919104:2550136831]	auto[1]	74	1			T5	2		T59	2		T42	2
auto[2550136832:2684354559]	auto[0]	108	1			T3	2		T46	4		T43	2
auto[2550136832:2684354559]	auto[1]	50	1			T3	2		T123	2		T124	2
auto[2684354560:2818572287]	auto[0]	134	1			T3	2		T24	2		T25	2
auto[2684354560:2818572287]	auto[1]	60	1			T5	2		T59	2		T80	2
auto[2818572288:2952790015]	auto[0]	152	1			T24	2		T28	2		T5	2
auto[2818572288:2952790015]	auto[1]	78	1			T115	2		T5	2		T49	2
auto[2952790016:3087007743]	auto[0]	100	1			T81	4		T59	4		T35	2
auto[2952790016:3087007743]	auto[1]	70	1			T44	2		T77	2		T78	2
auto[3087007744:3221225471]	auto[0]	120	1			T123	2		T50	4		T234	2
auto[3087007744:3221225471]	auto[1]	58	1			T115	2		T126	2		T50	2
auto[3221225472:3355443199]	auto[0]	136	1			T24	2		T56	4		T36	2
auto[3221225472:3355443199]	auto[1]	94	1			T3	2		T115	2		T5	2
auto[3355443200:3489660927]	auto[0]	128	1			T3	2		T81	2		T5	4
auto[3355443200:3489660927]	auto[1]	76	1			T3	2		T42	2		T236	2
auto[3489660928:3623878655]	auto[0]	180	1			T3	2		T116	2		T76	2
auto[3489660928:3623878655]	auto[1]	78	1			T197	2		T56	2		T42	2
auto[3623878656:3758096383]	auto[0]	128	1			T3	2		T44	2		T77	2
auto[3623878656:3758096383]	auto[1]	66	1			T61	2		T17	2		T67	2
auto[3758096384:3892314111]	auto[0]	154	1			T2	2		T5	2		T76	2
auto[3758096384:3892314111]	auto[1]	76	1			T3	2		T115	2		T50	2
auto[3892314112:4026531839]	auto[0]	158	1			T3	2		T5	6		T59	2
auto[3892314112:4026531839]	auto[1]	60	1			T116	2		T36	2		T131	2
auto[4026531840:4160749567]	auto[0]	174	1			T3	2		T11	2		T25	2
auto[4026531840:4160749567]	auto[1]	66	1			T2	2		T181	2		T37	2
auto[4160749568:4294967295]	auto[0]	182	1			T3	6		T24	2		T5	4
auto[4160749568:4294967295]	auto[1]	90	1			T14	2		T81	4		T126	2