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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 99.00 98.07 98.65 97.67 98.93 98.41 91.22


Total test records in report: 1085
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1009 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.892768523 Jul 02 07:52:55 AM PDT 24 Jul 02 07:53:09 AM PDT 24 267849192 ps
T1010 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.652745641 Jul 02 07:52:53 AM PDT 24 Jul 02 07:53:00 AM PDT 24 72635254 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2601518577 Jul 02 07:52:52 AM PDT 24 Jul 02 07:53:06 AM PDT 24 511684996 ps
T1012 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4070570012 Jul 02 07:53:13 AM PDT 24 Jul 02 07:53:17 AM PDT 24 12317558 ps
T1013 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3579910562 Jul 02 07:53:22 AM PDT 24 Jul 02 07:53:26 AM PDT 24 10667825 ps
T1014 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1967922927 Jul 02 07:53:14 AM PDT 24 Jul 02 07:53:29 AM PDT 24 1387689002 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1893737141 Jul 02 07:52:42 AM PDT 24 Jul 02 07:52:54 AM PDT 24 112339240 ps
T1016 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2522061419 Jul 02 07:52:59 AM PDT 24 Jul 02 07:53:06 AM PDT 24 496365584 ps
T1017 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2971731631 Jul 02 07:52:53 AM PDT 24 Jul 02 07:52:59 AM PDT 24 45416060 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.270535497 Jul 02 07:52:49 AM PDT 24 Jul 02 07:52:59 AM PDT 24 58137563 ps
T1019 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1742080245 Jul 02 07:53:08 AM PDT 24 Jul 02 07:53:15 AM PDT 24 144391415 ps
T168 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2067288253 Jul 02 07:53:00 AM PDT 24 Jul 02 07:53:07 AM PDT 24 111845370 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3078275087 Jul 02 07:52:49 AM PDT 24 Jul 02 07:52:57 AM PDT 24 125664344 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1261989447 Jul 02 07:52:57 AM PDT 24 Jul 02 07:53:05 AM PDT 24 46268423 ps
T1022 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2262580541 Jul 02 07:53:51 AM PDT 24 Jul 02 07:53:56 AM PDT 24 35111386 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2934024517 Jul 02 07:53:09 AM PDT 24 Jul 02 07:53:15 AM PDT 24 486159411 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1352789179 Jul 02 07:53:04 AM PDT 24 Jul 02 07:53:10 AM PDT 24 38312334 ps
T1025 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.148831229 Jul 02 07:53:18 AM PDT 24 Jul 02 07:53:26 AM PDT 24 368017889 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2086051478 Jul 02 07:53:01 AM PDT 24 Jul 02 07:53:07 AM PDT 24 103712352 ps
T1027 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4060966500 Jul 02 07:53:12 AM PDT 24 Jul 02 07:53:17 AM PDT 24 36539710 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3083279402 Jul 02 07:53:12 AM PDT 24 Jul 02 07:53:17 AM PDT 24 75475829 ps
T1029 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2708941124 Jul 02 07:52:59 AM PDT 24 Jul 02 07:53:06 AM PDT 24 300733629 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.74581299 Jul 02 07:53:00 AM PDT 24 Jul 02 07:53:05 AM PDT 24 42361202 ps
T1031 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.593725542 Jul 02 07:52:58 AM PDT 24 Jul 02 07:53:06 AM PDT 24 85323363 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.142856781 Jul 02 07:52:52 AM PDT 24 Jul 02 07:53:01 AM PDT 24 90201668 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.576727945 Jul 02 07:53:20 AM PDT 24 Jul 02 07:53:26 AM PDT 24 337245116 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.715347005 Jul 02 07:52:59 AM PDT 24 Jul 02 07:53:15 AM PDT 24 338651792 ps
T1035 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1121445543 Jul 02 07:53:06 AM PDT 24 Jul 02 07:53:11 AM PDT 24 37638764 ps
T1036 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.883734111 Jul 02 07:53:15 AM PDT 24 Jul 02 07:53:18 AM PDT 24 102747191 ps
T1037 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.140504839 Jul 02 07:52:58 AM PDT 24 Jul 02 07:53:17 AM PDT 24 255323672 ps
T1038 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1881558229 Jul 02 07:53:20 AM PDT 24 Jul 02 07:53:23 AM PDT 24 39990004 ps
T1039 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4148723606 Jul 02 07:53:19 AM PDT 24 Jul 02 07:53:21 AM PDT 24 54657123 ps
T1040 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1808249296 Jul 02 07:52:58 AM PDT 24 Jul 02 07:53:04 AM PDT 24 144047905 ps
T1041 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3370436387 Jul 02 07:52:59 AM PDT 24 Jul 02 07:53:09 AM PDT 24 143633350 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2077329255 Jul 02 07:52:54 AM PDT 24 Jul 02 07:53:00 AM PDT 24 56089987 ps
T1043 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.892161416 Jul 02 07:53:08 AM PDT 24 Jul 02 07:53:14 AM PDT 24 134849349 ps
T1044 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3085014393 Jul 02 07:53:10 AM PDT 24 Jul 02 07:53:21 AM PDT 24 1020464787 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4122211358 Jul 02 07:52:51 AM PDT 24 Jul 02 07:53:00 AM PDT 24 86449684 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1306426211 Jul 02 07:52:54 AM PDT 24 Jul 02 07:53:00 AM PDT 24 23184564 ps
T1047 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3935557110 Jul 02 07:52:51 AM PDT 24 Jul 02 07:52:59 AM PDT 24 240994462 ps
T154 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3837039205 Jul 02 07:52:55 AM PDT 24 Jul 02 07:53:05 AM PDT 24 351440823 ps
T164 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.173769589 Jul 02 07:52:52 AM PDT 24 Jul 02 07:53:06 AM PDT 24 796907959 ps
T1048 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2873791163 Jul 02 07:53:17 AM PDT 24 Jul 02 07:53:22 AM PDT 24 190420506 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4198710217 Jul 02 07:52:59 AM PDT 24 Jul 02 07:53:06 AM PDT 24 38271746 ps
T1050 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4126028482 Jul 02 07:53:51 AM PDT 24 Jul 02 07:53:58 AM PDT 24 26015700 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.798144085 Jul 02 07:52:53 AM PDT 24 Jul 02 07:53:00 AM PDT 24 12531554 ps
T1052 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4004341844 Jul 02 07:53:18 AM PDT 24 Jul 02 07:53:20 AM PDT 24 37192049 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.845676807 Jul 02 07:52:54 AM PDT 24 Jul 02 07:53:00 AM PDT 24 13560363 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.107834523 Jul 02 07:53:02 AM PDT 24 Jul 02 07:53:11 AM PDT 24 323777432 ps
T1055 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3056199995 Jul 02 07:53:04 AM PDT 24 Jul 02 07:53:15 AM PDT 24 317869980 ps
T1056 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4103581055 Jul 02 07:53:12 AM PDT 24 Jul 02 07:53:20 AM PDT 24 79903834 ps
T156 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3810554963 Jul 02 07:53:07 AM PDT 24 Jul 02 07:53:17 AM PDT 24 1045523186 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2930748874 Jul 02 07:53:05 AM PDT 24 Jul 02 07:53:11 AM PDT 24 77220882 ps
T1058 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1301958071 Jul 02 07:53:14 AM PDT 24 Jul 02 07:53:17 AM PDT 24 16630824 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.876366037 Jul 02 07:53:03 AM PDT 24 Jul 02 07:53:09 AM PDT 24 30766738 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1640373175 Jul 02 07:53:04 AM PDT 24 Jul 02 07:53:09 AM PDT 24 16416915 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3335601868 Jul 02 07:53:02 AM PDT 24 Jul 02 07:53:07 AM PDT 24 54730393 ps
T160 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1161686535 Jul 02 07:53:06 AM PDT 24 Jul 02 07:53:14 AM PDT 24 826038166 ps
T1062 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3779677963 Jul 02 07:53:46 AM PDT 24 Jul 02 07:53:49 AM PDT 24 17001603 ps
T1063 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3257948275 Jul 02 07:53:05 AM PDT 24 Jul 02 07:53:18 AM PDT 24 467483829 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1801989461 Jul 02 07:52:56 AM PDT 24 Jul 02 07:53:02 AM PDT 24 95676796 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2148115996 Jul 02 07:52:48 AM PDT 24 Jul 02 07:52:58 AM PDT 24 45549705 ps
T1066 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3294736042 Jul 02 07:53:03 AM PDT 24 Jul 02 07:53:08 AM PDT 24 14763021 ps
T1067 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.107582759 Jul 02 07:53:10 AM PDT 24 Jul 02 07:53:15 AM PDT 24 46356425 ps
T1068 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1148271846 Jul 02 07:53:15 AM PDT 24 Jul 02 07:53:18 AM PDT 24 14742422 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.361218110 Jul 02 07:53:02 AM PDT 24 Jul 02 07:53:09 AM PDT 24 91367514 ps
T167 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2850088979 Jul 02 07:52:52 AM PDT 24 Jul 02 07:53:04 AM PDT 24 707748820 ps
T1070 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.89300236 Jul 02 07:53:04 AM PDT 24 Jul 02 07:53:16 AM PDT 24 1021404892 ps
T1071 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2322886742 Jul 02 07:52:56 AM PDT 24 Jul 02 07:53:01 AM PDT 24 18508243 ps
T1072 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2525643178 Jul 02 07:53:21 AM PDT 24 Jul 02 07:53:26 AM PDT 24 46191160 ps
T1073 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2762339883 Jul 02 07:53:10 AM PDT 24 Jul 02 07:53:22 AM PDT 24 387818048 ps
T1074 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3582624587 Jul 02 07:53:21 AM PDT 24 Jul 02 07:53:26 AM PDT 24 11547669 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2964684662 Jul 02 07:52:51 AM PDT 24 Jul 02 07:53:12 AM PDT 24 1382367300 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4158541040 Jul 02 07:52:43 AM PDT 24 Jul 02 07:53:04 AM PDT 24 424673600 ps
T1077 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.156620755 Jul 02 07:53:17 AM PDT 24 Jul 02 07:53:26 AM PDT 24 50587853 ps
T1078 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1058289868 Jul 02 07:52:51 AM PDT 24 Jul 02 07:52:59 AM PDT 24 149733711 ps
T1079 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.899290767 Jul 02 07:53:03 AM PDT 24 Jul 02 07:53:08 AM PDT 24 36533128 ps
T165 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1170832027 Jul 02 07:53:09 AM PDT 24 Jul 02 07:53:15 AM PDT 24 110044742 ps
T1080 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3555978537 Jul 02 07:53:10 AM PDT 24 Jul 02 07:53:15 AM PDT 24 15679198 ps
T161 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2240023485 Jul 02 07:53:13 AM PDT 24 Jul 02 07:53:23 AM PDT 24 957061066 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3336382527 Jul 02 07:53:16 AM PDT 24 Jul 02 07:53:20 AM PDT 24 148825514 ps
T1082 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.141086783 Jul 02 07:53:03 AM PDT 24 Jul 02 07:53:08 AM PDT 24 10172965 ps
T1083 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.784123261 Jul 02 07:53:55 AM PDT 24 Jul 02 07:54:03 AM PDT 24 29835429 ps
T1084 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1908636091 Jul 02 07:52:45 AM PDT 24 Jul 02 07:52:56 AM PDT 24 25125322 ps
T1085 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2139338663 Jul 02 07:53:10 AM PDT 24 Jul 02 07:53:15 AM PDT 24 101022133 ps

Test location /workspace/coverage/default/47.keymgr_stress_all.3659979591
Short name T3
Test name
Test status
Simulation time 44278113789 ps
CPU time 507.85 seconds
Started Jul 02 07:58:14 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 222300 kb
Host smart-e8380755-03d3-486e-8c7d-38d491992226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659979591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3659979591
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1648175971
Short name T5
Test name
Test status
Simulation time 1312575303 ps
CPU time 25.97 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:50 AM PDT 24
Peak memory 220752 kb
Host smart-eb833e29-7f80-41b3-9b65-3faf25b9eaae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648175971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1648175971
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.88456242
Short name T59
Test name
Test status
Simulation time 1765862570 ps
CPU time 14.93 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 222604 kb
Host smart-60dae1c9-a6c8-45b1-a93c-ff465c6ab555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88456242 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.88456242
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1652922241
Short name T47
Test name
Test status
Simulation time 237704819 ps
CPU time 9.66 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 222600 kb
Host smart-b22680d4-4ff0-40ec-a51b-4ad613cf99c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652922241 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1652922241
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2309752101
Short name T10
Test name
Test status
Simulation time 1455352476 ps
CPU time 12.72 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 240152 kb
Host smart-06363996-80cc-4c77-9911-735edbd6de26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309752101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2309752101
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4262010602
Short name T58
Test name
Test status
Simulation time 4279429378 ps
CPU time 33.82 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 222528 kb
Host smart-cd07eedb-1d8b-4f93-994f-af7555cdf9d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262010602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4262010602
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.383597422
Short name T115
Test name
Test status
Simulation time 1704140679 ps
CPU time 42.91 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:58 AM PDT 24
Peak memory 214520 kb
Host smart-aff4a1f5-b8d1-403d-9cb0-44688659733d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383597422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.383597422
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.201668521
Short name T111
Test name
Test status
Simulation time 1046777192 ps
CPU time 6.16 seconds
Started Jul 02 07:52:46 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 220076 kb
Host smart-40255f13-422e-41a2-ba7f-5f7f673a390c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201668521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.201668521
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.247488159
Short name T122
Test name
Test status
Simulation time 659995627 ps
CPU time 21.18 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 222520 kb
Host smart-2148eb00-213f-428e-a780-f8346f3f5795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247488159 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.247488159
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.809679723
Short name T116
Test name
Test status
Simulation time 129246731 ps
CPU time 5.17 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 214288 kb
Host smart-96c7c5e0-1fa8-4090-ae0f-186618d6fd95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809679723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.809679723
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4127477314
Short name T50
Test name
Test status
Simulation time 3012402103 ps
CPU time 21.76 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 222388 kb
Host smart-db6eaef5-58cf-4d73-b5e4-96efd5281227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127477314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4127477314
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4284723790
Short name T4
Test name
Test status
Simulation time 108711793 ps
CPU time 2.5 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 210112 kb
Host smart-617d6313-8abc-4602-a147-ed294fcbf9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284723790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4284723790
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2567267692
Short name T17
Test name
Test status
Simulation time 177078894 ps
CPU time 3.87 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 217552 kb
Host smart-ca026291-0595-4c02-b4a8-02893121386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567267692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2567267692
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1022267909
Short name T77
Test name
Test status
Simulation time 558140748 ps
CPU time 14.74 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 215292 kb
Host smart-8395734e-09d7-4b86-851e-86faec850ebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022267909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1022267909
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4078288624
Short name T21
Test name
Test status
Simulation time 81855978 ps
CPU time 4.06 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 209384 kb
Host smart-111288ec-a2a1-47c2-a04a-2ca81374ab16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078288624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4078288624
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1597224512
Short name T129
Test name
Test status
Simulation time 2288609520 ps
CPU time 13 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:42 AM PDT 24
Peak memory 214740 kb
Host smart-84bc80a1-6b7d-4235-ac1a-95af2d7ca9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597224512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1597224512
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.262661913
Short name T72
Test name
Test status
Simulation time 2662939158 ps
CPU time 81.6 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 215940 kb
Host smart-9b607fc2-9a1d-42fc-8031-32e29c386637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262661913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.262661913
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.613019282
Short name T130
Test name
Test status
Simulation time 7272194640 ps
CPU time 98.69 seconds
Started Jul 02 07:56:47 AM PDT 24
Finished Jul 02 07:58:40 AM PDT 24
Peak memory 215420 kb
Host smart-3ae74930-f2dc-4c7a-b08d-3dccff1bba33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613019282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.613019282
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3298985517
Short name T2
Test name
Test status
Simulation time 1540329924 ps
CPU time 43.07 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 222416 kb
Host smart-b49bd4ff-e59d-436a-a44b-bc305ec02243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298985517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3298985517
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1528596327
Short name T336
Test name
Test status
Simulation time 165964749 ps
CPU time 9.12 seconds
Started Jul 02 07:57:19 AM PDT 24
Finished Jul 02 07:57:43 AM PDT 24
Peak memory 214304 kb
Host smart-36c09b5c-9445-41a0-9320-5f499c5492bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528596327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1528596327
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.588815831
Short name T18
Test name
Test status
Simulation time 423949138 ps
CPU time 8.11 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 214292 kb
Host smart-bc90b6c6-812c-49ee-b180-75023eb285b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588815831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.588815831
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2645098548
Short name T82
Test name
Test status
Simulation time 61898344 ps
CPU time 2.1 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 214308 kb
Host smart-32cc8846-138f-4a54-9008-aaf9b3f07041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645098548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2645098548
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3116036397
Short name T142
Test name
Test status
Simulation time 85871891 ps
CPU time 2.57 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 222664 kb
Host smart-127e40f4-0b93-4c7c-8d86-7295ef330b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116036397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3116036397
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2019707149
Short name T315
Test name
Test status
Simulation time 238442540 ps
CPU time 4.22 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 215236 kb
Host smart-a0e0e8e4-dc41-485b-8479-055c9f134f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019707149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2019707149
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.676214419
Short name T39
Test name
Test status
Simulation time 231839470 ps
CPU time 3.05 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:38 AM PDT 24
Peak memory 214196 kb
Host smart-6ef8b761-6178-4982-b7cd-2fc269710034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676214419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.676214419
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2727039276
Short name T42
Test name
Test status
Simulation time 512741006 ps
CPU time 13.37 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:39 AM PDT 24
Peak memory 222536 kb
Host smart-d73a65bd-3686-4705-a04b-798fa0cef4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727039276 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2727039276
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.794755097
Short name T225
Test name
Test status
Simulation time 346521739 ps
CPU time 5.38 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 214408 kb
Host smart-8dae9a08-0fc9-49b9-943a-64b7f13134a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794755097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.794755097
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3992069004
Short name T114
Test name
Test status
Simulation time 555734388 ps
CPU time 11.49 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:53:02 AM PDT 24
Peak memory 213988 kb
Host smart-3502e766-cb6b-4783-ac3a-73bae3a5b284
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992069004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3992069004
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3768622232
Short name T184
Test name
Test status
Simulation time 6541313009 ps
CPU time 61.51 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 222660 kb
Host smart-3349df54-bf14-446f-beaf-bc40b8db92dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768622232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3768622232
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.71896904
Short name T241
Test name
Test status
Simulation time 1419736350 ps
CPU time 14.54 seconds
Started Jul 02 07:56:15 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 215312 kb
Host smart-d52be754-7623-4cec-87b7-8de11bf7689f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71896904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.71896904
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1174408816
Short name T417
Test name
Test status
Simulation time 39138876 ps
CPU time 0.94 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 206016 kb
Host smart-13ac0686-17b5-43fe-8f1c-5654f9e3ae10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174408816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1174408816
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3810554963
Short name T156
Test name
Test status
Simulation time 1045523186 ps
CPU time 6.99 seconds
Started Jul 02 07:53:07 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 213640 kb
Host smart-d8e5b186-b8db-43e2-8406-ae43a0a8661a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810554963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3810554963
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.592816529
Short name T56
Test name
Test status
Simulation time 320206765 ps
CPU time 16.78 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:32 AM PDT 24
Peak memory 222656 kb
Host smart-532ce7bc-8d08-43c8-8633-c55dc5349919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592816529 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.592816529
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1672364782
Short name T396
Test name
Test status
Simulation time 617955120 ps
CPU time 8.33 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:57:23 AM PDT 24
Peak memory 214344 kb
Host smart-67757c76-33a3-45b8-b776-2239f383a3a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672364782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1672364782
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.126267529
Short name T52
Test name
Test status
Simulation time 1523660151 ps
CPU time 4.23 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 214120 kb
Host smart-5c6bdcd1-d9f2-4576-8e52-eed9bf36765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126267529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.126267529
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.438812621
Short name T12
Test name
Test status
Simulation time 59293449 ps
CPU time 2.89 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 210544 kb
Host smart-97f53aeb-529f-4dfa-9d33-76c05cda11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438812621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.438812621
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.232939611
Short name T162
Test name
Test status
Simulation time 174928124 ps
CPU time 2.4 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 210272 kb
Host smart-20b0d744-3add-4826-b067-6fab9325dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232939611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.232939611
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.245067594
Short name T833
Test name
Test status
Simulation time 432798051 ps
CPU time 6.05 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 222272 kb
Host smart-9904bf94-1c04-464a-a04b-68d0601c509a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245067594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.245067594
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3032297149
Short name T247
Test name
Test status
Simulation time 2455584472 ps
CPU time 45.43 seconds
Started Jul 02 07:57:17 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 222544 kb
Host smart-c91a11a2-7edd-47c2-98e5-d458f352b484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032297149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3032297149
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2463418691
Short name T153
Test name
Test status
Simulation time 473295711 ps
CPU time 5.85 seconds
Started Jul 02 07:52:50 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 214820 kb
Host smart-fe360064-5da5-407c-af76-ff9a2f44edd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463418691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2463418691
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4036898408
Short name T289
Test name
Test status
Simulation time 1156010528 ps
CPU time 42.48 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 215820 kb
Host smart-03275897-89ab-408b-8b28-453a94e05e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036898408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4036898408
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1892715850
Short name T185
Test name
Test status
Simulation time 5456053366 ps
CPU time 35.02 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:59:03 AM PDT 24
Peak memory 217064 kb
Host smart-3a58ddeb-f1b9-4740-9a1a-64acbd2bfc06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892715850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1892715850
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1161686535
Short name T160
Test name
Test status
Simulation time 826038166 ps
CPU time 4.33 seconds
Started Jul 02 07:53:06 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 213580 kb
Host smart-51b78c75-5f57-491d-a709-ed32afbb465c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161686535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1161686535
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4228750378
Short name T148
Test name
Test status
Simulation time 49066690 ps
CPU time 2.16 seconds
Started Jul 02 07:56:07 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 218092 kb
Host smart-f7f2901e-525d-4c11-ba47-8d646389ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228750378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4228750378
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2725498300
Short name T143
Test name
Test status
Simulation time 664763157 ps
CPU time 2.69 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 218112 kb
Host smart-4f7807bb-f153-4de6-948b-aca07f9c695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725498300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2725498300
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2796475819
Short name T28
Test name
Test status
Simulation time 430766478 ps
CPU time 4.19 seconds
Started Jul 02 07:57:06 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 209856 kb
Host smart-6c1fa42a-d335-41d7-9964-fb7f993b93fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796475819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2796475819
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1576316868
Short name T261
Test name
Test status
Simulation time 27705651 ps
CPU time 1.75 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 214216 kb
Host smart-bbc68b20-85e5-4c99-a64f-7e136368c722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576316868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1576316868
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2412340720
Short name T720
Test name
Test status
Simulation time 291672356 ps
CPU time 4.06 seconds
Started Jul 02 07:57:24 AM PDT 24
Finished Jul 02 07:57:43 AM PDT 24
Peak memory 221392 kb
Host smart-6ab94628-aa0b-4e17-a109-cd7d97175459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412340720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2412340720
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.948953555
Short name T155
Test name
Test status
Simulation time 147384453 ps
CPU time 5.55 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:30 AM PDT 24
Peak memory 205448 kb
Host smart-fffe381f-fa58-4f40-8683-a663feccfe7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948953555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.948953555
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2370959126
Short name T140
Test name
Test status
Simulation time 134724572 ps
CPU time 4.03 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:23 AM PDT 24
Peak memory 222676 kb
Host smart-4944258c-b800-45be-9007-63d1955199ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370959126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2370959126
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3971580035
Short name T145
Test name
Test status
Simulation time 42118784 ps
CPU time 2.82 seconds
Started Jul 02 07:57:28 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 222544 kb
Host smart-1b0495a6-7b3a-431b-942f-d6a138fae15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971580035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3971580035
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2758790799
Short name T883
Test name
Test status
Simulation time 175577286 ps
CPU time 8.71 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 215356 kb
Host smart-8175b03a-0439-4226-95fa-eb5dd9fc65c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758790799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2758790799
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2538029127
Short name T63
Test name
Test status
Simulation time 372154250 ps
CPU time 3.2 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:56:57 AM PDT 24
Peak memory 207820 kb
Host smart-2dddee07-2c9e-4856-90d8-a07909bb8801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538029127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2538029127
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1731331924
Short name T324
Test name
Test status
Simulation time 43618947 ps
CPU time 2.1 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 222388 kb
Host smart-6e421817-3ba1-420b-bff4-fae055af8b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731331924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1731331924
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.55912571
Short name T259
Test name
Test status
Simulation time 176370573 ps
CPU time 2.73 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 222280 kb
Host smart-ad914052-7968-4b98-a081-45ff3faaf863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55912571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.55912571
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.173769589
Short name T164
Test name
Test status
Simulation time 796907959 ps
CPU time 8.34 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 205396 kb
Host smart-c69c7b75-1d83-4c81-9311-91190ba4b91a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173769589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
173769589
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.862292416
Short name T14
Test name
Test status
Simulation time 299914619 ps
CPU time 3.6 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 222588 kb
Host smart-b7a9876a-6a71-469e-b6b0-99c91c2abe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862292416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.862292416
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2409856736
Short name T291
Test name
Test status
Simulation time 1888260837 ps
CPU time 17.53 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 216536 kb
Host smart-121a3249-45fb-47ec-86e9-05f2fef5d8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409856736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2409856736
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1707741129
Short name T224
Test name
Test status
Simulation time 53919418 ps
CPU time 3.38 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 214192 kb
Host smart-2a163d8e-2ae3-4a5e-804e-91fd5b638ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707741129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1707741129
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.866351498
Short name T218
Test name
Test status
Simulation time 684133672 ps
CPU time 28.04 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 216492 kb
Host smart-63d098fc-66cc-48ed-9416-a169a0b982a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866351498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.866351498
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.661515634
Short name T200
Test name
Test status
Simulation time 106447425 ps
CPU time 3.47 seconds
Started Jul 02 07:57:28 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 214220 kb
Host smart-c943da13-285b-4140-875d-fbac24f7dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661515634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.661515634
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_random.2537883576
Short name T15
Test name
Test status
Simulation time 471290708 ps
CPU time 7.3 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:45 AM PDT 24
Peak memory 214324 kb
Host smart-59b17800-f8b0-4ba0-b69c-7b95cf496202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537883576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2537883576
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2606694593
Short name T149
Test name
Test status
Simulation time 142793438 ps
CPU time 3.97 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 218572 kb
Host smart-8a52b268-869c-4537-ba9b-ee8605bfb8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606694593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2606694593
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.157189195
Short name T93
Test name
Test status
Simulation time 91827891 ps
CPU time 2.44 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 220892 kb
Host smart-bd09bbb1-aedc-432e-9259-6a3fa828bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157189195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.157189195
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2700263304
Short name T316
Test name
Test status
Simulation time 1431495095 ps
CPU time 20.55 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 215584 kb
Host smart-c0ed96fd-465c-4f6c-89f8-e3ea5ef5d650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700263304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2700263304
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1324812969
Short name T321
Test name
Test status
Simulation time 155437067 ps
CPU time 3.54 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 222396 kb
Host smart-5a9d8599-ff82-44e4-96bc-63d1862ab3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324812969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1324812969
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.834625060
Short name T723
Test name
Test status
Simulation time 77400390 ps
CPU time 3.85 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 222324 kb
Host smart-29590c15-e8e5-47bc-a258-eb4446307583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834625060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.834625060
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3320751063
Short name T405
Test name
Test status
Simulation time 130871828 ps
CPU time 7.26 seconds
Started Jul 02 07:57:28 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 214232 kb
Host smart-4131cc4e-3072-4465-be9e-19d468cbaa19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320751063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3320751063
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2023971687
Short name T191
Test name
Test status
Simulation time 2392513780 ps
CPU time 4.69 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:24 AM PDT 24
Peak memory 208168 kb
Host smart-676fca9c-a228-4557-83cf-7a46f014a29a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023971687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2023971687
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2522528917
Short name T310
Test name
Test status
Simulation time 3627090044 ps
CPU time 60.38 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 221492 kb
Host smart-2cd19c26-2089-4c2d-bea5-d1886a5b9aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522528917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2522528917
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1738699614
Short name T299
Test name
Test status
Simulation time 11974450958 ps
CPU time 46.87 seconds
Started Jul 02 07:57:04 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 217032 kb
Host smart-01ebe25f-756f-429f-b04c-0896bcaea794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738699614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1738699614
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.901041547
Short name T219
Test name
Test status
Simulation time 3471793646 ps
CPU time 30.37 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 214948 kb
Host smart-bde20e5b-7421-466d-9934-8a3cff15e73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901041547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.901041547
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3278462003
Short name T221
Test name
Test status
Simulation time 863472770 ps
CPU time 11.74 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:59 AM PDT 24
Peak memory 215536 kb
Host smart-c61df0e3-54df-4ef5-b079-dee7b9601c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278462003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3278462003
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2723065004
Short name T204
Test name
Test status
Simulation time 671822517 ps
CPU time 32.24 seconds
Started Jul 02 07:58:07 AM PDT 24
Finished Jul 02 07:59:02 AM PDT 24
Peak memory 220976 kb
Host smart-5498e9b9-8be2-488c-ac03-af91c566555a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723065004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2723065004
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2967834466
Short name T157
Test name
Test status
Simulation time 351549655 ps
CPU time 4.53 seconds
Started Jul 02 07:52:57 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 215068 kb
Host smart-44d4bfe0-8712-4edb-a5b1-381609ca55aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967834466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2967834466
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.660297794
Short name T158
Test name
Test status
Simulation time 340896117 ps
CPU time 4.26 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 213644 kb
Host smart-1245d55b-6f6a-4bfb-8421-09a6d18f02f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660297794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
660297794
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2067288253
Short name T168
Test name
Test status
Simulation time 111845370 ps
CPU time 3.42 seconds
Started Jul 02 07:53:00 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 205672 kb
Host smart-18e92f30-3985-46b4-ac57-4d7fe1cb20af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067288253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2067288253
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1294137506
Short name T41
Test name
Test status
Simulation time 308528795 ps
CPU time 9.67 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:40 AM PDT 24
Peak memory 230036 kb
Host smart-65a1aa83-4894-4dfb-869a-ac8b5e580f14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294137506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1294137506
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4022142286
Short name T30
Test name
Test status
Simulation time 173698984 ps
CPU time 6.04 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 219576 kb
Host smart-1bcb219e-e890-4c21-9639-b52c5af43118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022142286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4022142286
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3693636978
Short name T147
Test name
Test status
Simulation time 84299748 ps
CPU time 3.46 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 217580 kb
Host smart-acbc55f3-79d4-463f-a304-901c48ba42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693636978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3693636978
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3625130295
Short name T146
Test name
Test status
Simulation time 192889976 ps
CPU time 5.12 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 218340 kb
Host smart-87d51f73-6d83-4a8d-8fe6-0c9cbcaa6c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625130295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3625130295
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_random.1697601375
Short name T230
Test name
Test status
Simulation time 5146887701 ps
CPU time 30.47 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 218484 kb
Host smart-bf9b0b01-958b-44cf-b225-c0b35c54e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697601375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1697601375
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3411638936
Short name T292
Test name
Test status
Simulation time 146700349 ps
CPU time 3.46 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 214420 kb
Host smart-da9bf53e-a73e-4868-83f1-2529c7f216f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411638936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3411638936
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2621911274
Short name T798
Test name
Test status
Simulation time 92340746 ps
CPU time 4.2 seconds
Started Jul 02 07:56:26 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 222404 kb
Host smart-4d441ece-a01d-4a4e-8e5d-b1f856f415c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621911274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2621911274
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2253671689
Short name T532
Test name
Test status
Simulation time 523763350 ps
CPU time 5.66 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 210964 kb
Host smart-6a3a42d6-8b42-4fb3-b4b7-46b586fe37c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253671689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2253671689
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.223709152
Short name T339
Test name
Test status
Simulation time 566272923 ps
CPU time 2.81 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 208612 kb
Host smart-140c73f7-4d7b-468b-845c-9f07671a59fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223709152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.223709152
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2785463829
Short name T354
Test name
Test status
Simulation time 74459226 ps
CPU time 1.75 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:54 AM PDT 24
Peak memory 207144 kb
Host smart-ccc0bb07-ca7a-4094-b9bd-3fa5168af807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785463829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2785463829
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.519804080
Short name T606
Test name
Test status
Simulation time 157940839 ps
CPU time 3.92 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 217100 kb
Host smart-52c5d850-a793-4663-8cda-f5a8622404c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519804080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.519804080
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1154326751
Short name T302
Test name
Test status
Simulation time 1098254512 ps
CPU time 34.9 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 222440 kb
Host smart-704b9c5b-9713-4e0c-8673-924f251d2e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154326751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1154326751
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2023962585
Short name T258
Test name
Test status
Simulation time 123658743 ps
CPU time 3.21 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 214172 kb
Host smart-e592f7e0-95c4-4f0b-8a83-7e176f865394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023962585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2023962585
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.255054742
Short name T60
Test name
Test status
Simulation time 44126003 ps
CPU time 2.88 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 219940 kb
Host smart-5709ec30-6ace-4a2a-b5d8-d3f47c872d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255054742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.255054742
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.439477104
Short name T280
Test name
Test status
Simulation time 130450419 ps
CPU time 4.95 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 215468 kb
Host smart-2b3b1092-9391-40bc-8039-34b07910ce09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439477104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.439477104
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4130510134
Short name T6
Test name
Test status
Simulation time 116696278 ps
CPU time 2.4 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 220220 kb
Host smart-446ab140-96ac-4b11-8b84-b1f0805cf7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130510134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4130510134
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2390397911
Short name T908
Test name
Test status
Simulation time 219530123 ps
CPU time 11.87 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 214192 kb
Host smart-e027321f-a85e-424c-ab78-fa05630b28e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390397911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2390397911
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1767101606
Short name T328
Test name
Test status
Simulation time 1195528980 ps
CPU time 6 seconds
Started Jul 02 07:57:36 AM PDT 24
Finished Jul 02 07:58:01 AM PDT 24
Peak memory 209684 kb
Host smart-f1e8edf0-a13c-42f7-b205-7710ba80f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767101606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1767101606
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2970361610
Short name T25
Test name
Test status
Simulation time 170865102 ps
CPU time 4.49 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 214700 kb
Host smart-33541a99-ba9f-4829-bb81-160871e99388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970361610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2970361610
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_random.1765921327
Short name T312
Test name
Test status
Simulation time 385558097 ps
CPU time 5.03 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:07 AM PDT 24
Peak memory 214216 kb
Host smart-6755c989-1c2f-4563-8298-ac51ce258107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765921327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1765921327
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.110931383
Short name T355
Test name
Test status
Simulation time 282783679 ps
CPU time 3.87 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 214228 kb
Host smart-3ef1619e-e18b-4eeb-8450-2171ee7e53c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110931383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.110931383
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3314086307
Short name T295
Test name
Test status
Simulation time 325860462 ps
CPU time 4.85 seconds
Started Jul 02 07:57:54 AM PDT 24
Finished Jul 02 07:58:21 AM PDT 24
Peak memory 214288 kb
Host smart-a1178524-326d-43d4-8fe7-e41b460b69e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314086307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3314086307
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4121695790
Short name T150
Test name
Test status
Simulation time 64463791 ps
CPU time 3.67 seconds
Started Jul 02 07:56:47 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 222708 kb
Host smart-1d6459e3-4e5f-4af0-8ec1-c99320520842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121695790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4121695790
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.104358187
Short name T144
Test name
Test status
Simulation time 527075006 ps
CPU time 4.17 seconds
Started Jul 02 07:57:23 AM PDT 24
Finished Jul 02 07:57:42 AM PDT 24
Peak memory 222652 kb
Host smart-7f1029fd-61c6-4722-ab9d-d662e0cd3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104358187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.104358187
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2385860687
Short name T141
Test name
Test status
Simulation time 320809327 ps
CPU time 3.08 seconds
Started Jul 02 07:58:15 AM PDT 24
Finished Jul 02 07:58:40 AM PDT 24
Peak memory 218640 kb
Host smart-0d8bdfd3-3658-4b12-9ded-df54b6127ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385860687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2385860687
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4158541040
Short name T1076
Test name
Test status
Simulation time 424673600 ps
CPU time 10.17 seconds
Started Jul 02 07:52:43 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205456 kb
Host smart-3ff1235a-2b46-43b7-858a-fe6ffd0933db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158541040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
158541040
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2964684662
Short name T1075
Test name
Test status
Simulation time 1382367300 ps
CPU time 14.84 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 205452 kb
Host smart-6feae7e2-ac6f-463f-9cb9-affe43bd9957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964684662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
964684662
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1057948768
Short name T932
Test name
Test status
Simulation time 73056283 ps
CPU time 0.9 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 205260 kb
Host smart-af01ddef-4377-4619-b30b-ba27e5959896
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057948768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
057948768
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1893737141
Short name T1015
Test name
Test status
Simulation time 112339240 ps
CPU time 1.5 seconds
Started Jul 02 07:52:42 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 213640 kb
Host smart-2f7a513c-c0e8-464d-8bfd-26c174018e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893737141 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1893737141
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1908636091
Short name T1084
Test name
Test status
Simulation time 25125322 ps
CPU time 1.13 seconds
Started Jul 02 07:52:45 AM PDT 24
Finished Jul 02 07:52:56 AM PDT 24
Peak memory 205472 kb
Host smart-1d28e8c1-1156-4949-8110-66c8767424c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908636091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1908636091
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3378529019
Short name T924
Test name
Test status
Simulation time 33243025 ps
CPU time 0.8 seconds
Started Jul 02 07:52:42 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 205140 kb
Host smart-1301009b-a60a-40a7-bdd3-cd42a53a9d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378529019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3378529019
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.514393758
Short name T1006
Test name
Test status
Simulation time 265627988 ps
CPU time 1.82 seconds
Started Jul 02 07:52:44 AM PDT 24
Finished Jul 02 07:52:56 AM PDT 24
Peak memory 205428 kb
Host smart-e0b8f60f-51d1-4bdb-8734-376f62ee124b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514393758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.514393758
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.142856781
Short name T1032
Test name
Test status
Simulation time 90201668 ps
CPU time 3.67 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 213808 kb
Host smart-a40ed683-1c84-4f1f-a9c8-2fac6798f160
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142856781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.142856781
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.643624699
Short name T985
Test name
Test status
Simulation time 171372648 ps
CPU time 2.54 seconds
Started Jul 02 07:52:44 AM PDT 24
Finished Jul 02 07:52:56 AM PDT 24
Peak memory 213612 kb
Host smart-fffbfdd4-9141-42f1-8b64-98d07bd99940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643624699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.643624699
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2617275985
Short name T994
Test name
Test status
Simulation time 829526780 ps
CPU time 5.05 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205428 kb
Host smart-16f300bc-f278-45f4-bd5d-7e78faa02d39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617275985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
617275985
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3380777222
Short name T1005
Test name
Test status
Simulation time 2789460078 ps
CPU time 14.78 seconds
Started Jul 02 07:52:56 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 205452 kb
Host smart-0a144226-62af-4575-8c88-1a878b4ecb5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380777222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
380777222
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.652745641
Short name T1010
Test name
Test status
Simulation time 72635254 ps
CPU time 1.45 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205376 kb
Host smart-4916a7ba-e707-4566-bd88-fd97dffdd061
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652745641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.652745641
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1058289868
Short name T1078
Test name
Test status
Simulation time 149733711 ps
CPU time 1.68 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 215876 kb
Host smart-8dff4f1f-a817-45b1-abf5-69c767a2a6a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058289868 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1058289868
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1801989461
Short name T1064
Test name
Test status
Simulation time 95676796 ps
CPU time 0.97 seconds
Started Jul 02 07:52:56 AM PDT 24
Finished Jul 02 07:53:02 AM PDT 24
Peak memory 205368 kb
Host smart-96cecba6-687e-48b3-ae5e-27ce938ac3d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801989461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1801989461
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3820695456
Short name T933
Test name
Test status
Simulation time 12940955 ps
CPU time 0.72 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 205308 kb
Host smart-ed557a4e-38c2-474a-a820-a53fc670eb36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820695456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3820695456
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4062746811
Short name T1007
Test name
Test status
Simulation time 139179790 ps
CPU time 2.41 seconds
Started Jul 02 07:52:48 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 205536 kb
Host smart-97e3535c-70be-431c-81f5-22def63944bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062746811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4062746811
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.245816853
Short name T951
Test name
Test status
Simulation time 134130202 ps
CPU time 2.45 seconds
Started Jul 02 07:52:50 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 217728 kb
Host smart-4537a400-315f-4426-845b-4dc5d79a497b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245816853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.245816853
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3076145009
Short name T961
Test name
Test status
Simulation time 96886983 ps
CPU time 3.96 seconds
Started Jul 02 07:52:42 AM PDT 24
Finished Jul 02 07:52:56 AM PDT 24
Peak memory 214028 kb
Host smart-d6546193-6075-44e8-9796-131ef871b7f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076145009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3076145009
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2201759879
Short name T989
Test name
Test status
Simulation time 60193549 ps
CPU time 2.25 seconds
Started Jul 02 07:52:45 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 213764 kb
Host smart-4bea6a5e-145e-43ad-ad86-a75343a2be28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201759879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2201759879
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2494399161
Short name T373
Test name
Test status
Simulation time 72635168 ps
CPU time 2.06 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 213664 kb
Host smart-a1130ac3-eaf7-4be5-adc7-066471bcfb16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494399161 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2494399161
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3335601868
Short name T1061
Test name
Test status
Simulation time 54730393 ps
CPU time 1.09 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 205400 kb
Host smart-ada3342c-4605-40cc-8248-a7928353aa54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335601868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3335601868
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.141086783
Short name T1082
Test name
Test status
Simulation time 10172965 ps
CPU time 0.72 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:08 AM PDT 24
Peak memory 205252 kb
Host smart-6301d732-acd2-4392-80eb-73c5301a5404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141086783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.141086783
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2930748874
Short name T1057
Test name
Test status
Simulation time 77220882 ps
CPU time 2.38 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 205724 kb
Host smart-b63b16b0-d230-4ece-87db-04473b0e1dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930748874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2930748874
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1745551105
Short name T1002
Test name
Test status
Simulation time 462194947 ps
CPU time 9.78 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 213904 kb
Host smart-4281dd44-b5cc-4e69-8848-7499f27aef44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745551105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1745551105
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3056199995
Short name T1055
Test name
Test status
Simulation time 317869980 ps
CPU time 6.97 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213808 kb
Host smart-21606e48-f1af-4c36-b942-1030ea2be8c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056199995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3056199995
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.361218110
Short name T1069
Test name
Test status
Simulation time 91367514 ps
CPU time 2.66 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 213680 kb
Host smart-f6e4350a-b19b-4c5e-a63d-d41e3fea3fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361218110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.361218110
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3989757299
Short name T152
Test name
Test status
Simulation time 261531105 ps
CPU time 6.98 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205584 kb
Host smart-f0f53fe2-f892-4b59-8937-8cefa35e873a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989757299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3989757299
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1849510851
Short name T937
Test name
Test status
Simulation time 21038096 ps
CPU time 1.28 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205480 kb
Host smart-c32bceb0-ddd0-4db8-9a9d-e4ba3d3cb557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849510851 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1849510851
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.899290767
Short name T1079
Test name
Test status
Simulation time 36533128 ps
CPU time 1.19 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:08 AM PDT 24
Peak memory 205404 kb
Host smart-ad9cd4e8-63d1-4207-8191-6078f6bda96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899290767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.899290767
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1640373175
Short name T1060
Test name
Test status
Simulation time 16416915 ps
CPU time 0.77 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 205168 kb
Host smart-03357da9-668b-4795-8b5b-9ac5e5aeeeac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640373175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1640373175
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1126473724
Short name T970
Test name
Test status
Simulation time 386292396 ps
CPU time 1.88 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205500 kb
Host smart-fe147020-a0e3-4aa5-abc2-24116ca0fc3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126473724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1126473724
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1333683976
Short name T931
Test name
Test status
Simulation time 135481485 ps
CPU time 4.02 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 213980 kb
Host smart-0d5bc342-d0b0-4f27-8e54-70c412fdea20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333683976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1333683976
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.89300236
Short name T1070
Test name
Test status
Simulation time 1021404892 ps
CPU time 8.2 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 213956 kb
Host smart-87efd43b-5e29-49e0-9f80-a8d437ebe7b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89300236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_shadow_reg_errors_with_csr_rw.89300236
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1742080245
Short name T1019
Test name
Test status
Simulation time 144391415 ps
CPU time 2.68 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213624 kb
Host smart-f82b2910-0963-4729-bca8-421692341a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742080245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1742080245
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.559767284
Short name T151
Test name
Test status
Simulation time 802612762 ps
CPU time 6.66 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213692 kb
Host smart-b8f80375-d435-4578-a942-d737439fc01a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559767284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.559767284
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.876366037
Short name T1059
Test name
Test status
Simulation time 30766738 ps
CPU time 1.3 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 205552 kb
Host smart-eb0fb4f4-918e-476e-9af0-fd4c4b2fec1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876366037 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.876366037
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1829396590
Short name T983
Test name
Test status
Simulation time 12786361 ps
CPU time 1.06 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 205312 kb
Host smart-bfbd2670-0c41-4181-b8b4-ed50f836fcb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829396590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1829396590
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2934087216
Short name T925
Test name
Test status
Simulation time 23573461 ps
CPU time 0.72 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 205292 kb
Host smart-4d9a4df0-c305-48a3-a2e2-784c6db0d1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934087216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2934087216
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1352789179
Short name T1024
Test name
Test status
Simulation time 38312334 ps
CPU time 1.53 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 205772 kb
Host smart-5850dd75-bc2b-4277-8ca1-96336728875c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352789179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1352789179
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.576727945
Short name T1033
Test name
Test status
Simulation time 337245116 ps
CPU time 2.55 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 214048 kb
Host smart-0ab4f17e-f79e-4ef8-a9da-b6c698f0058d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576727945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.576727945
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1086048380
Short name T138
Test name
Test status
Simulation time 166731695 ps
CPU time 6.96 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 213932 kb
Host smart-9c60de34-dee3-4067-9a56-9f4e0f5d223d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086048380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1086048380
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1119015948
Short name T966
Test name
Test status
Simulation time 116202124 ps
CPU time 2.2 seconds
Started Jul 02 07:53:11 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 213700 kb
Host smart-f738370d-d3bc-423a-9102-a803d23e597b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119015948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1119015948
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2525643178
Short name T1072
Test name
Test status
Simulation time 46191160 ps
CPU time 1.86 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 213752 kb
Host smart-8c80193b-bb18-433c-8e59-045d2a8a37ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525643178 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2525643178
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3294736042
Short name T1066
Test name
Test status
Simulation time 14763021 ps
CPU time 1.15 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:08 AM PDT 24
Peak memory 205448 kb
Host smart-6c69b49c-8488-40d5-a169-682af377be3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294736042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3294736042
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3707100278
Short name T963
Test name
Test status
Simulation time 115971247 ps
CPU time 0.74 seconds
Started Jul 02 07:53:07 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 205308 kb
Host smart-ef2922d8-a507-40c4-ac47-875c5976c151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707100278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3707100278
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2692052912
Short name T972
Test name
Test status
Simulation time 189262242 ps
CPU time 1.45 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:13 AM PDT 24
Peak memory 205444 kb
Host smart-3d81780d-9ad4-4e92-9c45-971c033caf50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692052912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2692052912
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2721395792
Short name T942
Test name
Test status
Simulation time 332048592 ps
CPU time 2.79 seconds
Started Jul 02 07:53:04 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 213900 kb
Host smart-f7c5efb2-4f19-4c7b-9ce5-d6a27c34c92e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721395792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2721395792
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3257948275
Short name T1063
Test name
Test status
Simulation time 467483829 ps
CPU time 9.29 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 219916 kb
Host smart-d2780df2-eb9b-4e4e-a441-e561afa39944
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257948275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3257948275
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4185595238
Short name T999
Test name
Test status
Simulation time 147855479 ps
CPU time 2.18 seconds
Started Jul 02 07:53:06 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 216932 kb
Host smart-a7d21b69-eb5e-462e-a4a8-6ca70fad3bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185595238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4185595238
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1616544485
Short name T172
Test name
Test status
Simulation time 405693166 ps
CPU time 6.16 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 213712 kb
Host smart-f362514b-569d-4b42-844a-3dce78adf9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616544485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1616544485
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2934024517
Short name T1023
Test name
Test status
Simulation time 486159411 ps
CPU time 1.79 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213808 kb
Host smart-3cb12b79-0ba0-40d1-b52f-4b51b400eb32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934024517 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2934024517
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3385323534
Short name T955
Test name
Test status
Simulation time 102710817 ps
CPU time 1.19 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 205260 kb
Host smart-f0007c30-1730-4191-895b-696107771812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385323534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3385323534
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3896213241
Short name T943
Test name
Test status
Simulation time 66885650 ps
CPU time 0.81 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 205484 kb
Host smart-4c0af72d-5a02-477d-b137-0fdd9ab75b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896213241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3896213241
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.892161416
Short name T1043
Test name
Test status
Simulation time 134849349 ps
CPU time 2.5 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 205516 kb
Host smart-bb3e87ab-d83f-42e3-93c7-5945108b95cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892161416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.892161416
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3742044275
Short name T944
Test name
Test status
Simulation time 95028189 ps
CPU time 3.4 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 213836 kb
Host smart-d876423e-a2a8-433e-b2ed-94a01b1e632f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742044275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3742044275
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.992673512
Short name T119
Test name
Test status
Simulation time 388237810 ps
CPU time 5.33 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 214000 kb
Host smart-275d3b74-2b6b-46e7-a60a-622f6749278d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992673512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.992673512
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2139338663
Short name T1085
Test name
Test status
Simulation time 101022133 ps
CPU time 1.74 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213664 kb
Host smart-91424201-a7d1-450d-87c7-3dc02c502388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139338663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2139338663
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1121445543
Short name T1035
Test name
Test status
Simulation time 37638764 ps
CPU time 1.53 seconds
Started Jul 02 07:53:06 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 217152 kb
Host smart-8af64ffb-7a85-490d-b856-0f69db5bf6da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121445543 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1121445543
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.46993301
Short name T139
Test name
Test status
Simulation time 139847421 ps
CPU time 1.07 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205460 kb
Host smart-a057b276-e321-4421-82ff-60bf3df6c53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46993301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.46993301
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1191558206
Short name T1004
Test name
Test status
Simulation time 10309117 ps
CPU time 0.75 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205236 kb
Host smart-e4eb1958-550e-42e7-9e76-5047ab247e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191558206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1191558206
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3083279402
Short name T1028
Test name
Test status
Simulation time 75475829 ps
CPU time 2.15 seconds
Started Jul 02 07:53:12 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205508 kb
Host smart-11a9a50f-0fa9-440c-a8e6-f62a98089953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083279402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3083279402
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1002239416
Short name T950
Test name
Test status
Simulation time 64753151 ps
CPU time 1.82 seconds
Started Jul 02 07:53:07 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 213860 kb
Host smart-b8a3146a-23c0-44f8-ba6c-10051ac94172
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002239416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1002239416
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3085014393
Short name T1044
Test name
Test status
Simulation time 1020464787 ps
CPU time 7.07 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:21 AM PDT 24
Peak memory 213980 kb
Host smart-1f760481-c0a6-459d-a357-2cfdaf54b853
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085014393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3085014393
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4087944215
Short name T923
Test name
Test status
Simulation time 251995158 ps
CPU time 2.74 seconds
Started Jul 02 07:53:13 AM PDT 24
Finished Jul 02 07:53:19 AM PDT 24
Peak memory 215664 kb
Host smart-cedacf33-0293-4119-b5c8-f23bccc772cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087944215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4087944215
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1170832027
Short name T165
Test name
Test status
Simulation time 110044742 ps
CPU time 2.36 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213732 kb
Host smart-320ce775-21c4-4c3e-8cdf-9b2338e107b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170832027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1170832027
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3469087731
Short name T934
Test name
Test status
Simulation time 200484405 ps
CPU time 1.94 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 219224 kb
Host smart-0053d3c4-abb5-4025-9d15-68253159d690
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469087731 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3469087731
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.367917239
Short name T135
Test name
Test status
Simulation time 27606630 ps
CPU time 1.52 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 205544 kb
Host smart-c1267f54-35bd-44fd-b668-e2230b1b111c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367917239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.367917239
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1955584992
Short name T1000
Test name
Test status
Simulation time 12960651 ps
CPU time 0.74 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 205288 kb
Host smart-d0767257-dfed-44f0-b285-eb7c9e2ea8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955584992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1955584992
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1017443468
Short name T964
Test name
Test status
Simulation time 101743650 ps
CPU time 2.37 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 205536 kb
Host smart-c83bfa2a-ecb5-4e66-86f7-ae5bd4976391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017443468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1017443468
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4082198434
Short name T997
Test name
Test status
Simulation time 107328252 ps
CPU time 3.09 seconds
Started Jul 02 07:53:11 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 213788 kb
Host smart-4a1f5437-a29e-4c8d-be26-448766dfbe73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082198434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4082198434
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1967922927
Short name T1014
Test name
Test status
Simulation time 1387689002 ps
CPU time 12.42 seconds
Started Jul 02 07:53:14 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 213980 kb
Host smart-fa1945c1-ea6b-44bd-9198-6d1ab4a5e7f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967922927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1967922927
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.107582759
Short name T1067
Test name
Test status
Simulation time 46356425 ps
CPU time 1.86 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 213688 kb
Host smart-a4ff9446-b155-4bb8-8839-e0f6f45fa05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107582759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.107582759
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.740834614
Short name T953
Test name
Test status
Simulation time 238211140 ps
CPU time 6.62 seconds
Started Jul 02 07:53:07 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 213588 kb
Host smart-7b4465fc-27fe-4749-a121-4278d03b6c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740834614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.740834614
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1635093937
Short name T947
Test name
Test status
Simulation time 30956616 ps
CPU time 1.2 seconds
Started Jul 02 07:53:14 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205396 kb
Host smart-756e1344-818e-493f-9471-c90480317f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635093937 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1635093937
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2864283249
Short name T995
Test name
Test status
Simulation time 27086306 ps
CPU time 1.6 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205404 kb
Host smart-e951a294-b7c6-4389-9344-cb695d939c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864283249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2864283249
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1814521552
Short name T949
Test name
Test status
Simulation time 16652308 ps
CPU time 0.78 seconds
Started Jul 02 07:53:17 AM PDT 24
Finished Jul 02 07:53:19 AM PDT 24
Peak memory 205208 kb
Host smart-e3b938c5-dbfd-497c-856b-5fa4a94632b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814521552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1814521552
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2353349166
Short name T965
Test name
Test status
Simulation time 24415455 ps
CPU time 1.63 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205340 kb
Host smart-9ade008f-ff03-4901-b380-e48008880e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353349166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2353349166
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3971551710
Short name T940
Test name
Test status
Simulation time 96733621 ps
CPU time 3.04 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 213964 kb
Host smart-6a56bc28-68dc-4a11-8884-fbf65b9d6efc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971551710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3971551710
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.148831229
Short name T1025
Test name
Test status
Simulation time 368017889 ps
CPU time 6.61 seconds
Started Jul 02 07:53:18 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 219616 kb
Host smart-fafbeac3-79ad-45a2-9ddc-4e9d34443447
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148831229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.148831229
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4179875360
Short name T967
Test name
Test status
Simulation time 404329610 ps
CPU time 3.97 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 213528 kb
Host smart-30b377d3-6aaa-4661-948d-c81d3b501a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179875360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4179875360
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2837965421
Short name T364
Test name
Test status
Simulation time 399433827 ps
CPU time 3.48 seconds
Started Jul 02 07:53:09 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 205412 kb
Host smart-53b733f3-dc5a-4790-93e9-67870211d7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837965421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2837965421
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.956086744
Short name T977
Test name
Test status
Simulation time 63852957 ps
CPU time 1.63 seconds
Started Jul 02 07:53:14 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205860 kb
Host smart-4bf9fd81-bffd-4347-9fc4-11ada77a5dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956086744 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.956086744
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.883734111
Short name T1036
Test name
Test status
Simulation time 102747191 ps
CPU time 1.04 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205288 kb
Host smart-db818426-45b2-4c90-bf9e-8c1481ad9669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883734111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.883734111
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.519975368
Short name T939
Test name
Test status
Simulation time 10159346 ps
CPU time 0.8 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 205288 kb
Host smart-3874cf49-8ec9-43df-b193-cf763601034f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519975368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.519975368
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4060966500
Short name T1027
Test name
Test status
Simulation time 36539710 ps
CPU time 1.56 seconds
Started Jul 02 07:53:12 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205504 kb
Host smart-01572c09-e8ab-4857-805d-6bde4c9c78a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060966500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4060966500
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3336382527
Short name T1081
Test name
Test status
Simulation time 148825514 ps
CPU time 1.78 seconds
Started Jul 02 07:53:16 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 213796 kb
Host smart-3d973acc-a814-480d-9309-5af1d3709302
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336382527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3336382527
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4103581055
Short name T1056
Test name
Test status
Simulation time 79903834 ps
CPU time 4.67 seconds
Started Jul 02 07:53:12 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 219952 kb
Host smart-e36dc577-526b-44bb-ba8b-971196eff2e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103581055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4103581055
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2873791163
Short name T1048
Test name
Test status
Simulation time 190420506 ps
CPU time 3.22 seconds
Started Jul 02 07:53:17 AM PDT 24
Finished Jul 02 07:53:22 AM PDT 24
Peak memory 216664 kb
Host smart-f9dc2416-480c-425d-a4fe-540006f1ce6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873791163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2873791163
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.784123261
Short name T1083
Test name
Test status
Simulation time 29835429 ps
CPU time 1.81 seconds
Started Jul 02 07:53:55 AM PDT 24
Finished Jul 02 07:54:03 AM PDT 24
Peak memory 213828 kb
Host smart-500fd6a3-49c1-4b82-b130-621ad39c9239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784123261 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.784123261
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1532830870
Short name T136
Test name
Test status
Simulation time 44104304 ps
CPU time 0.98 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:25 AM PDT 24
Peak memory 205648 kb
Host smart-4ea9cbc5-af59-40e5-a8ad-b2294eee8d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532830870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1532830870
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2262580541
Short name T1022
Test name
Test status
Simulation time 35111386 ps
CPU time 0.79 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 205240 kb
Host smart-13cb774f-c2b0-4fb1-93a8-adbaf0461c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262580541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2262580541
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.703892040
Short name T988
Test name
Test status
Simulation time 24396021 ps
CPU time 1.59 seconds
Started Jul 02 07:53:13 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205460 kb
Host smart-0eb8ce29-da50-4708-9ebc-52a882beecc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703892040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.703892040
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2810080530
Short name T962
Test name
Test status
Simulation time 292091036 ps
CPU time 3.02 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 213880 kb
Host smart-43d54e4d-1978-47b1-bc4e-a83f499407dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810080530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2810080530
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2303267744
Short name T979
Test name
Test status
Simulation time 460988534 ps
CPU time 14.05 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 220120 kb
Host smart-80b867f2-73d6-4f6d-9049-333a20dba0cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303267744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2303267744
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2703030391
Short name T973
Test name
Test status
Simulation time 109501306 ps
CPU time 2.14 seconds
Started Jul 02 07:53:18 AM PDT 24
Finished Jul 02 07:53:21 AM PDT 24
Peak memory 216708 kb
Host smart-f2f18409-47fe-42db-bc24-f2e2b590d556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703030391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2703030391
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2240023485
Short name T161
Test name
Test status
Simulation time 957061066 ps
CPU time 7.41 seconds
Started Jul 02 07:53:13 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 213616 kb
Host smart-71a527a3-139d-451f-a0c0-83a8202f6616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240023485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2240023485
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1006700594
Short name T137
Test name
Test status
Simulation time 130273048 ps
CPU time 4.39 seconds
Started Jul 02 07:52:54 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205440 kb
Host smart-b5bfa0bc-444d-4fdc-a46c-f18fd811a38e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006700594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
006700594
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2875859246
Short name T928
Test name
Test status
Simulation time 2318584567 ps
CPU time 9.15 seconds
Started Jul 02 07:52:47 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 205492 kb
Host smart-e2b93fe9-d870-499a-bf2e-56917e1352f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875859246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
875859246
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1306426211
Short name T1046
Test name
Test status
Simulation time 23184564 ps
CPU time 1.31 seconds
Started Jul 02 07:52:54 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205408 kb
Host smart-afa2a3e6-399e-4ce0-96a8-42371db04ca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306426211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
306426211
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4157910254
Short name T990
Test name
Test status
Simulation time 29478410 ps
CPU time 1.89 seconds
Started Jul 02 07:52:47 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 213820 kb
Host smart-6bd3e752-4e42-49e5-a3a7-08ec0701da55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157910254 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4157910254
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.845676807
Short name T1053
Test name
Test status
Simulation time 13560363 ps
CPU time 0.96 seconds
Started Jul 02 07:52:54 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205652 kb
Host smart-7f092a91-0163-4612-a96c-09f6fd40d9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845676807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.845676807
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.798144085
Short name T1051
Test name
Test status
Simulation time 12531554 ps
CPU time 0.71 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205208 kb
Host smart-1810cfc3-22e8-4d31-820c-d5804c0daa97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798144085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.798144085
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2148115996
Short name T1065
Test name
Test status
Simulation time 45549705 ps
CPU time 2.01 seconds
Started Jul 02 07:52:48 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 205420 kb
Host smart-7a6e529f-e155-4aef-9560-15a27683c7cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148115996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2148115996
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.107834523
Short name T1054
Test name
Test status
Simulation time 323777432 ps
CPU time 5.38 seconds
Started Jul 02 07:53:02 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 218368 kb
Host smart-425339e2-b956-4e99-8750-9e7b506373df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107834523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.107834523
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.496936513
Short name T982
Test name
Test status
Simulation time 495581135 ps
CPU time 4.3 seconds
Started Jul 02 07:52:48 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 214280 kb
Host smart-b9206fe2-0f49-44e0-bcba-083c37f9b8d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496936513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.496936513
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1061847375
Short name T971
Test name
Test status
Simulation time 80310155 ps
CPU time 1.44 seconds
Started Jul 02 07:52:54 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 215600 kb
Host smart-1b999bac-506e-4ca1-911d-60a9856b821f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061847375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1061847375
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.834846978
Short name T163
Test name
Test status
Simulation time 211075116 ps
CPU time 4.71 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 213556 kb
Host smart-89e4f500-b807-415a-92c1-3536936260b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834846978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
834846978
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1301958071
Short name T1058
Test name
Test status
Simulation time 16630824 ps
CPU time 0.86 seconds
Started Jul 02 07:53:14 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205312 kb
Host smart-89437e2f-daed-450f-a3a1-6737bcbd76a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301958071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1301958071
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3555978537
Short name T1080
Test name
Test status
Simulation time 15679198 ps
CPU time 0.77 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205124 kb
Host smart-117ce3ff-d734-4b93-b2ca-ea4a7ce0f09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555978537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3555978537
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.722989589
Short name T929
Test name
Test status
Simulation time 12212447 ps
CPU time 0.7 seconds
Started Jul 02 07:53:14 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205068 kb
Host smart-bff41191-8781-4dd1-9c00-f29c665437ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722989589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.722989589
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1830806032
Short name T993
Test name
Test status
Simulation time 13668510 ps
CPU time 0.78 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205168 kb
Host smart-fbe1347c-d8be-460c-a01a-0bf788d1798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830806032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1830806032
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1275371588
Short name T954
Test name
Test status
Simulation time 10372398 ps
CPU time 0.69 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205288 kb
Host smart-0e1dcd9f-55a0-4261-b17c-42325061352d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275371588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1275371588
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3697231025
Short name T936
Test name
Test status
Simulation time 117020204 ps
CPU time 0.72 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:53:47 AM PDT 24
Peak memory 205312 kb
Host smart-4610e7ea-6a9b-4099-b71e-2f35a83e130b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697231025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3697231025
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3579910562
Short name T1013
Test name
Test status
Simulation time 10667825 ps
CPU time 0.84 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205524 kb
Host smart-60b01c32-b512-4afb-9683-b2c551c30aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579910562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3579910562
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4002626025
Short name T974
Test name
Test status
Simulation time 53185304 ps
CPU time 0.75 seconds
Started Jul 02 07:53:12 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 205256 kb
Host smart-ddf72ab1-6a93-4385-bb88-9f7ece60e19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002626025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4002626025
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4070570012
Short name T1012
Test name
Test status
Simulation time 12317558 ps
CPU time 0.87 seconds
Started Jul 02 07:53:13 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205064 kb
Host smart-74e2bf42-7971-474b-9db4-2f10e338a8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070570012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4070570012
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2164228590
Short name T1001
Test name
Test status
Simulation time 32919254 ps
CPU time 0.72 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 205288 kb
Host smart-8d5e3cd6-7847-4f19-81ba-c73607c9c151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164228590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2164228590
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2601518577
Short name T1011
Test name
Test status
Simulation time 511684996 ps
CPU time 8.65 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 205404 kb
Host smart-bd66ecb1-8632-4f28-a7c7-59674e958f77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601518577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
601518577
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2216263530
Short name T927
Test name
Test status
Simulation time 1309653179 ps
CPU time 32.48 seconds
Started Jul 02 07:52:48 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 205404 kb
Host smart-885a84dd-02c9-40e2-9e93-fe3bb2d900ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216263530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
216263530
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3078275087
Short name T1020
Test name
Test status
Simulation time 125664344 ps
CPU time 1.08 seconds
Started Jul 02 07:52:49 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 205440 kb
Host smart-2d69748c-17d2-44ee-8c1a-4bcc5fa920b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078275087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
078275087
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2077329255
Short name T1042
Test name
Test status
Simulation time 56089987 ps
CPU time 1.25 seconds
Started Jul 02 07:52:54 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205456 kb
Host smart-2fc989f9-4fff-49f0-bb62-b483aa39a071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077329255 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2077329255
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2971731631
Short name T1017
Test name
Test status
Simulation time 45416060 ps
CPU time 0.93 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 205324 kb
Host smart-39c369dc-555b-44f1-b2a4-b63a6df01a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971731631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2971731631
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1126974938
Short name T920
Test name
Test status
Simulation time 10287386 ps
CPU time 0.76 seconds
Started Jul 02 07:52:47 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 205140 kb
Host smart-5d8f0857-321b-49ff-a771-b69ee4dd94ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126974938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1126974938
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.784383373
Short name T133
Test name
Test status
Simulation time 242097697 ps
CPU time 2.49 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 205440 kb
Host smart-b0e95b2a-5849-4175-8f80-69c89e72f445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784383373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.784383373
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2600957608
Short name T958
Test name
Test status
Simulation time 1534029073 ps
CPU time 5.01 seconds
Started Jul 02 07:52:50 AM PDT 24
Finished Jul 02 07:53:02 AM PDT 24
Peak memory 213780 kb
Host smart-6792be78-6bf7-448c-98da-c356e3f485a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600957608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2600957608
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.270535497
Short name T1018
Test name
Test status
Simulation time 58137563 ps
CPU time 2.11 seconds
Started Jul 02 07:52:49 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 213696 kb
Host smart-1f4106b3-d2ca-4b92-8b95-4428c480d72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270535497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.270535497
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3837039205
Short name T154
Test name
Test status
Simulation time 351440823 ps
CPU time 5.2 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 213636 kb
Host smart-bf162832-bb4d-4a68-b280-d77d50363dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837039205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3837039205
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1148271846
Short name T1068
Test name
Test status
Simulation time 14742422 ps
CPU time 0.89 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205416 kb
Host smart-4e5a2da8-0f05-4c0b-9ab1-77be172e23fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148271846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1148271846
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2836535055
Short name T918
Test name
Test status
Simulation time 11661928 ps
CPU time 0.85 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 205316 kb
Host smart-403d1f1d-d697-4fcd-966d-e1c07186ee69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836535055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2836535055
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3487900262
Short name T956
Test name
Test status
Simulation time 43117426 ps
CPU time 0.75 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 205304 kb
Host smart-d47fe4e3-b730-45fc-abd4-b2d8d21f3c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487900262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3487900262
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1566090327
Short name T992
Test name
Test status
Simulation time 86743415 ps
CPU time 0.76 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205132 kb
Host smart-e544f800-eeb4-459d-b805-68d3542adc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566090327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1566090327
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.598841155
Short name T917
Test name
Test status
Simulation time 31853391 ps
CPU time 0.78 seconds
Started Jul 02 07:53:15 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 205060 kb
Host smart-c423c0f7-144f-4d62-bba7-27ba8179e557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598841155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.598841155
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3779677963
Short name T1062
Test name
Test status
Simulation time 17001603 ps
CPU time 0.91 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:49 AM PDT 24
Peak memory 205384 kb
Host smart-db1d33d5-381b-4504-934f-fcdf09aa96e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779677963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3779677963
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3505947465
Short name T952
Test name
Test status
Simulation time 39245105 ps
CPU time 0.68 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:25 AM PDT 24
Peak memory 205116 kb
Host smart-d47fcde8-11e0-4ab2-8388-1214093db09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505947465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3505947465
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4126028482
Short name T1050
Test name
Test status
Simulation time 26015700 ps
CPU time 0.75 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 205316 kb
Host smart-e2d32398-94dd-48ec-b6d9-15e5fb5d0791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126028482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4126028482
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3531160700
Short name T945
Test name
Test status
Simulation time 20733602 ps
CPU time 0.71 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205268 kb
Host smart-426ec0ff-4b3a-4d62-8d04-dd02a403ccf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531160700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3531160700
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2055679172
Short name T948
Test name
Test status
Simulation time 38766034 ps
CPU time 0.69 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 205264 kb
Host smart-8545f8fa-0732-4ee2-87e0-abe24b3be4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055679172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2055679172
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.892768523
Short name T1009
Test name
Test status
Simulation time 267849192 ps
CPU time 9.25 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 205444 kb
Host smart-54ffc820-6e19-4b19-ba29-a6e2a83139f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892768523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.892768523
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.140504839
Short name T1037
Test name
Test status
Simulation time 255323672 ps
CPU time 14.51 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205304 kb
Host smart-9f39cc0a-2a63-4a1c-bd5a-24d1fa99c1b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140504839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.140504839
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3916646511
Short name T941
Test name
Test status
Simulation time 263797714 ps
CPU time 1.38 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205340 kb
Host smart-29380f09-336d-49b2-8612-d476a8e0c028
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916646511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
916646511
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1682651653
Short name T922
Test name
Test status
Simulation time 81273438 ps
CPU time 1.37 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 213644 kb
Host smart-5bc674df-3c94-40bd-ad4f-73ab59c8ef81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682651653 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1682651653
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.607896490
Short name T980
Test name
Test status
Simulation time 70201209 ps
CPU time 1.02 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 205176 kb
Host smart-f2ce6928-6046-4021-ade4-e357200d83a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607896490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.607896490
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1253231022
Short name T959
Test name
Test status
Simulation time 28100205 ps
CPU time 0.91 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205284 kb
Host smart-c88fe5e6-0d68-405f-b6f0-74137124f723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253231022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1253231022
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4122211358
Short name T1045
Test name
Test status
Simulation time 86449684 ps
CPU time 2.75 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 205316 kb
Host smart-7dd8b31b-a2b4-4bb1-b6b0-8c05b4da42a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122211358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4122211358
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2708941124
Short name T1029
Test name
Test status
Simulation time 300733629 ps
CPU time 2.83 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 214152 kb
Host smart-ad2fcb11-a884-47f7-948f-650fed18b9be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708941124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2708941124
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1808147425
Short name T112
Test name
Test status
Simulation time 295786494 ps
CPU time 3.71 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 213996 kb
Host smart-2fb2e364-00e9-400d-ba78-d3788a581398
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808147425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1808147425
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.292691856
Short name T976
Test name
Test status
Simulation time 76079685 ps
CPU time 2.89 seconds
Started Jul 02 07:52:53 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 213764 kb
Host smart-01bec0a6-d808-47f8-abbb-abfd71d3a8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292691856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.292691856
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3582624587
Short name T1074
Test name
Test status
Simulation time 11547669 ps
CPU time 0.78 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205208 kb
Host smart-a5a8d2b6-ee95-41e9-b812-f2121b670ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582624587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3582624587
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1180061323
Short name T914
Test name
Test status
Simulation time 45167813 ps
CPU time 0.8 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:24 AM PDT 24
Peak memory 205132 kb
Host smart-b6681b61-75a0-4267-b316-e471e7efb048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180061323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1180061323
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.969642192
Short name T946
Test name
Test status
Simulation time 32272145 ps
CPU time 0.74 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 205184 kb
Host smart-36fe968f-d9ad-4ccb-8d20-0631f987bda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969642192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.969642192
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.156620755
Short name T1077
Test name
Test status
Simulation time 50587853 ps
CPU time 0.85 seconds
Started Jul 02 07:53:17 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205292 kb
Host smart-ce17e717-051b-4200-94fb-afd2c44d5fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156620755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.156620755
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1881558229
Short name T1038
Test name
Test status
Simulation time 39990004 ps
CPU time 0.76 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 205196 kb
Host smart-7e6a3c31-985c-408d-9f52-6bf6f10e839b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881558229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1881558229
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4148723606
Short name T1039
Test name
Test status
Simulation time 54657123 ps
CPU time 0.72 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:21 AM PDT 24
Peak memory 205248 kb
Host smart-a2931de8-2a31-40e5-b908-28b3659e4679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148723606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4148723606
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1487429506
Short name T1008
Test name
Test status
Simulation time 13622885 ps
CPU time 0.84 seconds
Started Jul 02 07:53:40 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 205320 kb
Host smart-cc4dbf5f-7cca-40e5-a41c-9dbc7f5b65f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487429506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1487429506
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4004341844
Short name T1052
Test name
Test status
Simulation time 37192049 ps
CPU time 0.85 seconds
Started Jul 02 07:53:18 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 205140 kb
Host smart-3f1981e7-2fca-4f36-8224-4d954dde4e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004341844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4004341844
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1175273746
Short name T916
Test name
Test status
Simulation time 8382623 ps
CPU time 0.75 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 205216 kb
Host smart-8b7d2be6-c589-494d-bd68-6a3b7f93e6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175273746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1175273746
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3629070663
Short name T957
Test name
Test status
Simulation time 39411085 ps
CPU time 0.79 seconds
Started Jul 02 07:53:18 AM PDT 24
Finished Jul 02 07:53:19 AM PDT 24
Peak memory 205108 kb
Host smart-1f03e49a-ad38-4117-a892-668b0a0ae7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629070663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3629070663
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4016880964
Short name T930
Test name
Test status
Simulation time 25410581 ps
CPU time 1.87 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 213648 kb
Host smart-2edfeb71-8014-44f4-bf03-7a6b3db960d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016880964 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4016880964
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.54677733
Short name T991
Test name
Test status
Simulation time 15486288 ps
CPU time 1.24 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 205456 kb
Host smart-3e7b2cc5-9f01-41a0-b445-3c702864ea41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54677733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.54677733
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.145801689
Short name T1003
Test name
Test status
Simulation time 150358864 ps
CPU time 0.78 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 205168 kb
Host smart-a2605f03-f522-4d52-9f01-c255d91947ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145801689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.145801689
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1241915598
Short name T986
Test name
Test status
Simulation time 24544712 ps
CPU time 1.65 seconds
Started Jul 02 07:52:55 AM PDT 24
Finished Jul 02 07:53:02 AM PDT 24
Peak memory 205416 kb
Host smart-08dbdbde-dc9e-4cb3-b01b-3705d11da518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241915598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1241915598
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2619192626
Short name T117
Test name
Test status
Simulation time 181992522 ps
CPU time 2.78 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 217776 kb
Host smart-6b5c8a3a-74e1-455a-aa61-317cb27d95be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619192626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2619192626
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3138751781
Short name T975
Test name
Test status
Simulation time 111531684 ps
CPU time 3.64 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 213780 kb
Host smart-18f462fb-e20b-4e1d-bcd4-997739dc08ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138751781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3138751781
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1261989447
Short name T1021
Test name
Test status
Simulation time 46268423 ps
CPU time 3.07 seconds
Started Jul 02 07:52:57 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 213508 kb
Host smart-3755710d-0c27-4008-a204-0feeeef26970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261989447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1261989447
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3370436387
Short name T1041
Test name
Test status
Simulation time 143633350 ps
CPU time 5.83 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 213612 kb
Host smart-f29cd9d9-5b0f-487f-af79-d81db80e5b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370436387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3370436387
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2714865109
Short name T926
Test name
Test status
Simulation time 52596707 ps
CPU time 1.28 seconds
Started Jul 02 07:53:00 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 213748 kb
Host smart-9fa74600-08bc-446f-98aa-e7210cecb8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714865109 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2714865109
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2322886742
Short name T1071
Test name
Test status
Simulation time 18508243 ps
CPU time 0.98 seconds
Started Jul 02 07:52:56 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 205504 kb
Host smart-b26f333d-2971-4d50-9a00-f809bba4ea85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322886742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2322886742
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2478293040
Short name T996
Test name
Test status
Simulation time 50205885 ps
CPU time 0.79 seconds
Started Jul 02 07:52:57 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 205212 kb
Host smart-437a4272-3060-4f73-9d66-b4fa8199b182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478293040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2478293040
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3935557110
Short name T1047
Test name
Test status
Simulation time 240994462 ps
CPU time 1.7 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 205236 kb
Host smart-2938a600-8487-4f58-aeeb-0bafa057b5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935557110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3935557110
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2999948920
Short name T921
Test name
Test status
Simulation time 173858336 ps
CPU time 3.36 seconds
Started Jul 02 07:52:51 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 218812 kb
Host smart-f808f259-2d7f-4cb0-a35d-e2c2fa7d0d6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999948920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2999948920
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3565134469
Short name T134
Test name
Test status
Simulation time 435515430 ps
CPU time 3.54 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 213744 kb
Host smart-f91f5600-9422-4b43-841c-68552050c1a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565134469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3565134469
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2522061419
Short name T1016
Test name
Test status
Simulation time 496365584 ps
CPU time 2.48 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 216776 kb
Host smart-46dd2d38-be30-4586-aa3c-45cee11fd090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522061419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2522061419
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2850088979
Short name T167
Test name
Test status
Simulation time 707748820 ps
CPU time 6.51 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 216364 kb
Host smart-d0cfc478-a1ad-419b-b419-8af890735b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850088979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2850088979
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1032424595
Short name T960
Test name
Test status
Simulation time 68195438 ps
CPU time 1.23 seconds
Started Jul 02 07:53:01 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 205408 kb
Host smart-99472ca5-0c06-43f3-ac63-dd418ca16465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032424595 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1032424595
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2876983913
Short name T968
Test name
Test status
Simulation time 29288125 ps
CPU time 1.61 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205444 kb
Host smart-983dde01-3943-4ddf-8600-d46431944e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876983913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2876983913
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.66966037
Short name T987
Test name
Test status
Simulation time 38663398 ps
CPU time 0.72 seconds
Started Jul 02 07:53:00 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 205228 kb
Host smart-07400f90-92f7-41ae-9693-bee7bdccec8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66966037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.66966037
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1586330240
Short name T984
Test name
Test status
Simulation time 194754592 ps
CPU time 2.18 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 205484 kb
Host smart-f13d943a-dc58-47fa-b40a-96b7eb4c3a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586330240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1586330240
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3349056065
Short name T113
Test name
Test status
Simulation time 114292385 ps
CPU time 2.59 seconds
Started Jul 02 07:52:57 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 214084 kb
Host smart-fff1caea-2ac0-4edf-a671-86107d78baea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349056065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3349056065
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.715347005
Short name T1034
Test name
Test status
Simulation time 338651792 ps
CPU time 11.9 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:15 AM PDT 24
Peak memory 214008 kb
Host smart-0fbc3cd2-18e5-421c-89d4-b45cf60c3c30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715347005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.715347005
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2206763514
Short name T915
Test name
Test status
Simulation time 204778982 ps
CPU time 1.89 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 213712 kb
Host smart-7a40859a-8ede-44bb-a10d-f4e9857f1252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206763514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2206763514
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3568191447
Short name T938
Test name
Test status
Simulation time 183254383 ps
CPU time 1.86 seconds
Started Jul 02 07:53:08 AM PDT 24
Finished Jul 02 07:53:13 AM PDT 24
Peak memory 213736 kb
Host smart-fd5e3c00-bc38-4e6c-a49a-83297d06317a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568191447 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3568191447
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2450162050
Short name T969
Test name
Test status
Simulation time 53020165 ps
CPU time 0.86 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 205292 kb
Host smart-f971e858-20da-4881-a7a3-f7125c095968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450162050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2450162050
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3731797444
Short name T935
Test name
Test status
Simulation time 15773411 ps
CPU time 0.87 seconds
Started Jul 02 07:53:13 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 205128 kb
Host smart-50f9b857-21d4-45bd-ad89-3564ff34ab6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731797444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3731797444
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4198710217
Short name T1049
Test name
Test status
Simulation time 38271746 ps
CPU time 2.6 seconds
Started Jul 02 07:52:59 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 205392 kb
Host smart-ff547493-ee47-43ce-bb8a-27f3a1be65ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198710217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4198710217
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2086051478
Short name T1026
Test name
Test status
Simulation time 103712352 ps
CPU time 2.09 seconds
Started Jul 02 07:53:01 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 213904 kb
Host smart-1ec989f5-6d95-48b2-9cec-e9128c29b3d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086051478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2086051478
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2762339883
Short name T1073
Test name
Test status
Simulation time 387818048 ps
CPU time 8.95 seconds
Started Jul 02 07:53:10 AM PDT 24
Finished Jul 02 07:53:22 AM PDT 24
Peak memory 213956 kb
Host smart-7d5011f7-0820-454d-907e-2b1e1c9ac04b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762339883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2762339883
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1587034929
Short name T919
Test name
Test status
Simulation time 247742629 ps
CPU time 2.92 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 216812 kb
Host smart-c00dd922-aa71-4dd6-b1ae-b393384dbe31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587034929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1587034929
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2388111409
Short name T978
Test name
Test status
Simulation time 198399720 ps
CPU time 2.49 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 217296 kb
Host smart-fdd3ce21-21f3-44c0-a1a0-7741357b7588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388111409 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2388111409
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1808249296
Short name T1040
Test name
Test status
Simulation time 144047905 ps
CPU time 1.12 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 205348 kb
Host smart-d61b7187-da70-4114-9d57-99366a6823af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808249296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1808249296
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.74581299
Short name T1030
Test name
Test status
Simulation time 42361202 ps
CPU time 0.72 seconds
Started Jul 02 07:53:00 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 205204 kb
Host smart-d72953ed-82a7-429c-a1d7-20032c2fe0c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74581299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.74581299
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3624068063
Short name T981
Test name
Test status
Simulation time 56975336 ps
CPU time 2.34 seconds
Started Jul 02 07:53:05 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 205376 kb
Host smart-5ba38b22-4b16-4231-9959-ad5a6a12f5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624068063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3624068063
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1008407813
Short name T118
Test name
Test status
Simulation time 306432383 ps
CPU time 2.49 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 214076 kb
Host smart-170a4f24-a0b1-477f-9b83-bb3edaad5e72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008407813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1008407813
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.593725542
Short name T1031
Test name
Test status
Simulation time 85323363 ps
CPU time 4 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 214064 kb
Host smart-f977ab7a-e6ab-457f-80b2-f99ac223d530
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593725542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.593725542
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2406317707
Short name T998
Test name
Test status
Simulation time 115737068 ps
CPU time 4.31 seconds
Started Jul 02 07:53:03 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 216068 kb
Host smart-75496afd-2892-41e6-907c-698e0ba13c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406317707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2406317707
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2993286813
Short name T171
Test name
Test status
Simulation time 184181062 ps
CPU time 2.55 seconds
Started Jul 02 07:52:58 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 213600 kb
Host smart-2f514da2-bc5e-4148-a59c-13623d4f9164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993286813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2993286813
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.804231520
Short name T818
Test name
Test status
Simulation time 67428728 ps
CPU time 0.93 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 205944 kb
Host smart-7623799e-11af-4e61-ac7e-b5e14d1e56dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804231520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.804231520
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1147973112
Short name T807
Test name
Test status
Simulation time 45927175 ps
CPU time 1.59 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 207788 kb
Host smart-e8af98f6-13a2-4dcc-8544-c58ced5db8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147973112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1147973112
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.747009376
Short name T539
Test name
Test status
Simulation time 145537879 ps
CPU time 2.37 seconds
Started Jul 02 07:55:59 AM PDT 24
Finished Jul 02 07:56:27 AM PDT 24
Peak memory 207964 kb
Host smart-97798350-8535-4d41-b900-e2a206d62654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747009376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.747009376
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1128442147
Short name T236
Test name
Test status
Simulation time 412479102 ps
CPU time 3.13 seconds
Started Jul 02 07:55:59 AM PDT 24
Finished Jul 02 07:56:27 AM PDT 24
Peak memory 214284 kb
Host smart-2d16bc6e-1160-4ec9-a59b-417ddfc2b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128442147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1128442147
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.453225151
Short name T623
Test name
Test status
Simulation time 511310997 ps
CPU time 3.83 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 209524 kb
Host smart-8686c5f0-3ea1-4c5e-8365-a4943d2ebcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453225151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.453225151
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3213377971
Short name T622
Test name
Test status
Simulation time 45453434 ps
CPU time 2.24 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:30 AM PDT 24
Peak memory 208248 kb
Host smart-30f9d0db-d183-41d4-ae5a-c3c6cac57b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213377971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3213377971
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1004833754
Short name T601
Test name
Test status
Simulation time 1356050034 ps
CPU time 13.75 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 207736 kb
Host smart-0a2a4625-4e30-4e08-9be8-853c257af23a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004833754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1004833754
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.919075929
Short name T641
Test name
Test status
Simulation time 186631667 ps
CPU time 4.12 seconds
Started Jul 02 07:55:59 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 208876 kb
Host smart-27985e1f-9616-4e80-a94e-edd0e3abcfca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919075929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.919075929
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1223783870
Short name T767
Test name
Test status
Simulation time 116246072 ps
CPU time 2.89 seconds
Started Jul 02 07:55:55 AM PDT 24
Finished Jul 02 07:56:23 AM PDT 24
Peak memory 208196 kb
Host smart-4c18d4bc-cf8d-46ea-9f8e-13768248bc84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223783870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1223783870
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1162386549
Short name T754
Test name
Test status
Simulation time 201607534 ps
CPU time 4.18 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 208128 kb
Host smart-37fe934a-62ce-416f-92c7-de07653e0947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162386549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1162386549
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.913863629
Short name T423
Test name
Test status
Simulation time 119453326 ps
CPU time 2.5 seconds
Started Jul 02 07:55:57 AM PDT 24
Finished Jul 02 07:56:24 AM PDT 24
Peak memory 207944 kb
Host smart-029b1ec1-3139-4eef-9a71-9e6b1af5a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913863629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.913863629
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.662699340
Short name T830
Test name
Test status
Simulation time 17900504983 ps
CPU time 40.84 seconds
Started Jul 02 07:56:21 AM PDT 24
Finished Jul 02 07:57:24 AM PDT 24
Peak memory 222476 kb
Host smart-f94a6e52-5abd-46af-890c-26d544d58df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662699340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.662699340
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1888150855
Short name T779
Test name
Test status
Simulation time 128262691 ps
CPU time 8.12 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:40 AM PDT 24
Peak memory 222600 kb
Host smart-01ed5993-adc7-4565-9786-a088680da817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888150855 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1888150855
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2291286493
Short name T75
Test name
Test status
Simulation time 267013682 ps
CPU time 6.08 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:38 AM PDT 24
Peak memory 208516 kb
Host smart-561fd83d-7423-4556-8b51-ea99480195ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291286493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2291286493
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.613862801
Short name T886
Test name
Test status
Simulation time 146090112 ps
CPU time 3.36 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 210904 kb
Host smart-6354c149-c4ac-43fc-bda7-672efb2cde1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613862801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.613862801
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.4160842804
Short name T620
Test name
Test status
Simulation time 44603889 ps
CPU time 1.85 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:26 AM PDT 24
Peak memory 208128 kb
Host smart-4b3751f2-fcf2-4244-93c4-cd4d95a7f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160842804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4160842804
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1095730575
Short name T22
Test name
Test status
Simulation time 327662746 ps
CPU time 4.31 seconds
Started Jul 02 07:55:58 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 220252 kb
Host smart-183ac209-5d8b-472f-a971-7bd844caf383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095730575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1095730575
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3942772917
Short name T529
Test name
Test status
Simulation time 157486960 ps
CPU time 3.16 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 220540 kb
Host smart-8e2e15d3-7d7f-46d8-be34-64faf05f0d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942772917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3942772917
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1135421324
Short name T749
Test name
Test status
Simulation time 404154876 ps
CPU time 5.26 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:41 AM PDT 24
Peak memory 210460 kb
Host smart-cbfd84ed-fda4-420e-9305-5f3d1373473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135421324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1135421324
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.480591528
Short name T891
Test name
Test status
Simulation time 84391913 ps
CPU time 3.45 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 207996 kb
Host smart-dcc47983-e824-4a50-bd6d-3599e18b2679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480591528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.480591528
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.646237544
Short name T881
Test name
Test status
Simulation time 185364690 ps
CPU time 2.48 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 206712 kb
Host smart-c148c171-afac-40f0-97bd-72986741e3ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646237544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.646237544
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1409012971
Short name T655
Test name
Test status
Simulation time 37585733 ps
CPU time 2.21 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:33 AM PDT 24
Peak memory 206796 kb
Host smart-57fa1948-29c2-4425-9d0a-f8860c81a3e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409012971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1409012971
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.315089177
Short name T350
Test name
Test status
Simulation time 114750343 ps
CPU time 2.31 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 206868 kb
Host smart-c92974d0-21eb-4dae-ba6f-c71bd8f08e01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315089177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.315089177
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3559625558
Short name T713
Test name
Test status
Simulation time 412823100 ps
CPU time 4.85 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 215852 kb
Host smart-b7f4ccc3-d52e-469d-abe5-8e99fd99febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559625558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3559625558
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.653618287
Short name T410
Test name
Test status
Simulation time 114467747 ps
CPU time 2.08 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 205928 kb
Host smart-c798822a-2662-4b0b-a122-9157ffb7d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653618287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.653618287
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.176293495
Short name T759
Test name
Test status
Simulation time 4456704159 ps
CPU time 46.17 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 215620 kb
Host smart-11096c85-2db4-45f5-b2e9-940f27ed6204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176293495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.176293495
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2261801913
Short name T810
Test name
Test status
Simulation time 339845816 ps
CPU time 6.13 seconds
Started Jul 02 07:55:56 AM PDT 24
Finished Jul 02 07:56:27 AM PDT 24
Peak memory 222600 kb
Host smart-7fb057ac-c578-4a29-929c-85edeae10d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261801913 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2261801913
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1728667465
Short name T638
Test name
Test status
Simulation time 469904328 ps
CPU time 4.85 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:33 AM PDT 24
Peak memory 207320 kb
Host smart-36326572-9ca6-4eb6-bbd6-c6b8c6d5bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728667465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1728667465
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2776889023
Short name T800
Test name
Test status
Simulation time 644804117 ps
CPU time 6.23 seconds
Started Jul 02 07:55:58 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 210204 kb
Host smart-c5123a4f-5f6f-46f8-8298-0c533eda6fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776889023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2776889023
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2824770000
Short name T446
Test name
Test status
Simulation time 21845558 ps
CPU time 0.75 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 205972 kb
Host smart-06e28a3a-367b-474d-85f5-4ca68fc5217c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824770000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2824770000
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.256680855
Short name T38
Test name
Test status
Simulation time 627618169 ps
CPU time 8.97 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 214288 kb
Host smart-e35208a8-2b2d-4fff-8a4a-9872a8c53ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256680855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.256680855
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2026462611
Short name T745
Test name
Test status
Simulation time 16594053 ps
CPU time 1.58 seconds
Started Jul 02 07:56:35 AM PDT 24
Finished Jul 02 07:56:52 AM PDT 24
Peak memory 206772 kb
Host smart-30fb54a2-2080-4e2f-8155-36001d2baf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026462611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2026462611
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2986240510
Short name T581
Test name
Test status
Simulation time 30379854 ps
CPU time 1.96 seconds
Started Jul 02 07:56:29 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 214296 kb
Host smart-4ac37f5c-74fc-4f9f-8914-8ebaae4b9c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986240510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2986240510
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1159569566
Short name T267
Test name
Test status
Simulation time 190052613 ps
CPU time 3.93 seconds
Started Jul 02 07:56:26 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 222388 kb
Host smart-6958b9c4-cc9e-414b-b08d-196a64f80d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159569566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1159569566
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3744173150
Short name T103
Test name
Test status
Simulation time 684756231 ps
CPU time 21.11 seconds
Started Jul 02 07:56:44 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 222364 kb
Host smart-f888a63c-3dad-402c-9162-7f6b34cafd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744173150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3744173150
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.477100718
Short name T464
Test name
Test status
Simulation time 196089162 ps
CPU time 2.64 seconds
Started Jul 02 07:56:43 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 206860 kb
Host smart-eab40b7d-dd26-437b-b4a5-4525cbfa3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477100718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.477100718
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3127931227
Short name T718
Test name
Test status
Simulation time 137786548 ps
CPU time 2.27 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 207152 kb
Host smart-f3861a5b-3a3c-4d7f-9b03-3ae480f3e009
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127931227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3127931227
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2690226448
Short name T693
Test name
Test status
Simulation time 1437262521 ps
CPU time 4.01 seconds
Started Jul 02 07:56:28 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 206964 kb
Host smart-3cf01285-862a-4536-af2e-520dafbe4260
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690226448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2690226448
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.174137893
Short name T254
Test name
Test status
Simulation time 630019831 ps
CPU time 5.72 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 208680 kb
Host smart-98405ef3-ad27-4b37-8a8f-84c82d3f7f2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174137893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.174137893
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2878418621
Short name T263
Test name
Test status
Simulation time 93153857 ps
CPU time 2.34 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 209508 kb
Host smart-ed51f0e3-74c5-48bd-8b58-7dd7c4203fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878418621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2878418621
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.867412545
Short name T857
Test name
Test status
Simulation time 170822765 ps
CPU time 2.36 seconds
Started Jul 02 07:56:36 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 208476 kb
Host smart-0d0e55ea-e042-40bc-aee9-b6c7d1d3194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867412545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.867412545
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2775426838
Short name T48
Test name
Test status
Simulation time 968102899 ps
CPU time 34.52 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 216528 kb
Host smart-cc2ff2de-5216-4d07-b0d0-84d83eabfc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775426838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2775426838
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.961311025
Short name T81
Test name
Test status
Simulation time 118092351 ps
CPU time 8.04 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:57:02 AM PDT 24
Peak memory 222688 kb
Host smart-e8634ec8-112f-4b94-ba48-07f7d64810b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961311025 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.961311025
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1068196670
Short name T722
Test name
Test status
Simulation time 1145197505 ps
CPU time 25.08 seconds
Started Jul 02 07:56:42 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 214284 kb
Host smart-03189f83-f0e7-4265-966c-1538642f1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068196670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1068196670
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3313419435
Short name T128
Test name
Test status
Simulation time 327253072 ps
CPU time 1.57 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:02 AM PDT 24
Peak memory 209960 kb
Host smart-5500922d-cf2d-439c-8261-5e9d46f9aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313419435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3313419435
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1093330472
Short name T526
Test name
Test status
Simulation time 40218724 ps
CPU time 0.69 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 205800 kb
Host smart-cbf9ac33-e993-462d-b0b4-9a8fbeb67309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093330472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1093330472
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3981691829
Short name T250
Test name
Test status
Simulation time 181174855 ps
CPU time 3.62 seconds
Started Jul 02 07:56:42 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 214228 kb
Host smart-06de9079-ebfa-4a69-929f-bcfc656b4bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981691829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3981691829
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2022527481
Short name T257
Test name
Test status
Simulation time 673689243 ps
CPU time 2.9 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 209944 kb
Host smart-1d75b659-881b-4353-9dc4-de905d696bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022527481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2022527481
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.598172721
Short name T293
Test name
Test status
Simulation time 108632444 ps
CPU time 4.77 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 215248 kb
Host smart-d4040282-9538-447f-8f33-b396ed7f74fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598172721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.598172721
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.136633354
Short name T359
Test name
Test status
Simulation time 71415950 ps
CPU time 2.26 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 220816 kb
Host smart-19124417-b401-4845-bf03-c661863b85a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136633354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.136633354
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.127168878
Short name T223
Test name
Test status
Simulation time 1555367965 ps
CPU time 21.06 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 209680 kb
Host smart-1d9ed0f3-d08b-44f4-8159-317e11b5d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127168878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.127168878
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3241193859
Short name T586
Test name
Test status
Simulation time 122738085 ps
CPU time 4.26 seconds
Started Jul 02 07:56:29 AM PDT 24
Finished Jul 02 07:56:52 AM PDT 24
Peak memory 218132 kb
Host smart-220540d4-57b2-4e8d-867e-15bb02cfdd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241193859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3241193859
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.487153423
Short name T811
Test name
Test status
Simulation time 167841659 ps
CPU time 2.82 seconds
Started Jul 02 07:56:48 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 208632 kb
Host smart-a169b486-7484-471d-a354-856ba272f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487153423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.487153423
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4255815660
Short name T824
Test name
Test status
Simulation time 254263111 ps
CPU time 3.89 seconds
Started Jul 02 07:56:42 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 208920 kb
Host smart-d447e8d7-71b9-4d7f-bacf-54411b7e7c27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255815660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4255815660
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.354355131
Short name T567
Test name
Test status
Simulation time 6536410480 ps
CPU time 51.55 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 208988 kb
Host smart-6866e197-db81-4d83-a41d-5b74c3ed9c50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354355131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.354355131
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1386836119
Short name T433
Test name
Test status
Simulation time 49091167 ps
CPU time 2.51 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 207120 kb
Host smart-e436bad2-0686-4a43-9371-4d3e1ee71dc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386836119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1386836119
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2545682131
Short name T624
Test name
Test status
Simulation time 43343668 ps
CPU time 2.04 seconds
Started Jul 02 07:56:52 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 207428 kb
Host smart-ea8ea381-bd44-4a96-b704-94763f66951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545682131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2545682131
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3681547383
Short name T109
Test name
Test status
Simulation time 122939955 ps
CPU time 2.89 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 207008 kb
Host smart-fdf683a2-b239-4baa-9314-bb29d91f4290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681547383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3681547383
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2752972101
Short name T719
Test name
Test status
Simulation time 385355949 ps
CPU time 4.17 seconds
Started Jul 02 07:56:43 AM PDT 24
Finished Jul 02 07:57:02 AM PDT 24
Peak memory 220608 kb
Host smart-f94a0030-e8f7-4258-884f-45ac5a95ca6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752972101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2752972101
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1421528654
Short name T51
Test name
Test status
Simulation time 227798283 ps
CPU time 8.36 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 219840 kb
Host smart-cc95069a-3ed8-43e0-ab91-d4e60697a22a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421528654 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1421528654
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2843747220
Short name T501
Test name
Test status
Simulation time 319268017 ps
CPU time 4.06 seconds
Started Jul 02 07:56:36 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 208204 kb
Host smart-d952947b-a361-4e32-b554-841708c2f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843747220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2843747220
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1910362559
Short name T573
Test name
Test status
Simulation time 37084536 ps
CPU time 0.75 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 205872 kb
Host smart-9a401911-f001-47e4-9824-05f0711cdbe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910362559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1910362559
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2948669183
Short name T872
Test name
Test status
Simulation time 83726641 ps
CPU time 1.79 seconds
Started Jul 02 07:56:28 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 208144 kb
Host smart-0eb2bed8-96ef-4a15-b740-ccc2a065dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948669183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2948669183
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3783316228
Short name T46
Test name
Test status
Simulation time 367179169 ps
CPU time 2.46 seconds
Started Jul 02 07:56:32 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 214244 kb
Host smart-9e732405-e750-437c-a7c1-e07d55a56350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783316228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3783316228
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.1585219665
Short name T668
Test name
Test status
Simulation time 678883317 ps
CPU time 8.08 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 214160 kb
Host smart-fcfc7674-5246-43ef-a194-fb80dea0f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585219665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1585219665
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.738432116
Short name T734
Test name
Test status
Simulation time 331780463 ps
CPU time 4.93 seconds
Started Jul 02 07:56:30 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 207884 kb
Host smart-d384bfd5-e305-431a-9704-8c27b56b096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738432116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.738432116
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3849611897
Short name T683
Test name
Test status
Simulation time 9114353922 ps
CPU time 37.13 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:41 AM PDT 24
Peak memory 208612 kb
Host smart-f9392102-5741-4c73-b81a-9f5eb94a97b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849611897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3849611897
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4150761628
Short name T384
Test name
Test status
Simulation time 7800558753 ps
CPU time 33.79 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 208584 kb
Host smart-9b91b64a-93e4-4d63-bb02-27805faefe53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150761628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4150761628
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2823724777
Short name T905
Test name
Test status
Simulation time 132492034 ps
CPU time 2.41 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:56:57 AM PDT 24
Peak memory 206956 kb
Host smart-4aaaf1d3-874a-4894-8c6b-8f373744c385
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823724777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2823724777
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2893562502
Short name T351
Test name
Test status
Simulation time 72659797 ps
CPU time 3.22 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 209296 kb
Host smart-62542b2a-ce3d-467d-bc2c-72c1d6b79f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893562502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2893562502
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.730250440
Short name T816
Test name
Test status
Simulation time 270896845 ps
CPU time 4.4 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 208188 kb
Host smart-5f333291-cc51-45ee-9bd1-3983fe788c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730250440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.730250440
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2171570203
Short name T755
Test name
Test status
Simulation time 337811608 ps
CPU time 16.56 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 221980 kb
Host smart-35889a60-977e-4d6b-80f1-f06edea4b7c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171570203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2171570203
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2462268069
Short name T831
Test name
Test status
Simulation time 1044188909 ps
CPU time 31.75 seconds
Started Jul 02 07:56:32 AM PDT 24
Finished Jul 02 07:57:20 AM PDT 24
Peak memory 214284 kb
Host smart-4e4f676a-95e7-44c7-87e1-f73070c1043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462268069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2462268069
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3893637024
Short name T159
Test name
Test status
Simulation time 69976305 ps
CPU time 2.76 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 210460 kb
Host smart-97a4faaa-d98a-4795-a5e0-c24fcfd55637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893637024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3893637024
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1955174342
Short name T428
Test name
Test status
Simulation time 35630945 ps
CPU time 0.73 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:56:54 AM PDT 24
Peak memory 205996 kb
Host smart-54d636fe-6e86-42fb-85a0-5e5f359316c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955174342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1955174342
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2465274813
Short name T375
Test name
Test status
Simulation time 269484922 ps
CPU time 13.83 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 215420 kb
Host smart-32178d51-f0a2-4cd4-bfb7-bb6e7a437808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465274813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2465274813
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4180608579
Short name T801
Test name
Test status
Simulation time 188378721 ps
CPU time 2.81 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 208976 kb
Host smart-e1b877d6-930b-42ba-954b-b85b67aff538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180608579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4180608579
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1441763509
Short name T89
Test name
Test status
Simulation time 7809627922 ps
CPU time 22.3 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 209736 kb
Host smart-9c1e5f02-b8ff-43f5-babf-2a55d1832ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441763509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1441763509
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1248811423
Short name T294
Test name
Test status
Simulation time 49649219 ps
CPU time 1.99 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:54 AM PDT 24
Peak memory 221200 kb
Host smart-66967b8d-48c8-416a-87b9-7c71431a132c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248811423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1248811423
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1397750685
Short name T206
Test name
Test status
Simulation time 42254867 ps
CPU time 2.81 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 214220 kb
Host smart-04771c37-d4fe-4bf3-b270-5428143d6211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397750685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1397750685
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4211998003
Short name T523
Test name
Test status
Simulation time 230504373 ps
CPU time 5.84 seconds
Started Jul 02 07:56:35 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 209652 kb
Host smart-9edb213c-5d1a-415e-95e9-b12f520f8748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211998003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4211998003
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.728114978
Short name T705
Test name
Test status
Simulation time 219091899 ps
CPU time 2.78 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 206880 kb
Host smart-d64620fa-1bf5-4219-adab-0d4980e8a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728114978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.728114978
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1079925188
Short name T729
Test name
Test status
Simulation time 697810303 ps
CPU time 5.38 seconds
Started Jul 02 07:56:36 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 208512 kb
Host smart-657afd64-4be5-4a1d-80a2-e42aa19f6693
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079925188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1079925188
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.202272137
Short name T657
Test name
Test status
Simulation time 54518910 ps
CPU time 2.65 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 206852 kb
Host smart-6a35ae8b-b56d-4ff8-994b-aa04af65b4f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202272137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.202272137
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1641495246
Short name T283
Test name
Test status
Simulation time 38407564 ps
CPU time 1.68 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 209088 kb
Host smart-00980529-2ded-42c8-9f56-b490ab8326d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641495246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1641495246
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2169521462
Short name T490
Test name
Test status
Simulation time 295995504 ps
CPU time 3.61 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:56:59 AM PDT 24
Peak memory 206696 kb
Host smart-b57f15c9-540d-4724-b88f-d64332bb5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169521462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2169521462
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1817668426
Short name T690
Test name
Test status
Simulation time 2095217714 ps
CPU time 5 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:57:00 AM PDT 24
Peak memory 209984 kb
Host smart-fdbdb064-2dc2-4fa8-8957-d26af1335f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817668426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1817668426
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2496795829
Short name T34
Test name
Test status
Simulation time 128012131 ps
CPU time 2.03 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 210280 kb
Host smart-bfcef1ff-3068-4143-8889-83abf6a3000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496795829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2496795829
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3994510590
Short name T467
Test name
Test status
Simulation time 56795856 ps
CPU time 0.88 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 205972 kb
Host smart-b460f56b-eac7-4110-8ccf-362629429a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994510590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3994510590
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.471751404
Short name T27
Test name
Test status
Simulation time 414043235 ps
CPU time 3.98 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 210600 kb
Host smart-bb1473c7-1c27-4eaf-8bd5-f2869d37a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471751404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.471751404
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.566553042
Short name T83
Test name
Test status
Simulation time 1080737733 ps
CPU time 4.03 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 214176 kb
Host smart-749e7b4e-9079-4433-b9d7-3e41e1c305db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566553042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.566553042
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.1784169306
Short name T181
Test name
Test status
Simulation time 324431874 ps
CPU time 7.92 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 214328 kb
Host smart-64934c3c-735f-4538-9ee1-6ba7295cfd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784169306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1784169306
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3444685445
Short name T773
Test name
Test status
Simulation time 81423588 ps
CPU time 1.95 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 208612 kb
Host smart-6e046ce0-bd3d-4911-819b-e7be098fb886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444685445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3444685445
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1550118545
Short name T352
Test name
Test status
Simulation time 266620438 ps
CPU time 5.88 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:57:00 AM PDT 24
Peak memory 207016 kb
Host smart-13590d8a-c8c0-4fe4-87f1-4a233cb5936b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550118545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1550118545
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3931393640
Short name T884
Test name
Test status
Simulation time 23622607 ps
CPU time 1.87 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 207656 kb
Host smart-80d52d4d-5616-43f7-a995-40a6fe85b259
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931393640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3931393640
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.46142809
Short name T466
Test name
Test status
Simulation time 236036748 ps
CPU time 2.93 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 208732 kb
Host smart-ebe39ed6-518b-41af-ac2c-50d4e37fa6fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46142809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.46142809
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1864496576
Short name T407
Test name
Test status
Simulation time 477135262 ps
CPU time 3.59 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 216036 kb
Host smart-dfba86dd-a1a4-4eeb-845d-a08b50e2e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864496576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1864496576
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3706486119
Short name T514
Test name
Test status
Simulation time 296796568 ps
CPU time 3.26 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:56:57 AM PDT 24
Peak memory 206924 kb
Host smart-eafd7789-21f5-4343-aeb8-37883096856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706486119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3706486119
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2644019142
Short name T301
Test name
Test status
Simulation time 682895657 ps
CPU time 5.61 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:57:00 AM PDT 24
Peak memory 214284 kb
Host smart-53baef39-4df3-4323-92ea-fce16f3e6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644019142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2644019142
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2587966664
Short name T658
Test name
Test status
Simulation time 130026919 ps
CPU time 3.17 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 210552 kb
Host smart-3ed4ff25-d0d8-46bd-9a0f-d44aa6a7221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587966664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2587966664
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3621973362
Short name T415
Test name
Test status
Simulation time 53187952 ps
CPU time 0.77 seconds
Started Jul 02 07:56:48 AM PDT 24
Finished Jul 02 07:57:04 AM PDT 24
Peak memory 206008 kb
Host smart-2711f6ea-35c7-4058-8469-fafcecd5b66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621973362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3621973362
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4213175970
Short name T372
Test name
Test status
Simulation time 98497017 ps
CPU time 3.63 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 215348 kb
Host smart-4c38b819-1d1d-4fea-b93c-ae3660c95366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213175970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4213175970
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4188981732
Short name T778
Test name
Test status
Simulation time 190511569 ps
CPU time 4.65 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:10 AM PDT 24
Peak memory 214788 kb
Host smart-ac9ecf9e-a1a8-4aeb-b223-df83edce87f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188981732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4188981732
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1171466638
Short name T430
Test name
Test status
Simulation time 354224210 ps
CPU time 2.35 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 207624 kb
Host smart-a93ac826-1e61-437f-977e-fe157e7670b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171466638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1171466638
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1446423032
Short name T35
Test name
Test status
Simulation time 118121873 ps
CPU time 3.03 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 214532 kb
Host smart-547ea1e7-e735-4c9b-89cb-78c09386c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446423032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1446423032
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2821540913
Short name T360
Test name
Test status
Simulation time 162187442 ps
CPU time 2.38 seconds
Started Jul 02 07:56:41 AM PDT 24
Finished Jul 02 07:56:59 AM PDT 24
Peak memory 214216 kb
Host smart-2950ff2c-e1fc-478e-86bc-08476da2f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821540913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2821540913
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3727815318
Short name T214
Test name
Test status
Simulation time 454171604 ps
CPU time 5.33 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:57:00 AM PDT 24
Peak memory 219972 kb
Host smart-51a2965a-04a0-4521-80dc-35c6fe25f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727815318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3727815318
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.202709382
Short name T290
Test name
Test status
Simulation time 42939971 ps
CPU time 2.86 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:17 AM PDT 24
Peak memory 210128 kb
Host smart-b140737f-0d74-425e-a574-9f5721e4dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202709382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.202709382
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.311227557
Short name T463
Test name
Test status
Simulation time 1875661962 ps
CPU time 38.96 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 207988 kb
Host smart-76e0d497-6619-4789-8abf-c5dd2f7a265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311227557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.311227557
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3584328677
Short name T495
Test name
Test status
Simulation time 163263541 ps
CPU time 2.55 seconds
Started Jul 02 07:56:41 AM PDT 24
Finished Jul 02 07:56:59 AM PDT 24
Peak memory 207136 kb
Host smart-0e4a2486-a7ca-4e5b-94d1-9419c16ccd15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584328677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3584328677
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2985745728
Short name T785
Test name
Test status
Simulation time 221802807 ps
CPU time 2.15 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 208892 kb
Host smart-c7293175-b74d-49b4-b842-3f6c19fcbca0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985745728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2985745728
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1340419022
Short name T422
Test name
Test status
Simulation time 129150492 ps
CPU time 2.47 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 206820 kb
Host smart-9e719970-f62c-455d-95af-8940bb68916c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340419022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1340419022
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3648453278
Short name T603
Test name
Test status
Simulation time 63817623 ps
CPU time 3.03 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 208956 kb
Host smart-beca543d-ead5-4f35-881e-5ca6a1004697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648453278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3648453278
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2220829482
Short name T882
Test name
Test status
Simulation time 109660595 ps
CPU time 3.86 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 208476 kb
Host smart-ebe2c32d-4b41-40f3-afc4-83fc01903268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220829482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2220829482
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4094551374
Short name T33
Test name
Test status
Simulation time 319010227 ps
CPU time 7.34 seconds
Started Jul 02 07:56:56 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 206796 kb
Host smart-c30b86e3-4d0b-4b83-9ece-7c98884e6b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094551374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4094551374
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2457425536
Short name T209
Test name
Test status
Simulation time 1781725392 ps
CPU time 19.01 seconds
Started Jul 02 07:56:42 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 220732 kb
Host smart-1837bab3-a9ad-44c4-9a3f-e9aa6c0e4cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457425536 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2457425536
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.785348245
Short name T796
Test name
Test status
Simulation time 152954856 ps
CPU time 3.28 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:10 AM PDT 24
Peak memory 209032 kb
Host smart-4381e573-9a04-48fc-a816-2188e9d4b8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785348245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.785348245
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2550996938
Short name T169
Test name
Test status
Simulation time 163010936 ps
CPU time 2.06 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 210076 kb
Host smart-8fb4f350-034b-48d1-a049-5246a1ec5ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550996938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2550996938
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1981082588
Short name T102
Test name
Test status
Simulation time 34621754 ps
CPU time 0.71 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 206008 kb
Host smart-4f044672-0d67-4b04-9247-16bc801fbf3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981082588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1981082588
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4211191585
Short name T795
Test name
Test status
Simulation time 321482366 ps
CPU time 2.38 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 209564 kb
Host smart-72e6def7-63ea-48f7-aa3c-eeb29007c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211191585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4211191585
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1934652173
Short name T561
Test name
Test status
Simulation time 950333781 ps
CPU time 4.14 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 207484 kb
Host smart-68278bb4-a472-4b1e-aff3-3382dce1d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934652173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1934652173
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3531513252
Short name T306
Test name
Test status
Simulation time 180816468 ps
CPU time 4.5 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 207328 kb
Host smart-03e0eb1c-c226-46ed-8930-ff5cff69e10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531513252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3531513252
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.847543534
Short name T797
Test name
Test status
Simulation time 90407329 ps
CPU time 3.19 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 209236 kb
Host smart-01b2f8d9-2726-47a2-b3db-c10ff3a02028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847543534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.847543534
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2379433121
Short name T251
Test name
Test status
Simulation time 143119592 ps
CPU time 3.53 seconds
Started Jul 02 07:56:47 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 208824 kb
Host smart-43c8ae57-8d95-412d-98cd-1a95c4b893a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379433121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2379433121
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2755123349
Short name T599
Test name
Test status
Simulation time 150561155 ps
CPU time 2.39 seconds
Started Jul 02 07:56:39 AM PDT 24
Finished Jul 02 07:56:57 AM PDT 24
Peak memory 206888 kb
Host smart-86426d6f-aba2-4f6b-a509-08965cb46e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755123349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2755123349
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1445735952
Short name T461
Test name
Test status
Simulation time 689683510 ps
CPU time 7.13 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 207992 kb
Host smart-7756e824-f17f-44f6-9e01-10c2d7dbd2db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445735952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1445735952
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1887046958
Short name T635
Test name
Test status
Simulation time 86734472 ps
CPU time 2.61 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 208716 kb
Host smart-451d60b5-ad16-4826-b9ed-a95777daf953
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887046958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1887046958
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.8656487
Short name T548
Test name
Test status
Simulation time 59856746 ps
CPU time 3.06 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 206828 kb
Host smart-35ae54ea-4a0d-492f-842c-5d2b9b2c7824
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8656487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.8656487
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2227637971
Short name T879
Test name
Test status
Simulation time 555671355 ps
CPU time 4.3 seconds
Started Jul 02 07:56:47 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 215684 kb
Host smart-51505794-5cf1-46ae-bfd2-c2db99b177d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227637971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2227637971
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.108030279
Short name T500
Test name
Test status
Simulation time 144131915 ps
CPU time 2.3 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 207036 kb
Host smart-d403d4d6-73f0-4464-a041-3188bac17fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108030279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.108030279
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3618567936
Short name T296
Test name
Test status
Simulation time 42264053 ps
CPU time 2.88 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 210076 kb
Host smart-719116d9-4f19-4af1-a02b-436e731bdbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618567936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3618567936
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2333649401
Short name T40
Test name
Test status
Simulation time 178948192 ps
CPU time 3.44 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:07 AM PDT 24
Peak memory 209800 kb
Host smart-b0162cc9-34c2-42f6-8fed-c93cbf947a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333649401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2333649401
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3871088066
Short name T438
Test name
Test status
Simulation time 15349607 ps
CPU time 0.76 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 206008 kb
Host smart-20403eb8-01cb-4f48-a52a-5a507fc8a124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871088066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3871088066
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3175616682
Short name T698
Test name
Test status
Simulation time 112175279 ps
CPU time 2.69 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 214340 kb
Host smart-d5adbe78-e8d0-4fa0-bab8-584a62e683f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175616682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3175616682
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.940492199
Short name T69
Test name
Test status
Simulation time 69854525 ps
CPU time 1.5 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 208520 kb
Host smart-f8ca2d77-1c71-42a8-9ede-af670c25f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940492199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.940492199
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3325484333
Short name T92
Test name
Test status
Simulation time 1435473376 ps
CPU time 5.49 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:10 AM PDT 24
Peak memory 221492 kb
Host smart-aef4f458-4113-432d-be0d-ccc325408fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325484333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3325484333
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.201803216
Short name T856
Test name
Test status
Simulation time 89146350 ps
CPU time 4.07 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 209460 kb
Host smart-6fb9e1c8-1a01-4c34-b091-365baf0ecd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201803216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.201803216
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3832243141
Short name T774
Test name
Test status
Simulation time 189847111 ps
CPU time 6.16 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:17 AM PDT 24
Peak memory 208136 kb
Host smart-bbb3b75f-c1bb-4439-8e68-b7320018ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832243141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3832243141
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3801648157
Short name T520
Test name
Test status
Simulation time 452908560 ps
CPU time 7.47 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 207992 kb
Host smart-1681e5f9-3bac-482f-a0a7-e674ce7bf082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801648157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3801648157
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1060195040
Short name T569
Test name
Test status
Simulation time 628906323 ps
CPU time 4.78 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 208884 kb
Host smart-d727da3f-a492-4e28-9266-24e78566c694
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060195040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1060195040
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.681086867
Short name T192
Test name
Test status
Simulation time 955748542 ps
CPU time 3.42 seconds
Started Jul 02 07:56:46 AM PDT 24
Finished Jul 02 07:57:04 AM PDT 24
Peak memory 207592 kb
Host smart-a4c1b76f-faa5-4fbb-8d21-6856a087cefd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681086867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.681086867
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1239419652
Short name T199
Test name
Test status
Simulation time 265033870 ps
CPU time 4.38 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 208528 kb
Host smart-398178e7-7be3-43ed-897a-61780fab50fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239419652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1239419652
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.467060362
Short name T799
Test name
Test status
Simulation time 269528698 ps
CPU time 6.32 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 208852 kb
Host smart-d519791e-8ac8-4551-8442-f6beb72b3251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467060362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.467060362
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1106930686
Short name T473
Test name
Test status
Simulation time 890095056 ps
CPU time 3.46 seconds
Started Jul 02 07:56:45 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 206876 kb
Host smart-50f4d00e-0c68-466a-99df-1b905ce59beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106930686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1106930686
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3967372747
Short name T177
Test name
Test status
Simulation time 824261545 ps
CPU time 14.05 seconds
Started Jul 02 07:56:52 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 219600 kb
Host smart-4d387836-ac69-48d4-bf09-7f82b0ef567a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967372747 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3967372747
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2024006395
Short name T337
Test name
Test status
Simulation time 264513763 ps
CPU time 4.44 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:10 AM PDT 24
Peak memory 208640 kb
Host smart-e27c708b-15d9-4159-927e-e6b5f0dd43b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024006395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2024006395
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1688609612
Short name T465
Test name
Test status
Simulation time 61303796 ps
CPU time 3.11 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 210408 kb
Host smart-d993fe33-9ca9-4ca7-8a15-19526210ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688609612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1688609612
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3803801163
Short name T904
Test name
Test status
Simulation time 19930480 ps
CPU time 0.83 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 205900 kb
Host smart-c0c6397b-1ea3-447e-beb7-6869a8ee88ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803801163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3803801163
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4209285127
Short name T378
Test name
Test status
Simulation time 224129158 ps
CPU time 4.38 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 214624 kb
Host smart-7eb45269-303c-48ef-a937-dd4c99a5ae9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209285127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4209285127
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1536947500
Short name T762
Test name
Test status
Simulation time 61526847 ps
CPU time 2.99 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 218520 kb
Host smart-5e90c36b-e78b-493b-87fd-a233f96e3c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536947500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1536947500
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1819955967
Short name T44
Test name
Test status
Simulation time 141105879 ps
CPU time 3.84 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 209368 kb
Host smart-4023ed62-547b-49c7-bdd9-d9315aba2d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819955967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1819955967
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1097690829
Short name T357
Test name
Test status
Simulation time 105827183 ps
CPU time 5.05 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 214348 kb
Host smart-24c0e7f7-4fa8-4e88-87c6-181e42b9c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097690829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1097690829
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1779552200
Short name T853
Test name
Test status
Simulation time 111541312 ps
CPU time 4.08 seconds
Started Jul 02 07:56:48 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 214200 kb
Host smart-ca2f906d-3265-4e69-96ff-360f6682ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779552200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1779552200
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.622450508
Short name T863
Test name
Test status
Simulation time 174455579 ps
CPU time 4.1 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 210096 kb
Host smart-a3de6af2-f251-485f-bf49-b2b3ff5ba46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622450508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.622450508
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.594483416
Short name T874
Test name
Test status
Simulation time 69772707 ps
CPU time 3.46 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 206968 kb
Host smart-3adb0798-42a2-4c83-b2ad-244d29529893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594483416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.594483416
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2037229708
Short name T764
Test name
Test status
Simulation time 49472377 ps
CPU time 2.52 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:57:17 AM PDT 24
Peak memory 206972 kb
Host smart-f6d8c42c-52db-44c5-81c6-dda9d61907f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037229708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2037229708
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3194152216
Short name T855
Test name
Test status
Simulation time 7506673923 ps
CPU time 69.88 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 209316 kb
Host smart-64b32bfe-26e3-4db6-a6f0-b535099ecee9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194152216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3194152216
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3528007832
Short name T791
Test name
Test status
Simulation time 213695022 ps
CPU time 2.76 seconds
Started Jul 02 07:57:01 AM PDT 24
Finished Jul 02 07:57:20 AM PDT 24
Peak memory 206840 kb
Host smart-7efe423b-6559-4917-9886-82389cb871fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528007832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3528007832
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1479565305
Short name T739
Test name
Test status
Simulation time 4962947064 ps
CPU time 64.03 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 208680 kb
Host smart-5e520492-c6b5-4d05-a5e7-5a099dec762b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479565305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1479565305
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4131612430
Short name T560
Test name
Test status
Simulation time 51451779 ps
CPU time 2.37 seconds
Started Jul 02 07:56:52 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 208356 kb
Host smart-cb969494-ade2-4236-a576-39ce45ad84ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131612430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4131612430
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2371120005
Short name T871
Test name
Test status
Simulation time 47697781 ps
CPU time 1.71 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 206724 kb
Host smart-71194abc-4f42-45b7-84c4-47a4314e0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371120005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2371120005
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2752759907
Short name T253
Test name
Test status
Simulation time 96364426 ps
CPU time 3.23 seconds
Started Jul 02 07:57:19 AM PDT 24
Finished Jul 02 07:57:37 AM PDT 24
Peak memory 214316 kb
Host smart-662653ae-473a-4c39-99b6-58ada3023805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752759907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2752759907
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4219336330
Short name T166
Test name
Test status
Simulation time 229822839 ps
CPU time 2.1 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 210404 kb
Host smart-eb415d60-434e-4933-b466-49aef988d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219336330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4219336330
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2826510633
Short name T589
Test name
Test status
Simulation time 40291749 ps
CPU time 0.75 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 205896 kb
Host smart-a1ea2b94-e678-49b4-9406-6e9664fe5b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826510633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2826510633
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.355216764
Short name T394
Test name
Test status
Simulation time 1485459883 ps
CPU time 16.8 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 214320 kb
Host smart-38ce1e09-b278-4088-838e-89a16b19c17d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355216764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.355216764
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.522289558
Short name T256
Test name
Test status
Simulation time 155951332 ps
CPU time 1.95 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 209724 kb
Host smart-78c456af-8e74-4022-a6fd-eaf68c233420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522289558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.522289558
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.305344768
Short name T459
Test name
Test status
Simulation time 262410676 ps
CPU time 3.81 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 206728 kb
Host smart-f26d6d29-a004-4cd7-96cd-a03c2d20abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305344768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.305344768
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1817392486
Short name T821
Test name
Test status
Simulation time 1806282498 ps
CPU time 5.83 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 222388 kb
Host smart-43eb979b-a458-489b-9918-f60b67b78b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817392486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1817392486
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.433904543
Short name T265
Test name
Test status
Simulation time 254031336 ps
CPU time 3.28 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 208480 kb
Host smart-2ad65409-f978-4003-8676-3139795df6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433904543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.433904543
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.199083913
Short name T476
Test name
Test status
Simulation time 297504583 ps
CPU time 5.15 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 208432 kb
Host smart-43448956-2f4c-4180-b64f-39ab564eca1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199083913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.199083913
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.788613943
Short name T835
Test name
Test status
Simulation time 137039029 ps
CPU time 2.44 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 206796 kb
Host smart-f96ac9fe-eb9a-4777-a757-11bf202f1a8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788613943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.788613943
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1787751640
Short name T708
Test name
Test status
Simulation time 103062404 ps
CPU time 2.76 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 206940 kb
Host smart-62438001-1147-4582-bd0e-93576643591c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787751640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1787751640
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1907685264
Short name T838
Test name
Test status
Simulation time 143660021 ps
CPU time 2.15 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 207924 kb
Host smart-acd7bbe8-60b7-451c-af51-2695bc55bb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907685264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1907685264
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1405552821
Short name T418
Test name
Test status
Simulation time 139501080 ps
CPU time 3.52 seconds
Started Jul 02 07:56:50 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 208124 kb
Host smart-a3b15299-55ce-4abc-a337-1d37e08139c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405552821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1405552821
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2280750899
Short name T54
Test name
Test status
Simulation time 152942766 ps
CPU time 3.58 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:13 AM PDT 24
Peak memory 217272 kb
Host smart-de4adea8-9965-4f0d-ad6e-befe1bd13e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280750899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2280750899
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.134171744
Short name T216
Test name
Test status
Simulation time 302695717 ps
CPU time 17.51 seconds
Started Jul 02 07:56:53 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 222540 kb
Host smart-afaff6f4-f680-4935-af85-57d84fbd6804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134171744 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.134171744
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4054260535
Short name T469
Test name
Test status
Simulation time 68464881 ps
CPU time 2.37 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 207880 kb
Host smart-e6142b55-114a-4eb9-aba4-c89ac39e374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054260535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4054260535
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2651423442
Short name T363
Test name
Test status
Simulation time 236114305 ps
CPU time 2.71 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:12 AM PDT 24
Peak memory 211028 kb
Host smart-977db28d-d3cd-4cc1-82a0-ca4d51798726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651423442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2651423442
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.325652019
Short name T577
Test name
Test status
Simulation time 123333494 ps
CPU time 0.91 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:32 AM PDT 24
Peak memory 205896 kb
Host smart-125f04b2-3296-43f4-8613-40798c497cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325652019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.325652019
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1193786103
Short name T402
Test name
Test status
Simulation time 86063850 ps
CPU time 3.35 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 215416 kb
Host smart-e11ce870-4892-429c-82c7-afcfc7940de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193786103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1193786103
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.43182780
Short name T71
Test name
Test status
Simulation time 516365758 ps
CPU time 6.19 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 209136 kb
Host smart-844b2d32-4fa2-476b-a6e6-bb845a7da1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43182780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.43182780
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.602875684
Short name T238
Test name
Test status
Simulation time 233737498 ps
CPU time 2.51 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 214772 kb
Host smart-7794801f-9ba6-44e3-854d-a7be8d5d0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602875684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.602875684
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3067589994
Short name T686
Test name
Test status
Simulation time 130715849 ps
CPU time 3.53 seconds
Started Jul 02 07:56:04 AM PDT 24
Finished Jul 02 07:56:34 AM PDT 24
Peak memory 214448 kb
Host smart-5c6dd0b2-3ecc-4305-a0c3-d862c4be7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067589994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3067589994
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1646750176
Short name T226
Test name
Test status
Simulation time 76252432 ps
CPU time 3.26 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 218072 kb
Host smart-2058e25c-b0ca-44d7-a3d8-8ea771c85c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646750176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1646750176
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3418302313
Short name T197
Test name
Test status
Simulation time 1431132736 ps
CPU time 8.59 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 208532 kb
Host smart-1bbd7626-bc3c-428e-aeca-25ee9c5d379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418302313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3418302313
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2245353559
Short name T9
Test name
Test status
Simulation time 1066208085 ps
CPU time 6.86 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:40 AM PDT 24
Peak memory 230780 kb
Host smart-2376c7ef-911a-47cb-85cf-ba1346cd4679
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245353559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2245353559
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1822121684
Short name T235
Test name
Test status
Simulation time 318520862 ps
CPU time 2.9 seconds
Started Jul 02 07:55:56 AM PDT 24
Finished Jul 02 07:56:24 AM PDT 24
Peak memory 206780 kb
Host smart-ef5d8b49-0ded-4595-a6b3-683ed40f9aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822121684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1822121684
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1956021908
Short name T568
Test name
Test status
Simulation time 75577156 ps
CPU time 3.52 seconds
Started Jul 02 07:56:15 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 208708 kb
Host smart-87151695-b70c-4e39-af46-d446f4189ac2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956021908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1956021908
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4039290495
Short name T385
Test name
Test status
Simulation time 147524977 ps
CPU time 4.58 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 208748 kb
Host smart-8d8e6778-997d-446a-938d-7c938b58b0c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039290495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4039290495
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1253233743
Short name T424
Test name
Test status
Simulation time 903930037 ps
CPU time 4.73 seconds
Started Jul 02 07:56:07 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 206792 kb
Host smart-0f80d483-bd4a-48df-8d90-62beeddd1002
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253233743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1253233743
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4047004362
Short name T346
Test name
Test status
Simulation time 176145215 ps
CPU time 2.7 seconds
Started Jul 02 07:56:04 AM PDT 24
Finished Jul 02 07:56:33 AM PDT 24
Peak memory 218228 kb
Host smart-582f9b41-ae1d-4a61-bb5d-467555cb4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047004362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4047004362
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3175205891
Short name T517
Test name
Test status
Simulation time 21576848 ps
CPU time 1.69 seconds
Started Jul 02 07:55:59 AM PDT 24
Finished Jul 02 07:56:26 AM PDT 24
Peak memory 206644 kb
Host smart-57eda626-6d4a-4d3f-978d-01ce8532cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175205891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3175205891
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1482888362
Short name T728
Test name
Test status
Simulation time 510140390 ps
CPU time 7.92 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:41 AM PDT 24
Peak memory 215704 kb
Host smart-2d27ed89-92a2-4b9c-9b93-4c29353d390a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482888362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1482888362
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1570393003
Short name T578
Test name
Test status
Simulation time 188215654 ps
CPU time 3.29 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 208060 kb
Host smart-a0e9aeae-1d93-4d7d-8d4b-c3571552dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570393003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1570393003
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2645184068
Short name T105
Test name
Test status
Simulation time 62820571 ps
CPU time 2.41 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 209876 kb
Host smart-8ac7b26b-c8a9-43b5-82d2-9615ba831d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645184068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2645184068
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1994622311
Short name T435
Test name
Test status
Simulation time 27238434 ps
CPU time 0.91 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 205868 kb
Host smart-fab98567-a153-4818-b3f6-912b56a45f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994622311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1994622311
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3317190551
Short name T319
Test name
Test status
Simulation time 627974057 ps
CPU time 3.96 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:10 AM PDT 24
Peak memory 207056 kb
Host smart-abd119bb-b0d5-4af9-85fb-7aa5dca5ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317190551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3317190551
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4191450406
Short name T726
Test name
Test status
Simulation time 68380462 ps
CPU time 1.35 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 214320 kb
Host smart-3ce9ee50-81d5-49b6-99ca-895000928155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191450406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4191450406
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3933187647
Short name T342
Test name
Test status
Simulation time 1998786120 ps
CPU time 14.77 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 220608 kb
Host smart-e19e0178-45cb-4551-badc-aa770be2e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933187647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3933187647
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1427634824
Short name T906
Test name
Test status
Simulation time 186358847 ps
CPU time 2.43 seconds
Started Jul 02 07:56:56 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 206480 kb
Host smart-0a8371fb-80cd-4945-a134-762d4dc7fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427634824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1427634824
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2332502244
Short name T269
Test name
Test status
Simulation time 126515512 ps
CPU time 5.42 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 208944 kb
Host smart-b49286d3-efcf-43a9-9477-055f287aac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332502244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2332502244
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2405042465
Short name T902
Test name
Test status
Simulation time 3743819725 ps
CPU time 7.26 seconds
Started Jul 02 07:56:56 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 208728 kb
Host smart-26fa8c93-f782-4979-ac62-e296555151c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405042465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2405042465
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2780049051
Short name T392
Test name
Test status
Simulation time 31411384 ps
CPU time 2.15 seconds
Started Jul 02 07:57:07 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 206940 kb
Host smart-8d70a20b-75ed-4711-b742-e2492f87274f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780049051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2780049051
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1755473782
Short name T617
Test name
Test status
Simulation time 32486781 ps
CPU time 2.26 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 207364 kb
Host smart-7b216a91-8650-47cb-94fe-343f99ef8fd3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755473782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1755473782
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1501078935
Short name T650
Test name
Test status
Simulation time 740700599 ps
CPU time 8.14 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 208300 kb
Host smart-5935375d-f0bc-4ca1-9e9e-2c34b7744695
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501078935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1501078935
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1225488232
Short name T431
Test name
Test status
Simulation time 103757352 ps
CPU time 2.04 seconds
Started Jul 02 07:57:01 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 207720 kb
Host smart-edafadf2-cb71-4391-b923-65ce1cfd611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225488232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1225488232
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2105983153
Short name T471
Test name
Test status
Simulation time 80726714 ps
CPU time 3.23 seconds
Started Jul 02 07:56:55 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 208244 kb
Host smart-b6444f0b-8826-4e2c-9564-182a24f407a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105983153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2105983153
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.4102711563
Short name T757
Test name
Test status
Simulation time 861643770 ps
CPU time 8.14 seconds
Started Jul 02 07:56:56 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 222508 kb
Host smart-1d238bfa-2e72-47fd-a5e1-998118915e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102711563 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.4102711563
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1440811014
Short name T741
Test name
Test status
Simulation time 323169360 ps
CPU time 8.02 seconds
Started Jul 02 07:56:54 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 214288 kb
Host smart-79b45712-b34a-4b68-a38a-c88a024ace0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440811014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1440811014
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1646369792
Short name T815
Test name
Test status
Simulation time 47454795 ps
CPU time 2.82 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 210500 kb
Host smart-e513e536-b8f3-4ab6-881d-caed6e673266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646369792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1646369792
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3766502481
Short name T505
Test name
Test status
Simulation time 30933828 ps
CPU time 0.71 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 205968 kb
Host smart-ceef6bc3-9adf-4cc6-8327-8060781c6345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766502481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3766502481
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3337229158
Short name T374
Test name
Test status
Simulation time 947841254 ps
CPU time 13.49 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 215504 kb
Host smart-54394faf-e9e4-4f3a-b116-df63949b2f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337229158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3337229158
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2093765704
Short name T37
Test name
Test status
Simulation time 113717674 ps
CPU time 3.91 seconds
Started Jul 02 07:57:15 AM PDT 24
Finished Jul 02 07:57:34 AM PDT 24
Peak memory 209276 kb
Host smart-230feda3-e5e0-4b8d-a84b-3de60e3baec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093765704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2093765704
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1347225646
Short name T61
Test name
Test status
Simulation time 3002868631 ps
CPU time 20.24 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 218404 kb
Host smart-935eafdf-7b3c-47e4-8558-0442bc712c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347225646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1347225646
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3219810795
Short name T695
Test name
Test status
Simulation time 93246720 ps
CPU time 2.24 seconds
Started Jul 02 07:57:01 AM PDT 24
Finished Jul 02 07:57:20 AM PDT 24
Peak memory 214320 kb
Host smart-ded5a99b-dd9c-4d78-8b37-9a32189defda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219810795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3219810795
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.228064915
Short name T565
Test name
Test status
Simulation time 58265277 ps
CPU time 2.89 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 222356 kb
Host smart-55f82c66-c3f7-4b91-b0be-e6562c2679dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228064915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.228064915
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1451438409
Short name T649
Test name
Test status
Simulation time 129548428 ps
CPU time 2.38 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 220208 kb
Host smart-f30fc6f4-77ad-4a68-90bd-3a7a33ccb15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451438409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1451438409
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1705575492
Short name T304
Test name
Test status
Simulation time 332657205 ps
CPU time 4.23 seconds
Started Jul 02 07:56:59 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 207852 kb
Host smart-2243066f-fb5d-46f4-84ca-c0cafbab64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705575492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1705575492
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.287754033
Short name T552
Test name
Test status
Simulation time 388558115 ps
CPU time 3.51 seconds
Started Jul 02 07:57:06 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 208772 kb
Host smart-0ec971bb-e6ff-40e9-9d46-6be4474be106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287754033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.287754033
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1556640452
Short name T106
Test name
Test status
Simulation time 36618702 ps
CPU time 2.62 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:21 AM PDT 24
Peak memory 208832 kb
Host smart-c46ab15e-9a66-459e-9138-e36ec4789d2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556640452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1556640452
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2842654802
Short name T712
Test name
Test status
Simulation time 358713829 ps
CPU time 3.4 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:23 AM PDT 24
Peak memory 207020 kb
Host smart-d1fed49a-e833-4918-baba-b0b393ed7051
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842654802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2842654802
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4100672375
Short name T844
Test name
Test status
Simulation time 1864076745 ps
CPU time 14.7 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 214196 kb
Host smart-4f24f178-a925-47dd-9727-3db943a102fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100672375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4100672375
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3875946831
Short name T483
Test name
Test status
Simulation time 226408133 ps
CPU time 2.89 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 208700 kb
Host smart-5395c706-3f34-42f7-b5e0-b1241271a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875946831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3875946831
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3010595111
Short name T340
Test name
Test status
Simulation time 162432360 ps
CPU time 5.06 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:23 AM PDT 24
Peak memory 214176 kb
Host smart-e17bf150-dd4a-4625-90df-bee5a6826a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010595111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3010595111
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1230638810
Short name T127
Test name
Test status
Simulation time 50829019 ps
CPU time 1.91 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:20 AM PDT 24
Peak memory 209908 kb
Host smart-02edfd30-d11e-4ca5-8d5e-184fde63a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230638810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1230638810
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1921937714
Short name T852
Test name
Test status
Simulation time 14050565 ps
CPU time 0.73 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 205944 kb
Host smart-4b4195ed-e953-4bbc-adbc-035033de087e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921937714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1921937714
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1462113022
Short name T329
Test name
Test status
Simulation time 623407522 ps
CPU time 5.96 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:24 AM PDT 24
Peak memory 214164 kb
Host smart-00a40db7-2a3d-475b-a67b-f9441036296a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462113022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1462113022
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.418583076
Short name T909
Test name
Test status
Simulation time 324602010 ps
CPU time 5.24 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:23 AM PDT 24
Peak memory 209060 kb
Host smart-f030e126-971c-4181-a6f5-dc0f1e397ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418583076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.418583076
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3914332521
Short name T90
Test name
Test status
Simulation time 1246337263 ps
CPU time 9.82 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:37 AM PDT 24
Peak memory 218700 kb
Host smart-7dc3d112-d5db-4b7c-b4e5-8426b4601c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914332521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3914332521
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.334726456
Short name T711
Test name
Test status
Simulation time 139766088 ps
CPU time 2.99 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 214312 kb
Host smart-d40fecbd-3066-4362-9872-b3eb7becf54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334726456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.334726456
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3666995168
Short name T389
Test name
Test status
Simulation time 35989955 ps
CPU time 2.68 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:17 AM PDT 24
Peak memory 208384 kb
Host smart-fb0815bb-2b1b-48f0-804f-6f33d04e1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666995168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3666995168
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1105824356
Short name T540
Test name
Test status
Simulation time 49585564 ps
CPU time 2.86 seconds
Started Jul 02 07:56:58 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 207440 kb
Host smart-7d78a15a-fe1e-425e-b825-e68568b3d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105824356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1105824356
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3851514319
Short name T814
Test name
Test status
Simulation time 7050200219 ps
CPU time 42.91 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 208868 kb
Host smart-541a9d0a-6de3-4bb1-9bc1-f15424a8e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851514319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3851514319
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1503246063
Short name T245
Test name
Test status
Simulation time 210784999 ps
CPU time 6.03 seconds
Started Jul 02 07:56:57 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 208500 kb
Host smart-11f53ec5-3906-49bb-8934-55b5686af5d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503246063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1503246063
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4232660240
Short name T282
Test name
Test status
Simulation time 147046458 ps
CPU time 3.99 seconds
Started Jul 02 07:57:06 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 208524 kb
Host smart-8973d233-a1cd-4631-b0af-1579d7d8dd9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232660240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4232660240
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.473096728
Short name T665
Test name
Test status
Simulation time 697355163 ps
CPU time 12.96 seconds
Started Jul 02 07:57:33 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 208192 kb
Host smart-d4cb772a-be0d-4374-b182-5983638ef59c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473096728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.473096728
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.812172967
Short name T812
Test name
Test status
Simulation time 119438607 ps
CPU time 2.21 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:18 AM PDT 24
Peak memory 208368 kb
Host smart-79538ff3-e033-4f57-8ee4-5a3cccd7cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812172967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.812172967
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.300322197
Short name T455
Test name
Test status
Simulation time 101186923 ps
CPU time 2.77 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 206828 kb
Host smart-ec920f30-e743-4f10-b369-a752b92ab877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300322197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.300322197
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2921890776
Short name T398
Test name
Test status
Simulation time 581677747 ps
CPU time 4.7 seconds
Started Jul 02 07:57:09 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 210392 kb
Host smart-27facec0-4083-43fe-81d4-170f45d51f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921890776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2921890776
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3951166053
Short name T369
Test name
Test status
Simulation time 538564891 ps
CPU time 1.9 seconds
Started Jul 02 07:57:01 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 209752 kb
Host smart-0f1b5359-9b36-49d9-8871-bab9edc00883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951166053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3951166053
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2349807227
Short name T533
Test name
Test status
Simulation time 13480180 ps
CPU time 0.71 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 205868 kb
Host smart-e3e00ad0-c8df-4ddb-8ef2-2fe7b15d537d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349807227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2349807227
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.652244535
Short name T68
Test name
Test status
Simulation time 897684491 ps
CPU time 3.42 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 209616 kb
Host smart-806c5b13-8dce-4b03-89c9-5c4e28fea711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652244535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.652244535
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3003568231
Short name T97
Test name
Test status
Simulation time 552761222 ps
CPU time 15.16 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 214288 kb
Host smart-6f5f1ce7-1a39-4b2e-a813-b4c805a63cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003568231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3003568231
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1936908393
Short name T381
Test name
Test status
Simulation time 315851170 ps
CPU time 4.18 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 222324 kb
Host smart-26c39aad-3b6e-46d4-b59f-16ff7796bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936908393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1936908393
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.795321939
Short name T212
Test name
Test status
Simulation time 178338687 ps
CPU time 3.81 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 210044 kb
Host smart-f4df1c92-b1c8-4847-b115-db9d243d8b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795321939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.795321939
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1730415904
Short name T896
Test name
Test status
Simulation time 223198941 ps
CPU time 5.87 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 210296 kb
Host smart-1d3f1e20-ea4d-46ba-8523-fa5996f9e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730415904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1730415904
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.785191648
Short name T685
Test name
Test status
Simulation time 220173640 ps
CPU time 2.11 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 206840 kb
Host smart-49bdd9e2-1b73-47ea-bd0e-64cd702619aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785191648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.785191648
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1043627796
Short name T598
Test name
Test status
Simulation time 108020905 ps
CPU time 3.05 seconds
Started Jul 02 07:57:00 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 206956 kb
Host smart-6e982141-80c6-4113-af04-1e58ce60b6c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043627796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1043627796
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4105349826
Short name T248
Test name
Test status
Simulation time 2439583887 ps
CPU time 15.87 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:41 AM PDT 24
Peak memory 208912 kb
Host smart-048563f4-2572-4e4a-a937-a04760764c99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105349826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4105349826
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3129637131
Short name T903
Test name
Test status
Simulation time 210102483 ps
CPU time 7.3 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 208700 kb
Host smart-fd4100c5-e368-4b4a-b7b4-4d0b30b00607
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129637131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3129637131
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1686751219
Short name T188
Test name
Test status
Simulation time 62859219 ps
CPU time 2.24 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 207020 kb
Host smart-94f8ebbf-111f-4c88-89ad-a73e281fcc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686751219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1686751219
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1418777256
Short name T637
Test name
Test status
Simulation time 245027613 ps
CPU time 2.77 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 207928 kb
Host smart-0c904cbc-54de-4351-9c23-8d617c0c6b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418777256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1418777256
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2985618947
Short name T298
Test name
Test status
Simulation time 8062837444 ps
CPU time 80.98 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:58:42 AM PDT 24
Peak memory 222436 kb
Host smart-6e5548f9-e14c-4685-ab26-6d58b12c21ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985618947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2985618947
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.688058466
Short name T790
Test name
Test status
Simulation time 61515462 ps
CPU time 2.26 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 207988 kb
Host smart-cf151df1-fb1b-4091-8488-99979c354790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688058466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.688058466
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.75254667
Short name T365
Test name
Test status
Simulation time 95670233 ps
CPU time 2.05 seconds
Started Jul 02 07:57:19 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 210436 kb
Host smart-0a1367b8-76ba-48e9-9171-4b4942605481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75254667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.75254667
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3274641654
Short name T450
Test name
Test status
Simulation time 80577284 ps
CPU time 0.9 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 205872 kb
Host smart-877a1041-9219-4d77-bcc4-4200e4085bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274641654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3274641654
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1001663098
Short name T643
Test name
Test status
Simulation time 57734865 ps
CPU time 2.46 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:21 AM PDT 24
Peak memory 214320 kb
Host smart-c8f6eb55-b237-4a56-bb96-e8c7335f6626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001663098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1001663098
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3894226243
Short name T31
Test name
Test status
Simulation time 70163504 ps
CPU time 3.81 seconds
Started Jul 02 07:57:02 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 210032 kb
Host smart-bdde25b9-8c04-48bf-ba35-bdaa1b4ea8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894226243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3894226243
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2540711390
Short name T647
Test name
Test status
Simulation time 88675883 ps
CPU time 3.9 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 214284 kb
Host smart-9513c806-cb6f-49ac-b0a6-6d3e036bb982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540711390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2540711390
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1281037944
Short name T86
Test name
Test status
Simulation time 30166889 ps
CPU time 2.13 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 214620 kb
Host smart-e9daa7fe-35aa-4b1b-a701-da1611d6a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281037944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1281037944
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3753769436
Short name T820
Test name
Test status
Simulation time 138206282 ps
CPU time 6.2 seconds
Started Jul 02 07:57:09 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 210104 kb
Host smart-c923e98b-9b0a-4bee-bb99-e85993878059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753769436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3753769436
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2801448729
Short name T252
Test name
Test status
Simulation time 1745603480 ps
CPU time 8.15 seconds
Started Jul 02 07:57:09 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 208548 kb
Host smart-10820f85-991a-4c94-b96a-2ab5a4e91bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801448729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2801448729
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1291115474
Short name T426
Test name
Test status
Simulation time 24088991 ps
CPU time 1.87 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 206776 kb
Host smart-8721efec-af3f-458e-afcc-b02ff79b0d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291115474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1291115474
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3948031834
Short name T104
Test name
Test status
Simulation time 2121360561 ps
CPU time 49.73 seconds
Started Jul 02 07:57:04 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 208992 kb
Host smart-9d20c2bb-e8a9-4b44-beef-5b29a528c8bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948031834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3948031834
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4232786688
Short name T687
Test name
Test status
Simulation time 110285252 ps
CPU time 3.95 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 206916 kb
Host smart-b9dad2c8-accc-40e2-9709-cf6f0efb62e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232786688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4232786688
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3671639831
Short name T697
Test name
Test status
Simulation time 113407723 ps
CPU time 3.93 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 208636 kb
Host smart-da049a07-3746-49fd-ae8e-16d767c681f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671639831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3671639831
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.291140838
Short name T187
Test name
Test status
Simulation time 410890799 ps
CPU time 8.96 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:38 AM PDT 24
Peak memory 208208 kb
Host smart-ec3c3d0c-ab16-4634-92c0-cad494d0274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291140838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.291140838
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1731184201
Short name T640
Test name
Test status
Simulation time 246602731 ps
CPU time 2.64 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 206784 kb
Host smart-e9bb9f20-0ef0-4212-b2d8-49d052e70a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731184201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1731184201
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.320347918
Short name T535
Test name
Test status
Simulation time 4081850773 ps
CPU time 22.96 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 222592 kb
Host smart-a63bedda-4e23-448b-a862-1121163cd2a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320347918 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.320347918
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3368452374
Short name T478
Test name
Test status
Simulation time 1085903377 ps
CPU time 6.34 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 208752 kb
Host smart-fbd4367e-47c3-48f6-9c43-0737b1aa22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368452374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3368452374
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.4109254642
Short name T563
Test name
Test status
Simulation time 91098760 ps
CPU time 1.72 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 209880 kb
Host smart-51b47549-5009-4795-9725-79ac5463ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109254642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.4109254642
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2546237280
Short name T419
Test name
Test status
Simulation time 201281258 ps
CPU time 0.91 seconds
Started Jul 02 07:57:23 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 205972 kb
Host smart-1168124f-498c-4b52-a472-c38e1fee208e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546237280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2546237280
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3950627961
Short name T404
Test name
Test status
Simulation time 576115621 ps
CPU time 5.1 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:32 AM PDT 24
Peak memory 215252 kb
Host smart-d6ca22d5-028c-4152-8f18-af135d8d226e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950627961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3950627961
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1507179123
Short name T213
Test name
Test status
Simulation time 105513099 ps
CPU time 2.66 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 214316 kb
Host smart-584a9fb8-9b27-4344-a14f-ff1d24374647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507179123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1507179123
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1542623071
Short name T644
Test name
Test status
Simulation time 338844574 ps
CPU time 4.19 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 218148 kb
Host smart-9dd34f2e-2d1d-42d0-b6a3-01367248c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542623071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1542623071
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3922521854
Short name T98
Test name
Test status
Simulation time 594839751 ps
CPU time 16.05 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 209576 kb
Host smart-e1c92a1c-7927-4bab-af05-5d676ecdee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922521854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3922521854
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1182874278
Short name T724
Test name
Test status
Simulation time 164213101 ps
CPU time 3.19 seconds
Started Jul 02 07:57:06 AM PDT 24
Finished Jul 02 07:57:25 AM PDT 24
Peak memory 214272 kb
Host smart-0690a1b4-4c28-4477-97b8-9ac28421c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182874278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1182874278
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2321871277
Short name T482
Test name
Test status
Simulation time 234394683 ps
CPU time 3.43 seconds
Started Jul 02 07:57:15 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 217936 kb
Host smart-3fe351a2-342c-42fb-a286-4e1e8e813c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321871277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2321871277
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2056827056
Short name T513
Test name
Test status
Simulation time 314210943 ps
CPU time 4.1 seconds
Started Jul 02 07:57:15 AM PDT 24
Finished Jul 02 07:57:34 AM PDT 24
Peak memory 207416 kb
Host smart-3fbb5983-b735-41f5-afe0-df79d27737b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056827056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2056827056
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3685504224
Short name T249
Test name
Test status
Simulation time 79694963 ps
CPU time 2.22 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 206840 kb
Host smart-83d19f86-2c29-4e0b-a1e5-88dd436d59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685504224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3685504224
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2577180974
Short name T353
Test name
Test status
Simulation time 69681573 ps
CPU time 1.69 seconds
Started Jul 02 07:57:07 AM PDT 24
Finished Jul 02 07:57:24 AM PDT 24
Peak memory 206800 kb
Host smart-77d81dde-5206-4ca6-8c58-a458b53b1d75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577180974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2577180974
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4045350897
Short name T768
Test name
Test status
Simulation time 2398999476 ps
CPU time 31.89 seconds
Started Jul 02 07:57:05 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 208380 kb
Host smart-9439abb6-c907-4875-a9a1-a9d5da27b264
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045350897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4045350897
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1882933382
Short name T870
Test name
Test status
Simulation time 85439319 ps
CPU time 1.89 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 206880 kb
Host smart-af10dab3-be43-48df-85ca-6054f7a7b07e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882933382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1882933382
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.179043107
Short name T777
Test name
Test status
Simulation time 167770886 ps
CPU time 2.27 seconds
Started Jul 02 07:57:23 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 207260 kb
Host smart-514dc39c-c74d-4649-9cd1-ed9a245e88aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179043107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.179043107
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.792842084
Short name T748
Test name
Test status
Simulation time 71640204 ps
CPU time 2.65 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 206708 kb
Host smart-7bec3c14-84a7-417c-836f-982b770fb9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792842084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.792842084
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3673914697
Short name T808
Test name
Test status
Simulation time 1768101874 ps
CPU time 32.53 seconds
Started Jul 02 07:57:26 AM PDT 24
Finished Jul 02 07:58:14 AM PDT 24
Peak memory 222284 kb
Host smart-4c77e8ab-5871-4dc3-8d46-4b7d03d41175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673914697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3673914697
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3260182566
Short name T613
Test name
Test status
Simulation time 214815126 ps
CPU time 3.51 seconds
Started Jul 02 07:57:34 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 208556 kb
Host smart-f3978738-57a4-4506-b262-c890c703307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260182566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3260182566
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3827500598
Short name T761
Test name
Test status
Simulation time 94938572 ps
CPU time 1.75 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:21 AM PDT 24
Peak memory 209700 kb
Host smart-aa04dd2b-3b58-456a-8725-b64d95de6aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827500598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3827500598
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3941632396
Short name T521
Test name
Test status
Simulation time 7796232 ps
CPU time 0.69 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 205848 kb
Host smart-b1e6bc97-f166-4ba1-bec1-fe62d5a68fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941632396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3941632396
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.231157669
Short name T246
Test name
Test status
Simulation time 127091292 ps
CPU time 5.87 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 215220 kb
Host smart-f79e8e72-b718-454b-8423-0d78bdd287a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231157669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.231157669
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.602950742
Short name T867
Test name
Test status
Simulation time 66269865 ps
CPU time 2.13 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:38 AM PDT 24
Peak memory 207580 kb
Host smart-7d0b4a30-eb45-4bef-ad14-6b77d9c6c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602950742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.602950742
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1609048098
Short name T85
Test name
Test status
Simulation time 31412211 ps
CPU time 2.34 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 214328 kb
Host smart-ba88d55b-ebbc-4533-b684-98c5ca05e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609048098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1609048098
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3546421052
Short name T642
Test name
Test status
Simulation time 46516026 ps
CPU time 2.69 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 214104 kb
Host smart-4f62a1e8-5c0a-4ea6-b9d4-df5ef32c59a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546421052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3546421052
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3762732751
Short name T393
Test name
Test status
Simulation time 80207381 ps
CPU time 3.92 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:44 AM PDT 24
Peak memory 220056 kb
Host smart-777f2b13-191c-4c51-a6d9-93a6b88c125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762732751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3762732751
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3963498453
Short name T78
Test name
Test status
Simulation time 287790861 ps
CPU time 7.11 seconds
Started Jul 02 07:57:09 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 209264 kb
Host smart-ddf8d22d-6856-4d48-9b43-a1151063246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963498453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3963498453
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.703177378
Short name T595
Test name
Test status
Simulation time 128838852 ps
CPU time 2.26 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 206800 kb
Host smart-f0595c44-25a3-46b2-bbc9-33382d3aadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703177378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.703177378
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1126784073
Short name T509
Test name
Test status
Simulation time 260259133 ps
CPU time 6.22 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 208560 kb
Host smart-825ea7c7-866a-4a1c-80d5-fbf03da975b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126784073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1126784073
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1744367254
Short name T576
Test name
Test status
Simulation time 768464011 ps
CPU time 21.31 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:57 AM PDT 24
Peak memory 208636 kb
Host smart-5e83292c-bb1b-46ae-b5aa-4c715ea7263b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744367254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1744367254
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3596145572
Short name T869
Test name
Test status
Simulation time 105443783 ps
CPU time 2.69 seconds
Started Jul 02 07:57:11 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 208632 kb
Host smart-b73a2761-523f-4c4f-8a76-db1678d55f53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596145572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3596145572
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.302514179
Short name T126
Test name
Test status
Simulation time 356322173 ps
CPU time 2.16 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 218104 kb
Host smart-cf9fa458-517c-4627-83ce-59278f2fed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302514179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.302514179
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2786102445
Short name T408
Test name
Test status
Simulation time 423081528 ps
CPU time 2.73 seconds
Started Jul 02 07:57:03 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 206688 kb
Host smart-bcf17c23-0fa1-4c80-a502-af531125b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786102445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2786102445
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3006473342
Short name T704
Test name
Test status
Simulation time 2551536712 ps
CPU time 24.84 seconds
Started Jul 02 07:57:08 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 215832 kb
Host smart-8245252e-1471-4e80-91c6-5abb54dff71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006473342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3006473342
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1326997265
Short name T594
Test name
Test status
Simulation time 198258499 ps
CPU time 2.99 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 207696 kb
Host smart-d19f95d0-6ec7-475f-9fb2-27ea36e047b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326997265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1326997265
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2258192965
Short name T736
Test name
Test status
Simulation time 43773427 ps
CPU time 2.03 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 209612 kb
Host smart-d3b7d8ff-b24d-43cc-aea6-50d1e5904ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258192965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2258192965
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3267713009
Short name T645
Test name
Test status
Simulation time 9018132 ps
CPU time 0.77 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 205848 kb
Host smart-33730e81-8fc5-4ac3-839d-fdf0a5b05124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267713009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3267713009
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2573297350
Short name T802
Test name
Test status
Simulation time 12495997969 ps
CPU time 123.69 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:59:31 AM PDT 24
Peak memory 215652 kb
Host smart-69e3fed2-ec0f-442e-b8b9-1e2a9bc1a865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573297350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2573297350
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2675503325
Short name T766
Test name
Test status
Simulation time 99287360 ps
CPU time 1.59 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 208984 kb
Host smart-bd78b0f9-7275-4562-a5ad-bfa6d50c3cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675503325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2675503325
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_random.2766759353
Short name T780
Test name
Test status
Simulation time 294229624 ps
CPU time 5.95 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 208188 kb
Host smart-8c6d8bf9-3721-4197-ad67-5f59c3a0830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766759353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2766759353
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3378047788
Short name T13
Test name
Test status
Simulation time 980949682 ps
CPU time 24.31 seconds
Started Jul 02 07:57:07 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 207948 kb
Host smart-4c119ea5-2688-4158-84ee-e1c15c6a7dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378047788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3378047788
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4022808008
Short name T515
Test name
Test status
Simulation time 95537438 ps
CPU time 3.78 seconds
Started Jul 02 07:57:06 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 208580 kb
Host smart-0e790166-99c3-4d76-9e11-0858fd020802
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022808008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4022808008
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1332457216
Short name T669
Test name
Test status
Simulation time 570813744 ps
CPU time 4.9 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 208560 kb
Host smart-aba7b574-a1fd-46b8-b5fb-e49e381baf5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332457216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1332457216
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1877734896
Short name T255
Test name
Test status
Simulation time 524897372 ps
CPU time 4.68 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:34 AM PDT 24
Peak memory 208688 kb
Host smart-1f19e92c-2336-43ce-a40f-ba5f0cd2191b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877734896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1877734896
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3111648680
Short name T124
Test name
Test status
Simulation time 91999514 ps
CPU time 2.75 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:57:45 AM PDT 24
Peak memory 210196 kb
Host smart-c0131aae-9889-4327-9740-13e123fa2ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111648680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3111648680
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2914547804
Short name T646
Test name
Test status
Simulation time 343674917 ps
CPU time 6.64 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:33 AM PDT 24
Peak memory 207940 kb
Host smart-593c4631-cf33-47cb-8821-70ab486c5761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914547804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2914547804
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3572365686
Short name T772
Test name
Test status
Simulation time 171795643 ps
CPU time 2.26 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:51 AM PDT 24
Peak memory 208736 kb
Host smart-b3811b74-dc6f-4022-b1dc-3f7d1ad479bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572365686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3572365686
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3513764761
Short name T600
Test name
Test status
Simulation time 636928716 ps
CPU time 9.08 seconds
Started Jul 02 07:57:20 AM PDT 24
Finished Jul 02 07:57:44 AM PDT 24
Peak memory 208560 kb
Host smart-9ffd92ef-4aad-4d79-bdd1-fa34c962ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513764761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3513764761
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2394069084
Short name T370
Test name
Test status
Simulation time 1720207069 ps
CPU time 13.34 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 210188 kb
Host smart-7bbfbadd-0c63-4830-84e2-7537cf264981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394069084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2394069084
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1151623022
Short name T470
Test name
Test status
Simulation time 15119256 ps
CPU time 0.73 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:29 AM PDT 24
Peak memory 205868 kb
Host smart-f0e50f00-b471-43c7-a774-8f4a08789d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151623022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1151623022
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3709764199
Short name T376
Test name
Test status
Simulation time 59255231 ps
CPU time 4.22 seconds
Started Jul 02 07:57:17 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 215476 kb
Host smart-0d7ec3e3-c2f5-4381-adea-8e9add4bdc47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709764199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3709764199
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.245065086
Short name T847
Test name
Test status
Simulation time 133143835 ps
CPU time 2.89 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:03 AM PDT 24
Peak memory 214216 kb
Host smart-2d556830-4688-4739-a181-a1fcaf445723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245065086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.245065086
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3232133381
Short name T487
Test name
Test status
Simulation time 128403084 ps
CPU time 3.15 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:32 AM PDT 24
Peak memory 209076 kb
Host smart-46fcd86b-9c75-48ea-a225-a874dbc60ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232133381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3232133381
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.25414748
Short name T95
Test name
Test status
Simulation time 202879073 ps
CPU time 3.57 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 219356 kb
Host smart-34b2431c-9f7a-4200-bccd-953ae82bf62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25414748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.25414748
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1524154565
Short name T651
Test name
Test status
Simulation time 47372952 ps
CPU time 2.4 seconds
Started Jul 02 07:57:19 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 214136 kb
Host smart-b815dbe7-4421-472a-a70c-c7417771b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524154565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1524154565
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3693112699
Short name T179
Test name
Test status
Simulation time 171684173 ps
CPU time 3.15 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:38 AM PDT 24
Peak memory 208460 kb
Host smart-088d7685-0db7-4030-a1c8-9468f0c02439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693112699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3693112699
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3958189405
Short name T445
Test name
Test status
Simulation time 197154782 ps
CPU time 4.84 seconds
Started Jul 02 07:57:20 AM PDT 24
Finished Jul 02 07:57:44 AM PDT 24
Peak memory 209780 kb
Host smart-fbcd9a13-fc7c-4273-90f7-530f90e30fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958189405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3958189405
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3806023217
Short name T285
Test name
Test status
Simulation time 60388754 ps
CPU time 3.01 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 206876 kb
Host smart-0b855b6a-2195-48ec-84ca-c0ea2fe3033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806023217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3806023217
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.771932571
Short name T817
Test name
Test status
Simulation time 162384209 ps
CPU time 3.08 seconds
Started Jul 02 07:57:23 AM PDT 24
Finished Jul 02 07:57:41 AM PDT 24
Peak memory 208564 kb
Host smart-2a612e3b-321d-4252-aaad-be1940e692be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771932571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.771932571
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.88050578
Short name T447
Test name
Test status
Simulation time 185821380 ps
CPU time 4.48 seconds
Started Jul 02 07:57:23 AM PDT 24
Finished Jul 02 07:57:43 AM PDT 24
Peak memory 207988 kb
Host smart-a4ac543f-a584-41ff-a101-931b17d57fdf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88050578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.88050578
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.909613936
Short name T444
Test name
Test status
Simulation time 2489732494 ps
CPU time 44.55 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 208440 kb
Host smart-d9fc4d45-950f-432e-aae7-c7aa8f55851c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909613936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.909613936
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.458779888
Short name T488
Test name
Test status
Simulation time 532108244 ps
CPU time 4.91 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 209988 kb
Host smart-93b1d319-b998-4cd5-bb59-629f5d9154ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458779888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.458779888
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2858441365
Short name T456
Test name
Test status
Simulation time 266973891 ps
CPU time 3.16 seconds
Started Jul 02 07:57:18 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 208176 kb
Host smart-10c89d44-114e-4610-872d-3406f8758d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858441365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2858441365
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2963726815
Short name T174
Test name
Test status
Simulation time 350053982 ps
CPU time 7.37 seconds
Started Jul 02 07:57:18 AM PDT 24
Finished Jul 02 07:57:41 AM PDT 24
Peak memory 218464 kb
Host smart-4a22770b-2f28-4c7d-a37b-85941798ae46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963726815 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2963726815
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.258864981
Short name T274
Test name
Test status
Simulation time 430854395 ps
CPU time 6.09 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 214232 kb
Host smart-cd16e084-de4d-4e19-87f1-165e2d99b36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258864981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.258864981
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.469810003
Short name T203
Test name
Test status
Simulation time 155907307 ps
CPU time 3.23 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 209932 kb
Host smart-7f964311-9b11-49ca-8e55-a51c3564f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469810003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.469810003
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.330284023
Short name T662
Test name
Test status
Simulation time 44869993 ps
CPU time 0.74 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:41 AM PDT 24
Peak memory 205940 kb
Host smart-ea19221b-0e0f-47d5-8b0d-e0a8ee2f3faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330284023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.330284023
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3076704805
Short name T66
Test name
Test status
Simulation time 198648251 ps
CPU time 2.36 seconds
Started Jul 02 07:57:28 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 214216 kb
Host smart-d7c80bf6-5bd5-4533-aa9b-ab8a68d3b7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076704805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3076704805
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1161241417
Short name T700
Test name
Test status
Simulation time 448893093 ps
CPU time 3.72 seconds
Started Jul 02 07:57:18 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 214268 kb
Host smart-d3bfa872-7097-4b52-9f00-18db1e6925a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161241417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1161241417
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3489755501
Short name T308
Test name
Test status
Simulation time 85563511 ps
CPU time 3.58 seconds
Started Jul 02 07:57:16 AM PDT 24
Finished Jul 02 07:57:35 AM PDT 24
Peak memory 214272 kb
Host smart-c7c9ffea-2b62-4587-a048-c5bfe67cdf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489755501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3489755501
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.184806651
Short name T582
Test name
Test status
Simulation time 1920972254 ps
CPU time 7.33 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:49 AM PDT 24
Peak memory 210336 kb
Host smart-2bfbe3e0-b5a1-448b-bf36-2b3ca0840cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184806651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.184806651
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4196006871
Short name T691
Test name
Test status
Simulation time 767767235 ps
CPU time 8.22 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 207928 kb
Host smart-43e35e7a-bf42-496a-9f08-fcf4c49f9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196006871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4196006871
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3588928491
Short name T776
Test name
Test status
Simulation time 296138985 ps
CPU time 3.19 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:43 AM PDT 24
Peak memory 208616 kb
Host smart-48c06286-19f7-4f4c-9ea7-bf8436596f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588928491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3588928491
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.859713458
Short name T334
Test name
Test status
Simulation time 446058123 ps
CPU time 2.68 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:57:45 AM PDT 24
Peak memory 206792 kb
Host smart-12ccb68e-3681-4284-a443-e80ab78fe82d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859713458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.859713458
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1889681254
Short name T516
Test name
Test status
Simulation time 179965392 ps
CPU time 2.54 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 206904 kb
Host smart-6fb5db0c-6ee2-4291-8ff3-93333583deef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889681254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1889681254
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.179347247
Short name T744
Test name
Test status
Simulation time 32160179 ps
CPU time 2.16 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 206980 kb
Host smart-19fc5d39-59a5-4edb-b68f-92c4f41951fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179347247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.179347247
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2374262342
Short name T564
Test name
Test status
Simulation time 5197351471 ps
CPU time 33.12 seconds
Started Jul 02 07:57:14 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 214404 kb
Host smart-752348f1-fee7-4019-aa3d-33de27253aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374262342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2374262342
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3052399000
Short name T747
Test name
Test status
Simulation time 1227862539 ps
CPU time 6.71 seconds
Started Jul 02 07:57:10 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 207804 kb
Host smart-ebc4619e-a7a0-42a7-a687-718af56fde30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052399000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3052399000
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2657523515
Short name T182
Test name
Test status
Simulation time 4732046552 ps
CPU time 109.37 seconds
Started Jul 02 07:57:17 AM PDT 24
Finished Jul 02 07:59:22 AM PDT 24
Peak memory 221248 kb
Host smart-d718fbc3-45c2-4416-b11e-d17523b6262b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657523515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2657523515
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.76457082
Short name T175
Test name
Test status
Simulation time 695624886 ps
CPU time 8.26 seconds
Started Jul 02 07:57:25 AM PDT 24
Finished Jul 02 07:57:48 AM PDT 24
Peak memory 218512 kb
Host smart-04c8b872-716f-47b3-9b2e-f1f4c7daf224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76457082 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.76457082
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.349180102
Short name T429
Test name
Test status
Simulation time 685293216 ps
CPU time 16.62 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 208592 kb
Host smart-466edc71-89dd-4aac-a9b9-87261fb6ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349180102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.349180102
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2911837162
Short name T57
Test name
Test status
Simulation time 37964541 ps
CPU time 1.55 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 210096 kb
Host smart-cfd85a0f-d14f-4a92-a0f1-0970831edcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911837162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2911837162
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2429801182
Short name T786
Test name
Test status
Simulation time 133863108 ps
CPU time 0.8 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 205808 kb
Host smart-84e6198a-c1aa-4d80-bc00-870a50799fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429801182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2429801182
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3108722396
Short name T732
Test name
Test status
Simulation time 158746763 ps
CPU time 3.41 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 214332 kb
Host smart-b64c40a2-a775-487e-b560-fb7d56216f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108722396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3108722396
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.362103649
Short name T522
Test name
Test status
Simulation time 110436555 ps
CPU time 2.3 seconds
Started Jul 02 07:56:02 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 208492 kb
Host smart-31394049-f336-499c-8b67-f4af7677aaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362103649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.362103649
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3173188181
Short name T862
Test name
Test status
Simulation time 122717589 ps
CPU time 2.64 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 209084 kb
Host smart-8fc39d16-cbca-46e8-afe7-f61ce9cea000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173188181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3173188181
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1460475901
Short name T325
Test name
Test status
Simulation time 124938642 ps
CPU time 3.41 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 214540 kb
Host smart-bf99db94-6904-4aab-8ae0-a298c51a18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460475901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1460475901
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3847338970
Short name T557
Test name
Test status
Simulation time 383401885 ps
CPU time 4.31 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 211368 kb
Host smart-16abf6d3-18b3-411e-a125-dc88d2ee689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847338970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3847338970
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.4239210779
Short name T440
Test name
Test status
Simulation time 232946551 ps
CPU time 2.11 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 206772 kb
Host smart-9e21751c-b115-4968-bcc8-e0ec7d93be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239210779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4239210779
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.280138927
Short name T390
Test name
Test status
Simulation time 1236395270 ps
CPU time 6.59 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 209076 kb
Host smart-fe89c498-b270-4007-82c3-d014342e841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280138927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.280138927
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1920422241
Short name T8
Test name
Test status
Simulation time 1426397572 ps
CPU time 12.66 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 238148 kb
Host smart-9216be27-0989-4b71-a67b-efafcc2049aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920422241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1920422241
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1459221077
Short name T519
Test name
Test status
Simulation time 524262789 ps
CPU time 3.42 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:34 AM PDT 24
Peak memory 208580 kb
Host smart-959dcf04-fd72-44e7-b264-bace8c5ca4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459221077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1459221077
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3204897051
Short name T335
Test name
Test status
Simulation time 1052376717 ps
CPU time 19.9 seconds
Started Jul 02 07:56:10 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 208112 kb
Host smart-d02f931c-928d-4502-a04c-3d171a033906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204897051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3204897051
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3659743221
Short name T543
Test name
Test status
Simulation time 56569218 ps
CPU time 2.65 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 206768 kb
Host smart-23f1323a-4de3-4b0f-9d88-15cb7a58b880
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659743221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3659743221
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1103599825
Short name T437
Test name
Test status
Simulation time 235009596 ps
CPU time 3.39 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 208816 kb
Host smart-018355df-aa2f-4f80-ad28-cae3c60ac4f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103599825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1103599825
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.684833931
Short name T412
Test name
Test status
Simulation time 757994865 ps
CPU time 4.85 seconds
Started Jul 02 07:56:12 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 208408 kb
Host smart-7871eb11-7d2b-4c2f-b0cc-ddbf18e8b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684833931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.684833931
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2402187766
Short name T827
Test name
Test status
Simulation time 38358673 ps
CPU time 2.44 seconds
Started Jul 02 07:56:01 AM PDT 24
Finished Jul 02 07:56:29 AM PDT 24
Peak memory 208224 kb
Host smart-78b80139-5d0e-4431-90eb-6ac02f620aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402187766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2402187766
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1030237926
Short name T715
Test name
Test status
Simulation time 1015631534 ps
CPU time 24.46 seconds
Started Jul 02 07:56:04 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 215528 kb
Host smart-11c0c766-a717-4033-a913-ce3f9f18238e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030237926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1030237926
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2728576505
Short name T518
Test name
Test status
Simulation time 345754908 ps
CPU time 12.66 seconds
Started Jul 02 07:56:00 AM PDT 24
Finished Jul 02 07:56:38 AM PDT 24
Peak memory 222504 kb
Host smart-ba40a774-91b7-4d7d-8e0f-62e02fa46039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728576505 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2728576505
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.229745148
Short name T288
Test name
Test status
Simulation time 243288259 ps
CPU time 5.74 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 209936 kb
Host smart-d5c5b43f-03e2-4949-ad25-7abc9bb9550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229745148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.229745148
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.196572071
Short name T481
Test name
Test status
Simulation time 36994469 ps
CPU time 1.84 seconds
Started Jul 02 07:56:13 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 209816 kb
Host smart-e1a080e5-ce09-4c25-92bc-88629323b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196572071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.196572071
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.454686186
Short name T615
Test name
Test status
Simulation time 77479027 ps
CPU time 0.96 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:50 AM PDT 24
Peak memory 206120 kb
Host smart-6b896b18-f6bc-4a1a-8605-9defbb3d547f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454686186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.454686186
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1654112648
Short name T611
Test name
Test status
Simulation time 723369213 ps
CPU time 3.78 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 214292 kb
Host smart-b2616eb1-4c16-4280-b9d3-a9c556691158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654112648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1654112648
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2349139272
Short name T742
Test name
Test status
Simulation time 171212264 ps
CPU time 4.15 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:57:31 AM PDT 24
Peak memory 214196 kb
Host smart-481c5a16-1804-4de5-b7cc-4a8427cb73da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349139272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2349139272
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_random.354204691
Short name T699
Test name
Test status
Simulation time 2831026236 ps
CPU time 60.68 seconds
Started Jul 02 07:57:12 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 207808 kb
Host smart-27d18acd-121e-4ab2-a21d-87e013736e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354204691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.354204691
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2009646219
Short name T574
Test name
Test status
Simulation time 487882239 ps
CPU time 2.63 seconds
Started Jul 02 07:57:13 AM PDT 24
Finished Jul 02 07:57:30 AM PDT 24
Peak memory 207324 kb
Host smart-90fc91a1-db05-4c4c-a1c6-338d93744bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009646219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2009646219
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2769338491
Short name T498
Test name
Test status
Simulation time 9688541559 ps
CPU time 25.62 seconds
Started Jul 02 07:57:26 AM PDT 24
Finished Jul 02 07:58:07 AM PDT 24
Peak memory 208804 kb
Host smart-55107bb2-eea2-4e4c-a960-d0ee2a8ce5a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769338491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2769338491
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.311710657
Short name T468
Test name
Test status
Simulation time 727229261 ps
CPU time 16.51 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 208492 kb
Host smart-6e83f312-4b18-4b5c-ac9d-b4502518aeb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311710657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.311710657
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.4215981175
Short name T579
Test name
Test status
Simulation time 4752732994 ps
CPU time 30.98 seconds
Started Jul 02 07:57:30 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 208612 kb
Host smart-0cd75c2e-a470-4027-94fb-879a37c33302
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215981175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4215981175
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.390430388
Short name T672
Test name
Test status
Simulation time 35472888 ps
CPU time 1.79 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:00 AM PDT 24
Peak memory 218264 kb
Host smart-8895be96-7a20-4aa9-ab7b-3681c16b79bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390430388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.390430388
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1648389044
Short name T823
Test name
Test status
Simulation time 152395363 ps
CPU time 2.01 seconds
Started Jul 02 07:57:21 AM PDT 24
Finished Jul 02 07:57:39 AM PDT 24
Peak memory 208532 kb
Host smart-e822b9ee-6daf-4ba2-8f8f-e74c2aa029d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648389044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1648389044
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.242028534
Short name T183
Test name
Test status
Simulation time 3466833505 ps
CPU time 27.6 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 215348 kb
Host smart-117571b6-50ba-4f30-8ee9-3609d6aeac87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242028534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.242028534
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3983477857
Short name T682
Test name
Test status
Simulation time 255284096 ps
CPU time 10.74 seconds
Started Jul 02 07:57:30 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 219676 kb
Host smart-d5f985a2-61eb-4c98-9b84-2cdb5311580d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983477857 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3983477857
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1966003249
Short name T760
Test name
Test status
Simulation time 4143325592 ps
CPU time 15.47 seconds
Started Jul 02 07:57:30 AM PDT 24
Finished Jul 02 07:58:00 AM PDT 24
Peak memory 214364 kb
Host smart-ee715bb0-14e2-492c-b1df-46778fb25875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966003249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1966003249
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3465789199
Short name T368
Test name
Test status
Simulation time 147951536 ps
CPU time 1.9 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 210028 kb
Host smart-8d1fd3ed-bec7-4d64-9316-2c1bad9c3053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465789199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3465789199
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3848519383
Short name T460
Test name
Test status
Simulation time 31669782 ps
CPU time 0.8 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 205964 kb
Host smart-0130ddba-5651-4af3-a732-b1606a4b8955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848519383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3848519383
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3634032072
Short name T29
Test name
Test status
Simulation time 54712683 ps
CPU time 2.23 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:51 AM PDT 24
Peak memory 214312 kb
Host smart-fd5f8710-5874-453b-b8d0-7ac9fc4210ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634032072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3634032072
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2112010085
Short name T616
Test name
Test status
Simulation time 190019649 ps
CPU time 2.72 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 214216 kb
Host smart-8edb8375-5694-4629-a306-d169fbe755e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112010085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2112010085
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2259560628
Short name T227
Test name
Test status
Simulation time 1210604057 ps
CPU time 10.24 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:59 AM PDT 24
Peak memory 214304 kb
Host smart-f24536b1-1436-4061-8bdd-fab4f6e1190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259560628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2259560628
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2584540810
Short name T750
Test name
Test status
Simulation time 85261711 ps
CPU time 3.74 seconds
Started Jul 02 07:57:40 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 222404 kb
Host smart-100d11c0-5424-49d8-9341-8825d05c3670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584540810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2584540810
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2471669360
Short name T819
Test name
Test status
Simulation time 58322936 ps
CPU time 3.25 seconds
Started Jul 02 07:57:26 AM PDT 24
Finished Jul 02 07:57:45 AM PDT 24
Peak memory 222440 kb
Host smart-2a091502-9668-4b52-8ed3-363c1aa76a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471669360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2471669360
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_sideload.705020075
Short name T583
Test name
Test status
Simulation time 716628230 ps
CPU time 22.8 seconds
Started Jul 02 07:57:27 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 208580 kb
Host smart-b43157ae-f8ca-4153-ae8b-e108255c44da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705020075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.705020075
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.129525508
Short name T453
Test name
Test status
Simulation time 130292101 ps
CPU time 2.41 seconds
Started Jul 02 07:57:34 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 208532 kb
Host smart-f3412046-dec8-42c7-a876-751d8df38cd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129525508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.129525508
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2270763425
Short name T684
Test name
Test status
Simulation time 150524388 ps
CPU time 2.33 seconds
Started Jul 02 07:57:17 AM PDT 24
Finished Jul 02 07:57:34 AM PDT 24
Peak memory 206796 kb
Host smart-5134fc11-2d74-495c-80f2-043b472bcb28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270763425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2270763425
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4025932986
Short name T531
Test name
Test status
Simulation time 3866895305 ps
CPU time 52.92 seconds
Started Jul 02 07:57:26 AM PDT 24
Finished Jul 02 07:58:35 AM PDT 24
Peak memory 208984 kb
Host smart-f77ea4ae-7bcd-4daa-bdef-faec313c2906
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025932986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4025932986
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2644016475
Short name T484
Test name
Test status
Simulation time 1633698624 ps
CPU time 6.42 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 218144 kb
Host smart-d01dc473-b421-4c3a-b545-339e7642fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644016475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2644016475
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1027911945
Short name T625
Test name
Test status
Simulation time 1293690279 ps
CPU time 23.07 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 208260 kb
Host smart-9c214c89-dde0-4e7a-bbcb-b1cad68c242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027911945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1027911945
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2466840121
Short name T542
Test name
Test status
Simulation time 2495555842 ps
CPU time 50.81 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:49 AM PDT 24
Peak memory 220192 kb
Host smart-1a0d6beb-e14d-498c-b536-2135a2806235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466840121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2466840121
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.127080177
Short name T803
Test name
Test status
Simulation time 657452439 ps
CPU time 3.63 seconds
Started Jul 02 07:57:26 AM PDT 24
Finished Jul 02 07:57:46 AM PDT 24
Peak memory 214256 kb
Host smart-1753fe32-5f50-4ec8-acb8-edb77a6664d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127080177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.127080177
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2699280962
Short name T527
Test name
Test status
Simulation time 57890896 ps
CPU time 1.94 seconds
Started Jul 02 07:57:36 AM PDT 24
Finished Jul 02 07:57:57 AM PDT 24
Peak memory 209804 kb
Host smart-d1ada89b-a658-48f7-b2b1-21c5ba69ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699280962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2699280962
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2785352140
Short name T789
Test name
Test status
Simulation time 23063362 ps
CPU time 0.78 seconds
Started Jul 02 07:57:37 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 205836 kb
Host smart-6f61a304-c839-4763-a323-b77338187f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785352140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2785352140
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2618308328
Short name T395
Test name
Test status
Simulation time 220516107 ps
CPU time 5.91 seconds
Started Jul 02 07:57:31 AM PDT 24
Finished Jul 02 07:57:51 AM PDT 24
Peak memory 214284 kb
Host smart-3004f8b4-72f9-494e-a359-181c8608c4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618308328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2618308328
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2886188642
Short name T753
Test name
Test status
Simulation time 390256814 ps
CPU time 2.66 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 209380 kb
Host smart-27d3d1f9-3d21-43ed-8a7f-0fe8239b2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886188642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2886188642
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.969105207
Short name T343
Test name
Test status
Simulation time 244687339 ps
CPU time 1.93 seconds
Started Jul 02 07:57:34 AM PDT 24
Finished Jul 02 07:57:53 AM PDT 24
Peak memory 214376 kb
Host smart-04faca10-7c07-4d43-ba73-e83028f6e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969105207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.969105207
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2590778757
Short name T239
Test name
Test status
Simulation time 86979198 ps
CPU time 2.55 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 214276 kb
Host smart-d4562e9d-3665-40b0-af28-4cb8d72c8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590778757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2590778757
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.749452785
Short name T222
Test name
Test status
Simulation time 249102130 ps
CPU time 3.2 seconds
Started Jul 02 07:57:33 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 209008 kb
Host smart-d767bc1e-d412-4214-aad9-435b329d30cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749452785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.749452785
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4233985646
Short name T448
Test name
Test status
Simulation time 55548848 ps
CPU time 3.57 seconds
Started Jul 02 07:57:34 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 214292 kb
Host smart-abb6c936-e2a2-4ae0-8d47-dc53f923a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233985646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4233985646
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3451025577
Short name T472
Test name
Test status
Simulation time 138806995 ps
CPU time 4.49 seconds
Started Jul 02 07:57:22 AM PDT 24
Finished Jul 02 07:57:42 AM PDT 24
Peak memory 208476 kb
Host smart-2dd2fe25-acb7-4486-84cd-a788e080cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451025577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3451025577
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3097174000
Short name T792
Test name
Test status
Simulation time 227403581 ps
CPU time 3.75 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:07 AM PDT 24
Peak memory 207844 kb
Host smart-205febd6-3633-4e2e-b334-d21f46a6e8a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097174000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3097174000
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.394281528
Short name T436
Test name
Test status
Simulation time 309637513 ps
CPU time 5.53 seconds
Started Jul 02 07:57:29 AM PDT 24
Finished Jul 02 07:57:50 AM PDT 24
Peak memory 208664 kb
Host smart-1b477c1e-2fd9-4081-a425-a68ebfd2dfc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394281528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.394281528
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.898770066
Short name T634
Test name
Test status
Simulation time 61547039 ps
CPU time 2.24 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 206884 kb
Host smart-94a81879-0912-4e3b-b830-b670cae9767b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898770066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.898770066
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1537889627
Short name T738
Test name
Test status
Simulation time 254982475 ps
CPU time 2.8 seconds
Started Jul 02 07:57:31 AM PDT 24
Finished Jul 02 07:57:50 AM PDT 24
Peak memory 209100 kb
Host smart-3bd4ee6e-5713-4db3-a76e-138d7754d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537889627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1537889627
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.82475907
Short name T836
Test name
Test status
Simulation time 63799406 ps
CPU time 2.05 seconds
Started Jul 02 07:57:31 AM PDT 24
Finished Jul 02 07:57:49 AM PDT 24
Peak memory 206828 kb
Host smart-b0973f01-0938-43cf-90e2-2b6370cac5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82475907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.82475907
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1809882435
Short name T220
Test name
Test status
Simulation time 732233287 ps
CPU time 27.89 seconds
Started Jul 02 07:57:34 AM PDT 24
Finished Jul 02 07:58:19 AM PDT 24
Peak memory 216688 kb
Host smart-3dde662a-7e7b-4f27-bc8c-d05da5321938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809882435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1809882435
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2541163957
Short name T911
Test name
Test status
Simulation time 334806767 ps
CPU time 19.17 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 222428 kb
Host smart-f7794186-db28-4e96-b2fb-84ad879aaf74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541163957 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2541163957
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3509019966
Short name T474
Test name
Test status
Simulation time 35033041 ps
CPU time 2.24 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:49 AM PDT 24
Peak memory 207448 kb
Host smart-06bb4537-92d3-420f-b59d-1dff4e6bcf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509019966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3509019966
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1920409422
Short name T674
Test name
Test status
Simulation time 335212893 ps
CPU time 2.88 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 210268 kb
Host smart-140d1d42-f0d2-4491-a160-798a1647c34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920409422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1920409422
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2419415700
Short name T849
Test name
Test status
Simulation time 59458896 ps
CPU time 0.83 seconds
Started Jul 02 07:57:36 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 205984 kb
Host smart-95a14fee-0e49-4426-b974-736877fdcbcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419415700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2419415700
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1902543570
Short name T380
Test name
Test status
Simulation time 112383752 ps
CPU time 2.45 seconds
Started Jul 02 07:57:33 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 214352 kb
Host smart-a3ccc93e-95c1-459e-99c7-221d66778dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902543570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1902543570
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2591005844
Short name T23
Test name
Test status
Simulation time 190587397 ps
CPU time 4.16 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 222632 kb
Host smart-2d481f36-2d0b-466d-8a17-a0d51beb504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591005844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2591005844
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.115267264
Short name T717
Test name
Test status
Simulation time 217671996 ps
CPU time 2.3 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 207808 kb
Host smart-aa12ccd2-b1d2-4014-917a-590bde1c0059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115267264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.115267264
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3518679882
Short name T769
Test name
Test status
Simulation time 401932847 ps
CPU time 3.33 seconds
Started Jul 02 07:57:37 AM PDT 24
Finished Jul 02 07:58:00 AM PDT 24
Peak memory 222432 kb
Host smart-d5fcf254-3da2-4ddc-91da-c73824cf082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518679882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3518679882
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.931061608
Short name T260
Test name
Test status
Simulation time 97462707 ps
CPU time 1.84 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:57:59 AM PDT 24
Peak memory 214268 kb
Host smart-3fb111bf-cfa4-455f-8ed7-d1873080301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931061608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.931061608
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1567073921
Short name T696
Test name
Test status
Simulation time 148989964 ps
CPU time 4.41 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 222468 kb
Host smart-cd8bc580-f381-4439-b061-0d4f7628d907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567073921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1567073921
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2852485862
Short name T678
Test name
Test status
Simulation time 1992824356 ps
CPU time 5.71 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 214100 kb
Host smart-91b5736f-c1eb-4fda-8988-a2a7679044a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852485862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2852485862
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.562908901
Short name T427
Test name
Test status
Simulation time 48023962 ps
CPU time 2.37 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 206900 kb
Host smart-50d695fe-b442-42e3-b306-b58cb1c248db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562908901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.562908901
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2159238975
Short name T74
Test name
Test status
Simulation time 1119740042 ps
CPU time 11.36 seconds
Started Jul 02 07:57:40 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 208984 kb
Host smart-3a4404cb-fc73-4a07-8273-f5d906777369
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159238975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2159238975
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.653679104
Short name T193
Test name
Test status
Simulation time 129732277 ps
CPU time 2.54 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 206944 kb
Host smart-ffc3c886-071c-4336-9736-18727d2be203
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653679104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.653679104
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3854832632
Short name T297
Test name
Test status
Simulation time 1367207879 ps
CPU time 3.79 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 208440 kb
Host smart-ec4a4631-5dd5-4365-9d5a-ac2fa680a2a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854832632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3854832632
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.100391726
Short name T913
Test name
Test status
Simulation time 18899521 ps
CPU time 1.69 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 207100 kb
Host smart-400d8d05-511e-4440-80b1-290a8f9ef72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100391726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.100391726
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1515275734
Short name T733
Test name
Test status
Simulation time 204667051 ps
CPU time 0.95 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 206092 kb
Host smart-a2abea65-f454-4ac6-9f94-a7834f6fd9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515275734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1515275734
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1503189994
Short name T228
Test name
Test status
Simulation time 1596290041 ps
CPU time 49.01 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:58:42 AM PDT 24
Peak memory 208584 kb
Host smart-2225edba-4260-4cd7-91df-c1a78e131dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503189994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1503189994
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3973495738
Short name T845
Test name
Test status
Simulation time 312120590 ps
CPU time 4.9 seconds
Started Jul 02 07:57:31 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 210624 kb
Host smart-10f432e0-6f89-4519-aa73-3500858d9d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973495738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3973495738
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2221483648
Short name T506
Test name
Test status
Simulation time 93160639 ps
CPU time 0.89 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:50 AM PDT 24
Peak memory 205884 kb
Host smart-bbaefc04-ecef-4d81-972e-28e34e08bdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221483648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2221483648
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1927084888
Short name T286
Test name
Test status
Simulation time 11666834576 ps
CPU time 55.57 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:58:44 AM PDT 24
Peak memory 214276 kb
Host smart-d86d0f9a-4268-4cf2-b9ec-99745fd34ef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927084888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1927084888
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1474475336
Short name T233
Test name
Test status
Simulation time 80353748 ps
CPU time 3.24 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 209384 kb
Host smart-4c475934-26eb-4ba5-8a0f-36c24a03a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474475336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1474475336
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3240774734
Short name T202
Test name
Test status
Simulation time 274440417 ps
CPU time 3.81 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 208460 kb
Host smart-2af33349-eceb-4e9d-bc2c-5dcaf12c393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240774734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3240774734
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.881156988
Short name T277
Test name
Test status
Simulation time 818351557 ps
CPU time 5.5 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 222308 kb
Host smart-24c9b1c7-8623-4fbc-9ca7-717d6cfbe2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881156988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.881156988
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.997016604
Short name T875
Test name
Test status
Simulation time 592840108 ps
CPU time 3.25 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:07 AM PDT 24
Peak memory 219968 kb
Host smart-6d296e49-3b03-4aa6-8491-d3a497fab3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997016604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.997016604
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4055969017
Short name T190
Test name
Test status
Simulation time 777385480 ps
CPU time 3.94 seconds
Started Jul 02 07:57:33 AM PDT 24
Finished Jul 02 07:57:53 AM PDT 24
Peak memory 209492 kb
Host smart-2505b2cc-6b3d-4bcb-a0ed-99600158d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055969017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4055969017
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1556860282
Short name T737
Test name
Test status
Simulation time 203902088 ps
CPU time 2.51 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 206872 kb
Host smart-6ebd657f-bcd2-4d59-acce-2fcbed658c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556860282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1556860282
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4064730577
Short name T788
Test name
Test status
Simulation time 57297300 ps
CPU time 2.99 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 208344 kb
Host smart-ac4b6761-a6f3-4f55-882e-ae5baaadbe0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064730577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4064730577
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1831858671
Short name T843
Test name
Test status
Simulation time 90887735 ps
CPU time 3.03 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 208644 kb
Host smart-5abd8c1d-7741-4c49-b00e-c8cd3f3f997d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831858671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1831858671
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2297563006
Short name T110
Test name
Test status
Simulation time 170876938 ps
CPU time 5.37 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 208572 kb
Host smart-fae98af0-e35d-48d0-baf6-a0ceb01ec0c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297563006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2297563006
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.29888991
Short name T822
Test name
Test status
Simulation time 1081819002 ps
CPU time 2.36 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 215324 kb
Host smart-08015caf-e632-435c-93d4-b3100082e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29888991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.29888991
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.36800839
Short name T388
Test name
Test status
Simulation time 1559437661 ps
CPU time 3.58 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 207088 kb
Host smart-99bba4f1-be7e-4070-9b6c-796d27efab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36800839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.36800839
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4285554807
Short name T689
Test name
Test status
Simulation time 617353621 ps
CPU time 18.91 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 222424 kb
Host smart-81b50819-30ba-48c2-9725-67e29b9e5526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285554807 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4285554807
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3254104738
Short name T24
Test name
Test status
Simulation time 169830054 ps
CPU time 4.17 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 207700 kb
Host smart-36186a77-533d-4cd6-871a-3a58ca1c84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254104738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3254104738
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2833972489
Short name T538
Test name
Test status
Simulation time 289561017 ps
CPU time 7.76 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 210544 kb
Host smart-4c382bfb-49b6-4641-9bab-f1faa6bb468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833972489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2833972489
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3220691650
Short name T571
Test name
Test status
Simulation time 12491931 ps
CPU time 0.73 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 205888 kb
Host smart-9017186b-64c5-4053-ad7c-80207a8368ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220691650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3220691650
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4289833950
Short name T132
Test name
Test status
Simulation time 1543284010 ps
CPU time 37.49 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:41 AM PDT 24
Peak memory 214800 kb
Host smart-02be9880-b0e5-46e9-ae22-d4810c5e425c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289833950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4289833950
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.879761063
Short name T67
Test name
Test status
Simulation time 62060489 ps
CPU time 2.76 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 209936 kb
Host smart-5000c146-367a-4190-8170-93075b48ce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879761063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.879761063
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4019692970
Short name T593
Test name
Test status
Simulation time 24609033 ps
CPU time 1.76 seconds
Started Jul 02 07:57:54 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 214312 kb
Host smart-48338abb-967e-417f-acff-c7cdbd232778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019692970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4019692970
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.498039570
Short name T608
Test name
Test status
Simulation time 90994751 ps
CPU time 4.5 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 214532 kb
Host smart-7e81c7c3-3537-4b42-beef-6da2fb7335b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498039570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.498039570
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.461620480
Short name T559
Test name
Test status
Simulation time 278353870 ps
CPU time 2.37 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 216036 kb
Host smart-0f5c2a80-11f1-456a-89be-f074743d4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461620480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.461620480
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3768787059
Short name T399
Test name
Test status
Simulation time 410163695 ps
CPU time 4.3 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 207332 kb
Host smart-fab1af5a-7ccc-4e27-bb06-6989b45ca8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768787059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3768787059
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.636054919
Short name T864
Test name
Test status
Simulation time 212194319 ps
CPU time 2.89 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 207332 kb
Host smart-2babfa5b-f08f-4080-bfb5-90560d8002a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636054919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.636054919
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1278557740
Short name T692
Test name
Test status
Simulation time 877128225 ps
CPU time 27.33 seconds
Started Jul 02 07:57:37 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 209020 kb
Host smart-4d25d160-a4d9-48b1-b1d4-abf1ddbf50a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278557740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1278557740
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2061182522
Short name T541
Test name
Test status
Simulation time 70334146 ps
CPU time 2.98 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 206628 kb
Host smart-d7885f2c-d37d-4deb-8d0d-d9dec065ab45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061182522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2061182522
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1332975707
Short name T793
Test name
Test status
Simulation time 66546602 ps
CPU time 3.09 seconds
Started Jul 02 07:57:32 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 208084 kb
Host smart-f9017385-c13e-4f65-9c71-72e9fd611bd8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332975707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1332975707
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3271209740
Short name T813
Test name
Test status
Simulation time 40143959 ps
CPU time 2.16 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 214332 kb
Host smart-bf19fd13-d275-41b8-ad3c-f82080d49d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271209740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3271209740
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2895034066
Short name T451
Test name
Test status
Simulation time 64353725 ps
CPU time 3.06 seconds
Started Jul 02 07:57:36 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 208388 kb
Host smart-cae99949-56b8-4a97-88b4-9257b82d534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895034066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2895034066
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.447881631
Short name T876
Test name
Test status
Simulation time 119083752 ps
CPU time 3.7 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 207524 kb
Host smart-5fe616ec-bf7f-4055-876e-3a17c60b542c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447881631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.447881631
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2521293496
Short name T656
Test name
Test status
Simulation time 172303539 ps
CPU time 4.93 seconds
Started Jul 02 07:57:40 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 218140 kb
Host smart-9702cfe6-784e-4e9d-8854-9a971a3284c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521293496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2521293496
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1070876978
Short name T550
Test name
Test status
Simulation time 110822302 ps
CPU time 1.54 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 210296 kb
Host smart-d500c4b5-e421-4a40-ad1c-447619ab3451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070876978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1070876978
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.637346870
Short name T99
Test name
Test status
Simulation time 11960494 ps
CPU time 0.75 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 205972 kb
Host smart-521e64db-6370-41a4-aef9-b8dbd42cec61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637346870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.637346870
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3280055620
Short name T379
Test name
Test status
Simulation time 822527902 ps
CPU time 21.14 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 214348 kb
Host smart-82492197-8c4f-40bd-99a6-7b31abc5ab1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280055620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3280055620
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1174839016
Short name T19
Test name
Test status
Simulation time 92079475 ps
CPU time 2.64 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:01 AM PDT 24
Peak memory 217508 kb
Host smart-48bcdd78-ff72-47e1-af44-424899bf0603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174839016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1174839016
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1231008782
Short name T275
Test name
Test status
Simulation time 200782421 ps
CPU time 2.57 seconds
Started Jul 02 07:57:33 AM PDT 24
Finished Jul 02 07:57:52 AM PDT 24
Peak memory 214220 kb
Host smart-a240a6d2-07fd-4296-87c6-89f66bcd6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231008782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1231008782
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4282869941
Short name T201
Test name
Test status
Simulation time 1067969072 ps
CPU time 4.05 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 222500 kb
Host smart-a52368ce-6b38-44c9-b864-7455a1a093da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282869941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4282869941
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.465998100
Short name T740
Test name
Test status
Simulation time 144065857 ps
CPU time 3.22 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 214152 kb
Host smart-c51ef1a3-41a3-4c17-b3d1-3a1380f097c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465998100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.465998100
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.333066413
Short name T893
Test name
Test status
Simulation time 325236457 ps
CPU time 3.47 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 207924 kb
Host smart-cdf19db2-66d9-44e6-a818-50df52b8fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333066413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.333066413
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_sideload.525431856
Short name T585
Test name
Test status
Simulation time 137575593 ps
CPU time 2.19 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 206880 kb
Host smart-e1a7d878-2708-4f37-8265-62bd78ca5be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525431856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.525431856
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3535155917
Short name T770
Test name
Test status
Simulation time 161585414 ps
CPU time 2.59 seconds
Started Jul 02 07:57:35 AM PDT 24
Finished Jul 02 07:57:56 AM PDT 24
Peak memory 208920 kb
Host smart-674b20ac-3fcb-45f1-a3b7-daf7868c2712
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535155917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3535155917
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.430537871
Short name T710
Test name
Test status
Simulation time 815272399 ps
CPU time 6.35 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 208156 kb
Host smart-53875ea5-d246-4963-9be9-04912d9236ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430537871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.430537871
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2604448517
Short name T580
Test name
Test status
Simulation time 1419653671 ps
CPU time 39.99 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 208620 kb
Host smart-3cecd15b-9b20-4c17-af56-68513690e21d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604448517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2604448517
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.832438273
Short name T897
Test name
Test status
Simulation time 1331250381 ps
CPU time 3.39 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 210188 kb
Host smart-122b194f-cc28-410d-afe7-3ba69f092338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832438273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.832438273
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3932976314
Short name T421
Test name
Test status
Simulation time 217403287 ps
CPU time 2.61 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 208480 kb
Host smart-ea5aad6c-2b2c-4a9b-8c3e-70901666a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932976314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3932976314
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1874840857
Short name T121
Test name
Test status
Simulation time 243264030 ps
CPU time 9.62 seconds
Started Jul 02 07:57:39 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 222600 kb
Host smart-79fc04c4-c864-4763-bfef-454ee12aeefc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874840857 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1874840857
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2077305995
Short name T880
Test name
Test status
Simulation time 225289937 ps
CPU time 3.51 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 207300 kb
Host smart-28989f5c-cf40-4987-85e8-9b5927219f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077305995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2077305995
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4270200553
Short name T170
Test name
Test status
Simulation time 48092254 ps
CPU time 1.49 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:03 AM PDT 24
Peak memory 210068 kb
Host smart-993eb63c-ed09-4305-8342-7b5b0ca366c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270200553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4270200553
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.727526381
Short name T648
Test name
Test status
Simulation time 112817000 ps
CPU time 0.73 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 205868 kb
Host smart-3973e1cf-8928-4f9c-9032-803447dcb805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727526381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.727526381
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1902523639
Short name T401
Test name
Test status
Simulation time 331193056 ps
CPU time 3.52 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 214412 kb
Host smart-e88b3daa-a9bd-41f7-984e-54310f5fbeba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902523639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1902523639
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2319314099
Short name T281
Test name
Test status
Simulation time 353812855 ps
CPU time 3 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 220216 kb
Host smart-3dd5630f-1b8c-451e-bf07-e938219138ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319314099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2319314099
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3016372570
Short name T480
Test name
Test status
Simulation time 88697668 ps
CPU time 4.1 seconds
Started Jul 02 07:57:42 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 214308 kb
Host smart-d5c8254f-eb2e-46ca-8f79-d010c0202e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016372570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3016372570
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4164274286
Short name T276
Test name
Test status
Simulation time 153534292 ps
CPU time 3.08 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 218640 kb
Host smart-5aaa5a7a-fc91-4290-b4a1-c328831f694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164274286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4164274286
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3083171316
Short name T205
Test name
Test status
Simulation time 89933658 ps
CPU time 4.2 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 209916 kb
Host smart-d67133f4-0f2c-4440-a3e9-7baa6d824f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083171316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3083171316
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1345481641
Short name T664
Test name
Test status
Simulation time 126168843 ps
CPU time 3.86 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 207432 kb
Host smart-33bebc28-12b8-47d2-abac-750dde1b791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345481641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1345481641
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1811071380
Short name T653
Test name
Test status
Simulation time 23025033 ps
CPU time 1.85 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 208604 kb
Host smart-1aef02dd-242b-4da4-9f2f-385aea1ac10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811071380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1811071380
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1667556027
Short name T575
Test name
Test status
Simulation time 169215515 ps
CPU time 2.76 seconds
Started Jul 02 07:57:54 AM PDT 24
Finished Jul 02 07:58:19 AM PDT 24
Peak memory 206900 kb
Host smart-d455234a-98f6-40ff-87c5-8fcc7878d497
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667556027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1667556027
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2298409092
Short name T858
Test name
Test status
Simulation time 605201511 ps
CPU time 4.8 seconds
Started Jul 02 07:57:40 AM PDT 24
Finished Jul 02 07:58:06 AM PDT 24
Peak memory 208728 kb
Host smart-398d6731-c223-464c-ac58-9ed5822cdd60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298409092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2298409092
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.890973307
Short name T892
Test name
Test status
Simulation time 1463534792 ps
CPU time 35.6 seconds
Started Jul 02 07:57:56 AM PDT 24
Finished Jul 02 07:58:53 AM PDT 24
Peak memory 208536 kb
Host smart-3d537626-103d-4132-822c-a36c1c4c6e3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890973307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.890973307
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3026690596
Short name T486
Test name
Test status
Simulation time 968124920 ps
CPU time 7.04 seconds
Started Jul 02 07:57:36 AM PDT 24
Finished Jul 02 07:58:02 AM PDT 24
Peak memory 209228 kb
Host smart-cd6fef31-2b26-4966-b56e-1a74268bb202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026690596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3026690596
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2587624699
Short name T416
Test name
Test status
Simulation time 60020168 ps
CPU time 2.42 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:01 AM PDT 24
Peak memory 206840 kb
Host smart-1c4a35fd-db89-42b5-90a7-782509a8a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587624699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2587624699
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.799764178
Short name T264
Test name
Test status
Simulation time 483400062 ps
CPU time 7.44 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:19 AM PDT 24
Peak memory 222160 kb
Host smart-3b181115-d71e-4673-8c7a-086e2709bee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799764178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.799764178
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.844114438
Short name T344
Test name
Test status
Simulation time 320390252 ps
CPU time 3.11 seconds
Started Jul 02 07:57:49 AM PDT 24
Finished Jul 02 07:58:14 AM PDT 24
Peak memory 214308 kb
Host smart-512681df-aef2-422b-bb96-ad0e516f4de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844114438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.844114438
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3103396009
Short name T784
Test name
Test status
Simulation time 1665908407 ps
CPU time 5.55 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 210316 kb
Host smart-e3d366e5-ca91-46f6-9a6c-f2ae10572711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103396009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3103396009
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1458597784
Short name T503
Test name
Test status
Simulation time 32726545 ps
CPU time 0.95 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 206100 kb
Host smart-754dee35-903b-49c5-92dd-d0dd49530f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458597784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1458597784
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1704138788
Short name T131
Test name
Test status
Simulation time 134519878 ps
CPU time 4.03 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:07 AM PDT 24
Peak memory 214348 kb
Host smart-023e5176-e18a-476d-bda8-c304c8f1a38f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704138788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1704138788
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2488756146
Short name T663
Test name
Test status
Simulation time 116635805 ps
CPU time 3.43 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 216520 kb
Host smart-e344642d-199a-422a-b69e-ae27d5e9489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488756146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2488756146
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.660966917
Short name T494
Test name
Test status
Simulation time 37767130 ps
CPU time 1.54 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 207332 kb
Host smart-a8dbfe10-41ec-4ef2-82a6-16f30bb1af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660966917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.660966917
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.588841682
Short name T677
Test name
Test status
Simulation time 854843786 ps
CPU time 2.56 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 214224 kb
Host smart-ad2a8877-43e3-4975-a149-ce1fd7d557dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588841682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.588841682
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1449446858
Short name T358
Test name
Test status
Simulation time 126950819 ps
CPU time 5.17 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 214164 kb
Host smart-30dd9326-b085-4ccd-9048-cb620e470446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449446858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1449446858
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.820392020
Short name T572
Test name
Test status
Simulation time 111932953 ps
CPU time 2.18 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 215992 kb
Host smart-7b6dd491-5b22-44c5-b8d2-0bb9feaaa49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820392020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.820392020
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3393245312
Short name T332
Test name
Test status
Simulation time 85896229 ps
CPU time 2.93 seconds
Started Jul 02 07:57:56 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 208228 kb
Host smart-cd354f1e-fa8f-4b97-8a9e-c9b344570516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393245312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3393245312
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3443305637
Short name T189
Test name
Test status
Simulation time 398261672 ps
CPU time 3.91 seconds
Started Jul 02 07:57:55 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 207960 kb
Host smart-7cbc2933-a211-403c-a998-108966824194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443305637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3443305637
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1788094341
Short name T861
Test name
Test status
Simulation time 287863068 ps
CPU time 3.58 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 206960 kb
Host smart-d365655c-a5b5-4ae9-864d-53eb17227205
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788094341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1788094341
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3134150418
Short name T454
Test name
Test status
Simulation time 91478222 ps
CPU time 2.59 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 206940 kb
Host smart-b622a9fc-2e8d-4c7f-9ec5-702386ea0a17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134150418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3134150418
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.458994415
Short name T313
Test name
Test status
Simulation time 179605060 ps
CPU time 3 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 206840 kb
Host smart-ca42324d-8609-4bae-baf6-3abd2a66aab4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458994415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.458994415
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3285781138
Short name T549
Test name
Test status
Simulation time 106391530 ps
CPU time 3.08 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 210356 kb
Host smart-06930c0e-c4be-4e0b-9d1c-4a9bebc7c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285781138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3285781138
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3232491373
Short name T449
Test name
Test status
Simulation time 382263086 ps
CPU time 4.05 seconds
Started Jul 02 07:57:37 AM PDT 24
Finished Jul 02 07:58:01 AM PDT 24
Peak memory 208324 kb
Host smart-2fa60e72-3b42-45d2-870f-c7ebefd16b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232491373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3232491373
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.330966206
Short name T345
Test name
Test status
Simulation time 503089453 ps
CPU time 14.51 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 216648 kb
Host smart-cf6aec9a-a7d8-4491-b148-42714016dbb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330966206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.330966206
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1820337529
Short name T618
Test name
Test status
Simulation time 567970307 ps
CPU time 8.54 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 214256 kb
Host smart-a7d8d76c-3386-475d-8f04-3e9f6f7fae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820337529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1820337529
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2535115985
Short name T452
Test name
Test status
Simulation time 36922852 ps
CPU time 2.21 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 210144 kb
Host smart-b609a4af-a829-4da3-83ae-51bb06dce3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535115985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2535115985
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.109874906
Short name T499
Test name
Test status
Simulation time 9528130 ps
CPU time 0.68 seconds
Started Jul 02 07:57:43 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 205880 kb
Host smart-0f6302f8-9785-43ba-a38e-d718854af6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109874906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.109874906
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2079088391
Short name T403
Test name
Test status
Simulation time 198519726 ps
CPU time 5.76 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 215312 kb
Host smart-7eb2ea52-a144-42b3-97ef-4d38ef776f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079088391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2079088391
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4048819745
Short name T26
Test name
Test status
Simulation time 975487012 ps
CPU time 13.79 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 209160 kb
Host smart-b326afde-731e-48c1-9850-b98447e95790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048819745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4048819745
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3373512387
Short name T633
Test name
Test status
Simulation time 78200903 ps
CPU time 3.45 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 214272 kb
Host smart-95e5b1b1-8cc5-4dea-b0a7-665e8207bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373512387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3373512387
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.292776019
Short name T96
Test name
Test status
Simulation time 170873785 ps
CPU time 5.42 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 220684 kb
Host smart-f890ddeb-be3d-4922-840c-59c603cdfe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292776019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.292776019
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.418834593
Short name T701
Test name
Test status
Simulation time 121076060 ps
CPU time 5.4 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 214212 kb
Host smart-20d4a411-83ec-4696-b0f5-d61b764ba55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418834593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.418834593
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2922963700
Short name T895
Test name
Test status
Simulation time 344242447 ps
CPU time 7.02 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 222516 kb
Host smart-99037141-cef8-4ffa-afc6-dc1cdd2f6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922963700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2922963700
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1268624362
Short name T626
Test name
Test status
Simulation time 450584197 ps
CPU time 5.59 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 208072 kb
Host smart-742fb11b-cd5f-4012-97e0-d1475bce51d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268624362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1268624362
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1173286504
Short name T607
Test name
Test status
Simulation time 152244634 ps
CPU time 4.74 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 206820 kb
Host smart-cf8fd6d9-91e3-4150-b211-b4b4b0a5b4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173286504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1173286504
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1483944545
Short name T609
Test name
Test status
Simulation time 470332419 ps
CPU time 4.23 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 208588 kb
Host smart-762242e5-2bce-4626-b039-118e07baa151
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483944545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1483944545
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3104891310
Short name T673
Test name
Test status
Simulation time 120595179 ps
CPU time 3.8 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 208620 kb
Host smart-9c95590b-10f5-4785-9067-3a2a7b1a9b27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104891310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3104891310
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1355171295
Short name T1
Test name
Test status
Simulation time 225373911 ps
CPU time 3.01 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 208836 kb
Host smart-9e497083-ef24-46f0-8922-fbea9521568d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355171295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1355171295
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3370981089
Short name T804
Test name
Test status
Simulation time 189145962 ps
CPU time 2.98 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 208376 kb
Host smart-2126351f-e46a-4eaf-b78b-6cf6a90aec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370981089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3370981089
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2932675076
Short name T434
Test name
Test status
Simulation time 96410394 ps
CPU time 2.43 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 206768 kb
Host smart-4a06a42b-b53e-4114-8eda-30387b01c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932675076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2932675076
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3228139880
Short name T751
Test name
Test status
Simulation time 2180295597 ps
CPU time 22.42 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 222660 kb
Host smart-14907f09-b3da-4b70-8d0a-ff7700aefdc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228139880 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3228139880
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.134358787
Short name T383
Test name
Test status
Simulation time 1041875238 ps
CPU time 25.39 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 209040 kb
Host smart-8f983dd3-1fa1-443f-85cc-c21976d89442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134358787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.134358787
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.954484205
Short name T746
Test name
Test status
Simulation time 100213043 ps
CPU time 1.79 seconds
Started Jul 02 07:57:41 AM PDT 24
Finished Jul 02 07:58:04 AM PDT 24
Peak memory 209796 kb
Host smart-85fa8032-c1e8-4064-8456-45048a7eaa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954484205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.954484205
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1570913699
Short name T735
Test name
Test status
Simulation time 13124714 ps
CPU time 0.93 seconds
Started Jul 02 07:56:16 AM PDT 24
Finished Jul 02 07:56:41 AM PDT 24
Peak memory 206032 kb
Host smart-e5c8a84a-3b65-4db0-ae90-cc79ecc436c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570913699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1570913699
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1241864237
Short name T229
Test name
Test status
Simulation time 882043314 ps
CPU time 35.99 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 214312 kb
Host smart-36b5f779-0aaa-4072-958e-c7a90d629358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241864237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1241864237
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2652922196
Short name T590
Test name
Test status
Simulation time 318190585 ps
CPU time 1.98 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 207664 kb
Host smart-cc38d9a3-9537-4747-bab4-952e9378b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652922196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2652922196
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2498434068
Short name T88
Test name
Test status
Simulation time 484201313 ps
CPU time 6.68 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 222108 kb
Host smart-a25527a3-4c1e-4879-aa37-4682c35a60d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498434068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2498434068
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2306750640
Short name T36
Test name
Test status
Simulation time 242499904 ps
CPU time 3.6 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 222248 kb
Host smart-a5ceb3cf-a1e1-40a5-8026-703a5e61d41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306750640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2306750640
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3823135276
Short name T210
Test name
Test status
Simulation time 602669963 ps
CPU time 4.11 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 214416 kb
Host smart-b2b2bddd-3b7d-4048-925b-f16607ed5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823135276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3823135276
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1853713952
Short name T491
Test name
Test status
Simulation time 70684191 ps
CPU time 4.04 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:45 AM PDT 24
Peak memory 214212 kb
Host smart-1d3fafdc-b834-4b0f-af81-fcc1e7ae83bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853713952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1853713952
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2493589256
Short name T101
Test name
Test status
Simulation time 1547616995 ps
CPU time 14.13 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 229972 kb
Host smart-88835250-748b-4ae9-87cc-5552c17d9126
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493589256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2493589256
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1903049555
Short name T545
Test name
Test status
Simulation time 195984229 ps
CPU time 2.84 seconds
Started Jul 02 07:56:07 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 207196 kb
Host smart-1279e5a3-51ae-42f6-bb0a-6485a601173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903049555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1903049555
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.950532581
Short name T546
Test name
Test status
Simulation time 180140921 ps
CPU time 4.91 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 208764 kb
Host smart-8f5eb089-49a0-40d1-99f6-7aa2c8e15930
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950532581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.950532581
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1195081291
Short name T194
Test name
Test status
Simulation time 772960274 ps
CPU time 10.91 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 207784 kb
Host smart-28e64641-cbfe-4651-ab00-a9dfc0c5fb8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195081291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1195081291
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3951031157
Short name T489
Test name
Test status
Simulation time 44895226 ps
CPU time 2.32 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:33 AM PDT 24
Peak memory 208252 kb
Host smart-a6a6efb8-f4f3-4e9c-b49f-ca4251c73cca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951031157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3951031157
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3249056979
Short name T666
Test name
Test status
Simulation time 580059658 ps
CPU time 5.2 seconds
Started Jul 02 07:56:11 AM PDT 24
Finished Jul 02 07:56:41 AM PDT 24
Peak memory 209548 kb
Host smart-6c86b84f-a2f3-4b29-95c2-69ddc9578a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249056979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3249056979
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2390083944
Short name T547
Test name
Test status
Simulation time 184062351 ps
CPU time 2.45 seconds
Started Jul 02 07:56:03 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 207028 kb
Host smart-13d504de-d160-4d00-843d-c239eee4ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390083944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2390083944
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2803550008
Short name T208
Test name
Test status
Simulation time 9669432192 ps
CPU time 26.87 seconds
Started Jul 02 07:56:05 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 215936 kb
Host smart-8b610f10-a0eb-46fd-8bf9-85e58aef6cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803550008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2803550008
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2861493813
Short name T524
Test name
Test status
Simulation time 37529351 ps
CPU time 2.53 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 209608 kb
Host smart-b100a495-4780-4838-8ef9-57bd562960c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861493813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2861493813
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3528387457
Short name T366
Test name
Test status
Simulation time 39681999 ps
CPU time 2.15 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 210124 kb
Host smart-b80cb5b7-0105-4946-904e-ec770c21c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528387457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3528387457
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4168067186
Short name T497
Test name
Test status
Simulation time 53496646 ps
CPU time 0.73 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 205980 kb
Host smart-5b5edc07-e73c-45c1-8d00-6e41953e9606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168067186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4168067186
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1388296423
Short name T406
Test name
Test status
Simulation time 288195129 ps
CPU time 3.65 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 222388 kb
Host smart-cfa920d4-1c91-43aa-ad79-35a39462e2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388296423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1388296423
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1701724588
Short name T775
Test name
Test status
Simulation time 1030316913 ps
CPU time 3.25 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 210224 kb
Host smart-32d63cc1-cc64-422d-8197-1f9f96b8fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701724588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1701724588
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.423228070
Short name T555
Test name
Test status
Simulation time 1288750045 ps
CPU time 11.7 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:21 AM PDT 24
Peak memory 208244 kb
Host smart-762e50b9-4938-4a64-976f-068b2cf62aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423228070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.423228070
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1980205002
Short name T887
Test name
Test status
Simulation time 104329288 ps
CPU time 4.56 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 214356 kb
Host smart-d90883b6-c907-43d5-82eb-c90b3c788ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980205002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1980205002
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3213942397
Short name T537
Test name
Test status
Simulation time 32213645 ps
CPU time 2.33 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 216484 kb
Host smart-146160cc-8a03-4f46-9a38-db65ed982552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213942397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3213942397
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1385466183
Short name T730
Test name
Test status
Simulation time 41921394 ps
CPU time 2.13 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 209900 kb
Host smart-35bff331-4111-4ff2-a88e-01bd1848cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385466183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1385466183
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2918195403
Short name T243
Test name
Test status
Simulation time 457664634 ps
CPU time 6.58 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:21 AM PDT 24
Peak memory 214388 kb
Host smart-0bfc9642-d396-4151-b4d3-6b5231bec6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918195403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2918195403
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1475849324
Short name T414
Test name
Test status
Simulation time 21924986 ps
CPU time 1.84 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 206720 kb
Host smart-5f3a5f08-1952-4b9a-8709-273e253ff2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475849324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1475849324
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2289974661
Short name T596
Test name
Test status
Simulation time 35497703 ps
CPU time 2.42 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 208572 kb
Host smart-31b3171d-c802-4c90-9c47-208623edb8cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289974661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2289974661
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.423410666
Short name T511
Test name
Test status
Simulation time 41592036 ps
CPU time 2.36 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 206960 kb
Host smart-afe7bb71-142c-48d1-85f3-75a6757b7668
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423410666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.423410666
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1355662244
Short name T314
Test name
Test status
Simulation time 219148120 ps
CPU time 5.86 seconds
Started Jul 02 07:57:45 AM PDT 24
Finished Jul 02 07:58:14 AM PDT 24
Peak memory 208348 kb
Host smart-b3b3e581-26e7-4265-af66-4b6a53d0f45d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355662244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1355662244
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1809671778
Short name T107
Test name
Test status
Simulation time 350620074 ps
CPU time 2.79 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208140 kb
Host smart-bd7c5d25-1e49-4bca-beac-42f9893d1629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809671778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1809671778
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4239678534
Short name T703
Test name
Test status
Simulation time 64084516 ps
CPU time 2.17 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 208380 kb
Host smart-bcd51220-4e5d-43ea-b840-41a26dc0508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239678534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4239678534
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1763589707
Short name T504
Test name
Test status
Simulation time 1719207698 ps
CPU time 29.57 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:39 AM PDT 24
Peak memory 215796 kb
Host smart-2f076a76-102e-418d-8abb-1c789c45ee0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763589707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1763589707
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3970093446
Short name T73
Test name
Test status
Simulation time 896631700 ps
CPU time 19.35 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 221676 kb
Host smart-8fb23955-14e0-4397-89f8-634714e81864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970093446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3970093446
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2942513648
Short name T592
Test name
Test status
Simulation time 2100972092 ps
CPU time 33.9 seconds
Started Jul 02 07:57:38 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 208784 kb
Host smart-1288bda4-1058-43d3-a7a2-35f9c1d6d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942513648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2942513648
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4211951053
Short name T362
Test name
Test status
Simulation time 62883126 ps
CPU time 2.19 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 209884 kb
Host smart-0a995fd5-d465-4242-bc3a-028f4642ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211951053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4211951053
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.150460533
Short name T562
Test name
Test status
Simulation time 38638042 ps
CPU time 0.78 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 205936 kb
Host smart-4b79afd1-b781-4687-8a20-c3e0c5190461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150460533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.150460533
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1253886312
Short name T706
Test name
Test status
Simulation time 170432230 ps
CPU time 4.02 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:12 AM PDT 24
Peak memory 218212 kb
Host smart-22fdb346-c90a-4e38-b34b-a09b2364c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253886312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1253886312
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3052728784
Short name T829
Test name
Test status
Simulation time 90089336 ps
CPU time 2.52 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 209144 kb
Host smart-a7442fa7-4edb-4929-b34b-a82d7fecb706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052728784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3052728784
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1881656958
Short name T91
Test name
Test status
Simulation time 100147717 ps
CPU time 4.35 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 214212 kb
Host smart-969ab1c6-7e6a-43c1-b8c4-05a72777dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881656958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1881656958
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2801454102
Short name T322
Test name
Test status
Simulation time 320168454 ps
CPU time 2.45 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 219860 kb
Host smart-a62e711b-43ee-44b4-9569-18064bff58ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801454102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2801454102
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.328737798
Short name T62
Test name
Test status
Simulation time 461231951 ps
CPU time 4.31 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 218100 kb
Host smart-507322d3-8a25-4f79-927b-ae7e3b107654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328737798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.328737798
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.805789131
Short name T284
Test name
Test status
Simulation time 68128755 ps
CPU time 3.91 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:09 AM PDT 24
Peak memory 210116 kb
Host smart-037ce2a3-af4b-4043-90cf-7810f846ed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805789131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.805789131
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.4150356141
Short name T680
Test name
Test status
Simulation time 43480917 ps
CPU time 1.93 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 208476 kb
Host smart-ab1c124b-c96b-4c3e-998c-aac248821df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150356141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.4150356141
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2416761721
Short name T805
Test name
Test status
Simulation time 147300905 ps
CPU time 3.04 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 208704 kb
Host smart-b50046b1-1dd3-44cc-8d9e-e0258f812802
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416761721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2416761721
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1434859954
Short name T553
Test name
Test status
Simulation time 146026445 ps
CPU time 4.5 seconds
Started Jul 02 07:57:48 AM PDT 24
Finished Jul 02 07:58:14 AM PDT 24
Peak memory 207108 kb
Host smart-3198d602-790f-4253-9bdc-dfd440841d24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434859954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1434859954
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2524914787
Short name T333
Test name
Test status
Simulation time 49770946 ps
CPU time 2.58 seconds
Started Jul 02 07:57:56 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 206928 kb
Host smart-f58f929c-5018-4e69-9602-b09b9b5f145f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524914787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2524914787
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1829383543
Short name T765
Test name
Test status
Simulation time 107256954 ps
CPU time 2.24 seconds
Started Jul 02 07:57:54 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 207868 kb
Host smart-a1dd7881-50f9-4671-9a05-c0ba47bf0f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829383543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1829383543
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2535263637
Short name T667
Test name
Test status
Simulation time 157357042 ps
CPU time 3.11 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 208196 kb
Host smart-d80c76ed-1b09-4b67-94fa-37e71923bf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535263637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2535263637
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1867391362
Short name T846
Test name
Test status
Simulation time 534819741 ps
CPU time 5.91 seconds
Started Jul 02 07:57:57 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 220732 kb
Host smart-4869350b-887e-436f-9b1a-9bd7c038550e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867391362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1867391362
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1572943401
Short name T123
Test name
Test status
Simulation time 42740719 ps
CPU time 2.73 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208124 kb
Host smart-71e36ab8-3489-468f-ad1e-f030a0c6627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572943401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1572943401
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3734110678
Short name T367
Test name
Test status
Simulation time 168111172 ps
CPU time 2.4 seconds
Started Jul 02 07:57:56 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 209872 kb
Host smart-60c4f263-3b52-457e-ab3f-f0534d9e8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734110678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3734110678
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1503199901
Short name T837
Test name
Test status
Simulation time 12958221 ps
CPU time 0.71 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 205956 kb
Host smart-9f23a97a-ded7-4350-84dd-aca3d510338f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503199901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1503199901
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2834479983
Short name T272
Test name
Test status
Simulation time 95721206 ps
CPU time 5.46 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:14 AM PDT 24
Peak memory 214852 kb
Host smart-15b8d3e4-a930-4771-aa63-b027fb576feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834479983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2834479983
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1908545140
Short name T627
Test name
Test status
Simulation time 334819168 ps
CPU time 3.98 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 209180 kb
Host smart-e0a24cd5-9ab5-42ba-a237-cd8edb959235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908545140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1908545140
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2753458638
Short name T756
Test name
Test status
Simulation time 2239836301 ps
CPU time 11.53 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 209072 kb
Host smart-e9e84076-cae9-4bd2-a385-ae1e5a5f3fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753458638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2753458638
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2587745852
Short name T87
Test name
Test status
Simulation time 1311346645 ps
CPU time 38.03 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:59:07 AM PDT 24
Peak memory 214508 kb
Host smart-a2627789-74ce-4159-b8ec-40100012c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587745852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2587745852
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1319366571
Short name T7
Test name
Test status
Simulation time 54138910 ps
CPU time 2.45 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 215764 kb
Host smart-353b6a5a-7677-49b8-8369-39cb19ba4648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319366571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1319366571
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.92917555
Short name T660
Test name
Test status
Simulation time 135963638 ps
CPU time 5.5 seconds
Started Jul 02 07:57:44 AM PDT 24
Finished Jul 02 07:58:10 AM PDT 24
Peak memory 210192 kb
Host smart-f0b64cdd-b58c-4369-9ad5-89cf104049c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92917555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.92917555
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4065014648
Short name T477
Test name
Test status
Simulation time 33006274 ps
CPU time 2.35 seconds
Started Jul 02 07:57:56 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 206752 kb
Host smart-878f842c-4e1a-4a90-a787-3b9b8d8d9707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065014648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4065014648
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2381107218
Short name T584
Test name
Test status
Simulation time 1287439677 ps
CPU time 7.11 seconds
Started Jul 02 07:58:03 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 208520 kb
Host smart-6bb7cc3c-e8f5-45c0-874f-5ae42f02c3f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381107218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2381107218
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2409060409
Short name T828
Test name
Test status
Simulation time 45285967 ps
CPU time 2.39 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 206900 kb
Host smart-63eede67-4521-4b18-9a05-61720d4a357a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409060409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2409060409
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2895588265
Short name T566
Test name
Test status
Simulation time 594715363 ps
CPU time 7.15 seconds
Started Jul 02 07:57:49 AM PDT 24
Finished Jul 02 07:58:19 AM PDT 24
Peak memory 208668 kb
Host smart-24dcf8d4-904b-4204-8f14-6b49ca153413
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895588265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2895588265
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.891984885
Short name T386
Test name
Test status
Simulation time 320872114 ps
CPU time 4.4 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 214512 kb
Host smart-79ee6aa5-d2a6-4642-8548-931ee6040def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891984885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.891984885
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.615274574
Short name T621
Test name
Test status
Simulation time 276354137 ps
CPU time 2.79 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 208412 kb
Host smart-f24f3378-3510-4445-a301-cddf4d51b08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615274574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.615274574
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1134287737
Short name T659
Test name
Test status
Simulation time 1106357413 ps
CPU time 40.28 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:59:04 AM PDT 24
Peak memory 215552 kb
Host smart-b38ba856-9802-431d-9f2c-039d6d213a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134287737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1134287737
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.87114768
Short name T331
Test name
Test status
Simulation time 3634540624 ps
CPU time 48.19 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:56 AM PDT 24
Peak memory 214340 kb
Host smart-49b2f38c-5e78-4808-ba24-42d4d62cf6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87114768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.87114768
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.711478239
Short name T731
Test name
Test status
Simulation time 521650822 ps
CPU time 4.71 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 210780 kb
Host smart-17881757-4548-4576-a06d-badec8728c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711478239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.711478239
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.771960154
Short name T420
Test name
Test status
Simulation time 19740484 ps
CPU time 0.77 seconds
Started Jul 02 07:57:52 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 205872 kb
Host smart-75fdcf33-080f-47dc-ac39-5d49b56b88f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771960154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.771960154
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2093886387
Short name T910
Test name
Test status
Simulation time 69401280 ps
CPU time 4.07 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 215240 kb
Host smart-cac95896-adf3-4216-bbfc-30fd32b30161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093886387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2093886387
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.756006923
Short name T64
Test name
Test status
Simulation time 158568698 ps
CPU time 3.99 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 221572 kb
Host smart-39f284d7-d634-4ef2-95da-d7e6252ae471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756006923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.756006923
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1726170119
Short name T839
Test name
Test status
Simulation time 482221042 ps
CPU time 7.48 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 208564 kb
Host smart-8e5f0523-836d-4ec9-81b1-68b233aead2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726170119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1726170119
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1788753674
Short name T305
Test name
Test status
Simulation time 59672861 ps
CPU time 2.37 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 214296 kb
Host smart-ee4d3c71-4c81-4b68-9ae5-8d38176edf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788753674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1788753674
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2621307996
Short name T610
Test name
Test status
Simulation time 210279586 ps
CPU time 2.08 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 214120 kb
Host smart-785fc2bc-afe2-4d4b-957a-b31046308927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621307996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2621307996
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1784230500
Short name T782
Test name
Test status
Simulation time 96218737 ps
CPU time 2.21 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:35 AM PDT 24
Peak memory 219696 kb
Host smart-a4cc8006-7de0-4e2d-9a3a-960cde933646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784230500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1784230500
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.8390669
Short name T300
Test name
Test status
Simulation time 123351116 ps
CPU time 2.31 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 207304 kb
Host smart-cc050b4a-0c88-48c7-a918-3cb40e33001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8390669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.8390669
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1500794371
Short name T458
Test name
Test status
Simulation time 110389418 ps
CPU time 3.34 seconds
Started Jul 02 07:58:16 AM PDT 24
Finished Jul 02 07:58:42 AM PDT 24
Peak memory 208528 kb
Host smart-47c591b3-c352-4739-b9e4-8614fd14fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500794371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1500794371
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2886928163
Short name T588
Test name
Test status
Simulation time 517386199 ps
CPU time 3.38 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 208864 kb
Host smart-b2cc9490-1a96-4f91-9a3d-e8b55411fc07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886928163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2886928163
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2479047445
Short name T860
Test name
Test status
Simulation time 241623035 ps
CPU time 3.5 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 208708 kb
Host smart-83f540cb-8cbd-407d-a11c-fcbb304cdf8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479047445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2479047445
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2620201228
Short name T907
Test name
Test status
Simulation time 1190178412 ps
CPU time 6.76 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:38 AM PDT 24
Peak memory 207928 kb
Host smart-518227a9-d889-4358-8276-cf2dc99ff7ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620201228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2620201228
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2578607011
Short name T901
Test name
Test status
Simulation time 51238283 ps
CPU time 2.45 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 214356 kb
Host smart-74fd4fa8-8e74-4bda-b71b-14a06a76758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578607011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2578607011
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3727142678
Short name T889
Test name
Test status
Simulation time 108782740 ps
CPU time 3.14 seconds
Started Jul 02 07:57:55 AM PDT 24
Finished Jul 02 07:58:20 AM PDT 24
Peak memory 206788 kb
Host smart-3c594f6c-2ec0-4ef8-b70f-e70772a2015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727142678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3727142678
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1379801175
Short name T178
Test name
Test status
Simulation time 299781292 ps
CPU time 10.28 seconds
Started Jul 02 07:57:46 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 222688 kb
Host smart-21696fd5-45f4-4195-b3c5-f782f67cc489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379801175 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1379801175
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4270034260
Short name T898
Test name
Test status
Simulation time 126768161 ps
CPU time 5.13 seconds
Started Jul 02 07:57:55 AM PDT 24
Finished Jul 02 07:58:21 AM PDT 24
Peak memory 214296 kb
Host smart-164db8f2-f0f8-4f1b-9d88-d704366e8567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270034260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4270034260
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2266808097
Short name T725
Test name
Test status
Simulation time 140737310 ps
CPU time 3.01 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 210316 kb
Host smart-5515d742-ab74-4ea6-8c73-12394cc89598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266808097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2266808097
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2240516407
Short name T851
Test name
Test status
Simulation time 15964514 ps
CPU time 0.9 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 206100 kb
Host smart-f28b3973-5de8-40bd-bca9-2d17f31ecfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240516407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2240516407
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1958653770
Short name T371
Test name
Test status
Simulation time 141018006 ps
CPU time 3.68 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 214896 kb
Host smart-850520c8-c8a8-4485-9af7-e2ec8d105d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958653770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1958653770
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3623586902
Short name T619
Test name
Test status
Simulation time 177386425 ps
CPU time 1.65 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 207464 kb
Host smart-9b22311a-c416-4949-8c66-0b70b88ad0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623586902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3623586902
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.340801073
Short name T278
Test name
Test status
Simulation time 241714004 ps
CPU time 4.05 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 214996 kb
Host smart-e45346a8-dd11-402d-91b3-538968965f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340801073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.340801073
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1425606212
Short name T237
Test name
Test status
Simulation time 169104963 ps
CPU time 2.67 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 214092 kb
Host smart-dd92c942-74c8-4178-813a-c61978c3fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425606212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1425606212
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.713888983
Short name T43
Test name
Test status
Simulation time 156867902 ps
CPU time 2.83 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 214512 kb
Host smart-2feac3de-8aa6-4cf1-978b-1671439a59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713888983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.713888983
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1262973222
Short name T530
Test name
Test status
Simulation time 5705961861 ps
CPU time 36.57 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:59:09 AM PDT 24
Peak memory 208540 kb
Host smart-50706623-95e1-4c7e-a0bc-373a0d38f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262973222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1262973222
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1373597444
Short name T432
Test name
Test status
Simulation time 391212694 ps
CPU time 3.44 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 208344 kb
Host smart-3edd4b40-77c8-4ba7-a48a-8e76b5a53f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373597444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1373597444
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1556689044
Short name T877
Test name
Test status
Simulation time 288775182 ps
CPU time 5.92 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 208532 kb
Host smart-2d770e28-f41e-480d-9071-9262509d6b11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556689044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1556689044
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4073199894
Short name T832
Test name
Test status
Simulation time 182562916 ps
CPU time 3.84 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208708 kb
Host smart-aac44e7d-0050-4687-9f76-cb1aa6a5b390
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073199894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4073199894
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2547511463
Short name T502
Test name
Test status
Simulation time 352950257 ps
CPU time 3.87 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 208588 kb
Host smart-752f26cc-abd7-4061-800e-dbd98d3e0383
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547511463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2547511463
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2267768421
Short name T198
Test name
Test status
Simulation time 88794772 ps
CPU time 2.05 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 218224 kb
Host smart-232dd47c-cf4b-4523-be28-9980207977c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267768421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2267768421
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1819253713
Short name T841
Test name
Test status
Simulation time 187203455 ps
CPU time 2.38 seconds
Started Jul 02 07:58:03 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 206800 kb
Host smart-1e74421d-0f34-4a5d-8405-90461d200e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819253713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1819253713
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.788457499
Short name T341
Test name
Test status
Simulation time 500660074 ps
CPU time 16.02 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 218472 kb
Host smart-3dfcbe42-a354-445b-9a74-871a2e381d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788457499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.788457499
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4276448074
Short name T614
Test name
Test status
Simulation time 1236053541 ps
CPU time 20.73 seconds
Started Jul 02 07:57:47 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 208796 kb
Host smart-0b4982a4-8458-4239-9159-85c2ed4ab8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276448074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4276448074
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.464820576
Short name T528
Test name
Test status
Simulation time 716973408 ps
CPU time 10.85 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:43 AM PDT 24
Peak memory 210316 kb
Host smart-9d7a9b12-cb86-4421-b14d-5ba66c656972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464820576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.464820576
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.640849446
Short name T850
Test name
Test status
Simulation time 52600250 ps
CPU time 0.68 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 205984 kb
Host smart-eac9b29e-32c2-4500-ac11-42ff52654027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640849446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.640849446
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.969680123
Short name T752
Test name
Test status
Simulation time 85727032 ps
CPU time 1.74 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 218288 kb
Host smart-7a3b304c-ee76-457e-b19e-5421b10bb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969680123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.969680123
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3530865037
Short name T842
Test name
Test status
Simulation time 85439049 ps
CPU time 2.62 seconds
Started Jul 02 07:57:51 AM PDT 24
Finished Jul 02 07:58:16 AM PDT 24
Peak memory 207160 kb
Host smart-ce94901e-4d53-41ec-b255-884030b3e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530865037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3530865037
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1941296937
Short name T94
Test name
Test status
Simulation time 245942227 ps
CPU time 5.22 seconds
Started Jul 02 07:58:08 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 214340 kb
Host smart-10a2a2d7-b5a5-4241-b4c1-6276038992e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941296937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1941296937
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1963273458
Short name T240
Test name
Test status
Simulation time 421677888 ps
CPU time 4.56 seconds
Started Jul 02 07:58:12 AM PDT 24
Finished Jul 02 07:58:39 AM PDT 24
Peak memory 214320 kb
Host smart-ebb1f65c-5c1a-423f-a070-7ad43cf12758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963273458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1963273458
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2851450041
Short name T215
Test name
Test status
Simulation time 106525661 ps
CPU time 3.98 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 220364 kb
Host smart-972692a8-098d-4866-9688-5045a85f1e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851450041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2851450041
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2018643547
Short name T266
Test name
Test status
Simulation time 141841634 ps
CPU time 2.59 seconds
Started Jul 02 07:57:57 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 207568 kb
Host smart-6f5586f4-b884-489b-85a8-80888330528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018643547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2018643547
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2500543605
Short name T317
Test name
Test status
Simulation time 238988242 ps
CPU time 2.86 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 206756 kb
Host smart-fe0ead89-3ac8-4f60-a267-71b74015efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500543605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2500543605
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3635100157
Short name T479
Test name
Test status
Simulation time 479301539 ps
CPU time 3.38 seconds
Started Jul 02 07:58:07 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 208600 kb
Host smart-6042f6b0-1c2f-4ca0-a63d-960dba427c77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635100157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3635100157
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1955544295
Short name T694
Test name
Test status
Simulation time 1721586043 ps
CPU time 6.34 seconds
Started Jul 02 07:58:08 AM PDT 24
Finished Jul 02 07:58:38 AM PDT 24
Peak memory 206796 kb
Host smart-3ba349f9-da1e-4c9a-a39a-f3994e478c17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955544295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1955544295
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1928652302
Short name T496
Test name
Test status
Simulation time 835155285 ps
CPU time 6.05 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 208324 kb
Host smart-25c3d5ce-7876-4f0e-a80a-d564eb0654a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928652302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1928652302
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4186256568
Short name T676
Test name
Test status
Simulation time 138296791 ps
CPU time 3.87 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 209860 kb
Host smart-9f3f87f2-1a94-45de-a603-dec3778c250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186256568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4186256568
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4018823771
Short name T442
Test name
Test status
Simulation time 75637508 ps
CPU time 2.97 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 208372 kb
Host smart-e83d31e7-7635-4045-99f8-a5aacc6d817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018823771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4018823771
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1473771723
Short name T11
Test name
Test status
Simulation time 1125506382 ps
CPU time 19.48 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:52 AM PDT 24
Peak memory 218324 kb
Host smart-b9ba7aaa-aa97-4e92-ae52-9add21d04dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473771723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1473771723
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2459417599
Short name T100
Test name
Test status
Simulation time 8896974 ps
CPU time 0.84 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 205832 kb
Host smart-755f7aa6-adf7-45c1-a714-e5504cba5264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459417599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2459417599
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1505318383
Short name T80
Test name
Test status
Simulation time 68806346 ps
CPU time 3.95 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:35 AM PDT 24
Peak memory 214272 kb
Host smart-6ddf7816-146c-4dd4-94a7-5e996169d528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505318383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1505318383
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.968172077
Short name T32
Test name
Test status
Simulation time 574389533 ps
CPU time 2.03 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 220880 kb
Host smart-48c93b0a-4402-4161-898f-de6ab7dae6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968172077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.968172077
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3262776811
Short name T554
Test name
Test status
Simulation time 64831795 ps
CPU time 1.94 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 208040 kb
Host smart-4cdc2b11-1717-4ade-9b92-d08a94fc3c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262776811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3262776811
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1931941425
Short name T279
Test name
Test status
Simulation time 106420240 ps
CPU time 2.13 seconds
Started Jul 02 07:58:03 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 214204 kb
Host smart-c518e389-819a-4d5e-8d9b-7621556465af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931941425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1931941425
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2679084251
Short name T630
Test name
Test status
Simulation time 172353960 ps
CPU time 4.43 seconds
Started Jul 02 07:58:07 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 222480 kb
Host smart-b2a371a7-c2ae-4326-a8fe-f2cfef00d670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679084251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2679084251
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3491469565
Short name T397
Test name
Test status
Simulation time 161033541 ps
CPU time 3.4 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 214396 kb
Host smart-86ac4b16-a585-4daa-bb48-939fc1652099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491469565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3491469565
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2100654691
Short name T544
Test name
Test status
Simulation time 40265291 ps
CPU time 2.67 seconds
Started Jul 02 07:57:53 AM PDT 24
Finished Jul 02 07:58:18 AM PDT 24
Peak memory 207496 kb
Host smart-a8c3dc88-223c-43e1-a393-2e3f528b0aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100654691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2100654691
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.734619567
Short name T303
Test name
Test status
Simulation time 116025249 ps
CPU time 3.88 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 208428 kb
Host smart-ae15313b-33d0-4385-b17e-4523e3ede492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734619567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.734619567
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2778032873
Short name T443
Test name
Test status
Simulation time 452952421 ps
CPU time 5.62 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208780 kb
Host smart-aabe646f-104f-45c9-9861-54542db34f24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778032873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2778032873
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1015646599
Short name T854
Test name
Test status
Simulation time 402595772 ps
CPU time 8.19 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 208872 kb
Host smart-8cf30035-7c44-4b13-9dc5-d1b87fd6cb99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015646599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1015646599
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2965179790
Short name T475
Test name
Test status
Simulation time 189451187 ps
CPU time 2.56 seconds
Started Jul 02 07:57:58 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 206888 kb
Host smart-f3c95125-7f48-4aaa-8894-37a6e4345356
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965179790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2965179790
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.442599874
Short name T587
Test name
Test status
Simulation time 421254209 ps
CPU time 3.29 seconds
Started Jul 02 07:58:00 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 210024 kb
Host smart-09c8fcda-47e6-41cb-973e-2e7e12a63ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442599874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.442599874
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.983078319
Short name T507
Test name
Test status
Simulation time 203698653 ps
CPU time 2.56 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208664 kb
Host smart-b04800ef-d70c-4d78-a730-1319bca2d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983078319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.983078319
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2500288953
Short name T232
Test name
Test status
Simulation time 5214312148 ps
CPU time 35.51 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:59:03 AM PDT 24
Peak memory 215972 kb
Host smart-8e7e9dad-61c3-4a8b-890a-86ca5c7ec07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500288953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2500288953
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4232896720
Short name T234
Test name
Test status
Simulation time 107534386 ps
CPU time 4.46 seconds
Started Jul 02 07:58:23 AM PDT 24
Finished Jul 02 07:58:50 AM PDT 24
Peak memory 210088 kb
Host smart-dc7d6397-ad69-4f92-a6d2-87197fc0d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232896720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4232896720
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2720417062
Short name T186
Test name
Test status
Simulation time 60036206 ps
CPU time 2.65 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:35 AM PDT 24
Peak memory 209776 kb
Host smart-8a3ed636-fa0c-4997-8aec-b97f18924795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720417062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2720417062
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3328481205
Short name T180
Test name
Test status
Simulation time 14883810 ps
CPU time 0.77 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 205968 kb
Host smart-68c941f3-d113-4496-9aa1-8cc2dc5d9acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328481205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3328481205
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.4203872640
Short name T377
Test name
Test status
Simulation time 56025245 ps
CPU time 3.75 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 215460 kb
Host smart-cbee14c0-b81d-43a1-9bea-21f13dcb96d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203872640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.4203872640
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3177965865
Short name T70
Test name
Test status
Simulation time 126602871 ps
CPU time 2.32 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 208252 kb
Host smart-0161eabd-c9ab-4670-953f-efd3bad125f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177965865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3177965865
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4052974646
Short name T84
Test name
Test status
Simulation time 1453631333 ps
CPU time 4.66 seconds
Started Jul 02 07:57:50 AM PDT 24
Finished Jul 02 07:58:17 AM PDT 24
Peak memory 208844 kb
Host smart-202d2dce-76b0-46c3-a3f5-a65f325d9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052974646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4052974646
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4153247679
Short name T671
Test name
Test status
Simulation time 79236637 ps
CPU time 3.02 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 220664 kb
Host smart-ea8805df-e372-4408-b343-57512df04c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153247679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4153247679
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3632472166
Short name T441
Test name
Test status
Simulation time 895559103 ps
CPU time 4.5 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 210284 kb
Host smart-c6bb0332-c24f-47f6-836d-abcdd24e7cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632472166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3632472166
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2788765222
Short name T382
Test name
Test status
Simulation time 131813299 ps
CPU time 5.22 seconds
Started Jul 02 07:57:55 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 209612 kb
Host smart-c454bd62-03d0-4040-bae0-fdf188a21ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788765222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2788765222
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.898683434
Short name T512
Test name
Test status
Simulation time 142253740 ps
CPU time 4 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 208448 kb
Host smart-8ce4c558-3546-4951-871d-0cf54f19a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898683434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.898683434
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1183639575
Short name T652
Test name
Test status
Simulation time 34317321 ps
CPU time 2.28 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 208880 kb
Host smart-ace7f0b5-f06b-47b4-ba90-364908fa1f57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183639575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1183639575
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3203606402
Short name T702
Test name
Test status
Simulation time 226119174 ps
CPU time 2.68 seconds
Started Jul 02 07:58:03 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 206820 kb
Host smart-27548339-7824-4881-9669-c245dbf893e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203606402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3203606402
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3990084941
Short name T273
Test name
Test status
Simulation time 253514960 ps
CPU time 4.32 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:34 AM PDT 24
Peak memory 207940 kb
Host smart-46622df0-6e3f-4ac7-a8a0-a19588fe8ddb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990084941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3990084941
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1320754072
Short name T349
Test name
Test status
Simulation time 3813944829 ps
CPU time 15.92 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:50 AM PDT 24
Peak memory 214292 kb
Host smart-39ca2740-2197-4f99-9011-5ad810c21d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320754072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1320754072
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3589492796
Short name T825
Test name
Test status
Simulation time 49583086 ps
CPU time 2.44 seconds
Started Jul 02 07:58:14 AM PDT 24
Finished Jul 02 07:58:39 AM PDT 24
Peak memory 206784 kb
Host smart-4bbc7360-9b1a-4b5f-a2f0-2a1be134fae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589492796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3589492796
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3478102262
Short name T631
Test name
Test status
Simulation time 438054002 ps
CPU time 7.2 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 208668 kb
Host smart-261264ca-43b7-4618-864f-7f776cd83fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478102262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3478102262
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3321576470
Short name T912
Test name
Test status
Simulation time 212410400 ps
CPU time 2.23 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:24 AM PDT 24
Peak memory 210592 kb
Host smart-ba9c9399-6de8-4614-8e63-611a4cc2f639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321576470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3321576470
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.324268884
Short name T16
Test name
Test status
Simulation time 107193242 ps
CPU time 0.9 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 206104 kb
Host smart-39f71b68-abe8-4a4e-898f-920e4de1b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324268884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.324268884
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.795325510
Short name T65
Test name
Test status
Simulation time 622616363 ps
CPU time 3.42 seconds
Started Jul 02 07:58:07 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 214672 kb
Host smart-9bc2ed71-7302-4a86-8ce4-92d1469fc692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795325510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.795325510
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1645184950
Short name T840
Test name
Test status
Simulation time 430949692 ps
CPU time 8.44 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:38 AM PDT 24
Peak memory 214288 kb
Host smart-38708a7d-c2f6-43b9-96bb-0e66933aeed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645184950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1645184950
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.465793363
Short name T262
Test name
Test status
Simulation time 78645035 ps
CPU time 3.64 seconds
Started Jul 02 07:58:12 AM PDT 24
Finished Jul 02 07:58:38 AM PDT 24
Peak memory 214208 kb
Host smart-491787c8-ea8a-429d-9c51-647210f26660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465793363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.465793363
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1603420736
Short name T45
Test name
Test status
Simulation time 421085691 ps
CPU time 2.78 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 214284 kb
Host smart-dffc5f26-955e-4318-9a53-fd836abf3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603420736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1603420736
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2011913496
Short name T211
Test name
Test status
Simulation time 35934469 ps
CPU time 2.52 seconds
Started Jul 02 07:58:20 AM PDT 24
Finished Jul 02 07:58:45 AM PDT 24
Peak memory 214296 kb
Host smart-9a607367-8567-4ff6-9056-30dc8c03b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011913496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2011913496
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3052355171
Short name T311
Test name
Test status
Simulation time 55503289 ps
CPU time 3.36 seconds
Started Jul 02 07:58:05 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 218332 kb
Host smart-d66f5be7-34c1-4dfd-a267-405a9ffd74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052355171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3052355171
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4191889989
Short name T493
Test name
Test status
Simulation time 194935953 ps
CPU time 2.55 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 207180 kb
Host smart-7f547586-8d37-44c9-89d4-ba11bb6cf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191889989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4191889989
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1970211218
Short name T787
Test name
Test status
Simulation time 317458765 ps
CPU time 5.04 seconds
Started Jul 02 07:58:18 AM PDT 24
Finished Jul 02 07:58:46 AM PDT 24
Peak memory 208284 kb
Host smart-ff4a27c5-57dc-4b47-9ff8-bf9d5fd60dd1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970211218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1970211218
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1507393449
Short name T612
Test name
Test status
Simulation time 395352096 ps
CPU time 9.21 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:42 AM PDT 24
Peak memory 208432 kb
Host smart-a2df9c4d-da8f-4eaa-933b-a3fe37938724
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507393449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1507393449
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3591363070
Short name T639
Test name
Test status
Simulation time 69516651 ps
CPU time 3.03 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 208144 kb
Host smart-785d245d-150c-43fb-9f06-1da036e112b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591363070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3591363070
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.423510493
Short name T309
Test name
Test status
Simulation time 338159256 ps
CPU time 4.17 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 220604 kb
Host smart-39462f3c-4440-40d4-a1cf-96933d208994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423510493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.423510493
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3330781011
Short name T709
Test name
Test status
Simulation time 164649809 ps
CPU time 2.43 seconds
Started Jul 02 07:58:01 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 208464 kb
Host smart-4d4ed156-bde3-4ddd-91a6-ef0a7b2bcd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330781011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3330781011
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.627213082
Short name T176
Test name
Test status
Simulation time 390655893 ps
CPU time 13.38 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 222472 kb
Host smart-9f75e262-282f-41a0-8e96-6afc30c12f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627213082 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.627213082
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.462459004
Short name T462
Test name
Test status
Simulation time 589697755 ps
CPU time 5.17 seconds
Started Jul 02 07:58:12 AM PDT 24
Finished Jul 02 07:58:40 AM PDT 24
Peak memory 209816 kb
Host smart-fbdfac90-1fdc-4897-9205-31ef94bb2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462459004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.462459004
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3366930191
Short name T602
Test name
Test status
Simulation time 115998997 ps
CPU time 2.57 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:35 AM PDT 24
Peak memory 209976 kb
Host smart-03d9782f-d9db-415c-a01d-91591fada275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366930191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3366930191
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4143596740
Short name T721
Test name
Test status
Simulation time 15934712 ps
CPU time 0.81 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 205864 kb
Host smart-745d3641-0e84-4c03-a57b-704678ac4939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143596740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4143596740
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3829440779
Short name T400
Test name
Test status
Simulation time 1128672391 ps
CPU time 15.53 seconds
Started Jul 02 07:58:16 AM PDT 24
Finished Jul 02 07:58:54 AM PDT 24
Peak memory 214260 kb
Host smart-8b50da7b-8b43-4d4f-b870-f5895c05a7de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829440779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3829440779
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1225323338
Short name T457
Test name
Test status
Simulation time 241659668 ps
CPU time 5.27 seconds
Started Jul 02 07:58:19 AM PDT 24
Finished Jul 02 07:58:47 AM PDT 24
Peak memory 210688 kb
Host smart-c32d76d6-6a69-4f96-b0bb-6552517a5193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225323338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1225323338
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2867481942
Short name T49
Test name
Test status
Simulation time 89369800 ps
CPU time 1.5 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 208672 kb
Host smart-df9f6c4a-426a-44b7-ba76-46c5ddcca01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867481942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2867481942
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3342973327
Short name T848
Test name
Test status
Simulation time 592038217 ps
CPU time 4.22 seconds
Started Jul 02 07:58:09 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 215384 kb
Host smart-dc01e08a-486b-4fba-b581-6e9b50c8d0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342973327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3342973327
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.590272047
Short name T591
Test name
Test status
Simulation time 238112074 ps
CPU time 3.4 seconds
Started Jul 02 07:58:06 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 210536 kb
Host smart-9cf7598e-0183-4d93-aab6-32d18ac3757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590272047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.590272047
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1578457544
Short name T570
Test name
Test status
Simulation time 85504726 ps
CPU time 4.3 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:30 AM PDT 24
Peak memory 209376 kb
Host smart-6698858c-3b17-4c0a-8075-512769e93d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578457544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1578457544
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1003835467
Short name T629
Test name
Test status
Simulation time 106633308 ps
CPU time 3.03 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:31 AM PDT 24
Peak memory 206888 kb
Host smart-e80b487c-429c-4570-9059-2f5395b46178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003835467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1003835467
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.124873221
Short name T108
Test name
Test status
Simulation time 140173775 ps
CPU time 3.85 seconds
Started Jul 02 07:58:02 AM PDT 24
Finished Jul 02 07:58:29 AM PDT 24
Peak memory 206992 kb
Host smart-6d3a76fd-236a-4c06-b4eb-3d84f9c83f97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124873221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.124873221
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3382230775
Short name T809
Test name
Test status
Simulation time 1787350453 ps
CPU time 21.52 seconds
Started Jul 02 07:58:10 AM PDT 24
Finished Jul 02 07:58:54 AM PDT 24
Peak memory 208848 kb
Host smart-5fe0fa12-a69b-4fb5-b0c5-4b607cb3d0ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382230775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3382230775
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2737599533
Short name T271
Test name
Test status
Simulation time 791883907 ps
CPU time 19.28 seconds
Started Jul 02 07:58:08 AM PDT 24
Finished Jul 02 07:58:51 AM PDT 24
Peak memory 208820 kb
Host smart-670384b4-eb61-4f5e-b74f-b587330b0a22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737599533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2737599533
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1473871717
Short name T287
Test name
Test status
Simulation time 1093605908 ps
CPU time 32.48 seconds
Started Jul 02 07:58:18 AM PDT 24
Finished Jul 02 07:59:13 AM PDT 24
Peak memory 214296 kb
Host smart-7c3a2873-1647-4b2d-a0fa-4d45b54e958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473871717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1473871717
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2771437887
Short name T492
Test name
Test status
Simulation time 17834268 ps
CPU time 1.61 seconds
Started Jul 02 07:57:59 AM PDT 24
Finished Jul 02 07:58:23 AM PDT 24
Peak memory 206704 kb
Host smart-a533939a-24f7-4918-8168-9fdaa0ea30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771437887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2771437887
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2281216855
Short name T758
Test name
Test status
Simulation time 3220842804 ps
CPU time 31.76 seconds
Started Jul 02 07:58:32 AM PDT 24
Finished Jul 02 07:59:23 AM PDT 24
Peak memory 216140 kb
Host smart-e2329b8b-fe7a-4998-816a-e69bd9e53565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281216855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2281216855
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.897272897
Short name T597
Test name
Test status
Simulation time 803396613 ps
CPU time 8.99 seconds
Started Jul 02 07:58:04 AM PDT 24
Finished Jul 02 07:58:37 AM PDT 24
Peak memory 210368 kb
Host smart-104425e7-7192-46a6-a7d6-2c8fd9673ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897272897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.897272897
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3291421945
Short name T714
Test name
Test status
Simulation time 61663960 ps
CPU time 1.88 seconds
Started Jul 02 07:58:11 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 210352 kb
Host smart-8c3f536e-42a3-4e12-9f81-e43c5ac0d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291421945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3291421945
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2038620535
Short name T866
Test name
Test status
Simulation time 9220369 ps
CPU time 0.79 seconds
Started Jul 02 07:56:12 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 206184 kb
Host smart-368aba4f-3bde-4128-b5bd-4b7fcedb59bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038620535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2038620535
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2805216722
Short name T604
Test name
Test status
Simulation time 35543993 ps
CPU time 2.7 seconds
Started Jul 02 07:56:11 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 214184 kb
Host smart-759f24c5-fcff-4e5b-8793-2882110f9123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805216722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2805216722
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.301076641
Short name T207
Test name
Test status
Simulation time 175411905 ps
CPU time 3.92 seconds
Started Jul 02 07:56:10 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 221532 kb
Host smart-48ce1364-3316-4ea5-90dd-b0df803be0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301076641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.301076641
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2586548097
Short name T485
Test name
Test status
Simulation time 27498980 ps
CPU time 1.69 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 207824 kb
Host smart-5cfb38a2-9cb4-4067-aef4-fb8735f0e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586548097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2586548097
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4022580945
Short name T326
Test name
Test status
Simulation time 43746904 ps
CPU time 1.59 seconds
Started Jul 02 07:56:20 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 214212 kb
Host smart-279f83f9-06cb-4b81-87aa-15ddf9d23fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022580945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4022580945
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1316408108
Short name T890
Test name
Test status
Simulation time 142464651 ps
CPU time 3.73 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 206100 kb
Host smart-0d331aaf-2025-4cb2-a0b5-1f354403cde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316408108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1316408108
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2875446738
Short name T242
Test name
Test status
Simulation time 521299101 ps
CPU time 3.86 seconds
Started Jul 02 07:56:15 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 219692 kb
Host smart-98684291-08f8-4fc1-8449-7d22d69441ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875446738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2875446738
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.188103346
Short name T899
Test name
Test status
Simulation time 27716950 ps
CPU time 2.16 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 207056 kb
Host smart-7be71dea-6652-49ac-9ce7-251d4d91facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188103346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.188103346
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3776735680
Short name T439
Test name
Test status
Simulation time 141334267 ps
CPU time 4.28 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 206772 kb
Host smart-8b667227-070f-4837-8d35-c4eb10f2f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776735680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3776735680
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1144203193
Short name T681
Test name
Test status
Simulation time 232633542 ps
CPU time 3.84 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:37 AM PDT 24
Peak memory 208568 kb
Host smart-22b18a10-8c07-4390-ab4d-f020fb5c4789
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144203193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1144203193
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3442285807
Short name T888
Test name
Test status
Simulation time 110362194 ps
CPU time 3.79 seconds
Started Jul 02 07:56:06 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 206892 kb
Host smart-a1ca025b-5a76-4b25-9cdd-0773a94ead29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442285807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3442285807
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3723659222
Short name T195
Test name
Test status
Simulation time 186995871 ps
CPU time 2.94 seconds
Started Jul 02 07:56:19 AM PDT 24
Finished Jul 02 07:56:45 AM PDT 24
Peak memory 208780 kb
Host smart-59695acd-76aa-4386-b615-caca419c29a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723659222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3723659222
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2017461371
Short name T859
Test name
Test status
Simulation time 1566516196 ps
CPU time 7.7 seconds
Started Jul 02 07:56:09 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 208780 kb
Host smart-22410fde-0cd5-461c-8320-bc22e80978a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017461371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2017461371
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3261397081
Short name T425
Test name
Test status
Simulation time 1653631489 ps
CPU time 38.74 seconds
Started Jul 02 07:56:16 AM PDT 24
Finished Jul 02 07:57:19 AM PDT 24
Peak memory 208364 kb
Host smart-c9082a10-c671-4713-9cd1-d6c0db0ad0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261397081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3261397081
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1982670936
Short name T347
Test name
Test status
Simulation time 1290394090 ps
CPU time 40.37 seconds
Started Jul 02 07:56:26 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 215388 kb
Host smart-1a4b4d5e-8714-421c-b0e1-0c8aa60d428d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982670936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1982670936
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3683822690
Short name T76
Test name
Test status
Simulation time 455798306 ps
CPU time 5.25 seconds
Started Jul 02 07:56:19 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 218628 kb
Host smart-deb7a7d7-6a21-4b4a-835f-52f182809c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683822690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3683822690
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.56813189
Short name T675
Test name
Test status
Simulation time 78129048 ps
CPU time 1.74 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 214284 kb
Host smart-1a38878b-891a-4e1b-8794-1022b9fc23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56813189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.56813189
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1948834921
Short name T413
Test name
Test status
Simulation time 87129163 ps
CPU time 0.88 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 205968 kb
Host smart-cd0e0164-a7cf-411b-af6b-7b625d03a306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948834921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1948834921
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2779350488
Short name T794
Test name
Test status
Simulation time 561316270 ps
CPU time 29.21 seconds
Started Jul 02 07:56:12 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 214812 kb
Host smart-8205bbbb-2ffc-477b-9d4e-8bff26335ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779350488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2779350488
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3495244698
Short name T217
Test name
Test status
Simulation time 592230026 ps
CPU time 6.58 seconds
Started Jul 02 07:56:21 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 222824 kb
Host smart-2aff7b5b-28ce-46f2-9541-6f8f6140a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495244698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3495244698
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3085430771
Short name T781
Test name
Test status
Simulation time 35174302 ps
CPU time 1.85 seconds
Started Jul 02 07:56:08 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 208732 kb
Host smart-3532ea43-0df3-4f8c-ac86-aca4a6ccdb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085430771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3085430771
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4022802918
Short name T356
Test name
Test status
Simulation time 99715472 ps
CPU time 1.85 seconds
Started Jul 02 07:56:33 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 214368 kb
Host smart-307eb793-3de7-4bba-bf40-307ff6399bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022802918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4022802918
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3256627293
Short name T323
Test name
Test status
Simulation time 150062808 ps
CPU time 3.33 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:56:45 AM PDT 24
Peak memory 214192 kb
Host smart-88f73c2d-bfed-4811-86b5-54aeb66981f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256627293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3256627293
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3727755008
Short name T763
Test name
Test status
Simulation time 1314084803 ps
CPU time 4.04 seconds
Started Jul 02 07:56:24 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 209468 kb
Host smart-600ba2cb-293c-43e0-8b5b-d0a25c2247c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727755008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3727755008
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1612837759
Short name T707
Test name
Test status
Simulation time 249505712 ps
CPU time 3.64 seconds
Started Jul 02 07:56:10 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 209524 kb
Host smart-91f050d7-48ba-4b9b-a84c-a190b44b7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612837759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1612837759
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3825870668
Short name T244
Test name
Test status
Simulation time 1211444872 ps
CPU time 6.07 seconds
Started Jul 02 07:56:14 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 208444 kb
Host smart-8d369d22-a842-4336-9ad7-4e224fd3b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825870668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3825870668
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1737293350
Short name T318
Test name
Test status
Simulation time 508928121 ps
CPU time 4.19 seconds
Started Jul 02 07:56:21 AM PDT 24
Finished Jul 02 07:56:46 AM PDT 24
Peak memory 206956 kb
Host smart-f0de760c-a6d5-41eb-9d8b-5c988334f210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737293350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1737293350
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2329410865
Short name T834
Test name
Test status
Simulation time 174248936 ps
CPU time 4.43 seconds
Started Jul 02 07:56:10 AM PDT 24
Finished Jul 02 07:56:39 AM PDT 24
Peak memory 208760 kb
Host smart-aa519ed0-e553-4618-b600-6352f94abbef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329410865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2329410865
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.245211522
Short name T743
Test name
Test status
Simulation time 27368754 ps
CPU time 2.17 seconds
Started Jul 02 07:56:16 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 208612 kb
Host smart-625b431d-4c65-4311-92a1-591b31240b55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245211522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.245211522
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4123701810
Short name T79
Test name
Test status
Simulation time 79920910 ps
CPU time 3.87 seconds
Started Jul 02 07:56:33 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 214288 kb
Host smart-9fa473fe-8597-4781-b0e9-36e0682a8c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123701810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4123701810
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3878660803
Short name T125
Test name
Test status
Simulation time 49405545 ps
CPU time 2.39 seconds
Started Jul 02 07:56:10 AM PDT 24
Finished Jul 02 07:56:38 AM PDT 24
Peak memory 206636 kb
Host smart-f9f46dbe-9c61-4e34-99e4-50ae312fb9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878660803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3878660803
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.789687734
Short name T327
Test name
Test status
Simulation time 3053033654 ps
CPU time 30.83 seconds
Started Jul 02 07:56:35 AM PDT 24
Finished Jul 02 07:57:21 AM PDT 24
Peak memory 216784 kb
Host smart-91328dee-736e-4383-b337-b2df32c6e4aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789687734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.789687734
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1123609100
Short name T688
Test name
Test status
Simulation time 58961318 ps
CPU time 3.88 seconds
Started Jul 02 07:56:24 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 209808 kb
Host smart-2b94f2f3-c56a-4a3b-86a2-0cf7bcd51346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123609100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1123609100
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3271229372
Short name T771
Test name
Test status
Simulation time 13865008 ps
CPU time 0.74 seconds
Started Jul 02 07:56:33 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 205964 kb
Host smart-06537dd0-95b5-49b2-bb4a-992e7138864a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271229372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3271229372
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.975852427
Short name T173
Test name
Test status
Simulation time 69065887 ps
CPU time 2.28 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:46 AM PDT 24
Peak memory 214820 kb
Host smart-c0317215-ead4-4c3b-9acb-6bef369cb846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975852427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.975852427
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4284712640
Short name T348
Test name
Test status
Simulation time 35799767 ps
CPU time 2.38 seconds
Started Jul 02 07:56:19 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 222448 kb
Host smart-57e9da7d-8ee9-4235-897e-da7a0d397f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284712640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4284712640
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.313570219
Short name T20
Test name
Test status
Simulation time 140378974 ps
CPU time 5.51 seconds
Started Jul 02 07:56:19 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 214296 kb
Host smart-d4662103-f8bb-42a0-93fe-c53dbe083628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313570219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.313570219
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.625947457
Short name T508
Test name
Test status
Simulation time 73106248 ps
CPU time 2.99 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:44 AM PDT 24
Peak memory 214220 kb
Host smart-0842a625-bb2e-457b-bbe0-1eb4842461df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625947457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.625947457
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1471138242
Short name T510
Test name
Test status
Simulation time 698663679 ps
CPU time 7.62 seconds
Started Jul 02 07:56:14 AM PDT 24
Finished Jul 02 07:56:46 AM PDT 24
Peak memory 208012 kb
Host smart-d25fddc4-0704-4e6a-adc7-e780dd8f58f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471138242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1471138242
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1533063751
Short name T900
Test name
Test status
Simulation time 364823611 ps
CPU time 4.46 seconds
Started Jul 02 07:56:26 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 208676 kb
Host smart-f9d099b5-dc2d-41a2-9188-9d2259232859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533063751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1533063751
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1871219711
Short name T894
Test name
Test status
Simulation time 184422171 ps
CPU time 2.52 seconds
Started Jul 02 07:56:15 AM PDT 24
Finished Jul 02 07:56:42 AM PDT 24
Peak memory 206956 kb
Host smart-52d08f18-f0a0-4563-82d0-068970ee61ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871219711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1871219711
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1574591662
Short name T525
Test name
Test status
Simulation time 339267912 ps
CPU time 5.54 seconds
Started Jul 02 07:56:15 AM PDT 24
Finished Jul 02 07:56:45 AM PDT 24
Peak memory 208044 kb
Host smart-2b28ae80-ead2-4f5d-8b70-800edb05e8a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574591662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1574591662
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1213265477
Short name T716
Test name
Test status
Simulation time 42417507 ps
CPU time 2.56 seconds
Started Jul 02 07:56:17 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 208536 kb
Host smart-94e2b40d-07a5-4d80-b656-d6e8053096f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213265477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1213265477
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1590741379
Short name T387
Test name
Test status
Simulation time 70936046 ps
CPU time 1.54 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 207212 kb
Host smart-e4ea62f2-1180-4524-aeab-1ae5e0c65649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590741379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1590741379
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2687004367
Short name T806
Test name
Test status
Simulation time 2632998339 ps
CPU time 23.97 seconds
Started Jul 02 07:56:18 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 207788 kb
Host smart-a0e11aa7-5e96-4798-ab91-080bd8b26031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687004367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2687004367
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3049933274
Short name T361
Test name
Test status
Simulation time 331580440 ps
CPU time 9.35 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 215516 kb
Host smart-d0b514b5-4626-4820-ae92-b673ffe68b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049933274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3049933274
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3170239874
Short name T268
Test name
Test status
Simulation time 223546181 ps
CPU time 2.45 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:46 AM PDT 24
Peak memory 210276 kb
Host smart-38852615-ceba-4566-aa71-654638affcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170239874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3170239874
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2474287470
Short name T865
Test name
Test status
Simulation time 279870474 ps
CPU time 6.32 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 210596 kb
Host smart-70e74f3d-53ab-4083-9293-5af168148382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474287470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2474287470
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.32047249
Short name T411
Test name
Test status
Simulation time 181500801 ps
CPU time 0.98 seconds
Started Jul 02 07:56:21 AM PDT 24
Finished Jul 02 07:56:43 AM PDT 24
Peak memory 206000 kb
Host smart-3d0a9581-4d30-4495-a073-04524ae55966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.32047249
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2399279642
Short name T885
Test name
Test status
Simulation time 194879563 ps
CPU time 9.95 seconds
Started Jul 02 07:56:40 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 215400 kb
Host smart-b1f0ec3c-a0b9-41b2-b2f6-89e854c7ff80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399279642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2399279642
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3573940547
Short name T632
Test name
Test status
Simulation time 67502965 ps
CPU time 3.58 seconds
Started Jul 02 07:56:35 AM PDT 24
Finished Jul 02 07:56:54 AM PDT 24
Peak memory 218484 kb
Host smart-c77aea5f-4cc1-415f-8318-e2b671bd97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573940547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3573940547
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3579256461
Short name T868
Test name
Test status
Simulation time 86553914 ps
CPU time 1.55 seconds
Started Jul 02 07:56:25 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 208364 kb
Host smart-a88599c1-4e80-4a39-b560-6c93fc69e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579256461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3579256461
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.321614210
Short name T605
Test name
Test status
Simulation time 239519467 ps
CPU time 2.67 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 221132 kb
Host smart-e1fedc99-f4f0-4698-a461-4146aad4a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321614210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.321614210
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3833750862
Short name T307
Test name
Test status
Simulation time 44338173 ps
CPU time 2.04 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 220648 kb
Host smart-62266c28-ad76-42af-9563-34064aa5da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833750862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3833750862
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4075648658
Short name T534
Test name
Test status
Simulation time 166467633 ps
CPU time 3.51 seconds
Started Jul 02 07:56:25 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 219980 kb
Host smart-1bdce254-c46f-49b0-a279-64fb77cb0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075648658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4075648658
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.86207515
Short name T196
Test name
Test status
Simulation time 189291277 ps
CPU time 4.95 seconds
Started Jul 02 07:56:24 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 218244 kb
Host smart-dcc3d7b6-effc-42fc-9cb6-bbffe9807a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86207515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.86207515
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1593863208
Short name T826
Test name
Test status
Simulation time 255300121 ps
CPU time 9.26 seconds
Started Jul 02 07:56:28 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 208652 kb
Host smart-64eabfe2-c227-4d81-92f5-3d6b6a0afda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593863208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1593863208
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1201661993
Short name T727
Test name
Test status
Simulation time 131873389 ps
CPU time 2.51 seconds
Started Jul 02 07:56:33 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 206788 kb
Host smart-0d4a375c-c532-4c29-bc27-c40e0fe43478
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201661993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1201661993
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2279375971
Short name T270
Test name
Test status
Simulation time 55548196 ps
CPU time 2.85 seconds
Started Jul 02 07:56:20 AM PDT 24
Finished Jul 02 07:56:45 AM PDT 24
Peak memory 206816 kb
Host smart-66a80890-902d-40ec-8980-9bbefe93e9d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279375971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2279375971
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2862529603
Short name T661
Test name
Test status
Simulation time 230292198 ps
CPU time 2.81 seconds
Started Jul 02 07:56:51 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 206820 kb
Host smart-782c42bd-f8b3-47f6-882d-24e229085e68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862529603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2862529603
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3831270173
Short name T783
Test name
Test status
Simulation time 223216888 ps
CPU time 3.25 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 218096 kb
Host smart-f5dea10f-a694-4401-8d3b-ee860ff64c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831270173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3831270173
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3248575720
Short name T536
Test name
Test status
Simulation time 97137234 ps
CPU time 2.57 seconds
Started Jul 02 07:56:31 AM PDT 24
Finished Jul 02 07:56:51 AM PDT 24
Peak memory 206664 kb
Host smart-3d833edf-ebc9-4980-a2e7-abc9793248cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248575720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3248575720
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3626840708
Short name T320
Test name
Test status
Simulation time 7909474370 ps
CPU time 59.43 seconds
Started Jul 02 07:56:34 AM PDT 24
Finished Jul 02 07:57:49 AM PDT 24
Peak memory 216012 kb
Host smart-dcf7a52b-f1e5-4fd4-a6f1-5d4ba992ff1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626840708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3626840708
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.822612390
Short name T120
Test name
Test status
Simulation time 1524575130 ps
CPU time 11.13 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 222500 kb
Host smart-691606fd-06c4-45f0-86e8-71664456e001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822612390 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.822612390
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2325362321
Short name T391
Test name
Test status
Simulation time 566898728 ps
CPU time 7.65 seconds
Started Jul 02 07:56:23 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 208140 kb
Host smart-52dc0c7c-dbc9-4b52-84a5-69df1dbffe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325362321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2325362321
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.718268344
Short name T558
Test name
Test status
Simulation time 716008803 ps
CPU time 3.2 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 210776 kb
Host smart-04dfed12-c4a7-43cf-9931-124e914ba293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718268344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.718268344
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3972951395
Short name T628
Test name
Test status
Simulation time 23675483 ps
CPU time 0.8 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 205884 kb
Host smart-b9fa53f7-9228-43e3-b670-4c8b197f6d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972951395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3972951395
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.876510265
Short name T654
Test name
Test status
Simulation time 30286380 ps
CPU time 1.63 seconds
Started Jul 02 07:56:38 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 209788 kb
Host smart-b5c333b1-d175-410e-9cab-932a31bd9d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876510265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.876510265
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1380911066
Short name T878
Test name
Test status
Simulation time 84967307 ps
CPU time 2.96 seconds
Started Jul 02 07:56:28 AM PDT 24
Finished Jul 02 07:56:50 AM PDT 24
Peak memory 214356 kb
Host smart-4e7af165-5e73-4f0c-887c-06898f72f4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380911066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1380911066
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.138797711
Short name T330
Test name
Test status
Simulation time 1250100904 ps
CPU time 4.23 seconds
Started Jul 02 07:56:33 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 220364 kb
Host smart-e7513a04-e58e-41a3-8e09-3684b1053587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138797711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.138797711
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.38573737
Short name T679
Test name
Test status
Simulation time 240565089 ps
CPU time 5.51 seconds
Started Jul 02 07:56:35 AM PDT 24
Finished Jul 02 07:56:56 AM PDT 24
Peak memory 207504 kb
Host smart-36dcdb93-2c4b-4868-b8d5-300739669f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38573737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.38573737
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3591842064
Short name T338
Test name
Test status
Simulation time 643132494 ps
CPU time 7.63 seconds
Started Jul 02 07:56:42 AM PDT 24
Finished Jul 02 07:57:05 AM PDT 24
Peak memory 206588 kb
Host smart-a6a3b176-dd2b-4d4c-8728-202b1027e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591842064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3591842064
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1202471452
Short name T873
Test name
Test status
Simulation time 72625772 ps
CPU time 3.1 seconds
Started Jul 02 07:56:21 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 206736 kb
Host smart-54b3be39-191a-4e2e-920f-de022c67736d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202471452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1202471452
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2666051255
Short name T670
Test name
Test status
Simulation time 373931847 ps
CPU time 3.58 seconds
Started Jul 02 07:56:22 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 208852 kb
Host smart-1a49037c-e5a8-4ad7-b298-abb7d1bc7db1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666051255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2666051255
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3075356382
Short name T636
Test name
Test status
Simulation time 192300864 ps
CPU time 3.01 seconds
Started Jul 02 07:56:49 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 208688 kb
Host smart-416de8fb-6ece-434d-ae50-eab28c6545ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075356382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3075356382
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2594752850
Short name T556
Test name
Test status
Simulation time 160378328 ps
CPU time 2.42 seconds
Started Jul 02 07:56:26 AM PDT 24
Finished Jul 02 07:56:48 AM PDT 24
Peak memory 216024 kb
Host smart-81089c11-cdb8-45d8-b1ed-acc366462e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594752850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2594752850
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3886565580
Short name T409
Test name
Test status
Simulation time 403651078 ps
CPU time 4.29 seconds
Started Jul 02 07:56:36 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 207736 kb
Host smart-645e90d3-02e8-47fa-9b13-2565a10a31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886565580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3886565580
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2705863527
Short name T551
Test name
Test status
Simulation time 777858362 ps
CPU time 18.6 seconds
Started Jul 02 07:56:29 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 209064 kb
Host smart-e362d81c-cb49-4246-9b8a-d63004bf7a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705863527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2705863527
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2266560844
Short name T55
Test name
Test status
Simulation time 465943457 ps
CPU time 17.82 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:57:04 AM PDT 24
Peak memory 221108 kb
Host smart-09ac5a28-30b0-45b6-a4c4-ebe3cfdd05de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266560844 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2266560844
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3185880055
Short name T231
Test name
Test status
Simulation time 863274224 ps
CPU time 9.73 seconds
Started Jul 02 07:56:37 AM PDT 24
Finished Jul 02 07:57:02 AM PDT 24
Peak memory 208836 kb
Host smart-d66dce46-3bff-4dfd-bd1b-f9c84a705d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185880055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3185880055
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1207554031
Short name T53
Test name
Test status
Simulation time 376702393 ps
CPU time 7.02 seconds
Started Jul 02 07:56:27 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 209972 kb
Host smart-68efbd02-6104-4c4e-a142-f45598ca893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207554031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1207554031
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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