Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
61122 |
1 |
|
|
T1 |
17 |
|
T2 |
69 |
|
T3 |
73 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36995 |
1 |
|
|
T1 |
9 |
|
T2 |
69 |
|
T3 |
18 |
auto[1] |
24127 |
1 |
|
|
T1 |
8 |
|
T3 |
55 |
|
T11 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30442 |
1 |
|
|
T2 |
35 |
|
T3 |
37 |
|
T11 |
20 |
auto[1] |
30680 |
1 |
|
|
T1 |
17 |
|
T2 |
34 |
|
T3 |
36 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
18162 |
1 |
|
|
T2 |
35 |
|
T3 |
9 |
|
T11 |
3 |
all_values[0] |
auto[0] |
auto[1] |
18833 |
1 |
|
|
T1 |
9 |
|
T2 |
34 |
|
T3 |
9 |
all_values[0] |
auto[1] |
auto[0] |
12280 |
1 |
|
|
T3 |
28 |
|
T11 |
17 |
|
T14 |
22 |
all_values[0] |
auto[1] |
auto[1] |
11847 |
1 |
|
|
T1 |
8 |
|
T3 |
27 |
|
T11 |
16 |