Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11676

1

T1

12

T2

12

T3

20

auto[Attestation]

8169

1

T1

3

T2

14

T3

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2970	1			T1	6		T2	1		T3	2
auto[Aes]	3621	1			T2	7		T3	9		T11	11
auto[Kmac]	3475	1			T1	2		T2	6		T3	1
auto[Otbn]	3501	1			T1	4		T2	3		T3	7

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8126	1			T1	2		T2	8		T3	8
auto[OpGenId]	6278	1			T1	3		T2	9		T3	9
auto[OpGenSwOut]	6353	1			T1	5		T2	7		T3	14
auto[OpGenHwOut]	7214	1			T1	7		T2	10		T3	5
auto[OpDisable]	147	1			T50	2		T51	1		T52	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11121

1

T1

5

T2

11

T3

15

auto[OpDoneFail]

16997

1

T1

12

T2

23

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6977	1			T1	10		T2	1		T3	10
auto[StInit]	3810	1			T1	4		T2	6		T3	2
auto[StCreatorRootKey]	3349	1			T1	3		T2	1		T3	6
auto[StOwnerIntKey]	2922	1			T2	3		T3	6		T11	2
auto[StOwnerKey]	2550	1			T2	5		T3	1		T11	2
auto[StDisabled]	8510	1			T2	18		T3	11		T11	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	376	1			T1	1		T12	1		T24	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	99	1			T12	1		T24	1		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T24	1		T45	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	80	1			T197	1		T196	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	78	1			T24	1		T198	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	246	1			T24	2		T45	1		T199	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	357	1			T3	2		T16	3		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	92	1			T58	1		T66	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T3	1		T34	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T3	2		T16	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T66	1		T194	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	252	1			T2	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	350	1			T12	2		T34	2		T24	7
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T2	2		T35	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T16	1		T24	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T45	1		T41	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T24	1		T45	2		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	230	1			T3	1		T24	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	359	1			T1	2		T3	3		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T66	1		T42	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T3	1		T24	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T16	1		T24	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T140	1		T203	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	219	1			T3	1		T24	3		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	106	1			T45	3		T50	1		T48	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T1	1		T2	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T14	1		T24	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T202	1		T200	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T24	1		T204	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	232	1			T3	1		T14	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	102	1			T45	3		T50	4		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	99	1			T197	1		T205	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T45	1		T64	1		T103	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	96	1			T2	1		T24	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T67	1		T196	1		T91	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	235	1			T2	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	90	1			T45	1		T50	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	88	1			T199	1		T59	2		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T14	1		T24	1		T135	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T34	1		T24	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T14	1		T45	3		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	222	1			T16	1		T24	3		T135	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	86	1			T45	1		T51	2		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	84	1			T1	1		T16	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T137	1		T205	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T50	2		T48	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T193	1		T194	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	267	1			T2	1		T16	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	297	1			T1	2		T3	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T1	1		T45	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T1	1		T14	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T24	2		T140	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T24	1		T45	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	196	1			T16	1		T24	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	489	1			T11	3		T12	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T2	1		T11	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	136	1			T3	1		T24	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	95	1			T11	1		T45	2		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T2	1		T16	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	304	1			T2	1		T11	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	438	1			T1	1		T12	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T17	1		T45	2		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T16	1		T92	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T12	1		T14	1		T211	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T14	1		T92	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	305	1			T2	3		T24	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	426	1			T1	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T16	1		T24	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T35	1		T137	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T12	1		T24	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T196	1		T106	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T16	1		T24	4		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T24	1		T50	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	87	1			T140	1		T153	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T14	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	76	1			T24	2		T199	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T24	2		T48	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	193	1			T24	2		T205	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	75	1			T45	3		T50	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	102	1			T24	1		T93	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T11	1		T136	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	110	1			T3	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	101	1			T2	1		T11	1		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	302	1			T11	3		T24	2		T93	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T45	1		T50	1		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T45	1		T92	1		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	127	1			T1	1		T45	2		T135	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T92	1		T135	1		T137	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T24	1		T66	1		T153	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	280	1			T2	1		T24	3		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	89	1			T51	1		T48	2		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T14	1		T24	2		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T16	1		T137	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	111	1			T3	1		T14	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	114	1			T139	1		T216	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	289	1			T2	2		T24	1		T45	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	223	1			T24	2		T45	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	747	1			T1	1		T12	2		T24	8
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	222	1			T3	3		T34	1		T138	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	717	1			T2	1		T3	3		T16	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T16	1		T24	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	708	1			T2	2		T3	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T3	1		T24	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	697	1			T1	2		T3	4		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	189	1			T14	1		T24	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	468	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	225	1			T2	1		T24	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	455	1			T2	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	212	1			T14	2		T34	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	415	1			T16	1		T24	3		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T205	1		T207	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	457	1			T1	1		T2	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T1	1		T14	1		T24	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	600	1			T1	3		T3	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	293	1			T2	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	933	1			T2	2		T11	5		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	271	1			T12	1		T14	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	891	1			T1	1		T2	3		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	275	1			T12	1		T24	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	847	1			T1	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T14	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	380	1			T24	4		T45	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	291	1			T2	1		T3	1		T11	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	485	1			T11	3		T24	3		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T1	1		T45	2		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	482	1			T2	1		T24	4		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	283	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	533	1			T2	2		T14	1		T24	3