Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34686

1

T1

17

T2

37

T3

39

auto[1]

301

1

T14

3

T135

3

T138

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	34695	1			T1	17		T2	37		T3	39
auto[134217728:268435455]	5	1			T142	1		T401	2		T402	1
auto[268435456:402653183]	13	1			T140	1		T381	1		T379	1
auto[402653184:536870911]	11	1			T299	1		T347	1		T403	2
auto[536870912:671088639]	11	1			T14	1		T141	1		T153	1
auto[671088640:805306367]	9	1			T141	1		T379	3		T267	1
auto[805306368:939524095]	6	1			T311	1		T403	1		T404	1
auto[939524096:1073741823]	6	1			T299	1		T311	1		T306	2
auto[1073741824:1207959551]	2	1			T258	1		T405	1		-	-
auto[1207959552:1342177279]	9	1			T258	2		T299	1		T406	1
auto[1342177280:1476395007]	7	1			T135	1		T258	1		T306	1
auto[1476395008:1610612735]	12	1			T14	1		T135	1		T380	1
auto[1610612736:1744830463]	6	1			T347	1		T407	1		T401	1
auto[1744830464:1879048191]	7	1			T144	1		T406	1		T348	1
auto[1879048192:2013265919]	9	1			T138	1		T153	1		T299	1
auto[2013265920:2147483647]	7	1			T138	1		T153	1		T144	1
auto[2147483648:2281701375]	10	1			T14	1		T141	1		T142	1
auto[2281701376:2415919103]	8	1			T140	1		T380	1		T299	1
auto[2415919104:2550136831]	11	1			T141	1		T142	1		T299	1
auto[2550136832:2684354559]	4	1			T258	1		T408	1		T401	1
auto[2684354560:2818572287]	9	1			T254	1		T386	1		T267	1
auto[2818572288:2952790015]	22	1			T135	1		T141	2		T153	1
auto[2952790016:3087007743]	9	1			T142	2		T379	1		T386	1
auto[3087007744:3221225471]	9	1			T141	1		T145	1		T258	2
auto[3221225472:3355443199]	10	1			T153	1		T144	1		T254	1
auto[3355443200:3489660927]	9	1			T258	1		T379	1		T403	1
auto[3489660928:3623878655]	25	1			T138	2		T380	1		T254	1
auto[3623878656:3758096383]	11	1			T138	1		T153	2		T379	1
auto[3758096384:3892314111]	8	1			T299	1		T267	1		T306	1
auto[3892314112:4026531839]	9	1			T138	1		T254	1		T299	2
auto[4026531840:4160749567]	8	1			T140	1		T254	1		T258	3
auto[4160749568:4294967295]	10	1			T138	1		T140	1		T258	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34686	1			T1	17		T2	37		T3	39
auto[0:134217727]	auto[1]	9	1			T138	1		T140	1		T254	1
auto[134217728:268435455]	auto[1]	5	1			T142	1		T401	2		T402	1
auto[268435456:402653183]	auto[1]	13	1			T140	1		T381	1		T379	1
auto[402653184:536870911]	auto[1]	11	1			T299	1		T347	1		T403	2
auto[536870912:671088639]	auto[1]	11	1			T14	1		T141	1		T153	1
auto[671088640:805306367]	auto[1]	9	1			T141	1		T379	3		T267	1
auto[805306368:939524095]	auto[1]	6	1			T311	1		T403	1		T404	1
auto[939524096:1073741823]	auto[1]	6	1			T299	1		T311	1		T306	2
auto[1073741824:1207959551]	auto[1]	2	1			T258	1		T405	1		-	-
auto[1207959552:1342177279]	auto[1]	9	1			T258	2		T299	1		T406	1
auto[1342177280:1476395007]	auto[1]	7	1			T135	1		T258	1		T306	1
auto[1476395008:1610612735]	auto[1]	12	1			T14	1		T135	1		T380	1
auto[1610612736:1744830463]	auto[1]	6	1			T347	1		T407	1		T401	1
auto[1744830464:1879048191]	auto[1]	7	1			T144	1		T406	1		T348	1
auto[1879048192:2013265919]	auto[1]	9	1			T138	1		T153	1		T299	1
auto[2013265920:2147483647]	auto[1]	7	1			T138	1		T153	1		T144	1
auto[2147483648:2281701375]	auto[1]	10	1			T14	1		T141	1		T142	1
auto[2281701376:2415919103]	auto[1]	8	1			T140	1		T380	1		T299	1
auto[2415919104:2550136831]	auto[1]	11	1			T141	1		T142	1		T299	1
auto[2550136832:2684354559]	auto[1]	4	1			T258	1		T408	1		T401	1
auto[2684354560:2818572287]	auto[1]	9	1			T254	1		T386	1		T267	1
auto[2818572288:2952790015]	auto[1]	22	1			T135	1		T141	2		T153	1
auto[2952790016:3087007743]	auto[1]	9	1			T142	2		T379	1		T386	1
auto[3087007744:3221225471]	auto[1]	9	1			T141	1		T145	1		T258	2
auto[3221225472:3355443199]	auto[1]	10	1			T153	1		T144	1		T254	1
auto[3355443200:3489660927]	auto[1]	9	1			T258	1		T379	1		T403	1
auto[3489660928:3623878655]	auto[1]	25	1			T138	2		T380	1		T254	1
auto[3623878656:3758096383]	auto[1]	11	1			T138	1		T153	2		T379	1
auto[3758096384:3892314111]	auto[1]	8	1			T299	1		T267	1		T306	1
auto[3892314112:4026531839]	auto[1]	9	1			T138	1		T254	1		T299	2
auto[4026531840:4160749567]	auto[1]	8	1			T140	1		T254	1		T258	3
auto[4160749568:4294967295]	auto[1]	10	1			T138	1		T140	1		T258	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1641

1

T2

3

T3

2

T12

2

auto[1]

1783

1

T2

2

T3

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T24	1		T36	1		T46	1
auto[134217728:268435455]	108	1			T14	1		T36	1		T46	1
auto[268435456:402653183]	92	1			T16	1		T24	3		T138	1
auto[402653184:536870911]	131	1			T24	1		T53	1		T137	1
auto[536870912:671088639]	124	1			T16	3		T24	2		T138	1
auto[671088640:805306367]	112	1			T45	1		T114	1		T106	1
auto[805306368:939524095]	100	1			T45	1		T46	1		T215	1
auto[939524096:1073741823]	122	1			T24	1		T40	1		T204	1
auto[1073741824:1207959551]	96	1			T3	1		T24	1		T40	1
auto[1207959552:1342177279]	115	1			T2	1		T24	1		T53	1
auto[1342177280:1476395007]	102	1			T24	1		T53	1		T199	1
auto[1476395008:1610612735]	115	1			T12	1		T24	3		T36	2
auto[1610612736:1744830463]	112	1			T46	1		T196	1		T106	1
auto[1744830464:1879048191]	80	1			T2	1		T12	1		T40	1
auto[1879048192:2013265919]	91	1			T24	1		T45	1		T40	2
auto[2013265920:2147483647]	105	1			T14	1		T215	1		T202	1
auto[2147483648:2281701375]	107	1			T3	1		T24	1		T202	2
auto[2281701376:2415919103]	117	1			T24	2		T135	1		T199	1
auto[2415919104:2550136831]	109	1			T24	1		T140	1		T47	1
auto[2550136832:2684354559]	98	1			T36	1		T200	2		T117	1
auto[2684354560:2818572287]	101	1			T24	1		T215	1		T204	1
auto[2818572288:2952790015]	116	1			T24	1		T137	2		T40	1
auto[2952790016:3087007743]	103	1			T2	1		T137	1		T140	1
auto[3087007744:3221225471]	97	1			T2	1		T14	1		T46	2
auto[3221225472:3355443199]	109	1			T16	1		T24	1		T46	1
auto[3355443200:3489660927]	117	1			T12	1		T16	1		T45	1
auto[3489660928:3623878655]	113	1			T3	1		T200	1		T48	1
auto[3623878656:3758096383]	94	1			T45	1		T40	1		T193	1
auto[3758096384:3892314111]	110	1			T40	1		T211	1		T62	1
auto[3892314112:4026531839]	129	1			T36	1		T53	1		T135	2
auto[4026531840:4160749567]	96	1			T3	1		T14	1		T193	1
auto[4160749568:4294967295]	105	1			T2	1		T12	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T24	1		T47	1		T18	1
auto[0:134217727]	auto[1]	60	1			T36	1		T46	1		T50	1
auto[134217728:268435455]	auto[0]	56	1			T46	1		T48	2		T63	2
auto[134217728:268435455]	auto[1]	52	1			T14	1		T36	1		T4	1
auto[268435456:402653183]	auto[0]	45	1			T16	1		T24	1		T153	1
auto[268435456:402653183]	auto[1]	47	1			T24	2		T138	1		T50	1
auto[402653184:536870911]	auto[0]	53	1			T48	1		T61	2		T63	1
auto[402653184:536870911]	auto[1]	78	1			T24	1		T53	1		T137	1
auto[536870912:671088639]	auto[0]	65	1			T16	3		T24	1		T138	1
auto[536870912:671088639]	auto[1]	59	1			T24	1		T48	2		T263	1
auto[671088640:805306367]	auto[0]	52	1			T45	1		T106	1		T305	1
auto[671088640:805306367]	auto[1]	60	1			T114	1		T61	1		T63	1
auto[805306368:939524095]	auto[0]	49	1			T46	1		T62	1		T48	1
auto[805306368:939524095]	auto[1]	51	1			T45	1		T215	1		T204	1
auto[939524096:1073741823]	auto[0]	53	1			T24	1		T204	1		T48	2
auto[939524096:1073741823]	auto[1]	69	1			T40	1		T50	1		T52	1
auto[1073741824:1207959551]	auto[0]	44	1			T3	1		T40	1		T153	1
auto[1073741824:1207959551]	auto[1]	52	1			T24	1		T114	1		T52	1
auto[1207959552:1342177279]	auto[0]	62	1			T215	1		T25	1		T51	1
auto[1207959552:1342177279]	auto[1]	53	1			T2	1		T24	1		T53	1
auto[1342177280:1476395007]	auto[0]	40	1			T24	1		T53	1		T215	1
auto[1342177280:1476395007]	auto[1]	62	1			T199	1		T141	1		T48	1
auto[1476395008:1610612735]	auto[0]	55	1			T12	1		T24	2		T36	1
auto[1476395008:1610612735]	auto[1]	60	1			T24	1		T36	1		T45	1
auto[1610612736:1744830463]	auto[0]	52	1			T46	1		T196	1		T112	1
auto[1610612736:1744830463]	auto[1]	60	1			T106	1		T38	1		T299	1
auto[1744830464:1879048191]	auto[0]	43	1			T2	1		T40	1		T204	1
auto[1744830464:1879048191]	auto[1]	37	1			T12	1		T54	1		T196	1
auto[1879048192:2013265919]	auto[0]	46	1			T24	1		T45	1		T40	2
auto[1879048192:2013265919]	auto[1]	45	1			T91	2		T60	1		T65	1
auto[2013265920:2147483647]	auto[0]	50	1			T215	1		T202	1		T141	1
auto[2013265920:2147483647]	auto[1]	55	1			T14	1		T60	1		T65	1
auto[2147483648:2281701375]	auto[0]	49	1			T3	1		T200	2		T141	1
auto[2147483648:2281701375]	auto[1]	58	1			T24	1		T202	2		T114	1
auto[2281701376:2415919103]	auto[0]	63	1			T199	1		T202	1		T117	1
auto[2281701376:2415919103]	auto[1]	54	1			T24	2		T135	1		T202	1
auto[2415919104:2550136831]	auto[0]	57	1			T47	1		T117	1		T50	1
auto[2415919104:2550136831]	auto[1]	52	1			T24	1		T140	1		T213	1
auto[2550136832:2684354559]	auto[0]	43	1			T36	1		T200	1		T117	1
auto[2550136832:2684354559]	auto[1]	55	1			T200	1		T65	1		T97	1
auto[2684354560:2818572287]	auto[0]	49	1			T24	1		T4	1		T48	1
auto[2684354560:2818572287]	auto[1]	52	1			T215	1		T204	1		T211	1
auto[2818572288:2952790015]	auto[0]	60	1			T24	1		T40	1		T117	1
auto[2818572288:2952790015]	auto[1]	56	1			T137	2		T59	1		T196	1
auto[2952790016:3087007743]	auto[0]	46	1			T2	1		T63	1		T60	1
auto[2952790016:3087007743]	auto[1]	57	1			T137	1		T140	1		T106	1
auto[3087007744:3221225471]	auto[0]	49	1			T2	1		T46	2		T202	1
auto[3087007744:3221225471]	auto[1]	48	1			T14	1		T62	1		T50	1
auto[3221225472:3355443199]	auto[0]	51	1			T16	1		T24	1		T46	1
auto[3221225472:3355443199]	auto[1]	58	1			T205	1		T54	1		T4	1
auto[3355443200:3489660927]	auto[0]	51	1			T45	1		T112	2		T48	1
auto[3355443200:3489660927]	auto[1]	66	1			T12	1		T16	1		T138	1
auto[3489660928:3623878655]	auto[0]	58	1			T200	1		T48	1		T63	1
auto[3489660928:3623878655]	auto[1]	55	1			T3	1		T63	1		T145	1
auto[3623878656:3758096383]	auto[0]	49	1			T40	1		T193	1		T62	1
auto[3623878656:3758096383]	auto[1]	45	1			T45	1		T284	1		T51	1
auto[3758096384:3892314111]	auto[0]	51	1			T40	1		T211	1		T48	1
auto[3758096384:3892314111]	auto[1]	59	1			T62	1		T99	1		T65	1
auto[3892314112:4026531839]	auto[0]	58	1			T53	1		T135	1		T193	1
auto[3892314112:4026531839]	auto[1]	71	1			T36	1		T135	1		T141	1
auto[4026531840:4160749567]	auto[0]	43	1			T112	1		T50	1		T48	3
auto[4026531840:4160749567]	auto[1]	53	1			T3	1		T14	1		T193	1
auto[4160749568:4294967295]	auto[0]	61	1			T12	1		T16	1		T24	1
auto[4160749568:4294967295]	auto[1]	44	1			T2	1		T135	1		T48	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1636

1

T2

4

T3

2

T12

2

auto[1]

1787

1

T2

1

T3

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T12	1		T36	1		T53	1
auto[134217728:268435455]	120	1			T24	1		T45	1		T199	1
auto[268435456:402653183]	119	1			T3	1		T24	2		T215	1
auto[402653184:536870911]	110	1			T2	1		T3	1		T46	1
auto[536870912:671088639]	101	1			T16	1		T54	1		T114	1
auto[671088640:805306367]	87	1			T24	2		T202	1		T48	3
auto[805306368:939524095]	111	1			T12	1		T24	1		T45	1
auto[939524096:1073741823]	101	1			T14	1		T24	1		T199	1
auto[1073741824:1207959551]	103	1			T16	1		T24	1		T140	1
auto[1207959552:1342177279]	105	1			T24	3		T36	2		T40	2
auto[1342177280:1476395007]	118	1			T45	1		T137	1		T193	1
auto[1476395008:1610612735]	124	1			T24	1		T53	1		T140	1
auto[1610612736:1744830463]	85	1			T16	1		T24	1		T50	3
auto[1744830464:1879048191]	113	1			T53	1		T46	1		T215	1
auto[1879048192:2013265919]	107	1			T36	1		T40	1		T211	1
auto[2013265920:2147483647]	115	1			T2	1		T45	1		T137	1
auto[2147483648:2281701375]	109	1			T14	1		T24	2		T46	1
auto[2281701376:2415919103]	101	1			T2	1		T16	1		T24	2
auto[2415919104:2550136831]	110	1			T12	1		T199	1		T4	1
auto[2550136832:2684354559]	122	1			T3	1		T24	2		T137	1
auto[2684354560:2818572287]	94	1			T45	1		T204	1		T211	1
auto[2818572288:2952790015]	102	1			T3	1		T24	1		T205	1
auto[2952790016:3087007743]	107	1			T12	1		T135	1		T40	1
auto[3087007744:3221225471]	107	1			T2	1		T14	1		T36	1
auto[3221225472:3355443199]	115	1			T16	1		T24	1		T40	1
auto[3355443200:3489660927]	110	1			T24	1		T36	1		T40	1
auto[3489660928:3623878655]	86	1			T53	1		T46	1		T138	2
auto[3623878656:3758096383]	115	1			T2	1		T16	1		T24	1
auto[3758096384:3892314111]	104	1			T14	1		T16	1		T46	1
auto[3892314112:4026531839]	94	1			T62	1		T50	2		T48	1
auto[4026531840:4160749567]	125	1			T45	1		T202	1		T204	1
auto[4160749568:4294967295]	105	1			T153	1		T50	1		T48	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T53	1		T48	1		T63	1
auto[0:134217727]	auto[1]	55	1			T12	1		T36	1		T196	1
auto[134217728:268435455]	auto[0]	66	1			T24	1		T199	1		T200	1
auto[134217728:268435455]	auto[1]	54	1			T45	1		T284	1		T48	1
auto[268435456:402653183]	auto[0]	67	1			T3	1		T24	1		T215	1
auto[268435456:402653183]	auto[1]	52	1			T24	1		T25	1		T113	1
auto[402653184:536870911]	auto[0]	58	1			T2	1		T46	1		T25	1
auto[402653184:536870911]	auto[1]	52	1			T3	1		T65	2		T130	1
auto[536870912:671088639]	auto[0]	48	1			T54	1		T153	1		T50	1
auto[536870912:671088639]	auto[1]	53	1			T16	1		T114	1		T38	1
auto[671088640:805306367]	auto[0]	46	1			T24	1		T202	1		T48	1
auto[671088640:805306367]	auto[1]	41	1			T24	1		T48	2		T65	1
auto[805306368:939524095]	auto[0]	55	1			T12	1		T45	1		T135	1
auto[805306368:939524095]	auto[1]	56	1			T24	1		T137	1		T106	1
auto[939524096:1073741823]	auto[0]	40	1			T199	1		T200	1		T106	1
auto[939524096:1073741823]	auto[1]	61	1			T14	1		T24	1		T48	2
auto[1073741824:1207959551]	auto[0]	43	1			T16	1		T24	1		T47	1
auto[1073741824:1207959551]	auto[1]	60	1			T140	1		T114	1		T50	1
auto[1207959552:1342177279]	auto[0]	55	1			T24	1		T36	2		T40	1
auto[1207959552:1342177279]	auto[1]	50	1			T24	2		T40	1		T153	1
auto[1342177280:1476395007]	auto[0]	69	1			T45	1		T141	1		T112	1
auto[1342177280:1476395007]	auto[1]	49	1			T137	1		T193	1		T48	1
auto[1476395008:1610612735]	auto[0]	57	1			T140	1		T202	1		T50	1
auto[1476395008:1610612735]	auto[1]	67	1			T24	1		T53	1		T204	1
auto[1610612736:1744830463]	auto[0]	49	1			T16	1		T24	1		T50	2
auto[1610612736:1744830463]	auto[1]	36	1			T50	1		T52	1		T60	1
auto[1744830464:1879048191]	auto[0]	58	1			T46	1		T47	1		T51	1
auto[1744830464:1879048191]	auto[1]	55	1			T53	1		T215	1		T91	1
auto[1879048192:2013265919]	auto[0]	46	1			T36	1		T40	1		T117	1
auto[1879048192:2013265919]	auto[1]	61	1			T211	1		T193	1		T62	1
auto[2013265920:2147483647]	auto[0]	55	1			T2	1		T117	1		T112	1
auto[2013265920:2147483647]	auto[1]	60	1			T45	1		T137	1		T54	1
auto[2147483648:2281701375]	auto[0]	51	1			T24	1		T46	1		T200	1
auto[2147483648:2281701375]	auto[1]	58	1			T14	1		T24	1		T140	1
auto[2281701376:2415919103]	auto[0]	48	1			T2	1		T46	1		T193	1
auto[2281701376:2415919103]	auto[1]	53	1			T16	1		T24	2		T114	1
auto[2415919104:2550136831]	auto[0]	53	1			T4	1		T141	1		T50	1
auto[2415919104:2550136831]	auto[1]	57	1			T12	1		T199	1		T222	1
auto[2550136832:2684354559]	auto[0]	59	1			T3	1		T24	1		T215	2
auto[2550136832:2684354559]	auto[1]	63	1			T24	1		T137	1		T215	1
auto[2684354560:2818572287]	auto[0]	44	1			T45	1		T204	1		T153	1
auto[2684354560:2818572287]	auto[1]	50	1			T211	1		T113	1		T141	1
auto[2818572288:2952790015]	auto[0]	47	1			T205	1		T48	2		T63	2
auto[2818572288:2952790015]	auto[1]	55	1			T3	1		T24	1		T106	1
auto[2952790016:3087007743]	auto[0]	46	1			T12	1		T40	1		T54	1
auto[2952790016:3087007743]	auto[1]	61	1			T135	1		T204	1		T114	1
auto[3087007744:3221225471]	auto[0]	50	1			T46	1		T40	1		T52	1
auto[3087007744:3221225471]	auto[1]	57	1			T2	1		T14	1		T36	1
auto[3221225472:3355443199]	auto[0]	53	1			T16	1		T24	1		T40	1
auto[3221225472:3355443199]	auto[1]	62	1			T117	1		T50	1		T63	1
auto[3355443200:3489660927]	auto[0]	56	1			T24	1		T40	1		T200	1
auto[3355443200:3489660927]	auto[1]	54	1			T36	1		T4	1		T51	1
auto[3489660928:3623878655]	auto[0]	38	1			T53	1		T46	1		T40	1
auto[3489660928:3623878655]	auto[1]	48	1			T138	2		T202	1		T114	1
auto[3623878656:3758096383]	auto[0]	56	1			T2	1		T16	1		T24	1
auto[3623878656:3758096383]	auto[1]	59	1			T141	1		T48	1		T61	1
auto[3758096384:3892314111]	auto[0]	47	1			T16	1		T50	1		T51	1
auto[3758096384:3892314111]	auto[1]	57	1			T14	1		T46	1		T135	1
auto[3892314112:4026531839]	auto[0]	47	1			T62	1		T50	2		T48	1
auto[3892314112:4026531839]	auto[1]	47	1			T371	1		T69	1		T374	1
auto[4026531840:4160749567]	auto[0]	42	1			T204	1		T47	1		T48	1
auto[4026531840:4160749567]	auto[1]	83	1			T45	1		T202	1		T205	1
auto[4160749568:4294967295]	auto[0]	44	1			T48	2		T61	1		T107	1
auto[4160749568:4294967295]	auto[1]	61	1			T153	1		T50	1		T61	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1629

1

T2

4

T3

2

T12

2

auto[1]

1794

1

T2

1

T3

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	123	1			T16	1		T24	1		T47	1
auto[134217728:268435455]	97	1			T14	1		T46	1		T40	1
auto[268435456:402653183]	111	1			T24	2		T45	1		T114	1
auto[402653184:536870911]	99	1			T2	1		T12	2		T14	1
auto[536870912:671088639]	96	1			T199	1		T106	1		T62	1
auto[671088640:805306367]	113	1			T3	1		T24	2		T36	1
auto[805306368:939524095]	93	1			T3	1		T12	1		T138	1
auto[939524096:1073741823]	92	1			T16	1		T199	1		T113	1
auto[1073741824:1207959551]	111	1			T24	3		T36	1		T202	2
auto[1207959552:1342177279]	96	1			T24	1		T40	1		T199	1
auto[1342177280:1476395007]	114	1			T2	1		T14	1		T24	1
auto[1476395008:1610612735]	126	1			T16	2		T24	1		T36	1
auto[1610612736:1744830463]	106	1			T24	1		T137	1		T215	2
auto[1744830464:1879048191]	96	1			T24	1		T45	1		T50	2
auto[1879048192:2013265919]	110	1			T24	1		T196	1		T141	1
auto[2013265920:2147483647]	111	1			T12	1		T24	1		T36	1
auto[2147483648:2281701375]	100	1			T45	1		T53	1		T40	1
auto[2281701376:2415919103]	102	1			T45	1		T135	1		T202	1
auto[2415919104:2550136831]	105	1			T24	1		T46	1		T54	1
auto[2550136832:2684354559]	110	1			T2	1		T24	1		T135	1
auto[2684354560:2818572287]	113	1			T24	2		T46	1		T215	1
auto[2818572288:2952790015]	117	1			T3	1		T24	2		T45	1
auto[2952790016:3087007743]	96	1			T53	1		T40	1		T204	1
auto[3087007744:3221225471]	113	1			T16	2		T36	1		T53	2
auto[3221225472:3355443199]	100	1			T2	1		T3	1		T46	1
auto[3355443200:3489660927]	108	1			T138	1		T211	1		T50	1
auto[3489660928:3623878655]	127	1			T16	1		T24	1		T140	1
auto[3623878656:3758096383]	119	1			T2	1		T24	1		T200	1
auto[3758096384:3892314111]	108	1			T138	1		T117	1		T50	1
auto[3892314112:4026531839]	109	1			T205	1		T193	1		T103	1
auto[4026531840:4160749567]	109	1			T14	1		T137	1		T50	1
auto[4160749568:4294967295]	93	1			T46	2		T62	1		T117	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	65	1			T16	1		T24	1		T47	1
auto[0:134217727]	auto[1]	58	1			T50	1		T48	1		T61	1
auto[134217728:268435455]	auto[0]	41	1			T46	1		T112	1		T48	1
auto[134217728:268435455]	auto[1]	56	1			T14	1		T40	1		T215	1
auto[268435456:402653183]	auto[0]	55	1			T24	1		T45	1		T50	1
auto[268435456:402653183]	auto[1]	56	1			T24	1		T114	1		T4	1
auto[402653184:536870911]	auto[0]	44	1			T2	1		T12	1		T4	1
auto[402653184:536870911]	auto[1]	55	1			T12	1		T14	1		T36	1
auto[536870912:671088639]	auto[0]	43	1			T52	1		T61	1		T94	1
auto[536870912:671088639]	auto[1]	53	1			T199	1		T106	1		T62	1
auto[671088640:805306367]	auto[0]	48	1			T24	2		T40	1		T61	1
auto[671088640:805306367]	auto[1]	65	1			T3	1		T36	1		T205	1
auto[805306368:939524095]	auto[0]	46	1			T12	1		T204	1		T18	1
auto[805306368:939524095]	auto[1]	47	1			T3	1		T138	1		T200	1
auto[939524096:1073741823]	auto[0]	39	1			T16	1		T51	1		T48	1
auto[939524096:1073741823]	auto[1]	53	1			T199	1		T113	1		T48	2
auto[1073741824:1207959551]	auto[0]	47	1			T24	3		T202	2		T4	1
auto[1073741824:1207959551]	auto[1]	64	1			T36	1		T54	1		T106	1
auto[1207959552:1342177279]	auto[0]	43	1			T40	1		T199	1		T215	1
auto[1207959552:1342177279]	auto[1]	53	1			T24	1		T114	1		T48	1
auto[1342177280:1476395007]	auto[0]	56	1			T40	1		T141	1		T48	3
auto[1342177280:1476395007]	auto[1]	58	1			T2	1		T14	1		T24	1
auto[1476395008:1610612735]	auto[0]	63	1			T16	1		T36	1		T40	1
auto[1476395008:1610612735]	auto[1]	63	1			T16	1		T24	1		T140	1
auto[1610612736:1744830463]	auto[0]	51	1			T24	1		T215	2		T48	2
auto[1610612736:1744830463]	auto[1]	55	1			T137	1		T47	1		T62	1
auto[1744830464:1879048191]	auto[0]	45	1			T48	1		T63	2		T60	1
auto[1744830464:1879048191]	auto[1]	51	1			T24	1		T45	1		T50	2
auto[1879048192:2013265919]	auto[0]	51	1			T48	2		T130	1		T409	1
auto[1879048192:2013265919]	auto[1]	59	1			T24	1		T196	1		T141	1
auto[2013265920:2147483647]	auto[0]	59	1			T24	1		T36	1		T50	1
auto[2013265920:2147483647]	auto[1]	52	1			T12	1		T48	2		T63	2
auto[2147483648:2281701375]	auto[0]	44	1			T45	1		T40	1		T47	1
auto[2147483648:2281701375]	auto[1]	56	1			T53	1		T114	1		T193	1
auto[2281701376:2415919103]	auto[0]	42	1			T45	1		T135	1		T25	1
auto[2281701376:2415919103]	auto[1]	60	1			T202	1		T193	1		T48	2
auto[2415919104:2550136831]	auto[0]	55	1			T46	1		T117	1		T51	1
auto[2415919104:2550136831]	auto[1]	50	1			T24	1		T54	1		T153	1
auto[2550136832:2684354559]	auto[0]	50	1			T2	1		T202	1		T204	1
auto[2550136832:2684354559]	auto[1]	60	1			T24	1		T135	1		T137	1
auto[2684354560:2818572287]	auto[0]	65	1			T24	1		T46	1		T106	1
auto[2684354560:2818572287]	auto[1]	48	1			T24	1		T215	1		T196	1
auto[2818572288:2952790015]	auto[0]	56	1			T3	1		T24	1		T46	1
auto[2818572288:2952790015]	auto[1]	61	1			T24	1		T45	1		T48	1
auto[2952790016:3087007743]	auto[0]	46	1			T53	1		T40	1		T54	1
auto[2952790016:3087007743]	auto[1]	50	1			T204	1		T114	1		T25	1
auto[3087007744:3221225471]	auto[0]	55	1			T16	2		T53	1		T40	1
auto[3087007744:3221225471]	auto[1]	58	1			T36	1		T53	1		T205	1
auto[3221225472:3355443199]	auto[0]	51	1			T2	1		T3	1		T46	1
auto[3221225472:3355443199]	auto[1]	49	1			T135	1		T140	1		T202	1
auto[3355443200:3489660927]	auto[0]	53	1			T138	1		T50	1		T48	2
auto[3355443200:3489660927]	auto[1]	55	1			T211	1		T48	1		T61	1
auto[3489660928:3623878655]	auto[0]	54	1			T16	1		T140	1		T52	1
auto[3489660928:3623878655]	auto[1]	73	1			T24	1		T211	1		T52	1
auto[3623878656:3758096383]	auto[0]	52	1			T2	1		T24	1		T200	1
auto[3623878656:3758096383]	auto[1]	67	1			T59	1		T48	2		T61	1
auto[3758096384:3892314111]	auto[0]	52	1			T138	1		T117	1		T48	3
auto[3758096384:3892314111]	auto[1]	56	1			T50	1		T48	2		T61	1
auto[3892314112:4026531839]	auto[0]	57	1			T205	1		T48	1		T61	1
auto[3892314112:4026531839]	auto[1]	52	1			T193	1		T103	1		T50	2
auto[4026531840:4160749567]	auto[0]	53	1			T50	1		T51	1		T48	1
auto[4026531840:4160749567]	auto[1]	56	1			T14	1		T137	1		T213	1
auto[4160749568:4294967295]	auto[0]	48	1			T46	2		T117	1		T50	1
auto[4160749568:4294967295]	auto[1]	45	1			T62	1		T117	1		T389	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T2

3

T3

2

T12

2

auto[1]

1816

1

T2

2

T3

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T24	1		T40	1		T200	1
auto[134217728:268435455]	110	1			T2	1		T24	1		T36	2
auto[268435456:402653183]	109	1			T24	1		T204	1		T205	1
auto[402653184:536870911]	114	1			T3	1		T103	1		T47	1
auto[536870912:671088639]	104	1			T24	1		T138	1		T202	1
auto[671088640:805306367]	102	1			T12	1		T199	1		T202	1
auto[805306368:939524095]	102	1			T16	1		T54	1		T59	1
auto[939524096:1073741823]	110	1			T12	1		T24	1		T45	1
auto[1073741824:1207959551]	100	1			T24	2		T40	1		T47	1
auto[1207959552:1342177279]	111	1			T12	1		T140	1		T114	1
auto[1342177280:1476395007]	105	1			T24	1		T53	1		T135	1
auto[1476395008:1610612735]	106	1			T3	1		T140	1		T202	1
auto[1610612736:1744830463]	111	1			T14	1		T36	1		T45	1
auto[1744830464:1879048191]	110	1			T24	3		T135	1		T215	1
auto[1879048192:2013265919]	114	1			T2	1		T24	1		T202	1
auto[2013265920:2147483647]	117	1			T16	1		T24	1		T36	1
auto[2147483648:2281701375]	97	1			T3	1		T16	1		T215	1
auto[2281701376:2415919103]	97	1			T3	1		T40	2		T25	1
auto[2415919104:2550136831]	106	1			T14	1		T46	1		T205	1
auto[2550136832:2684354559]	112	1			T24	3		T153	1		T117	1
auto[2684354560:2818572287]	116	1			T40	1		T199	1		T204	1
auto[2818572288:2952790015]	104	1			T2	1		T14	1		T24	1
auto[2952790016:3087007743]	101	1			T53	1		T200	1		T48	1
auto[3087007744:3221225471]	107	1			T2	1		T14	1		T46	1
auto[3221225472:3355443199]	97	1			T2	1		T40	1		T113	1
auto[3355443200:3489660927]	105	1			T16	1		T24	1		T46	1
auto[3489660928:3623878655]	103	1			T24	2		T45	1		T53	1
auto[3623878656:3758096383]	93	1			T16	1		T36	1		T45	1
auto[3758096384:3892314111]	109	1			T12	1		T24	3		T202	1
auto[3892314112:4026531839]	125	1			T53	1		T46	1		T54	1
auto[4026531840:4160749567]	114	1			T16	1		T199	1		T18	1
auto[4160749568:4294967295]	104	1			T16	1		T36	1		T45	1