dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4490 1 T2 6 T3 6 T12 8
auto[1] 2358 1 T2 4 T3 2 T14 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 210 1 T53 2 T117 2 T48 4
auto[134217728:268435455] 212 1 T16 2 T53 2 T200 2
auto[268435456:402653183] 206 1 T24 2 T138 2 T153 2
auto[402653184:536870911] 240 1 T24 2 T36 2 T135 2
auto[536870912:671088639] 208 1 T2 2 T24 4 T135 2
auto[671088640:805306367] 238 1 T135 2 T137 2 T205 2
auto[805306368:939524095] 216 1 T2 2 T16 2 T46 2
auto[939524096:1073741823] 204 1 T14 2 T24 2 T40 2
auto[1073741824:1207959551] 226 1 T45 2 T204 2 T106 2
auto[1207959552:1342177279] 210 1 T46 2 T215 2 T141 2
auto[1342177280:1476395007] 240 1 T3 2 T16 2 T45 2
auto[1476395008:1610612735] 202 1 T2 2 T137 2 T51 2
auto[1610612736:1744830463] 212 1 T3 2 T53 2 T202 2
auto[1744830464:1879048191] 204 1 T14 2 T16 2 T24 2
auto[1879048192:2013265919] 206 1 T3 2 T45 2 T53 2
auto[2013265920:2147483647] 196 1 T2 2 T24 2 T137 2
auto[2147483648:2281701375] 212 1 T204 2 T59 2 T4 2
auto[2281701376:2415919103] 220 1 T12 2 T24 2 T36 2
auto[2415919104:2550136831] 226 1 T12 2 T46 2 T204 2
auto[2550136832:2684354559] 218 1 T2 2 T3 2 T16 2
auto[2684354560:2818572287] 214 1 T24 4 T40 2 T140 2
auto[2818572288:2952790015] 238 1 T16 2 T24 4 T114 2
auto[2952790016:3087007743] 210 1 T46 2 T199 2 T114 2
auto[3087007744:3221225471] 208 1 T14 2 T24 2 T36 2
auto[3221225472:3355443199] 208 1 T16 2 T24 2 T196 2
auto[3355443200:3489660927] 226 1 T24 6 T4 2 T62 2
auto[3489660928:3623878655] 168 1 T36 2 T40 2 T62 2
auto[3623878656:3758096383] 204 1 T24 2 T46 2 T50 4
auto[3758096384:3892314111] 210 1 T12 2 T14 2 T24 4
auto[3892314112:4026531839] 190 1 T36 4 T135 2 T40 2
auto[4026531840:4160749567] 216 1 T24 2 T137 2 T40 4
auto[4160749568:4294967295] 250 1 T12 2 T24 4 T46 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 170 1 T53 2 T117 2 T48 2
auto[0:134217727] auto[1] 40 1 T48 2 T61 2 T65 2
auto[134217728:268435455] auto[0] 156 1 T16 2 T53 2 T193 2
auto[134217728:268435455] auto[1] 56 1 T200 2 T25 2 T263 2
auto[268435456:402653183] auto[0] 132 1 T24 2 T138 2 T153 2
auto[268435456:402653183] auto[1] 74 1 T112 2 T389 2 T69 2
auto[402653184:536870911] auto[0] 168 1 T24 2 T135 2 T200 2
auto[402653184:536870911] auto[1] 72 1 T36 2 T48 2 T63 2
auto[536870912:671088639] auto[0] 138 1 T2 2 T24 2 T200 2
auto[536870912:671088639] auto[1] 70 1 T24 2 T135 2 T211 2
auto[671088640:805306367] auto[0] 156 1 T135 2 T137 2 T112 2
auto[671088640:805306367] auto[1] 82 1 T205 2 T61 2 T276 2
auto[805306368:939524095] auto[0] 134 1 T16 2 T138 2 T202 2
auto[805306368:939524095] auto[1] 82 1 T2 2 T46 2 T25 2
auto[939524096:1073741823] auto[0] 130 1 T40 2 T50 2 T63 2
auto[939524096:1073741823] auto[1] 74 1 T14 2 T24 2 T50 2
auto[1073741824:1207959551] auto[0] 144 1 T45 2 T50 2 T48 4
auto[1073741824:1207959551] auto[1] 82 1 T204 2 T106 2 T48 2
auto[1207959552:1342177279] auto[0] 138 1 T141 2 T48 6 T94 2
auto[1207959552:1342177279] auto[1] 72 1 T46 2 T215 2 T153 2
auto[1342177280:1476395007] auto[0] 156 1 T3 2 T16 2 T114 2
auto[1342177280:1476395007] auto[1] 84 1 T45 2 T140 2 T215 2
auto[1476395008:1610612735] auto[0] 130 1 T51 2 T48 4 T63 2
auto[1476395008:1610612735] auto[1] 72 1 T2 2 T137 2 T48 2
auto[1610612736:1744830463] auto[0] 146 1 T3 2 T53 2 T202 2
auto[1610612736:1744830463] auto[1] 66 1 T205 2 T54 2 T65 2
auto[1744830464:1879048191] auto[0] 138 1 T16 2 T24 2 T45 2
auto[1744830464:1879048191] auto[1] 66 1 T14 2 T54 2 T196 2
auto[1879048192:2013265919] auto[0] 144 1 T45 2 T138 2 T193 2
auto[1879048192:2013265919] auto[1] 62 1 T3 2 T53 2 T54 2
auto[2013265920:2147483647] auto[0] 138 1 T2 2 T137 2 T200 2
auto[2013265920:2147483647] auto[1] 58 1 T24 2 T204 2 T65 2
auto[2147483648:2281701375] auto[0] 150 1 T4 2 T48 8 T63 2
auto[2147483648:2281701375] auto[1] 62 1 T204 2 T59 2 T106 2
auto[2281701376:2415919103] auto[0] 132 1 T12 2 T46 2 T40 2
auto[2281701376:2415919103] auto[1] 88 1 T24 2 T36 2 T215 2
auto[2415919104:2550136831] auto[0] 132 1 T12 2 T200 2 T153 2
auto[2415919104:2550136831] auto[1] 94 1 T46 2 T204 2 T417 2
auto[2550136832:2684354559] auto[0] 134 1 T2 2 T3 2 T16 2
auto[2550136832:2684354559] auto[1] 84 1 T205 2 T25 2 T141 2
auto[2684354560:2818572287] auto[0] 130 1 T24 2 T199 2 T47 2
auto[2684354560:2818572287] auto[1] 84 1 T24 2 T40 2 T140 2
auto[2818572288:2952790015] auto[0] 152 1 T16 2 T24 4 T48 4
auto[2818572288:2952790015] auto[1] 86 1 T114 2 T61 2 T60 4
auto[2952790016:3087007743] auto[0] 134 1 T46 2 T114 2 T61 4
auto[2952790016:3087007743] auto[1] 76 1 T199 2 T91 2 T48 2
auto[3087007744:3221225471] auto[0] 126 1 T14 2 T40 2 T193 2
auto[3087007744:3221225471] auto[1] 82 1 T24 2 T36 2 T193 2
auto[3221225472:3355443199] auto[0] 130 1 T16 2 T52 2 T61 2
auto[3221225472:3355443199] auto[1] 78 1 T24 2 T196 2 T48 6
auto[3355443200:3489660927] auto[0] 142 1 T24 4 T4 2 T50 2
auto[3355443200:3489660927] auto[1] 84 1 T24 2 T62 2 T48 2
auto[3489660928:3623878655] auto[0] 98 1 T36 2 T40 2 T61 6
auto[3489660928:3623878655] auto[1] 70 1 T62 2 T258 2 T218 2
auto[3623878656:3758096383] auto[0] 140 1 T24 2 T50 2 T51 2
auto[3623878656:3758096383] auto[1] 64 1 T46 2 T50 2 T65 2
auto[3758096384:3892314111] auto[0] 136 1 T12 2 T24 4 T45 2
auto[3758096384:3892314111] auto[1] 74 1 T14 2 T45 2 T140 2
auto[3892314112:4026531839] auto[0] 120 1 T36 4 T135 2 T40 2
auto[3892314112:4026531839] auto[1] 70 1 T59 2 T103 2 T117 2
auto[4026531840:4160749567] auto[0] 152 1 T24 2 T137 2 T40 2
auto[4026531840:4160749567] auto[1] 64 1 T40 2 T114 2 T106 2
auto[4160749568:4294967295] auto[0] 164 1 T12 2 T24 4 T202 2
auto[4160749568:4294967295] auto[1] 86 1 T46 2 T215 2 T114 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%