Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3039

1

T2

5

T3

4

T12

4

auto[1]

278

1

T14

3

T135

3

T138

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T114	1		T211	1		T112	1
auto[134217728:268435455]	109	1			T2	1		T12	1		T24	2
auto[268435456:402653183]	121	1			T24	1		T36	1		T40	1
auto[402653184:536870911]	131	1			T2	1		T135	1		T137	1
auto[536870912:671088639]	87	1			T24	1		T45	1		T46	1
auto[671088640:805306367]	108	1			T200	1		T196	1		T25	1
auto[805306368:939524095]	112	1			T3	1		T12	1		T24	1
auto[939524096:1073741823]	108	1			T12	1		T16	1		T24	1
auto[1073741824:1207959551]	95	1			T24	1		T36	1		T46	1
auto[1207959552:1342177279]	103	1			T138	1		T112	1		T51	1
auto[1342177280:1476395007]	103	1			T24	1		T199	1		T59	1
auto[1476395008:1610612735]	89	1			T14	1		T45	1		T40	1
auto[1610612736:1744830463]	91	1			T16	1		T24	1		T137	1
auto[1744830464:1879048191]	100	1			T16	1		T215	1		T202	2
auto[1879048192:2013265919]	117	1			T36	1		T135	1		T40	1
auto[2013265920:2147483647]	108	1			T12	1		T14	1		T24	2
auto[2147483648:2281701375]	102	1			T14	1		T24	1		T141	1
auto[2281701376:2415919103]	115	1			T3	1		T16	1		T135	1
auto[2415919104:2550136831]	103	1			T2	1		T14	1		T135	1
auto[2550136832:2684354559]	85	1			T24	1		T54	1		T61	1
auto[2684354560:2818572287]	108	1			T36	1		T45	1		T40	1
auto[2818572288:2952790015]	103	1			T24	1		T135	1		T138	1
auto[2952790016:3087007743]	94	1			T3	1		T24	3		T40	1
auto[3087007744:3221225471]	91	1			T53	1		T202	1		T200	1
auto[3221225472:3355443199]	96	1			T138	1		T202	1		T61	1
auto[3355443200:3489660927]	110	1			T16	1		T24	1		T36	1
auto[3489660928:3623878655]	114	1			T3	1		T24	1		T140	1
auto[3623878656:3758096383]	111	1			T2	1		T14	1		T16	1
auto[3758096384:3892314111]	101	1			T24	1		T138	2		T50	1
auto[3892314112:4026531839]	114	1			T14	1		T135	1		T141	2
auto[4026531840:4160749567]	99	1			T2	1		T36	1		T40	2
auto[4160749568:4294967295]	86	1			T14	1		T16	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T114	1		T211	1		T112	1
auto[0:134217727]	auto[1]	8	1			T258	1		T267	1		T347	1
auto[134217728:268435455]	auto[0]	99	1			T2	1		T12	1		T24	2
auto[134217728:268435455]	auto[1]	10	1			T153	1		T142	1		T254	1
auto[268435456:402653183]	auto[0]	113	1			T24	1		T36	1		T40	1
auto[268435456:402653183]	auto[1]	8	1			T381	1		T386	1		T387	1
auto[402653184:536870911]	auto[0]	126	1			T2	1		T135	1		T137	1
auto[402653184:536870911]	auto[1]	5	1			T299	1		T403	2		T420	1
auto[536870912:671088639]	auto[0]	76	1			T24	1		T45	1		T46	1
auto[536870912:671088639]	auto[1]	11	1			T135	1		T138	1		T381	1
auto[671088640:805306367]	auto[0]	102	1			T200	1		T196	1		T25	1
auto[671088640:805306367]	auto[1]	6	1			T153	1		T142	1		T144	1
auto[805306368:939524095]	auto[0]	108	1			T3	1		T12	1		T24	1
auto[805306368:939524095]	auto[1]	4	1			T141	1		T258	1		T306	1
auto[939524096:1073741823]	auto[0]	97	1			T12	1		T16	1		T24	1
auto[939524096:1073741823]	auto[1]	11	1			T140	2		T153	1		T379	1
auto[1073741824:1207959551]	auto[0]	88	1			T24	1		T36	1		T46	1
auto[1073741824:1207959551]	auto[1]	7	1			T299	1		T311	1		T414	1
auto[1207959552:1342177279]	auto[0]	94	1			T112	1		T51	1		T48	2
auto[1207959552:1342177279]	auto[1]	9	1			T138	1		T254	1		T299	1
auto[1342177280:1476395007]	auto[0]	94	1			T24	1		T199	1		T59	1
auto[1342177280:1476395007]	auto[1]	9	1			T258	2		T299	1		T381	1
auto[1476395008:1610612735]	auto[0]	77	1			T45	1		T40	1		T205	1
auto[1476395008:1610612735]	auto[1]	12	1			T14	1		T141	1		T153	1
auto[1610612736:1744830463]	auto[0]	85	1			T16	1		T24	1		T137	1
auto[1610612736:1744830463]	auto[1]	6	1			T267	1		T403	1		T306	1
auto[1744830464:1879048191]	auto[0]	91	1			T16	1		T215	1		T202	2
auto[1744830464:1879048191]	auto[1]	9	1			T258	1		T379	1		T267	1
auto[1879048192:2013265919]	auto[0]	110	1			T36	1		T135	1		T40	1
auto[1879048192:2013265919]	auto[1]	7	1			T153	1		T254	1		T379	1
auto[2013265920:2147483647]	auto[0]	99	1			T12	1		T14	1		T24	2
auto[2013265920:2147483647]	auto[1]	9	1			T138	1		T254	1		T267	1
auto[2147483648:2281701375]	auto[0]	91	1			T14	1		T24	1		T50	1
auto[2147483648:2281701375]	auto[1]	11	1			T141	1		T153	1		T403	1
auto[2281701376:2415919103]	auto[0]	102	1			T3	1		T16	1		T138	1
auto[2281701376:2415919103]	auto[1]	13	1			T135	1		T138	1		T141	1
auto[2415919104:2550136831]	auto[0]	92	1			T2	1		T135	1		T140	1
auto[2415919104:2550136831]	auto[1]	11	1			T14	1		T258	1		T381	1
auto[2550136832:2684354559]	auto[0]	81	1			T24	1		T54	1		T61	1
auto[2550136832:2684354559]	auto[1]	4	1			T347	1		T403	1		T405	1
auto[2684354560:2818572287]	auto[0]	99	1			T36	1		T45	1		T40	1
auto[2684354560:2818572287]	auto[1]	9	1			T141	1		T144	2		T258	1
auto[2818572288:2952790015]	auto[0]	91	1			T24	1		T138	1		T48	1
auto[2818572288:2952790015]	auto[1]	12	1			T135	1		T254	1		T299	1
auto[2952790016:3087007743]	auto[0]	90	1			T3	1		T24	3		T40	1
auto[2952790016:3087007743]	auto[1]	4	1			T141	1		T299	1		T386	1
auto[3087007744:3221225471]	auto[0]	84	1			T53	1		T202	1		T200	1
auto[3087007744:3221225471]	auto[1]	7	1			T141	1		T153	1		T142	1
auto[3221225472:3355443199]	auto[0]	85	1			T202	1		T61	1		T63	1
auto[3221225472:3355443199]	auto[1]	11	1			T138	1		T380	1		T254	2
auto[3355443200:3489660927]	auto[0]	98	1			T16	1		T24	1		T36	1
auto[3355443200:3489660927]	auto[1]	12	1			T142	1		T145	1		T381	1
auto[3489660928:3623878655]	auto[0]	105	1			T3	1		T24	1		T113	1
auto[3489660928:3623878655]	auto[1]	9	1			T140	1		T141	1		T381	1
auto[3623878656:3758096383]	auto[0]	105	1			T2	1		T14	1		T16	1
auto[3623878656:3758096383]	auto[1]	6	1			T254	1		T258	1		T408	1
auto[3758096384:3892314111]	auto[0]	91	1			T24	1		T50	1		T48	2
auto[3758096384:3892314111]	auto[1]	10	1			T138	2		T254	1		T258	1
auto[3892314112:4026531839]	auto[0]	98	1			T135	1		T141	1		T153	1
auto[3892314112:4026531839]	auto[1]	16	1			T14	1		T141	1		T153	1
auto[4026531840:4160749567]	auto[0]	90	1			T2	1		T36	1		T40	2
auto[4026531840:4160749567]	auto[1]	9	1			T258	1		T381	1		T331	1
auto[4160749568:4294967295]	auto[0]	83	1			T14	1		T16	1		T24	1
auto[4160749568:4294967295]	auto[1]	3	1			T403	2		T405	1		-	-