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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1602 1 T2 3 T3 2 T12 2
auto[1] 1821 1 T2 2 T3 2 T12 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 115 1 T24 4 T36 1 T45 1
auto[134217728:268435455] 107 1 T24 1 T45 1 T137 1
auto[268435456:402653183] 109 1 T24 1 T45 1 T137 2
auto[402653184:536870911] 115 1 T16 1 T46 1 T215 1
auto[536870912:671088639] 125 1 T3 1 T16 2 T205 1
auto[671088640:805306367] 119 1 T2 1 T12 1 T24 1
auto[805306368:939524095] 120 1 T14 1 T36 1 T46 1
auto[939524096:1073741823] 107 1 T24 2 T36 1 T53 1
auto[1073741824:1207959551] 112 1 T3 1 T24 2 T53 1
auto[1207959552:1342177279] 108 1 T16 1 T24 1 T40 1
auto[1342177280:1476395007] 107 1 T3 1 T12 1 T14 1
auto[1476395008:1610612735] 119 1 T40 1 T51 1 T48 3
auto[1610612736:1744830463] 100 1 T138 1 T40 1 T215 2
auto[1744830464:1879048191] 99 1 T16 1 T46 1 T40 1
auto[1879048192:2013265919] 94 1 T36 1 T38 1 T51 1
auto[2013265920:2147483647] 115 1 T24 1 T53 1 T202 1
auto[2147483648:2281701375] 108 1 T24 1 T45 1 T202 1
auto[2281701376:2415919103] 105 1 T24 1 T36 1 T45 1
auto[2415919104:2550136831] 94 1 T14 1 T24 1 T202 1
auto[2550136832:2684354559] 105 1 T135 1 T199 2 T215 1
auto[2684354560:2818572287] 97 1 T2 1 T205 1 T153 1
auto[2818572288:2952790015] 98 1 T16 1 T40 1 T200 1
auto[2952790016:3087007743] 102 1 T114 1 T211 1 T47 1
auto[3087007744:3221225471] 113 1 T2 1 T24 1 T36 1
auto[3221225472:3355443199] 117 1 T24 1 T140 1 T114 1
auto[3355443200:3489660927] 100 1 T3 1 T14 1 T138 1
auto[3489660928:3623878655] 96 1 T215 1 T4 1 T52 1
auto[3623878656:3758096383] 92 1 T12 1 T24 1 T53 1
auto[3758096384:3892314111] 92 1 T2 1 T24 1 T46 1
auto[3892314112:4026531839] 126 1 T16 1 T202 2 T52 1
auto[4026531840:4160749567] 93 1 T12 1 T202 1 T204 1
auto[4160749568:4294967295] 114 1 T2 1 T24 2 T46 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 55 1 T24 3 T48 1 T63 1
auto[0:134217727] auto[1] 60 1 T24 1 T36 1 T45 1
auto[134217728:268435455] auto[0] 51 1 T24 1 T45 1 T48 2
auto[134217728:268435455] auto[1] 56 1 T137 1 T140 1 T54 1
auto[268435456:402653183] auto[0] 61 1 T24 1 T196 1 T47 1
auto[268435456:402653183] auto[1] 48 1 T45 1 T137 2 T59 1
auto[402653184:536870911] auto[0] 47 1 T16 1 T46 1 T215 1
auto[402653184:536870911] auto[1] 68 1 T193 1 T91 1 T94 1
auto[536870912:671088639] auto[0] 61 1 T16 1 T200 1 T106 1
auto[536870912:671088639] auto[1] 64 1 T3 1 T16 1 T205 1
auto[671088640:805306367] auto[0] 59 1 T47 1 T62 1 T48 2
auto[671088640:805306367] auto[1] 60 1 T2 1 T12 1 T24 1
auto[805306368:939524095] auto[0] 52 1 T46 1 T50 1 T48 1
auto[805306368:939524095] auto[1] 68 1 T14 1 T36 1 T135 1
auto[939524096:1073741823] auto[0] 54 1 T24 2 T36 1 T53 1
auto[939524096:1073741823] auto[1] 53 1 T135 1 T48 3 T63 1
auto[1073741824:1207959551] auto[0] 56 1 T3 1 T24 1 T53 1
auto[1073741824:1207959551] auto[1] 56 1 T24 1 T135 1 T4 1
auto[1207959552:1342177279] auto[0] 56 1 T16 1 T40 1 T205 1
auto[1207959552:1342177279] auto[1] 52 1 T24 1 T114 1 T193 1
auto[1342177280:1476395007] auto[0] 45 1 T3 1 T12 1 T46 1
auto[1342177280:1476395007] auto[1] 62 1 T14 1 T24 1 T114 1
auto[1476395008:1610612735] auto[0] 57 1 T40 1 T48 2 T61 1
auto[1476395008:1610612735] auto[1] 62 1 T51 1 T48 1 T61 2
auto[1610612736:1744830463] auto[0] 43 1 T215 1 T63 1 T98 1
auto[1610612736:1744830463] auto[1] 57 1 T138 1 T40 1 T215 1
auto[1744830464:1879048191] auto[0] 48 1 T16 1 T46 1 T40 1
auto[1744830464:1879048191] auto[1] 51 1 T54 1 T62 1 T51 1
auto[1879048192:2013265919] auto[0] 46 1 T51 1 T48 2 T63 1
auto[1879048192:2013265919] auto[1] 48 1 T36 1 T38 1 T48 1
auto[2013265920:2147483647] auto[0] 56 1 T53 1 T202 1 T153 1
auto[2013265920:2147483647] auto[1] 59 1 T24 1 T25 1 T50 1
auto[2147483648:2281701375] auto[0] 44 1 T45 1 T25 1 T51 1
auto[2147483648:2281701375] auto[1] 64 1 T24 1 T202 1 T114 1
auto[2281701376:2415919103] auto[0] 47 1 T45 1 T46 1 T200 1
auto[2281701376:2415919103] auto[1] 58 1 T24 1 T36 1 T47 1
auto[2415919104:2550136831] auto[0] 48 1 T24 1 T25 1 T50 1
auto[2415919104:2550136831] auto[1] 46 1 T14 1 T202 1 T196 1
auto[2550136832:2684354559] auto[0] 50 1 T199 1 T48 2 T60 2
auto[2550136832:2684354559] auto[1] 55 1 T135 1 T199 1 T215 1
auto[2684354560:2818572287] auto[0] 49 1 T2 1 T153 1 T50 1
auto[2684354560:2818572287] auto[1] 48 1 T205 1 T222 1 T410 1
auto[2818572288:2952790015] auto[0] 52 1 T16 1 T40 1 T200 1
auto[2818572288:2952790015] auto[1] 46 1 T54 1 T50 1 T52 2
auto[2952790016:3087007743] auto[0] 39 1 T47 1 T112 1 T51 1
auto[2952790016:3087007743] auto[1] 63 1 T114 1 T211 1 T117 1
auto[3087007744:3221225471] auto[0] 55 1 T2 1 T24 1 T36 1
auto[3087007744:3221225471] auto[1] 58 1 T45 1 T50 1 T143 1
auto[3221225472:3355443199] auto[0] 42 1 T48 1 T143 1 T145 1
auto[3221225472:3355443199] auto[1] 75 1 T24 1 T140 1 T114 1
auto[3355443200:3489660927] auto[0] 43 1 T112 1 T48 1 T94 1
auto[3355443200:3489660927] auto[1] 57 1 T3 1 T14 1 T138 1
auto[3489660928:3623878655] auto[0] 51 1 T4 1 T52 1 T61 1
auto[3489660928:3623878655] auto[1] 45 1 T215 1 T48 2 T208 1
auto[3623878656:3758096383] auto[0] 48 1 T12 1 T40 1 T54 1
auto[3623878656:3758096383] auto[1] 44 1 T24 1 T53 1 T141 1
auto[3758096384:3892314111] auto[0] 45 1 T24 1 T46 1 T200 1
auto[3758096384:3892314111] auto[1] 47 1 T2 1 T140 1 T204 1
auto[3892314112:4026531839] auto[0] 51 1 T202 1 T48 1 T263 1
auto[3892314112:4026531839] auto[1] 75 1 T16 1 T202 1 T52 1
auto[4026531840:4160749567] auto[0] 35 1 T202 1 T141 1 T48 2
auto[4026531840:4160749567] auto[1] 58 1 T12 1 T204 1 T48 1
auto[4160749568:4294967295] auto[0] 56 1 T2 1 T24 1 T117 1
auto[4160749568:4294967295] auto[1] 58 1 T24 1 T46 1 T59 1

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