Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7258

1

T2

11

T3

14

T12

7

auto[1]

271

1

T14

2

T135

5

T138

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3054	1			T2	5		T3	7		T12	3
auto[134217728:268435455]	180	1			T12	1		T16	1		T24	4
auto[268435456:402653183]	158	1			T2	1		T14	1		T24	1
auto[402653184:536870911]	155	1			T14	1		T16	1		T24	2
auto[536870912:671088639]	155	1			T138	1		T204	1		T59	1
auto[671088640:805306367]	146	1			T3	1		T24	1		T135	1
auto[805306368:939524095]	145	1			T2	1		T16	1		T24	1
auto[939524096:1073741823]	143	1			T24	1		T53	1		T215	1
auto[1073741824:1207959551]	144	1			T2	1		T36	2		T45	1
auto[1207959552:1342177279]	134	1			T24	1		T137	2		T141	2
auto[1342177280:1476395007]	137	1			T3	1		T16	1		T24	1
auto[1476395008:1610612735]	145	1			T2	1		T24	2		T137	1
auto[1610612736:1744830463]	151	1			T24	1		T138	1		T215	1
auto[1744830464:1879048191]	123	1			T24	1		T36	1		T137	1
auto[1879048192:2013265919]	141	1			T14	1		T16	1		T24	3
auto[2013265920:2147483647]	159	1			T2	1		T16	1		T24	2
auto[2147483648:2281701375]	139	1			T24	3		T137	1		T40	1
auto[2281701376:2415919103]	123	1			T3	1		T12	1		T24	2
auto[2415919104:2550136831]	173	1			T24	1		T137	1		T199	1
auto[2550136832:2684354559]	146	1			T24	1		T36	1		T138	1
auto[2684354560:2818572287]	150	1			T2	1		T53	1		T135	1
auto[2818572288:2952790015]	121	1			T16	1		T138	1		T199	1
auto[2952790016:3087007743]	124	1			T24	2		T45	1		T135	1
auto[3087007744:3221225471]	135	1			T3	1		T16	2		T24	2
auto[3221225472:3355443199]	133	1			T24	3		T46	1		T135	1
auto[3355443200:3489660927]	131	1			T12	1		T24	1		T138	1
auto[3489660928:3623878655]	134	1			T14	2		T16	1		T24	1
auto[3623878656:3758096383]	143	1			T24	2		T40	1		T103	1
auto[3758096384:3892314111]	142	1			T16	1		T24	1		T36	1
auto[3892314112:4026531839]	147	1			T12	1		T45	1		T135	1
auto[4026531840:4160749567]	146	1			T16	2		T40	1		T215	1
auto[4160749568:4294967295]	172	1			T3	3		T14	1		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3051	1			T2	5		T3	7		T12	3
auto[0:134217727]	auto[1]	3	1			T406	1		T247	1		T413	1
auto[134217728:268435455]	auto[0]	173	1			T12	1		T16	1		T24	4
auto[134217728:268435455]	auto[1]	7	1			T140	2		T347	1		T403	1
auto[268435456:402653183]	auto[0]	146	1			T2	1		T24	1		T45	3
auto[268435456:402653183]	auto[1]	12	1			T14	1		T140	1		T380	1
auto[402653184:536870911]	auto[0]	147	1			T14	1		T16	1		T24	2
auto[402653184:536870911]	auto[1]	8	1			T135	1		T141	1		T403	1
auto[536870912:671088639]	auto[0]	146	1			T204	1		T59	1		T61	1
auto[536870912:671088639]	auto[1]	9	1			T138	1		T141	1		T386	1
auto[671088640:805306367]	auto[0]	137	1			T3	1		T24	1		T135	1
auto[671088640:805306367]	auto[1]	9	1			T254	1		T258	1		T381	1
auto[805306368:939524095]	auto[0]	135	1			T2	1		T16	1		T24	1
auto[805306368:939524095]	auto[1]	10	1			T386	1		T357	1		T403	2
auto[939524096:1073741823]	auto[0]	137	1			T24	1		T53	1		T215	1
auto[939524096:1073741823]	auto[1]	6	1			T258	2		T387	1		T401	1
auto[1073741824:1207959551]	auto[0]	135	1			T2	1		T36	2		T45	1
auto[1073741824:1207959551]	auto[1]	9	1			T357	1		T387	1		T404	2
auto[1207959552:1342177279]	auto[0]	124	1			T24	1		T137	2		T141	1
auto[1207959552:1342177279]	auto[1]	10	1			T141	1		T258	3		T311	1
auto[1342177280:1476395007]	auto[0]	132	1			T3	1		T16	1		T24	1
auto[1342177280:1476395007]	auto[1]	5	1			T141	1		T258	1		T331	1
auto[1476395008:1610612735]	auto[0]	137	1			T2	1		T24	2		T137	1
auto[1476395008:1610612735]	auto[1]	8	1			T140	1		T141	1		T258	1
auto[1610612736:1744830463]	auto[0]	144	1			T24	1		T138	1		T215	1
auto[1610612736:1744830463]	auto[1]	7	1			T153	1		T379	1		T267	1
auto[1744830464:1879048191]	auto[0]	115	1			T24	1		T36	1		T137	1
auto[1744830464:1879048191]	auto[1]	8	1			T153	1		T386	1		T407	1
auto[1879048192:2013265919]	auto[0]	134	1			T14	1		T16	1		T24	3
auto[1879048192:2013265919]	auto[1]	7	1			T379	1		T357	1		T306	2
auto[2013265920:2147483647]	auto[0]	146	1			T2	1		T16	1		T24	2
auto[2013265920:2147483647]	auto[1]	13	1			T135	1		T140	1		T141	2
auto[2147483648:2281701375]	auto[0]	129	1			T24	3		T137	1		T40	1
auto[2147483648:2281701375]	auto[1]	10	1			T140	2		T141	1		T254	1
auto[2281701376:2415919103]	auto[0]	117	1			T3	1		T12	1		T24	2
auto[2281701376:2415919103]	auto[1]	6	1			T144	1		T414	1		T334	2
auto[2415919104:2550136831]	auto[0]	166	1			T24	1		T137	1		T199	1
auto[2415919104:2550136831]	auto[1]	7	1			T141	1		T299	1		T306	1
auto[2550136832:2684354559]	auto[0]	137	1			T24	1		T36	1		T114	1
auto[2550136832:2684354559]	auto[1]	9	1			T138	1		T140	1		T254	1
auto[2684354560:2818572287]	auto[0]	140	1			T2	1		T53	1		T135	1
auto[2684354560:2818572287]	auto[1]	10	1			T138	2		T142	1		T144	1
auto[2818572288:2952790015]	auto[0]	112	1			T16	1		T138	1		T199	1
auto[2818572288:2952790015]	auto[1]	9	1			T380	1		T258	1		T379	1
auto[2952790016:3087007743]	auto[0]	116	1			T24	2		T45	1		T215	1
auto[2952790016:3087007743]	auto[1]	8	1			T135	1		T379	1		T403	2
auto[3087007744:3221225471]	auto[0]	125	1			T3	1		T16	2		T24	2
auto[3087007744:3221225471]	auto[1]	10	1			T254	1		T258	1		T299	1
auto[3221225472:3355443199]	auto[0]	122	1			T24	3		T46	1		T48	2
auto[3221225472:3355443199]	auto[1]	11	1			T135	1		T258	1		T311	3
auto[3355443200:3489660927]	auto[0]	118	1			T12	1		T24	1		T40	1
auto[3355443200:3489660927]	auto[1]	13	1			T138	1		T254	1		T299	1
auto[3489660928:3623878655]	auto[0]	127	1			T14	2		T16	1		T24	1
auto[3489660928:3623878655]	auto[1]	7	1			T142	1		T258	1		T299	1
auto[3623878656:3758096383]	auto[0]	136	1			T24	2		T40	1		T103	1
auto[3623878656:3758096383]	auto[1]	7	1			T258	1		T379	1		T311	1
auto[3758096384:3892314111]	auto[0]	133	1			T16	1		T24	1		T36	1
auto[3758096384:3892314111]	auto[1]	9	1			T153	1		T379	1		T311	1
auto[3892314112:4026531839]	auto[0]	138	1			T12	1		T45	1		T135	1
auto[3892314112:4026531839]	auto[1]	9	1			T299	2		T379	1		T403	1
auto[4026531840:4160749567]	auto[0]	137	1			T16	2		T40	1		T215	1
auto[4026531840:4160749567]	auto[1]	9	1			T299	1		T357	1		T347	1
auto[4160749568:4294967295]	auto[0]	166	1			T3	3		T45	1		T137	1
auto[4160749568:4294967295]	auto[1]	6	1			T14	1		T135	1		T254	1