Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4586

1

T2

10

T3

6

T12

8

auto[1]

2262

1

T3

2

T16

4

T24

20

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	210	1			T24	6		T46	4		T153	2
auto[134217728:268435455]	222	1			T24	4		T45	2		T113	2
auto[268435456:402653183]	244	1			T3	2		T14	2		T24	4
auto[402653184:536870911]	228	1			T24	2		T45	2		T199	4
auto[536870912:671088639]	214	1			T24	2		T36	2		T45	2
auto[671088640:805306367]	218	1			T14	2		T36	2		T46	2
auto[805306368:939524095]	206	1			T36	2		T46	2		T40	2
auto[939524096:1073741823]	228	1			T114	2		T59	2		T193	2
auto[1073741824:1207959551]	246	1			T16	4		T24	2		T45	4
auto[1207959552:1342177279]	160	1			T3	2		T14	2		T40	2
auto[1342177280:1476395007]	198	1			T45	2		T137	2		T202	2
auto[1476395008:1610612735]	172	1			T12	2		T140	2		T25	2
auto[1610612736:1744830463]	178	1			T2	6		T53	2		T202	2
auto[1744830464:1879048191]	208	1			T40	2		T48	8		T61	2
auto[1879048192:2013265919]	170	1			T3	4		T215	2		T114	2
auto[2013265920:2147483647]	226	1			T2	2		T24	2		T137	2
auto[2147483648:2281701375]	220	1			T16	2		T46	2		T138	2
auto[2281701376:2415919103]	208	1			T12	2		T202	4		T205	2
auto[2415919104:2550136831]	188	1			T16	4		T24	2		T199	2
auto[2550136832:2684354559]	208	1			T36	2		T135	2		T50	2
auto[2684354560:2818572287]	220	1			T12	2		T46	2		T114	2
auto[2818572288:2952790015]	224	1			T2	2		T135	2		T62	2
auto[2952790016:3087007743]	192	1			T24	2		T135	2		T215	2
auto[3087007744:3221225471]	180	1			T53	2		T25	2		T112	2
auto[3221225472:3355443199]	272	1			T24	2		T53	2		T135	2
auto[3355443200:3489660927]	242	1			T14	2		T138	4		T200	2
auto[3489660928:3623878655]	190	1			T24	2		T46	2		T38	2
auto[3623878656:3758096383]	232	1			T24	6		T40	2		T215	2
auto[3758096384:3892314111]	242	1			T16	2		T36	2		T40	2
auto[3892314112:4026531839]	206	1			T24	2		T36	2		T204	2
auto[4026531840:4160749567]	242	1			T16	2		T24	6		T53	2
auto[4160749568:4294967295]	254	1			T12	2		T24	2		T200	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	138	1			T24	2		T46	2		T153	2
auto[0:134217727]	auto[1]	72	1			T24	4		T46	2		T51	2
auto[134217728:268435455]	auto[0]	126	1			T117	2		T48	2		T94	2
auto[134217728:268435455]	auto[1]	96	1			T24	4		T45	2		T113	2
auto[268435456:402653183]	auto[0]	172	1			T3	2		T14	2		T24	4
auto[268435456:402653183]	auto[1]	72	1			T18	2		T284	2		T38	2
auto[402653184:536870911]	auto[0]	164	1			T45	2		T199	4		T52	2
auto[402653184:536870911]	auto[1]	64	1			T24	2		T204	2		T275	2
auto[536870912:671088639]	auto[0]	152	1			T24	2		T45	2		T200	2
auto[536870912:671088639]	auto[1]	62	1			T36	2		T62	2		T63	2
auto[671088640:805306367]	auto[0]	144	1			T14	2		T46	2		T140	2
auto[671088640:805306367]	auto[1]	74	1			T36	2		T50	2		T99	2
auto[805306368:939524095]	auto[0]	146	1			T36	2		T40	2		T112	2
auto[805306368:939524095]	auto[1]	60	1			T46	2		T141	2		T106	2
auto[939524096:1073741823]	auto[0]	168	1			T114	2		T59	2		T193	2
auto[939524096:1073741823]	auto[1]	60	1			T336	2		T19	2		T219	2
auto[1073741824:1207959551]	auto[0]	156	1			T16	4		T45	4		T40	2
auto[1073741824:1207959551]	auto[1]	90	1			T24	2		T205	2		T54	2
auto[1207959552:1342177279]	auto[0]	106	1			T14	2		T40	2		T48	4
auto[1207959552:1342177279]	auto[1]	54	1			T3	2		T60	2		T69	4
auto[1342177280:1476395007]	auto[0]	136	1			T137	2		T202	2		T204	2
auto[1342177280:1476395007]	auto[1]	62	1			T45	2		T263	2		T131	4
auto[1476395008:1610612735]	auto[0]	108	1			T12	2		T140	2		T25	2
auto[1476395008:1610612735]	auto[1]	64	1			T106	2		T50	2		T26	2
auto[1610612736:1744830463]	auto[0]	120	1			T2	6		T202	2		T141	2
auto[1610612736:1744830463]	auto[1]	58	1			T53	2		T196	2		T52	2
auto[1744830464:1879048191]	auto[0]	156	1			T48	4		T61	2		T60	2
auto[1744830464:1879048191]	auto[1]	52	1			T40	2		T48	4		T99	2
auto[1879048192:2013265919]	auto[0]	106	1			T3	4		T114	2		T50	2
auto[1879048192:2013265919]	auto[1]	64	1			T215	2		T52	2		T61	2
auto[2013265920:2147483647]	auto[0]	164	1			T2	2		T24	2		T137	2
auto[2013265920:2147483647]	auto[1]	62	1			T47	2		T63	2		T416	2
auto[2147483648:2281701375]	auto[0]	156	1			T16	2		T46	2		T138	2
auto[2147483648:2281701375]	auto[1]	64	1			T65	2		T412	2		T95	2
auto[2281701376:2415919103]	auto[0]	136	1			T12	2		T202	2		T205	2
auto[2281701376:2415919103]	auto[1]	72	1			T202	2		T106	2		T62	2
auto[2415919104:2550136831]	auto[0]	110	1			T16	2		T200	2		T211	2
auto[2415919104:2550136831]	auto[1]	78	1			T16	2		T24	2		T199	2
auto[2550136832:2684354559]	auto[0]	134	1			T36	2		T135	2		T51	2
auto[2550136832:2684354559]	auto[1]	74	1			T50	2		T268	2		T218	2
auto[2684354560:2818572287]	auto[0]	144	1			T12	2		T46	2		T117	2
auto[2684354560:2818572287]	auto[1]	76	1			T114	2		T51	2		T48	6
auto[2818572288:2952790015]	auto[0]	158	1			T2	2		T135	2		T112	2
auto[2818572288:2952790015]	auto[1]	66	1			T62	2		T61	2		T21	2
auto[2952790016:3087007743]	auto[0]	136	1			T24	2		T135	2		T215	2
auto[2952790016:3087007743]	auto[1]	56	1			T202	2		T196	2		T48	2
auto[3087007744:3221225471]	auto[0]	128	1			T25	2		T112	2		T50	2
auto[3087007744:3221225471]	auto[1]	52	1			T53	2		T48	2		T144	2
auto[3221225472:3355443199]	auto[0]	198	1			T24	2		T53	2		T135	2
auto[3221225472:3355443199]	auto[1]	74	1			T215	2		T196	2		T60	2
auto[3355443200:3489660927]	auto[0]	148	1			T14	2		T138	2		T200	2
auto[3355443200:3489660927]	auto[1]	94	1			T138	2		T61	2		T336	2
auto[3489660928:3623878655]	auto[0]	128	1			T24	2		T46	2		T50	4
auto[3489660928:3623878655]	auto[1]	62	1			T38	2		T52	2		T389	2
auto[3623878656:3758096383]	auto[0]	150	1			T24	2		T50	2		T52	2
auto[3623878656:3758096383]	auto[1]	82	1			T24	4		T40	2		T215	2
auto[3758096384:3892314111]	auto[0]	174	1			T16	2		T36	2		T40	2
auto[3758096384:3892314111]	auto[1]	68	1			T112	2		T61	2		T65	2
auto[3892314112:4026531839]	auto[0]	124	1			T24	2		T204	2		T117	2
auto[3892314112:4026531839]	auto[1]	82	1			T36	2		T4	2		T117	2
auto[4026531840:4160749567]	auto[0]	142	1			T24	4		T53	2		T137	4
auto[4026531840:4160749567]	auto[1]	100	1			T16	2		T24	2		T91	2
auto[4160749568:4294967295]	auto[0]	158	1			T12	2		T24	2		T200	2
auto[4160749568:4294967295]	auto[1]	96	1			T114	2		T113	2		T141	2