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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.04 98.03 98.26 100.00 99.02 98.41 91.17


Total test records in report: 1084
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T161 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2226720393 Jul 03 05:20:10 PM PDT 24 Jul 03 05:20:20 PM PDT 24 708206227 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2802706324 Jul 03 05:20:06 PM PDT 24 Jul 03 05:20:09 PM PDT 24 72725245 ps
T1008 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4174793387 Jul 03 05:20:30 PM PDT 24 Jul 03 05:20:31 PM PDT 24 93984200 ps
T1009 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3505296897 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:24 PM PDT 24 116654421 ps
T1010 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.855419995 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:29 PM PDT 24 176447000 ps
T1011 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2395135943 Jul 03 05:20:28 PM PDT 24 Jul 03 05:20:29 PM PDT 24 40771490 ps
T1012 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.83200427 Jul 03 05:20:17 PM PDT 24 Jul 03 05:20:18 PM PDT 24 38110400 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1937287344 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:27 PM PDT 24 104453456 ps
T1014 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3309333835 Jul 03 05:20:52 PM PDT 24 Jul 03 05:20:53 PM PDT 24 12029408 ps
T1015 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2178828446 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:21 PM PDT 24 445959390 ps
T1016 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.45375589 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:25 PM PDT 24 13590018 ps
T1017 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4061280308 Jul 03 05:20:19 PM PDT 24 Jul 03 05:20:23 PM PDT 24 177983508 ps
T1018 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3027674430 Jul 03 05:20:26 PM PDT 24 Jul 03 05:20:27 PM PDT 24 23877995 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.94200706 Jul 03 05:20:12 PM PDT 24 Jul 03 05:20:14 PM PDT 24 29560743 ps
T1020 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.40932425 Jul 03 05:20:11 PM PDT 24 Jul 03 05:20:15 PM PDT 24 345127453 ps
T1021 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3788148828 Jul 03 05:20:21 PM PDT 24 Jul 03 05:20:36 PM PDT 24 727014938 ps
T1022 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3905555073 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:24 PM PDT 24 96360499 ps
T1023 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2154216779 Jul 03 05:20:13 PM PDT 24 Jul 03 05:20:18 PM PDT 24 382621266 ps
T1024 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1374668589 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:20 PM PDT 24 105944635 ps
T1025 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1062077187 Jul 03 05:20:22 PM PDT 24 Jul 03 05:20:24 PM PDT 24 8467224 ps
T156 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2792277271 Jul 03 05:20:07 PM PDT 24 Jul 03 05:20:11 PM PDT 24 484717470 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3998718994 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:26 PM PDT 24 63582399 ps
T1027 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2936003519 Jul 03 05:20:14 PM PDT 24 Jul 03 05:20:15 PM PDT 24 13891653 ps
T1028 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.661058333 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:22 PM PDT 24 176545913 ps
T1029 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1917532984 Jul 03 05:20:09 PM PDT 24 Jul 03 05:20:17 PM PDT 24 460047337 ps
T1030 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.532359039 Jul 03 05:20:10 PM PDT 24 Jul 03 05:20:13 PM PDT 24 129776555 ps
T1031 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.656814206 Jul 03 05:20:16 PM PDT 24 Jul 03 05:20:19 PM PDT 24 30359721 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2906695896 Jul 03 05:20:13 PM PDT 24 Jul 03 05:20:15 PM PDT 24 100388218 ps
T1033 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2928315876 Jul 03 05:20:05 PM PDT 24 Jul 03 05:20:07 PM PDT 24 111412262 ps
T1034 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2319202200 Jul 03 05:20:26 PM PDT 24 Jul 03 05:20:28 PM PDT 24 10473559 ps
T1035 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2671329214 Jul 03 05:20:13 PM PDT 24 Jul 03 05:20:17 PM PDT 24 122557838 ps
T1036 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3111212236 Jul 03 05:20:15 PM PDT 24 Jul 03 05:20:19 PM PDT 24 222999141 ps
T1037 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2278877662 Jul 03 05:20:15 PM PDT 24 Jul 03 05:20:18 PM PDT 24 173967608 ps
T1038 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.43035130 Jul 03 05:20:19 PM PDT 24 Jul 03 05:20:21 PM PDT 24 63556045 ps
T1039 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1263935235 Jul 03 05:20:05 PM PDT 24 Jul 03 05:20:06 PM PDT 24 8930008 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2510818263 Jul 03 05:20:01 PM PDT 24 Jul 03 05:20:03 PM PDT 24 8099654 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1151340437 Jul 03 05:20:10 PM PDT 24 Jul 03 05:20:13 PM PDT 24 30281803 ps
T1042 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3346458173 Jul 03 05:20:11 PM PDT 24 Jul 03 05:20:28 PM PDT 24 2674855563 ps
T1043 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1789063638 Jul 03 05:20:22 PM PDT 24 Jul 03 05:20:24 PM PDT 24 15016558 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2718237634 Jul 03 05:20:14 PM PDT 24 Jul 03 05:20:16 PM PDT 24 32667662 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.837740144 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:20 PM PDT 24 9951262 ps
T1046 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1790650393 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:28 PM PDT 24 647841954 ps
T1047 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1606837302 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:22 PM PDT 24 120321702 ps
T1048 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.487145458 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:24 PM PDT 24 162394791 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.417065499 Jul 03 05:20:02 PM PDT 24 Jul 03 05:20:04 PM PDT 24 63769462 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1400968400 Jul 03 05:20:02 PM PDT 24 Jul 03 05:20:06 PM PDT 24 365939807 ps
T1051 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4032023504 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:24 PM PDT 24 156929971 ps
T1052 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.280104351 Jul 03 05:20:22 PM PDT 24 Jul 03 05:20:24 PM PDT 24 23902670 ps
T1053 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1807273932 Jul 03 05:20:24 PM PDT 24 Jul 03 05:20:25 PM PDT 24 13606133 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1471314050 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:19 PM PDT 24 44383982 ps
T1055 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1098695731 Jul 03 05:20:19 PM PDT 24 Jul 03 05:20:23 PM PDT 24 571235416 ps
T1056 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3839406155 Jul 03 05:20:27 PM PDT 24 Jul 03 05:20:29 PM PDT 24 38894352 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3526219930 Jul 03 05:20:17 PM PDT 24 Jul 03 05:20:19 PM PDT 24 9884240 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2834051102 Jul 03 05:20:03 PM PDT 24 Jul 03 05:20:10 PM PDT 24 971044416 ps
T1059 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1708049546 Jul 03 05:20:15 PM PDT 24 Jul 03 05:20:19 PM PDT 24 154538057 ps
T1060 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2608832399 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:23 PM PDT 24 23117001 ps
T157 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4009117137 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:23 PM PDT 24 400872927 ps
T1061 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2075879925 Jul 03 05:20:01 PM PDT 24 Jul 03 05:20:03 PM PDT 24 535686308 ps
T1062 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.69028017 Jul 03 05:20:10 PM PDT 24 Jul 03 05:20:13 PM PDT 24 535865286 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.507935102 Jul 03 05:20:22 PM PDT 24 Jul 03 05:20:24 PM PDT 24 54326018 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1561852053 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:20 PM PDT 24 191596479 ps
T1065 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3326517661 Jul 03 05:20:25 PM PDT 24 Jul 03 05:20:27 PM PDT 24 37041311 ps
T1066 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1157449011 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:26 PM PDT 24 1412181837 ps
T170 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2536767774 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:25 PM PDT 24 786801098 ps
T1067 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.763916916 Jul 03 05:20:02 PM PDT 24 Jul 03 05:20:05 PM PDT 24 52897899 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3518776717 Jul 03 05:20:22 PM PDT 24 Jul 03 05:20:25 PM PDT 24 81520156 ps
T1069 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3178034713 Jul 03 05:20:11 PM PDT 24 Jul 03 05:20:12 PM PDT 24 33309443 ps
T1070 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1636635166 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:22 PM PDT 24 460997448 ps
T1071 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3506543830 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:28 PM PDT 24 513578553 ps
T1072 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1582729642 Jul 03 05:20:05 PM PDT 24 Jul 03 05:20:07 PM PDT 24 34066542 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3291464702 Jul 03 05:20:05 PM PDT 24 Jul 03 05:20:18 PM PDT 24 1436598840 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1452889989 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:25 PM PDT 24 24868293 ps
T1075 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3006332209 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:26 PM PDT 24 439362513 ps
T1076 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3231922567 Jul 03 05:20:20 PM PDT 24 Jul 03 05:20:29 PM PDT 24 551187933 ps
T1077 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3256539347 Jul 03 05:20:24 PM PDT 24 Jul 03 05:20:26 PM PDT 24 43542884 ps
T1078 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3685528895 Jul 03 05:20:18 PM PDT 24 Jul 03 05:20:22 PM PDT 24 58609504 ps
T1079 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.396095522 Jul 03 05:20:11 PM PDT 24 Jul 03 05:20:12 PM PDT 24 27730368 ps
T165 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1219362457 Jul 03 05:20:23 PM PDT 24 Jul 03 05:20:31 PM PDT 24 1066556116 ps
T1080 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2955586302 Jul 03 05:20:02 PM PDT 24 Jul 03 05:20:06 PM PDT 24 181167812 ps
T1081 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2276936528 Jul 03 05:20:19 PM PDT 24 Jul 03 05:20:21 PM PDT 24 10082813 ps
T1082 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3647433841 Jul 03 05:20:27 PM PDT 24 Jul 03 05:20:29 PM PDT 24 34955636 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2034355294 Jul 03 05:20:03 PM PDT 24 Jul 03 05:20:09 PM PDT 24 1618721595 ps
T1084 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.86562200 Jul 03 05:20:17 PM PDT 24 Jul 03 05:20:28 PM PDT 24 1720260105 ps
T172 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.480090307 Jul 03 05:20:16 PM PDT 24 Jul 03 05:20:24 PM PDT 24 399813719 ps

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2482431954
Short name T16
Test name
Test status
Simulation time 224853960 ps
CPU time 6.21 seconds
Started Jul 03 05:56:20 PM PDT 24
Finished Jul 03 05:56:27 PM PDT 24
Peak memory 218520 kb
Host smart-a5816020-26e2-43a1-b058-0e51b9823964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482431954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2482431954
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.969142942
Short name T48
Test name
Test status
Simulation time 65282117995 ps
CPU time 103.84 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 217144 kb
Host smart-2400db22-7d98-4614-8357-36fc702a2c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969142942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.969142942
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2441101736
Short name T24
Test name
Test status
Simulation time 5919985965 ps
CPU time 29.55 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:30 PM PDT 24
Peak memory 222732 kb
Host smart-ba3adf3b-4a1f-4c1d-b371-7f1230850190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441101736 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2441101736
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1803981060
Short name T64
Test name
Test status
Simulation time 39691206 ps
CPU time 1.65 seconds
Started Jul 03 05:56:51 PM PDT 24
Finished Jul 03 05:56:53 PM PDT 24
Peak memory 210044 kb
Host smart-b2cfc4e3-b644-46cc-925c-5af5f38c37ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803981060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1803981060
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3122917395
Short name T8
Test name
Test status
Simulation time 2326704137 ps
CPU time 12.75 seconds
Started Jul 03 05:56:25 PM PDT 24
Finished Jul 03 05:56:39 PM PDT 24
Peak memory 232760 kb
Host smart-9d8c205b-ce1e-4327-925b-a25e2eb3f394
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122917395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3122917395
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4173248007
Short name T69
Test name
Test status
Simulation time 546771800 ps
CPU time 21.67 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:22 PM PDT 24
Peak memory 222612 kb
Host smart-d6642190-3de7-48a1-8743-3a93bdee69f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173248007 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4173248007
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2351345141
Short name T50
Test name
Test status
Simulation time 1485566148 ps
CPU time 27.68 seconds
Started Jul 03 05:57:47 PM PDT 24
Finished Jul 03 05:58:15 PM PDT 24
Peak memory 222440 kb
Host smart-dd4d58d4-ba91-4362-a542-7e892501ff2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351345141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2351345141
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3785970788
Short name T258
Test name
Test status
Simulation time 1607189753 ps
CPU time 21.23 seconds
Started Jul 03 05:58:29 PM PDT 24
Finished Jul 03 05:58:51 PM PDT 24
Peak memory 215248 kb
Host smart-f4996a98-eee0-4ef1-8d2b-78b97b5c36a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785970788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3785970788
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1681293929
Short name T36
Test name
Test status
Simulation time 129936417 ps
CPU time 5.05 seconds
Started Jul 03 05:58:18 PM PDT 24
Finished Jul 03 05:58:24 PM PDT 24
Peak memory 214340 kb
Host smart-8ad79950-6144-46b5-a5f2-a2a5411c4177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681293929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1681293929
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1730951632
Short name T4
Test name
Test status
Simulation time 1386493379 ps
CPU time 6.55 seconds
Started Jul 03 05:57:39 PM PDT 24
Finished Jul 03 05:57:46 PM PDT 24
Peak memory 222748 kb
Host smart-74329d8c-ae59-457f-ab14-de3b78cea0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730951632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1730951632
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3036545904
Short name T125
Test name
Test status
Simulation time 145002068 ps
CPU time 8.26 seconds
Started Jul 03 05:20:07 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 214192 kb
Host smart-1d553f3d-da35-4724-ae1f-1a8b2d18f5b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036545904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3036545904
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3451544310
Short name T141
Test name
Test status
Simulation time 578491933 ps
CPU time 8.75 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:10 PM PDT 24
Peak memory 215424 kb
Host smart-929d8d72-dd2e-4627-8b50-3d721bd71e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451544310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3451544310
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.566717827
Short name T7
Test name
Test status
Simulation time 233111487 ps
CPU time 1.78 seconds
Started Jul 03 05:56:31 PM PDT 24
Finished Jul 03 05:56:33 PM PDT 24
Peak memory 217064 kb
Host smart-154b365b-721f-4fd5-8f49-69209f2a5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566717827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.566717827
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1671439999
Short name T65
Test name
Test status
Simulation time 515803045 ps
CPU time 24.89 seconds
Started Jul 03 05:59:29 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 222524 kb
Host smart-c72f8a62-19cb-4c41-b9e5-1cc1aca5f506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671439999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1671439999
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4033614273
Short name T55
Test name
Test status
Simulation time 632431695 ps
CPU time 31.73 seconds
Started Jul 03 05:57:22 PM PDT 24
Finished Jul 03 05:57:54 PM PDT 24
Peak memory 222576 kb
Host smart-27c87454-f99c-42a5-9598-ba9f6bdc258a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033614273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4033614273
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2504689131
Short name T299
Test name
Test status
Simulation time 9120937207 ps
CPU time 117.12 seconds
Started Jul 03 06:00:02 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 214372 kb
Host smart-b5f16611-1795-47c8-9b6c-c85835226fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504689131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2504689131
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1368463522
Short name T23
Test name
Test status
Simulation time 74140246 ps
CPU time 3.36 seconds
Started Jul 03 05:56:54 PM PDT 24
Finished Jul 03 05:56:58 PM PDT 24
Peak memory 214332 kb
Host smart-78203380-5c0e-46db-a59f-a52d3055f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368463522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1368463522
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4020169599
Short name T153
Test name
Test status
Simulation time 1665678188 ps
CPU time 45.36 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 05:59:38 PM PDT 24
Peak memory 215712 kb
Host smart-9daa9313-9e5e-41ec-9ed2-d13e3eadc0c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020169599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4020169599
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3081971294
Short name T331
Test name
Test status
Simulation time 872487324 ps
CPU time 9.12 seconds
Started Jul 03 05:59:06 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 215132 kb
Host smart-42837174-5c9e-412c-aa19-7113f7cba0dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081971294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3081971294
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3697696194
Short name T138
Test name
Test status
Simulation time 64524990 ps
CPU time 4.17 seconds
Started Jul 03 05:57:31 PM PDT 24
Finished Jul 03 05:57:36 PM PDT 24
Peak memory 214532 kb
Host smart-005f8ff4-bc77-4c6c-8a25-8892310d2aa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697696194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3697696194
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3671166196
Short name T18
Test name
Test status
Simulation time 88522922 ps
CPU time 3 seconds
Started Jul 03 05:56:56 PM PDT 24
Finished Jul 03 05:57:00 PM PDT 24
Peak memory 210736 kb
Host smart-e6ccc76a-11a2-4de0-aab6-e2cb2812e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671166196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3671166196
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3358202361
Short name T61
Test name
Test status
Simulation time 730066928 ps
CPU time 15.95 seconds
Started Jul 03 05:56:07 PM PDT 24
Finished Jul 03 05:56:23 PM PDT 24
Peak memory 215092 kb
Host smart-8b9908b5-9b5d-4f0b-a82b-485b93073fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358202361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3358202361
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1668223644
Short name T227
Test name
Test status
Simulation time 2175757238 ps
CPU time 32.47 seconds
Started Jul 03 05:56:51 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 215460 kb
Host smart-58e74386-3acc-4362-bd29-e33572bf960d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668223644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1668223644
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.666984516
Short name T293
Test name
Test status
Simulation time 141481468 ps
CPU time 7.18 seconds
Started Jul 03 05:56:46 PM PDT 24
Finished Jul 03 05:56:54 PM PDT 24
Peak memory 215456 kb
Host smart-4071b8ab-df7d-4912-be9b-c93e658a929f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666984516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.666984516
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2283592026
Short name T294
Test name
Test status
Simulation time 186334583 ps
CPU time 2.78 seconds
Started Jul 03 05:59:09 PM PDT 24
Finished Jul 03 05:59:12 PM PDT 24
Peak memory 208740 kb
Host smart-be4cc615-3fe8-4fc1-8e08-d04b6a01952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283592026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2283592026
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1373593872
Short name T118
Test name
Test status
Simulation time 53173378 ps
CPU time 2.34 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:03 PM PDT 24
Peak memory 222672 kb
Host smart-b7c5d310-2174-4564-a803-d6a583036ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373593872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1373593872
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2845460591
Short name T40
Test name
Test status
Simulation time 147678699 ps
CPU time 2.87 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 222372 kb
Host smart-a3857b8f-5a4f-402d-b88b-c648470ada30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845460591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2845460591
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.810289626
Short name T128
Test name
Test status
Simulation time 134245048 ps
CPU time 3.95 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213916 kb
Host smart-0ab36ac9-9896-46c6-9469-e71f79b7efd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810289626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.810289626
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3915486545
Short name T28
Test name
Test status
Simulation time 590733274 ps
CPU time 5.33 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:18 PM PDT 24
Peak memory 209408 kb
Host smart-e106f8f4-850d-4e18-a58a-7fd9a0e118ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915486545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3915486545
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.130872548
Short name T135
Test name
Test status
Simulation time 85917796 ps
CPU time 3.36 seconds
Started Jul 03 05:59:19 PM PDT 24
Finished Jul 03 05:59:22 PM PDT 24
Peak memory 215300 kb
Host smart-63cae1ac-a723-4054-a31f-9a22d8f3fb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130872548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.130872548
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1574377281
Short name T102
Test name
Test status
Simulation time 1396404805 ps
CPU time 34.53 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:53 PM PDT 24
Peak memory 221980 kb
Host smart-86e6a755-a441-446b-8d84-041c604a3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574377281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1574377281
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4203435750
Short name T21
Test name
Test status
Simulation time 251799250 ps
CPU time 3.06 seconds
Started Jul 03 05:59:14 PM PDT 24
Finished Jul 03 05:59:17 PM PDT 24
Peak memory 221176 kb
Host smart-812f4bf9-37c2-419f-89c0-3bd367622741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203435750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4203435750
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3174345981
Short name T273
Test name
Test status
Simulation time 10139235955 ps
CPU time 317.57 seconds
Started Jul 03 05:57:49 PM PDT 24
Finished Jul 03 06:03:07 PM PDT 24
Peak memory 217940 kb
Host smart-515df36c-7af8-40aa-90f9-793dce3d8b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174345981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3174345981
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2636497879
Short name T229
Test name
Test status
Simulation time 12515364657 ps
CPU time 46.77 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:59:07 PM PDT 24
Peak memory 222524 kb
Host smart-2943564c-4bb6-47cd-8b7a-8d3273c8fbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636497879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2636497879
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.99588131
Short name T401
Test name
Test status
Simulation time 2559606256 ps
CPU time 30.14 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 214364 kb
Host smart-7eae27d5-e095-422e-8b42-920a3a457b5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99588131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.99588131
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2104000122
Short name T263
Test name
Test status
Simulation time 551561228 ps
CPU time 4.06 seconds
Started Jul 03 06:00:01 PM PDT 24
Finished Jul 03 06:00:05 PM PDT 24
Peak memory 214324 kb
Host smart-ea98122a-9cd9-4174-b5c3-1fa201674ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104000122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2104000122
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3458393587
Short name T422
Test name
Test status
Simulation time 44233523 ps
CPU time 0.87 seconds
Started Jul 03 05:58:07 PM PDT 24
Finished Jul 03 05:58:09 PM PDT 24
Peak memory 206024 kb
Host smart-1b583737-8a1a-4cbf-8352-a0c12e8a52f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458393587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3458393587
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.726891893
Short name T218
Test name
Test status
Simulation time 8905736116 ps
CPU time 64.22 seconds
Started Jul 03 05:58:38 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 216812 kb
Host smart-2e5a5b72-2a85-43dd-8804-9714c9daa7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726891893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.726891893
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2644470433
Short name T225
Test name
Test status
Simulation time 37182777956 ps
CPU time 432.4 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 217180 kb
Host smart-357a66f7-9e93-4e0f-a317-e53e150ac2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644470433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2644470433
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2590932775
Short name T406
Test name
Test status
Simulation time 1238190442 ps
CPU time 12.03 seconds
Started Jul 03 05:58:40 PM PDT 24
Finished Jul 03 05:58:53 PM PDT 24
Peak memory 214248 kb
Host smart-94eb1fe3-5446-4b2c-9beb-c201c413a1ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590932775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2590932775
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3561011189
Short name T63
Test name
Test status
Simulation time 425341223 ps
CPU time 9.6 seconds
Started Jul 03 05:56:43 PM PDT 24
Finished Jul 03 05:56:53 PM PDT 24
Peak memory 221084 kb
Host smart-95bf31b1-14e8-45b7-bb52-307dc3c6578d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561011189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3561011189
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1222717044
Short name T68
Test name
Test status
Simulation time 241385699 ps
CPU time 6.05 seconds
Started Jul 03 05:59:57 PM PDT 24
Finished Jul 03 06:00:03 PM PDT 24
Peak memory 211208 kb
Host smart-887b9c45-adae-415d-b79b-4d604fd3e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222717044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1222717044
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2271837777
Short name T906
Test name
Test status
Simulation time 7741353617 ps
CPU time 69.1 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 06:00:03 PM PDT 24
Peak memory 222564 kb
Host smart-d06171cd-063b-4037-bc04-f7b03ed9ae39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271837777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2271837777
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.480090307
Short name T172
Test name
Test status
Simulation time 399813719 ps
CPU time 7.94 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213608 kb
Host smart-cd7dcf71-9977-4676-84bc-1d45406e477c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480090307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
480090307
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1493097131
Short name T247
Test name
Test status
Simulation time 58142022 ps
CPU time 4.04 seconds
Started Jul 03 05:57:17 PM PDT 24
Finished Jul 03 05:57:21 PM PDT 24
Peak memory 215488 kb
Host smart-fb2fcd72-9922-4587-b46c-9a0fb88af4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493097131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1493097131
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1642657782
Short name T222
Test name
Test status
Simulation time 80483017 ps
CPU time 2.88 seconds
Started Jul 03 05:57:28 PM PDT 24
Finished Jul 03 05:57:31 PM PDT 24
Peak memory 209812 kb
Host smart-db41d555-458a-4d43-a6d2-c666fc62ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642657782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1642657782
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1507570256
Short name T191
Test name
Test status
Simulation time 1078394718 ps
CPU time 40.13 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:57 PM PDT 24
Peak memory 215072 kb
Host smart-4b783568-5cbd-4435-9717-c3997e1b71c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507570256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1507570256
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2316249447
Short name T262
Test name
Test status
Simulation time 500376179 ps
CPU time 6.01 seconds
Started Jul 03 05:59:33 PM PDT 24
Finished Jul 03 05:59:39 PM PDT 24
Peak memory 222424 kb
Host smart-95e822f8-d4c5-4e80-a702-269f1e359b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316249447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2316249447
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2977914020
Short name T334
Test name
Test status
Simulation time 1750905464 ps
CPU time 36.93 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 06:00:23 PM PDT 24
Peak memory 214592 kb
Host smart-53fa5d38-4035-4e19-b57d-ea3c8cfb7de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977914020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2977914020
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1219362457
Short name T165
Test name
Test status
Simulation time 1066556116 ps
CPU time 7.34 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:31 PM PDT 24
Peak memory 213764 kb
Host smart-fa8a12e9-111b-47a8-929b-6bf0a3b81a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219362457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1219362457
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1295237517
Short name T162
Test name
Test status
Simulation time 97261753 ps
CPU time 4.43 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 213688 kb
Host smart-389c358b-ed97-40ab-a2d9-9d78e29e4b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295237517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1295237517
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1639669910
Short name T169
Test name
Test status
Simulation time 102240764 ps
CPU time 2.76 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 213784 kb
Host smart-2a63b622-078c-48da-88cf-a4a1741606ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639669910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1639669910
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.607449531
Short name T121
Test name
Test status
Simulation time 1027982259 ps
CPU time 3.4 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:04 PM PDT 24
Peak memory 218556 kb
Host smart-b151fdaa-49f4-41cf-a189-0b32ddfcdae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607449531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.607449531
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2990376963
Short name T60
Test name
Test status
Simulation time 2604967121 ps
CPU time 18.91 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:53 PM PDT 24
Peak memory 222684 kb
Host smart-77adb17b-3f3b-4e06-9d58-d2dacf634706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990376963 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2990376963
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1108238156
Short name T98
Test name
Test status
Simulation time 377699390 ps
CPU time 4.78 seconds
Started Jul 03 05:59:54 PM PDT 24
Finished Jul 03 05:59:59 PM PDT 24
Peak memory 215216 kb
Host smart-7df19f98-f5bd-42a9-ad0a-85478e4c900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108238156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1108238156
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1481756141
Short name T364
Test name
Test status
Simulation time 185251184 ps
CPU time 12.43 seconds
Started Jul 03 05:56:16 PM PDT 24
Finished Jul 03 05:56:28 PM PDT 24
Peak memory 222916 kb
Host smart-f1227baf-7026-480f-ab4f-207b35bf3361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481756141 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1481756141
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1772238136
Short name T9
Test name
Test status
Simulation time 546295840 ps
CPU time 12.2 seconds
Started Jul 03 05:56:06 PM PDT 24
Finished Jul 03 05:56:19 PM PDT 24
Peak memory 231620 kb
Host smart-89349d40-9dae-406a-8840-9551e2247936
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772238136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1772238136
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2998902001
Short name T32
Test name
Test status
Simulation time 227746323 ps
CPU time 2.67 seconds
Started Jul 03 05:58:19 PM PDT 24
Finished Jul 03 05:58:22 PM PDT 24
Peak memory 215056 kb
Host smart-6a396ddb-55bb-4d3e-82b3-ff6e95442eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998902001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2998902001
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.294263867
Short name T812
Test name
Test status
Simulation time 471424573 ps
CPU time 12.78 seconds
Started Jul 03 05:56:52 PM PDT 24
Finished Jul 03 05:57:05 PM PDT 24
Peak memory 214284 kb
Host smart-c469acf5-20f6-425f-90c7-3e796426f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294263867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.294263867
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2296328846
Short name T347
Test name
Test status
Simulation time 89585894 ps
CPU time 5.09 seconds
Started Jul 03 05:56:12 PM PDT 24
Finished Jul 03 05:56:18 PM PDT 24
Peak memory 215808 kb
Host smart-50d9026a-04b5-4025-92ad-7a96b0f714b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296328846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2296328846
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.544229388
Short name T322
Test name
Test status
Simulation time 851148168 ps
CPU time 5.55 seconds
Started Jul 03 05:57:15 PM PDT 24
Finished Jul 03 05:57:20 PM PDT 24
Peak memory 222392 kb
Host smart-ffac8a06-0f73-4fe4-9ecf-09932d773e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544229388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.544229388
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.974473316
Short name T312
Test name
Test status
Simulation time 39706750 ps
CPU time 2.9 seconds
Started Jul 03 05:58:24 PM PDT 24
Finished Jul 03 05:58:28 PM PDT 24
Peak memory 208800 kb
Host smart-f3d2419e-a157-4116-b4e4-56c99dcf62df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974473316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.974473316
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.4115568404
Short name T45
Test name
Test status
Simulation time 3976455675 ps
CPU time 19.4 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:45 PM PDT 24
Peak memory 223352 kb
Host smart-3cd8b21e-8ac6-4a7a-84d0-fdeeb248cdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115568404 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.4115568404
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2827207652
Short name T176
Test name
Test status
Simulation time 384944149 ps
CPU time 2.45 seconds
Started Jul 03 05:56:12 PM PDT 24
Finished Jul 03 05:56:15 PM PDT 24
Peak memory 210288 kb
Host smart-eb15946f-5e8f-4612-87cc-0aba152082fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827207652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2827207652
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2170428343
Short name T171
Test name
Test status
Simulation time 65971226 ps
CPU time 1.46 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:20 PM PDT 24
Peak memory 209956 kb
Host smart-3120c26f-119f-4716-b15a-da347ded7bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170428343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2170428343
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2225442993
Short name T119
Test name
Test status
Simulation time 304989802 ps
CPU time 3.91 seconds
Started Jul 03 05:56:19 PM PDT 24
Finished Jul 03 05:56:23 PM PDT 24
Peak memory 222700 kb
Host smart-6d4a5fa4-9b9c-4559-81c0-0f8c61fd83d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225442993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2225442993
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.816207713
Short name T122
Test name
Test status
Simulation time 276260668 ps
CPU time 3.78 seconds
Started Jul 03 05:57:28 PM PDT 24
Finished Jul 03 05:57:32 PM PDT 24
Peak memory 217136 kb
Host smart-810cbadc-36e8-42a2-a680-f538d352e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816207713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.816207713
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3471855652
Short name T348
Test name
Test status
Simulation time 290209553 ps
CPU time 13.73 seconds
Started Jul 03 05:56:06 PM PDT 24
Finished Jul 03 05:56:20 PM PDT 24
Peak memory 222384 kb
Host smart-de641503-64e1-4f3d-9313-b54175ee809d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471855652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3471855652
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3307155343
Short name T349
Test name
Test status
Simulation time 42669965294 ps
CPU time 136.3 seconds
Started Jul 03 05:57:12 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 222568 kb
Host smart-c1b495bb-5e67-4305-8d58-8c9d217593a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307155343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3307155343
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.541182565
Short name T290
Test name
Test status
Simulation time 112991681 ps
CPU time 5.74 seconds
Started Jul 03 05:57:16 PM PDT 24
Finished Jul 03 05:57:22 PM PDT 24
Peak memory 222424 kb
Host smart-5aac3363-b824-4601-ba4a-115626e5ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541182565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.541182565
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3851270654
Short name T380
Test name
Test status
Simulation time 40150210 ps
CPU time 2.84 seconds
Started Jul 03 05:57:21 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 215216 kb
Host smart-1bd9a1d6-b39f-4aa7-bccd-1b0e5d8e6c3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851270654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3851270654
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1964047025
Short name T232
Test name
Test status
Simulation time 5375271001 ps
CPU time 82.34 seconds
Started Jul 03 05:57:44 PM PDT 24
Finished Jul 03 05:59:06 PM PDT 24
Peak memory 216608 kb
Host smart-bd820049-e6ac-4426-83fd-9af63506ab9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964047025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1964047025
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1330549431
Short name T245
Test name
Test status
Simulation time 777545532 ps
CPU time 15.04 seconds
Started Jul 03 05:57:48 PM PDT 24
Finished Jul 03 05:58:03 PM PDT 24
Peak memory 222632 kb
Host smart-2fc09ae2-8bcf-4e28-950a-3c7968061083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330549431 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1330549431
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3116758811
Short name T235
Test name
Test status
Simulation time 449572872 ps
CPU time 20.31 seconds
Started Jul 03 05:58:05 PM PDT 24
Finished Jul 03 05:58:25 PM PDT 24
Peak memory 222652 kb
Host smart-ef08976f-f35a-46e7-a44e-a03c8048c18b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116758811 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3116758811
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1675093909
Short name T296
Test name
Test status
Simulation time 228668838 ps
CPU time 3.51 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:35 PM PDT 24
Peak memory 208700 kb
Host smart-7644d705-4fe5-4d4a-8073-466fc5abdb7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675093909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1675093909
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.361992392
Short name T367
Test name
Test status
Simulation time 89831220 ps
CPU time 2.23 seconds
Started Jul 03 06:00:04 PM PDT 24
Finished Jul 03 06:00:07 PM PDT 24
Peak memory 214548 kb
Host smart-d5e7bf38-61cc-411e-ab62-f690afc37ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361992392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.361992392
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3827905663
Short name T22
Test name
Test status
Simulation time 493571564 ps
CPU time 2.36 seconds
Started Jul 03 05:56:53 PM PDT 24
Finished Jul 03 05:56:56 PM PDT 24
Peak memory 214360 kb
Host smart-28219522-9de8-46c7-88cb-82244ff8e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827905663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3827905663
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1912513612
Short name T173
Test name
Test status
Simulation time 98519337 ps
CPU time 5.43 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 213708 kb
Host smart-c55f4e41-935b-4483-ba4f-d4fd5f825333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912513612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1912513612
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2226720393
Short name T161
Test name
Test status
Simulation time 708206227 ps
CPU time 9.36 seconds
Started Jul 03 05:20:10 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 216116 kb
Host smart-a9b46cac-2572-49b6-b603-9cd1828ecf91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226720393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2226720393
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1663214287
Short name T174
Test name
Test status
Simulation time 82362440 ps
CPU time 2.03 seconds
Started Jul 03 05:57:50 PM PDT 24
Finished Jul 03 05:57:53 PM PDT 24
Peak memory 209960 kb
Host smart-88c1ac5b-ba1f-42fc-9a1f-e994bbf1b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663214287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1663214287
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.481871702
Short name T164
Test name
Test status
Simulation time 105119071 ps
CPU time 2.82 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 210020 kb
Host smart-e298e23a-338f-4fe5-ab4f-3810027e8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481871702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.481871702
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1954413830
Short name T167
Test name
Test status
Simulation time 568443570 ps
CPU time 10.06 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:32 PM PDT 24
Peak memory 213804 kb
Host smart-dce7d6ab-9015-415c-94d9-8f6506b33f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954413830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1954413830
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.444891031
Short name T241
Test name
Test status
Simulation time 968952275 ps
CPU time 7.2 seconds
Started Jul 03 05:56:05 PM PDT 24
Finished Jul 03 05:56:13 PM PDT 24
Peak memory 220748 kb
Host smart-7003db8d-99b1-449b-985c-7a4d2f9b9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444891031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.444891031
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1085652051
Short name T485
Test name
Test status
Simulation time 23194390 ps
CPU time 1.81 seconds
Started Jul 03 05:56:12 PM PDT 24
Finished Jul 03 05:56:14 PM PDT 24
Peak memory 207168 kb
Host smart-dad3fb58-0d6a-4c6b-a439-68f43545807b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085652051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1085652051
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3472120568
Short name T857
Test name
Test status
Simulation time 33734255 ps
CPU time 2.48 seconds
Started Jul 03 05:57:08 PM PDT 24
Finished Jul 03 05:57:11 PM PDT 24
Peak memory 217168 kb
Host smart-1e5ae17d-49c5-4180-a532-66dd5bc76d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472120568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3472120568
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2055065797
Short name T356
Test name
Test status
Simulation time 552822668 ps
CPU time 7.03 seconds
Started Jul 03 05:57:21 PM PDT 24
Finished Jul 03 05:57:29 PM PDT 24
Peak memory 218296 kb
Host smart-27ed671f-13b0-4080-bb5f-10a15a4418e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055065797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2055065797
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1841691873
Short name T278
Test name
Test status
Simulation time 178689917 ps
CPU time 3.57 seconds
Started Jul 03 05:57:25 PM PDT 24
Finished Jul 03 05:57:29 PM PDT 24
Peak memory 214276 kb
Host smart-5166b6ac-a43b-4fb5-a61b-1aad0f7e6b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841691873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1841691873
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1742801446
Short name T362
Test name
Test status
Simulation time 196047661 ps
CPU time 3.79 seconds
Started Jul 03 05:57:27 PM PDT 24
Finished Jul 03 05:57:31 PM PDT 24
Peak memory 215192 kb
Host smart-25cc2420-3805-4620-a73a-a9e9462ddac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742801446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1742801446
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3169578383
Short name T361
Test name
Test status
Simulation time 279566529 ps
CPU time 3.83 seconds
Started Jul 03 05:57:33 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 222248 kb
Host smart-c77c7c71-db57-4286-b16a-92f96e5533e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169578383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3169578383
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3304694238
Short name T342
Test name
Test status
Simulation time 144812645 ps
CPU time 1.85 seconds
Started Jul 03 05:57:39 PM PDT 24
Finished Jul 03 05:57:42 PM PDT 24
Peak memory 214332 kb
Host smart-1ed6b389-bfe8-4ad0-9533-8b25d9bb4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304694238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3304694238
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1123186577
Short name T244
Test name
Test status
Simulation time 208353709 ps
CPU time 3.94 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 210172 kb
Host smart-a29031c3-f28e-4d0f-bb22-37e2322519b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123186577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1123186577
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3842057551
Short name T339
Test name
Test status
Simulation time 89376226 ps
CPU time 4.07 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 220140 kb
Host smart-1f66a699-270b-4deb-8820-e269b840e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842057551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3842057551
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4259950969
Short name T365
Test name
Test status
Simulation time 712066933 ps
CPU time 9.92 seconds
Started Jul 03 05:58:07 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 215164 kb
Host smart-890216b6-09b8-4409-a8d2-6ca2eceedb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259950969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4259950969
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.941853077
Short name T82
Test name
Test status
Simulation time 273134160 ps
CPU time 2.38 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:15 PM PDT 24
Peak memory 208612 kb
Host smart-d08655d9-d5d2-4771-b84a-1405166fd754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941853077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.941853077
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3580820343
Short name T871
Test name
Test status
Simulation time 1196311144 ps
CPU time 12.54 seconds
Started Jul 03 05:58:22 PM PDT 24
Finished Jul 03 05:58:35 PM PDT 24
Peak memory 220156 kb
Host smart-3a12852b-60cf-4998-9d7a-f0d30f47b567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580820343 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3580820343
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1054681783
Short name T101
Test name
Test status
Simulation time 310371016 ps
CPU time 3.87 seconds
Started Jul 03 05:58:34 PM PDT 24
Finished Jul 03 05:58:39 PM PDT 24
Peak memory 214308 kb
Host smart-95c2959f-9497-4c05-81b4-c5ca573059fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054681783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1054681783
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2930892881
Short name T237
Test name
Test status
Simulation time 338556974 ps
CPU time 4.66 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 222392 kb
Host smart-708d5ef8-6d49-429e-abef-077998036f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930892881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2930892881
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3215933950
Short name T403
Test name
Test status
Simulation time 548956745 ps
CPU time 12.38 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:14 PM PDT 24
Peak memory 215592 kb
Host smart-f5c141e1-36b2-4f36-a43c-65d8a1a2cdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215933950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3215933950
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2031532775
Short name T316
Test name
Test status
Simulation time 2978667439 ps
CPU time 60.19 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 06:00:28 PM PDT 24
Peak memory 209096 kb
Host smart-46d98aed-5d7d-4186-9d6f-a91b8f104c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031532775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2031532775
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1288657157
Short name T267
Test name
Test status
Simulation time 959634801 ps
CPU time 13.22 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 214808 kb
Host smart-313daa1b-ac35-484d-b719-d7037e510398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288657157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1288657157
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3853389343
Short name T133
Test name
Test status
Simulation time 580604809 ps
CPU time 10.2 seconds
Started Jul 03 06:00:11 PM PDT 24
Finished Jul 03 06:00:22 PM PDT 24
Peak memory 222524 kb
Host smart-a43d4ed0-247f-4743-8c01-af94603c1c76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853389343 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3853389343
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_random.806731120
Short name T317
Test name
Test status
Simulation time 261362421 ps
CPU time 5.83 seconds
Started Jul 03 05:56:37 PM PDT 24
Finished Jul 03 05:56:43 PM PDT 24
Peak memory 207936 kb
Host smart-e21bfe30-a877-45f2-a5a4-a316a0cacfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806731120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.806731120
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.247023513
Short name T328
Test name
Test status
Simulation time 291516780 ps
CPU time 10.4 seconds
Started Jul 03 05:56:38 PM PDT 24
Finished Jul 03 05:56:49 PM PDT 24
Peak memory 214324 kb
Host smart-44db291b-935a-4040-b6f6-83e50260fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247023513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.247023513
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2747510454
Short name T120
Test name
Test status
Simulation time 94150934 ps
CPU time 2.27 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 216064 kb
Host smart-2f3e9aeb-d9eb-433a-8400-057fa3939d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747510454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2747510454
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1452337885
Short name T1006
Test name
Test status
Simulation time 775065569 ps
CPU time 5.49 seconds
Started Jul 03 05:19:59 PM PDT 24
Finished Jul 03 05:20:05 PM PDT 24
Peak memory 205620 kb
Host smart-c6a67d5d-e0d7-4377-a8ee-f7b9bfe1fb8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452337885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
452337885
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3700692172
Short name T385
Test name
Test status
Simulation time 450226304 ps
CPU time 8.61 seconds
Started Jul 03 05:19:59 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 205608 kb
Host smart-fce072a3-7a71-4e48-8cfb-a05def345ba3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700692172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
700692172
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1634554296
Short name T920
Test name
Test status
Simulation time 24655780 ps
CPU time 0.9 seconds
Started Jul 03 05:19:59 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 205536 kb
Host smart-ab426e08-8474-4e56-9e70-18390223669e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634554296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
634554296
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2492710242
Short name T158
Test name
Test status
Simulation time 236311128 ps
CPU time 1.6 seconds
Started Jul 03 05:20:01 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 213836 kb
Host smart-b6872a07-ab2f-408b-a0c0-4e4b8f308629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492710242 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2492710242
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.529271371
Short name T956
Test name
Test status
Simulation time 54665032 ps
CPU time 1.14 seconds
Started Jul 03 05:20:03 PM PDT 24
Finished Jul 03 05:20:05 PM PDT 24
Peak memory 205548 kb
Host smart-ef5e9e3f-e2bd-41a9-bb6e-65f5bc9b72fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529271371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.529271371
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1278572694
Short name T935
Test name
Test status
Simulation time 9724604 ps
CPU time 0.76 seconds
Started Jul 03 05:20:00 PM PDT 24
Finished Jul 03 05:20:01 PM PDT 24
Peak memory 205272 kb
Host smart-2d1f6386-e745-4d32-9517-440807cdeb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278572694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1278572694
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2955586302
Short name T1080
Test name
Test status
Simulation time 181167812 ps
CPU time 2.65 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 213704 kb
Host smart-4067a74a-a08b-45b7-893c-e27a016d47b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955586302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2955586302
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1400968400
Short name T1050
Test name
Test status
Simulation time 365939807 ps
CPU time 3.58 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 214084 kb
Host smart-07dcf3ec-38df-47c0-a777-233e8c26c3b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400968400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1400968400
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2449424671
Short name T987
Test name
Test status
Simulation time 123683213 ps
CPU time 2.1 seconds
Started Jul 03 05:20:01 PM PDT 24
Finished Jul 03 05:20:04 PM PDT 24
Peak memory 213764 kb
Host smart-d17bb412-5de6-4cdd-8959-7ab35f3ee70a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449424671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2449424671
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3280508364
Short name T166
Test name
Test status
Simulation time 381305873 ps
CPU time 2.5 seconds
Started Jul 03 05:20:00 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 213700 kb
Host smart-c662ebdf-65af-44f1-bef9-38bcb2bf1807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280508364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3280508364
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2834051102
Short name T1058
Test name
Test status
Simulation time 971044416 ps
CPU time 6.47 seconds
Started Jul 03 05:20:03 PM PDT 24
Finished Jul 03 05:20:10 PM PDT 24
Peak memory 205540 kb
Host smart-9f974773-94b1-4939-80d7-a42b594c644d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834051102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
834051102
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2913735516
Short name T1003
Test name
Test status
Simulation time 538749916 ps
CPU time 6.6 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 205536 kb
Host smart-0a7776ff-3df3-456d-b5dd-2098faa43a82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913735516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
913735516
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2622076461
Short name T957
Test name
Test status
Simulation time 16362895 ps
CPU time 1.02 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 205600 kb
Host smart-4e575d3a-b6e1-4843-a4a6-c349aad9738c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622076461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
622076461
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.341640148
Short name T964
Test name
Test status
Simulation time 178859062 ps
CPU time 1.04 seconds
Started Jul 03 05:20:07 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 205640 kb
Host smart-b969133d-a50f-430c-90e8-d1937b94e7be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341640148 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.341640148
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.417065499
Short name T1049
Test name
Test status
Simulation time 63769462 ps
CPU time 1.12 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:04 PM PDT 24
Peak memory 205604 kb
Host smart-f9ca12a0-ae18-4eca-b4e1-7e8254207aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417065499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.417065499
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2510818263
Short name T1040
Test name
Test status
Simulation time 8099654 ps
CPU time 0.82 seconds
Started Jul 03 05:20:01 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 205384 kb
Host smart-cbb48f67-36a6-4598-8089-455ae6c76fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510818263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2510818263
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2075879925
Short name T1061
Test name
Test status
Simulation time 535686308 ps
CPU time 2.08 seconds
Started Jul 03 05:20:01 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 205528 kb
Host smart-aa8de76f-7db9-47ee-be1d-e73a623e5730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075879925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2075879925
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2115661309
Short name T127
Test name
Test status
Simulation time 145155118 ps
CPU time 1.75 seconds
Started Jul 03 05:20:01 PM PDT 24
Finished Jul 03 05:20:03 PM PDT 24
Peak memory 214152 kb
Host smart-bfc42269-12e4-40f0-98a2-d3d3e30786eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115661309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2115661309
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3526594112
Short name T990
Test name
Test status
Simulation time 876420651 ps
CPU time 5.4 seconds
Started Jul 03 05:20:03 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 220076 kb
Host smart-93842c52-7e06-4428-af87-4111d24a3a1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526594112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3526594112
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4218003070
Short name T942
Test name
Test status
Simulation time 639697941 ps
CPU time 4.64 seconds
Started Jul 03 05:20:00 PM PDT 24
Finished Jul 03 05:20:05 PM PDT 24
Peak memory 213772 kb
Host smart-54fcf161-a7fc-4437-8463-776c858be871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218003070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4218003070
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.763916916
Short name T1067
Test name
Test status
Simulation time 52897899 ps
CPU time 2.55 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:05 PM PDT 24
Peak memory 205584 kb
Host smart-a2de8f72-4911-4351-832b-0793963d5a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763916916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
763916916
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1561852053
Short name T1064
Test name
Test status
Simulation time 191596479 ps
CPU time 1.63 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 213840 kb
Host smart-97794581-ec36-484f-97cc-f2515b46f2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561852053 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1561852053
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1365856541
Short name T984
Test name
Test status
Simulation time 447621708 ps
CPU time 1.7 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 205512 kb
Host smart-6276349f-f072-4211-b4cd-dcaeea41c843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365856541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1365856541
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1833537251
Short name T934
Test name
Test status
Simulation time 12205096 ps
CPU time 0.78 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 205324 kb
Host smart-9fd7d18c-3df3-4f36-8cfa-b9dd1779f351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833537251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1833537251
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3621426704
Short name T148
Test name
Test status
Simulation time 400449043 ps
CPU time 2.19 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205484 kb
Host smart-31f834e3-075a-4a84-84af-6f88e5f33c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621426704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3621426704
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2030831079
Short name T986
Test name
Test status
Simulation time 819856257 ps
CPU time 1.6 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 214060 kb
Host smart-0cddaa1e-d12f-43e7-b584-29ef05616243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030831079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2030831079
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1708049546
Short name T1059
Test name
Test status
Simulation time 154538057 ps
CPU time 4.4 seconds
Started Jul 03 05:20:15 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 214152 kb
Host smart-729a710d-103d-4715-a3de-16da14870962
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708049546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1708049546
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2428619222
Short name T997
Test name
Test status
Simulation time 48723352 ps
CPU time 3.4 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 216756 kb
Host smart-badd0583-01b5-48bf-ace3-39facbfc4300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428619222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2428619222
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3566787182
Short name T1001
Test name
Test status
Simulation time 54034293 ps
CPU time 3.16 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 205948 kb
Host smart-0406375f-7812-4139-94fc-43befbb78136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566787182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3566787182
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.656814206
Short name T1031
Test name
Test status
Simulation time 30359721 ps
CPU time 1.49 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 216404 kb
Host smart-c21775ac-b63b-4524-b19e-3c56a245754f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656814206 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.656814206
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1471314050
Short name T1054
Test name
Test status
Simulation time 44383982 ps
CPU time 1.03 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 205388 kb
Host smart-620bcb4e-23c6-4d82-b476-971fd6743333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471314050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1471314050
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.94165092
Short name T917
Test name
Test status
Simulation time 13020098 ps
CPU time 0.81 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 205340 kb
Host smart-43c1c831-1f21-41ee-a985-2a2f1c36129a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94165092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.94165092
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3129143885
Short name T147
Test name
Test status
Simulation time 184699034 ps
CPU time 1.54 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 205500 kb
Host smart-93ea6dad-7ff0-4248-9a75-9041eba6ec2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129143885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3129143885
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4032023504
Short name T1051
Test name
Test status
Simulation time 156929971 ps
CPU time 3.26 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213852 kb
Host smart-1e9a96ad-8e1a-40b4-9822-79e5c64c4b66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032023504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4032023504
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3006332209
Short name T1075
Test name
Test status
Simulation time 439362513 ps
CPU time 4.75 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 220532 kb
Host smart-c22fd046-fe52-4412-9511-edb07d0dd517
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006332209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3006332209
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1834064459
Short name T943
Test name
Test status
Simulation time 457134749 ps
CPU time 4.05 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213712 kb
Host smart-903e2bbe-2d88-4f90-8336-f1ff2a22075b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834064459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1834064459
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1639928593
Short name T924
Test name
Test status
Simulation time 59212860 ps
CPU time 3.13 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213756 kb
Host smart-398c3c57-8693-4a4f-bca5-7f0e95eff587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639928593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1639928593
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3896364513
Short name T982
Test name
Test status
Simulation time 260242459 ps
CPU time 1.92 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 205548 kb
Host smart-04d7a7f2-91ad-4247-94bb-2f9ac9c1904c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896364513 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3896364513
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3328649948
Short name T983
Test name
Test status
Simulation time 118126125 ps
CPU time 1.18 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205504 kb
Host smart-76bfae60-c5bd-4bb6-a4c4-6cceac2a41b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328649948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3328649948
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2276936528
Short name T1081
Test name
Test status
Simulation time 10082813 ps
CPU time 0.84 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205404 kb
Host smart-9bfdf0f5-7f51-458c-b3a9-5c6c7a9853f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276936528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2276936528
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1724234606
Short name T995
Test name
Test status
Simulation time 114843609 ps
CPU time 4.03 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 205432 kb
Host smart-fecf6f57-b778-4079-aa7b-d32c65e04e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724234606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1724234606
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3014446703
Short name T941
Test name
Test status
Simulation time 141537702 ps
CPU time 2.13 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 214100 kb
Host smart-9b7db293-e132-4c65-a4c9-5afc9c717d21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014446703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3014446703
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1488113122
Short name T977
Test name
Test status
Simulation time 872252581 ps
CPU time 8.46 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 213996 kb
Host smart-9f9e6852-5ab4-4e9a-9396-a73d5d8fca7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488113122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1488113122
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4061280308
Short name T1017
Test name
Test status
Simulation time 177983508 ps
CPU time 2.91 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 213704 kb
Host smart-0d00df2b-f15d-434d-b9f2-5f931f83769e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061280308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4061280308
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1452889989
Short name T1074
Test name
Test status
Simulation time 24868293 ps
CPU time 1.33 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 213876 kb
Host smart-ad1c0aee-8c07-49cf-9cc4-b25b9888caaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452889989 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1452889989
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3526219930
Short name T1057
Test name
Test status
Simulation time 9884240 ps
CPU time 1.06 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 205528 kb
Host smart-69b0785c-ff87-4ad0-b964-3fa89a5447d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526219930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3526219930
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.837740144
Short name T1045
Test name
Test status
Simulation time 9951262 ps
CPU time 0.71 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 205364 kb
Host smart-ea667714-d7cb-45b5-a2c5-053a52aa0276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837740144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.837740144
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1933955917
Short name T151
Test name
Test status
Simulation time 147731856 ps
CPU time 2.05 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205660 kb
Host smart-092e6219-b718-4fca-a216-01e851fbd277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933955917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1933955917
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2136598082
Short name T980
Test name
Test status
Simulation time 107726042 ps
CPU time 3.82 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 213984 kb
Host smart-7d273d49-d72c-4bbb-9198-019f199da059
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136598082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2136598082
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3767446642
Short name T123
Test name
Test status
Simulation time 517458567 ps
CPU time 6.6 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 214144 kb
Host smart-fafb1d07-1aea-4660-a813-5b9ba2258a88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767446642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3767446642
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3685528895
Short name T1078
Test name
Test status
Simulation time 58609504 ps
CPU time 2.11 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 215944 kb
Host smart-fefad6f7-3b7b-4609-88d8-2160b0d26f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685528895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3685528895
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4009117137
Short name T157
Test name
Test status
Simulation time 400872927 ps
CPU time 3.28 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 213840 kb
Host smart-11386001-0f4c-4bda-a087-30df496962a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009117137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4009117137
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.43035130
Short name T1038
Test name
Test status
Simulation time 63556045 ps
CPU time 1.18 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205572 kb
Host smart-4b219cbc-e495-4199-9b21-2fd056f06ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43035130 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.43035130
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2608832399
Short name T1060
Test name
Test status
Simulation time 23117001 ps
CPU time 1.13 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205568 kb
Host smart-3f692a1d-7484-425c-8a69-68188d34601a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608832399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2608832399
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1062077187
Short name T1025
Test name
Test status
Simulation time 8467224 ps
CPU time 0.77 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 204908 kb
Host smart-2deab8ee-2b64-4451-a18a-533f1bd2220c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062077187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1062077187
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1098695731
Short name T1055
Test name
Test status
Simulation time 571235416 ps
CPU time 3.01 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205536 kb
Host smart-cd82e10c-2a10-4ce4-983b-9ddfd056d514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098695731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1098695731
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3412632652
Short name T972
Test name
Test status
Simulation time 204156578 ps
CPU time 7.19 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 220152 kb
Host smart-c330d688-524c-45e4-891d-c02c1df9c941
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412632652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3412632652
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1606837302
Short name T1047
Test name
Test status
Simulation time 120321702 ps
CPU time 2.74 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 213716 kb
Host smart-628c1b7c-36d8-4bc7-bd95-deff5f21eade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606837302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1606837302
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2536767774
Short name T170
Test name
Test status
Simulation time 786801098 ps
CPU time 6.33 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 216160 kb
Host smart-f2c8ffc1-4d03-4892-890b-75bb614520d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536767774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2536767774
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.151426994
Short name T918
Test name
Test status
Simulation time 23965813 ps
CPU time 1.42 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 213744 kb
Host smart-0a745d79-d2bf-4557-8b36-e26a89ecb914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151426994 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.151426994
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.758716930
Short name T950
Test name
Test status
Simulation time 12814297 ps
CPU time 1.02 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205528 kb
Host smart-a8040b39-af62-41b6-a141-701aeca4fe76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758716930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.758716930
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1704665937
Short name T948
Test name
Test status
Simulation time 35694334 ps
CPU time 0.8 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205392 kb
Host smart-0458a24f-f425-40f7-b455-8b6b1487181c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704665937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1704665937
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1636635166
Short name T1070
Test name
Test status
Simulation time 460997448 ps
CPU time 1.73 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 205588 kb
Host smart-1f0e32b3-4942-4f1b-ab33-bfe812642051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636635166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1636635166
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1904746142
Short name T932
Test name
Test status
Simulation time 511731501 ps
CPU time 1.97 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 214112 kb
Host smart-ab9837f6-6522-437a-b2f6-e6531dff47a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904746142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1904746142
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1790650393
Short name T1046
Test name
Test status
Simulation time 647841954 ps
CPU time 8.32 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 220108 kb
Host smart-91052a66-51d1-4424-9747-266a4cb7d42a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790650393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1790650393
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.961302803
Short name T952
Test name
Test status
Simulation time 120667790 ps
CPU time 3.77 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213780 kb
Host smart-6a7fabbe-d4b9-4f26-9215-812aa4ab88e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961302803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.961302803
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2758688161
Short name T923
Test name
Test status
Simulation time 58254791 ps
CPU time 1.61 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213912 kb
Host smart-77953ec6-ae86-4f81-8323-9966b54c0ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758688161 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2758688161
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3788616721
Short name T960
Test name
Test status
Simulation time 33598043 ps
CPU time 1.17 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205048 kb
Host smart-17981560-392c-423c-a104-6bc3f7044eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788616721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3788616721
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3256539347
Short name T1077
Test name
Test status
Simulation time 43542884 ps
CPU time 0.72 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205260 kb
Host smart-0b8c23d9-b70a-416a-897d-a1c9770f2b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256539347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3256539347
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3998718994
Short name T1026
Test name
Test status
Simulation time 63582399 ps
CPU time 1.98 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205560 kb
Host smart-e4caac29-ddec-495c-b47a-46b29152a061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998718994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3998718994
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.941707187
Short name T969
Test name
Test status
Simulation time 119656792 ps
CPU time 2.21 seconds
Started Jul 03 05:20:16 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 214084 kb
Host smart-6a7c15a3-2b9a-4df0-9daa-59f01d292a69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941707187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.941707187
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3080237516
Short name T150
Test name
Test status
Simulation time 1504792857 ps
CPU time 7.98 seconds
Started Jul 03 05:20:15 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 214112 kb
Host smart-f61b8491-931b-43ab-9274-3736aeb9f1f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080237516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3080237516
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2893941205
Short name T962
Test name
Test status
Simulation time 213231020 ps
CPU time 3.32 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 213748 kb
Host smart-8fc00b42-17e0-4cf5-85c6-adfa6d4dc244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893941205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2893941205
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3905555073
Short name T1022
Test name
Test status
Simulation time 96360499 ps
CPU time 2.87 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213728 kb
Host smart-41c9f7d5-1cd2-4a5b-946e-f8ed0847e3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905555073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3905555073
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.92064136
Short name T184
Test name
Test status
Simulation time 31092998 ps
CPU time 1.23 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205688 kb
Host smart-14b2bea4-4d96-4206-9d38-50db90cf53dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92064136 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.92064136
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.280104351
Short name T1052
Test name
Test status
Simulation time 23902670 ps
CPU time 1.4 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205472 kb
Host smart-4d29413d-efef-46c0-be91-3ad41a17febe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280104351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.280104351
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.566332966
Short name T936
Test name
Test status
Simulation time 35501338 ps
CPU time 0.72 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205368 kb
Host smart-96909e14-d82f-4673-ba5c-002d94f2bbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566332966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.566332966
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1045333250
Short name T149
Test name
Test status
Simulation time 19781957 ps
CPU time 1.26 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205504 kb
Host smart-47a10150-f788-442f-bc3f-90a9231f4a12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045333250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1045333250
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4116786039
Short name T951
Test name
Test status
Simulation time 299833858 ps
CPU time 1.9 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 214084 kb
Host smart-25b2925d-bb48-4cbc-acd3-f41da17376e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116786039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4116786039
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3231922567
Short name T1076
Test name
Test status
Simulation time 551187933 ps
CPU time 8.29 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 219944 kb
Host smart-3c5c73ab-f1c0-4ff8-b431-cfe03b4e38f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231922567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3231922567
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3518776717
Short name T1068
Test name
Test status
Simulation time 81520156 ps
CPU time 2.83 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 215588 kb
Host smart-f2da856e-2c1c-4b3c-8356-d8e6a7747db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518776717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3518776717
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1491651737
Short name T921
Test name
Test status
Simulation time 554883464 ps
CPU time 1.85 seconds
Started Jul 03 05:20:19 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 213836 kb
Host smart-f08c7935-74f0-4dd1-8d3a-8505b316c050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491651737 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1491651737
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.543420625
Short name T939
Test name
Test status
Simulation time 366207520 ps
CPU time 1.5 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205508 kb
Host smart-5fab209a-9865-4c73-85b8-95d838bcd10a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543420625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.543420625
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3441677758
Short name T913
Test name
Test status
Simulation time 13316540 ps
CPU time 0.87 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 205360 kb
Host smart-5c2aabd2-5887-446a-8edb-8cd805288a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441677758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3441677758
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.661058333
Short name T1028
Test name
Test status
Simulation time 176545913 ps
CPU time 1.4 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 205516 kb
Host smart-223eeb77-bade-427c-a7dd-87ab4bbc35e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661058333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.661058333
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4118279728
Short name T991
Test name
Test status
Simulation time 94560235 ps
CPU time 1.69 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 214004 kb
Host smart-803fe5d2-9a4a-4aa2-9924-7eebb4b9e71e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118279728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4118279728
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.855419995
Short name T1010
Test name
Test status
Simulation time 176447000 ps
CPU time 4.82 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 214024 kb
Host smart-0e32833e-9594-4200-a4c9-e24f7c1f41eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855419995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.855419995
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.507935102
Short name T1063
Test name
Test status
Simulation time 54326018 ps
CPU time 2.15 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213732 kb
Host smart-68d146ed-b0bf-41e8-a7a7-db1dff30c143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507935102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.507935102
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1937287344
Short name T1013
Test name
Test status
Simulation time 104453456 ps
CPU time 3.38 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 213680 kb
Host smart-9e3efff0-9940-4040-b6cd-6f8814b46f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937287344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1937287344
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2649258198
Short name T944
Test name
Test status
Simulation time 29970605 ps
CPU time 1.23 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 205696 kb
Host smart-2006e7b8-4a25-46f1-826a-861b68cec9b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649258198 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2649258198
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3505296897
Short name T1009
Test name
Test status
Simulation time 116654421 ps
CPU time 0.95 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205368 kb
Host smart-c337409f-ee4f-496a-b936-4cbd011a25b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505296897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3505296897
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3337252403
Short name T931
Test name
Test status
Simulation time 13122645 ps
CPU time 0.91 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 205464 kb
Host smart-b9028dcc-9878-4666-a5ec-0333fb71e890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337252403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3337252403
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2120204063
Short name T989
Test name
Test status
Simulation time 87282009 ps
CPU time 1.53 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205616 kb
Host smart-4e262122-4569-4633-b431-ed359153dc93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120204063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2120204063
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3243998124
Short name T129
Test name
Test status
Simulation time 388041989 ps
CPU time 3.18 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 214020 kb
Host smart-122b19d1-5287-4edb-ac8a-d3ed3de43b00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243998124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3243998124
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2266357344
Short name T981
Test name
Test status
Simulation time 357008829 ps
CPU time 12.11 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:36 PM PDT 24
Peak memory 214056 kb
Host smart-1ceef371-14db-408a-8ec1-b5d2a4634fa6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266357344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2266357344
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3401038817
Short name T1004
Test name
Test status
Simulation time 376110498 ps
CPU time 3.12 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213720 kb
Host smart-15866b29-207a-4d84-85d0-2ae46c04b603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401038817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3401038817
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3506543830
Short name T1071
Test name
Test status
Simulation time 513578553 ps
CPU time 5.04 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205428 kb
Host smart-42e5241e-a4c7-445f-8326-00bb992dfde1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506543830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3506543830
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.967517764
Short name T1005
Test name
Test status
Simulation time 1103923612 ps
CPU time 9.46 seconds
Started Jul 03 05:20:07 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 205580 kb
Host smart-6917b927-92a0-4823-b950-0ca40e1149d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967517764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.967517764
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2943804122
Short name T919
Test name
Test status
Simulation time 3426786840 ps
CPU time 14.48 seconds
Started Jul 03 05:20:04 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 205644 kb
Host smart-82354468-67b8-400c-b577-08b756869d74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943804122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
943804122
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1582729642
Short name T1072
Test name
Test status
Simulation time 34066542 ps
CPU time 1.08 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:07 PM PDT 24
Peak memory 205528 kb
Host smart-4c525a52-0f0a-4600-92dd-0983214528ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582729642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
582729642
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1056019919
Short name T979
Test name
Test status
Simulation time 108370979 ps
CPU time 2.32 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 213860 kb
Host smart-0e521576-2fc0-4e45-9c0a-703125bba4dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056019919 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1056019919
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2811897598
Short name T954
Test name
Test status
Simulation time 16916625 ps
CPU time 0.98 seconds
Started Jul 03 05:20:06 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 205384 kb
Host smart-a8061b3d-e183-4c90-afe8-01180b42500a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811897598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2811897598
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2923590505
Short name T992
Test name
Test status
Simulation time 12752040 ps
CPU time 0.84 seconds
Started Jul 03 05:20:06 PM PDT 24
Finished Jul 03 05:20:07 PM PDT 24
Peak memory 205372 kb
Host smart-1cdb2309-a128-4fc5-80d9-6d9b4e0fcddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923590505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2923590505
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2802706324
Short name T1007
Test name
Test status
Simulation time 72725245 ps
CPU time 2.54 seconds
Started Jul 03 05:20:06 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 205540 kb
Host smart-227fbed6-cb20-40b0-be9d-93fb90acb7de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802706324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2802706324
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1377260749
Short name T959
Test name
Test status
Simulation time 488743338 ps
CPU time 1.77 seconds
Started Jul 03 05:20:03 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 213996 kb
Host smart-8d8d4c0f-70b3-4114-ade0-c861505ed6f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377260749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1377260749
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4279770058
Short name T970
Test name
Test status
Simulation time 356265110 ps
CPU time 4.18 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 214152 kb
Host smart-395adc41-91f6-4145-9e20-483cc82f096b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279770058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4279770058
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3560779676
Short name T945
Test name
Test status
Simulation time 791891359 ps
CPU time 3.65 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 213748 kb
Host smart-7e32e9be-4331-413e-899a-854eb1cf54cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560779676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3560779676
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2792277271
Short name T156
Test name
Test status
Simulation time 484717470 ps
CPU time 4.07 seconds
Started Jul 03 05:20:07 PM PDT 24
Finished Jul 03 05:20:11 PM PDT 24
Peak memory 205556 kb
Host smart-bd5aac6a-207a-483f-80f4-993ab36f3f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792277271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2792277271
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3647433841
Short name T1082
Test name
Test status
Simulation time 34955636 ps
CPU time 0.69 seconds
Started Jul 03 05:20:27 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 205416 kb
Host smart-8eb96143-a621-4b33-93d1-5dc3f23b6837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647433841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3647433841
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.99932553
Short name T929
Test name
Test status
Simulation time 12305516 ps
CPU time 0.75 seconds
Started Jul 03 05:20:27 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205332 kb
Host smart-ea6e3524-c02b-43b9-a1a7-8fbb4de9987b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99932553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.99932553
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2545465326
Short name T963
Test name
Test status
Simulation time 101779581 ps
CPU time 0.78 seconds
Started Jul 03 05:20:28 PM PDT 24
Finished Jul 03 05:20:30 PM PDT 24
Peak memory 205260 kb
Host smart-04a4f130-e31f-4a36-9d46-de5fc7883c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545465326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2545465326
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1529743821
Short name T912
Test name
Test status
Simulation time 8219832 ps
CPU time 0.73 seconds
Started Jul 03 05:20:27 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205260 kb
Host smart-65a68462-9458-48f3-99f8-0ba2523c5e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529743821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1529743821
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2395135943
Short name T1011
Test name
Test status
Simulation time 40771490 ps
CPU time 0.72 seconds
Started Jul 03 05:20:28 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 205300 kb
Host smart-e2641caf-98a6-4fde-8c42-8d5633e37d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395135943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2395135943
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.45375589
Short name T1016
Test name
Test status
Simulation time 13590018 ps
CPU time 0.85 seconds
Started Jul 03 05:20:23 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 205360 kb
Host smart-27550443-0456-422d-a28e-077e9770867a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45375589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.45375589
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1349563685
Short name T926
Test name
Test status
Simulation time 31363194 ps
CPU time 0.73 seconds
Started Jul 03 05:20:28 PM PDT 24
Finished Jul 03 05:20:30 PM PDT 24
Peak memory 205308 kb
Host smart-8b786f65-af29-4acd-9094-7608af571f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349563685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1349563685
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.854150911
Short name T978
Test name
Test status
Simulation time 43141489 ps
CPU time 0.71 seconds
Started Jul 03 05:20:35 PM PDT 24
Finished Jul 03 05:20:37 PM PDT 24
Peak memory 205388 kb
Host smart-c33d0ee7-7084-48e0-83ee-56a08a8c15fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854150911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.854150911
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3027674430
Short name T1018
Test name
Test status
Simulation time 23877995 ps
CPU time 0.68 seconds
Started Jul 03 05:20:26 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 205372 kb
Host smart-e692760d-2ca1-436b-a99b-f5d864db29fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027674430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3027674430
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2557152441
Short name T914
Test name
Test status
Simulation time 17920980 ps
CPU time 0.83 seconds
Started Jul 03 05:20:31 PM PDT 24
Finished Jul 03 05:20:32 PM PDT 24
Peak memory 205396 kb
Host smart-a27ac802-0b14-42fc-bc2b-e27878a7a7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557152441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2557152441
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.203095578
Short name T967
Test name
Test status
Simulation time 1696252370 ps
CPU time 10.86 seconds
Started Jul 03 05:20:04 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 205592 kb
Host smart-e648ba24-5268-465c-921e-c31b791c4c94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203095578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.203095578
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2034355294
Short name T1083
Test name
Test status
Simulation time 1618721595 ps
CPU time 6.15 seconds
Started Jul 03 05:20:03 PM PDT 24
Finished Jul 03 05:20:09 PM PDT 24
Peak memory 205560 kb
Host smart-ec56605e-9027-40eb-b557-9cf7a2f0ad31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034355294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
034355294
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.198127478
Short name T1002
Test name
Test status
Simulation time 38912273 ps
CPU time 1.23 seconds
Started Jul 03 05:20:02 PM PDT 24
Finished Jul 03 05:20:04 PM PDT 24
Peak memory 205604 kb
Host smart-9704c2a9-b644-4949-b5f7-88b3bb066ed6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198127478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.198127478
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1151340437
Short name T1041
Test name
Test status
Simulation time 30281803 ps
CPU time 2.15 seconds
Started Jul 03 05:20:10 PM PDT 24
Finished Jul 03 05:20:13 PM PDT 24
Peak memory 219092 kb
Host smart-33b3fcd9-9d50-4703-ae1b-2c1ca2db1abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151340437 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1151340437
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2928315876
Short name T1033
Test name
Test status
Simulation time 111412262 ps
CPU time 1.27 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:07 PM PDT 24
Peak memory 205488 kb
Host smart-93863a29-318a-4678-81d9-ca46915d4aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928315876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2928315876
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1263935235
Short name T1039
Test name
Test status
Simulation time 8930008 ps
CPU time 0.78 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 205352 kb
Host smart-cb81838f-7596-4a96-b6e3-fa4e89b7a0f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263935235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1263935235
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3409447702
Short name T973
Test name
Test status
Simulation time 332897287 ps
CPU time 1.52 seconds
Started Jul 03 05:20:04 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 205532 kb
Host smart-8e566ec1-8255-40b1-8c88-259e5def8112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409447702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3409447702
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1933504385
Short name T996
Test name
Test status
Simulation time 1525794985 ps
CPU time 2.03 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 213856 kb
Host smart-5a8df66a-4093-4b2b-a4e1-4c8d732b786f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933504385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1933504385
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3291464702
Short name T1073
Test name
Test status
Simulation time 1436598840 ps
CPU time 12.54 seconds
Started Jul 03 05:20:05 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 214336 kb
Host smart-ab0325e5-7cca-4092-834e-ed3a9c27b33a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291464702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3291464702
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1381814123
Short name T971
Test name
Test status
Simulation time 431634162 ps
CPU time 1.88 seconds
Started Jul 03 05:20:06 PM PDT 24
Finished Jul 03 05:20:08 PM PDT 24
Peak memory 221848 kb
Host smart-95704974-0bc1-4486-9890-b687abdfaac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381814123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1381814123
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3198799612
Short name T1000
Test name
Test status
Simulation time 256459974 ps
CPU time 0.93 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205380 kb
Host smart-3681e60e-21d2-4307-b7e7-ddbcdc745c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198799612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3198799612
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1699394886
Short name T975
Test name
Test status
Simulation time 29507207 ps
CPU time 0.92 seconds
Started Jul 03 05:20:26 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 205424 kb
Host smart-54bae9a7-b3a6-46ef-ad8a-68e21389727e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699394886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1699394886
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2010774258
Short name T994
Test name
Test status
Simulation time 46129701 ps
CPU time 0.71 seconds
Started Jul 03 05:20:25 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205576 kb
Host smart-a11a17b5-75db-439b-8211-992a2be6cc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010774258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2010774258
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3326517661
Short name T1065
Test name
Test status
Simulation time 37041311 ps
CPU time 0.8 seconds
Started Jul 03 05:20:25 PM PDT 24
Finished Jul 03 05:20:27 PM PDT 24
Peak memory 205400 kb
Host smart-9db4654e-fd3f-42b2-bbf6-55ed07379d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326517661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3326517661
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1807273932
Short name T1053
Test name
Test status
Simulation time 13606133 ps
CPU time 0.83 seconds
Started Jul 03 05:20:24 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 205660 kb
Host smart-d095bcd0-2f13-4f8a-844e-0595aecae926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807273932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1807273932
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2319202200
Short name T1034
Test name
Test status
Simulation time 10473559 ps
CPU time 0.84 seconds
Started Jul 03 05:20:26 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205388 kb
Host smart-36b716b4-cba4-444e-bb42-0129dc7003f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319202200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2319202200
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1920445225
Short name T938
Test name
Test status
Simulation time 14442485 ps
CPU time 0.8 seconds
Started Jul 03 05:20:36 PM PDT 24
Finished Jul 03 05:20:37 PM PDT 24
Peak memory 205312 kb
Host smart-f564fb75-a345-4346-aef8-f3fec63df88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920445225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1920445225
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1789063638
Short name T1043
Test name
Test status
Simulation time 15016558 ps
CPU time 0.84 seconds
Started Jul 03 05:20:22 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205156 kb
Host smart-75630849-ae6a-4e58-80fe-1cd2fc605d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789063638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1789063638
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2480299017
Short name T910
Test name
Test status
Simulation time 23241480 ps
CPU time 0.86 seconds
Started Jul 03 05:20:27 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205348 kb
Host smart-e7364875-2020-4f48-92a4-becb4a1ff32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480299017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2480299017
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3124808615
Short name T927
Test name
Test status
Simulation time 7005742 ps
CPU time 0.69 seconds
Started Jul 03 05:20:35 PM PDT 24
Finished Jul 03 05:20:37 PM PDT 24
Peak memory 205388 kb
Host smart-2994de87-a519-4303-b81d-119de3307835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124808615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3124808615
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1090569424
Short name T933
Test name
Test status
Simulation time 996041989 ps
CPU time 6.51 seconds
Started Jul 03 05:20:10 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 205604 kb
Host smart-03bad250-1884-4ed5-b2ce-2b6ed8a46d49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090569424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
090569424
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3346458173
Short name T1042
Test name
Test status
Simulation time 2674855563 ps
CPU time 16.91 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 205596 kb
Host smart-06e212f0-0f54-4a80-9163-1182305e290b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346458173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
346458173
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1232553514
Short name T961
Test name
Test status
Simulation time 70263060 ps
CPU time 0.93 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:11 PM PDT 24
Peak memory 205516 kb
Host smart-c062f90d-eb03-4811-ba37-a88e67ae88bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232553514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
232553514
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2718237634
Short name T1044
Test name
Test status
Simulation time 32667662 ps
CPU time 1.94 seconds
Started Jul 03 05:20:14 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 221988 kb
Host smart-a2a5aecd-2946-4f0e-bf16-2e5db070f071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718237634 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2718237634
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.973994957
Short name T946
Test name
Test status
Simulation time 36650429 ps
CPU time 0.97 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:10 PM PDT 24
Peak memory 205412 kb
Host smart-d613ceb6-be69-4899-9c7b-14dd5caef0a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973994957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.973994957
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4084024798
Short name T922
Test name
Test status
Simulation time 11402998 ps
CPU time 0.83 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:10 PM PDT 24
Peak memory 205296 kb
Host smart-924284d2-2b46-4fc3-b526-85b3ee20bda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084024798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4084024798
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2443761394
Short name T146
Test name
Test status
Simulation time 301815263 ps
CPU time 3.62 seconds
Started Jul 03 05:20:12 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 205500 kb
Host smart-2dc5672b-5174-4270-a7b0-9152598f7d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443761394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2443761394
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.532359039
Short name T1030
Test name
Test status
Simulation time 129776555 ps
CPU time 2.37 seconds
Started Jul 03 05:20:10 PM PDT 24
Finished Jul 03 05:20:13 PM PDT 24
Peak memory 218988 kb
Host smart-8cfbd2b0-eac6-4168-a661-fc0963f8fd6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532359039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.532359039
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1917532984
Short name T1029
Test name
Test status
Simulation time 460047337 ps
CPU time 7.63 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 220240 kb
Host smart-e1849666-f10b-4a9e-acc8-c04bf0af961b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917532984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1917532984
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.674206737
Short name T953
Test name
Test status
Simulation time 103499805 ps
CPU time 2.02 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 215932 kb
Host smart-2e5cd5b1-4033-459c-82ec-1f1bc53e8f85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674206737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.674206737
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3866907975
Short name T168
Test name
Test status
Simulation time 131520158 ps
CPU time 4.95 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 213684 kb
Host smart-ade5ddf7-2826-45a8-9e77-9fc775fea9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866907975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3866907975
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1937172732
Short name T916
Test name
Test status
Simulation time 55677978 ps
CPU time 0.82 seconds
Started Jul 03 05:20:35 PM PDT 24
Finished Jul 03 05:20:37 PM PDT 24
Peak memory 205388 kb
Host smart-5aca41bb-a0e9-4a3d-a360-e75b2fc5ff15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937172732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1937172732
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1515529199
Short name T928
Test name
Test status
Simulation time 53577192 ps
CPU time 0.73 seconds
Started Jul 03 05:20:25 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205388 kb
Host smart-d713a65a-4db4-4ad2-a948-a7f6ddb8935c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515529199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1515529199
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.36348548
Short name T940
Test name
Test status
Simulation time 21103230 ps
CPU time 0.74 seconds
Started Jul 03 05:20:50 PM PDT 24
Finished Jul 03 05:20:51 PM PDT 24
Peak memory 205244 kb
Host smart-d3b30f10-294e-462c-9d0f-a56234e6b37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36348548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.36348548
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2634449512
Short name T958
Test name
Test status
Simulation time 23301084 ps
CPU time 0.73 seconds
Started Jul 03 05:20:32 PM PDT 24
Finished Jul 03 05:20:34 PM PDT 24
Peak memory 205392 kb
Host smart-f6f8cbb8-8204-4a4b-8fae-57fa055c053f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634449512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2634449512
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.436466597
Short name T993
Test name
Test status
Simulation time 33628907 ps
CPU time 0.69 seconds
Started Jul 03 05:20:25 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 205384 kb
Host smart-76b2e00a-67c0-4e0f-bf32-1e5d7d7c8f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436466597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.436466597
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3309333835
Short name T1014
Test name
Test status
Simulation time 12029408 ps
CPU time 0.85 seconds
Started Jul 03 05:20:52 PM PDT 24
Finished Jul 03 05:20:53 PM PDT 24
Peak memory 205304 kb
Host smart-19e1624e-7585-483c-bbfa-e4a38683f1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309333835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3309333835
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3839406155
Short name T1056
Test name
Test status
Simulation time 38894352 ps
CPU time 0.81 seconds
Started Jul 03 05:20:27 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 205400 kb
Host smart-5026ca91-7709-42e2-9f1c-beda8be330bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839406155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3839406155
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3628566509
Short name T976
Test name
Test status
Simulation time 86854771 ps
CPU time 0.82 seconds
Started Jul 03 05:20:32 PM PDT 24
Finished Jul 03 05:20:34 PM PDT 24
Peak memory 205396 kb
Host smart-2cdd1b5e-1d72-4b9c-97fd-efac12b3e023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628566509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3628566509
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4174793387
Short name T1008
Test name
Test status
Simulation time 93984200 ps
CPU time 0.76 seconds
Started Jul 03 05:20:30 PM PDT 24
Finished Jul 03 05:20:31 PM PDT 24
Peak memory 205392 kb
Host smart-3fbf2053-bf2a-4a3b-99a4-a498b6aeaf09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174793387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4174793387
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1682088090
Short name T911
Test name
Test status
Simulation time 17243082 ps
CPU time 0.7 seconds
Started Jul 03 05:20:39 PM PDT 24
Finished Jul 03 05:20:40 PM PDT 24
Peak memory 205388 kb
Host smart-34ea39f9-15c9-4049-b635-e16fbb5fa74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682088090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1682088090
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1815014863
Short name T955
Test name
Test status
Simulation time 178364797 ps
CPU time 2.24 seconds
Started Jul 03 05:20:12 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 213748 kb
Host smart-38fc95f3-61ba-4657-bb2c-ee2f58957082
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815014863 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1815014863
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.396095522
Short name T1079
Test name
Test status
Simulation time 27730368 ps
CPU time 1.09 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:12 PM PDT 24
Peak memory 205548 kb
Host smart-26b3f235-0099-4deb-8e38-a5eedd45923c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396095522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.396095522
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3235416969
Short name T949
Test name
Test status
Simulation time 16234907 ps
CPU time 0.85 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:12 PM PDT 24
Peak memory 205360 kb
Host smart-ede94d63-ffbf-492c-8f34-bb575a0cd6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235416969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3235416969
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.69028017
Short name T1062
Test name
Test status
Simulation time 535865286 ps
CPU time 2.43 seconds
Started Jul 03 05:20:10 PM PDT 24
Finished Jul 03 05:20:13 PM PDT 24
Peak memory 205612 kb
Host smart-30dfb703-da9f-4fff-9263-aa7a49f8d31a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69028017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same
_csr_outstanding.69028017
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1946331538
Short name T998
Test name
Test status
Simulation time 576686603 ps
CPU time 2.49 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:14 PM PDT 24
Peak memory 214104 kb
Host smart-3f792f0c-933f-4563-b682-5d67c6a9048b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946331538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1946331538
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.40932425
Short name T1020
Test name
Test status
Simulation time 345127453 ps
CPU time 4.58 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 220140 kb
Host smart-760eee18-05da-46b8-8a0c-f99b98a644cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_shadow_reg_errors_with_csr_rw.40932425
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2906695896
Short name T1032
Test name
Test status
Simulation time 100388218 ps
CPU time 1.91 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 213768 kb
Host smart-cbe30a61-088c-409f-8c88-2f843912a438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906695896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2906695896
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3917851128
Short name T925
Test name
Test status
Simulation time 430088206 ps
CPU time 5.08 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 213848 kb
Host smart-f2cfe5ac-3cfc-481d-9aee-cd2d9d54c596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917851128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3917851128
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2936003519
Short name T1027
Test name
Test status
Simulation time 13891653 ps
CPU time 1.21 seconds
Started Jul 03 05:20:14 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 205664 kb
Host smart-faa2fc82-dfff-4f9f-bc8d-5b176bd620ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936003519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2936003519
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.94200706
Short name T1019
Test name
Test status
Simulation time 29560743 ps
CPU time 1.02 seconds
Started Jul 03 05:20:12 PM PDT 24
Finished Jul 03 05:20:14 PM PDT 24
Peak memory 205396 kb
Host smart-56242e94-0f3e-4ecd-a6ad-961da77c733c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94200706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.94200706
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3325560028
Short name T947
Test name
Test status
Simulation time 70713120 ps
CPU time 0.83 seconds
Started Jul 03 05:20:12 PM PDT 24
Finished Jul 03 05:20:13 PM PDT 24
Peak memory 205220 kb
Host smart-efdba14a-c255-437e-a919-a345157328b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325560028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3325560028
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2761909895
Short name T152
Test name
Test status
Simulation time 24285631 ps
CPU time 1.61 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 205504 kb
Host smart-3fdaa97f-f6a5-4a9e-8fcf-38909dc11151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761909895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2761909895
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1349909619
Short name T937
Test name
Test status
Simulation time 92381887 ps
CPU time 1.78 seconds
Started Jul 03 05:20:08 PM PDT 24
Finished Jul 03 05:20:10 PM PDT 24
Peak memory 214060 kb
Host smart-c8a3725d-26a4-4eaa-998b-eececaa342be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349909619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1349909619
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.600914569
Short name T124
Test name
Test status
Simulation time 229689731 ps
CPU time 7.61 seconds
Started Jul 03 05:20:09 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 214156 kb
Host smart-2c693c94-86c6-4472-877d-3358131890c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600914569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.600914569
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3592647111
Short name T966
Test name
Test status
Simulation time 51358233 ps
CPU time 3.33 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 213804 kb
Host smart-cfa15ca2-d9a2-4e90-bb28-5ef75fb0b00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592647111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3592647111
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.184991743
Short name T965
Test name
Test status
Simulation time 39629789 ps
CPU time 1.83 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 213704 kb
Host smart-124ceef4-adb4-4135-b34f-f878e62bd288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184991743 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.184991743
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3178034713
Short name T1069
Test name
Test status
Simulation time 33309443 ps
CPU time 0.94 seconds
Started Jul 03 05:20:11 PM PDT 24
Finished Jul 03 05:20:12 PM PDT 24
Peak memory 205348 kb
Host smart-5a89699c-19a9-4756-827e-7dccea53ce55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178034713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3178034713
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2300466254
Short name T915
Test name
Test status
Simulation time 11616535 ps
CPU time 0.74 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:14 PM PDT 24
Peak memory 205388 kb
Host smart-895c620b-5655-43bb-a84f-15f7089875c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300466254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2300466254
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3111212236
Short name T1036
Test name
Test status
Simulation time 222999141 ps
CPU time 4.1 seconds
Started Jul 03 05:20:15 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 205564 kb
Host smart-d523c7b4-4089-47dd-979d-df5ad1fd7b4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111212236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3111212236
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3410727270
Short name T126
Test name
Test status
Simulation time 418664590 ps
CPU time 2.28 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 214152 kb
Host smart-bed5f302-d60d-4d98-a30e-3df4708122d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410727270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3410727270
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2154216779
Short name T1023
Test name
Test status
Simulation time 382621266 ps
CPU time 4.78 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 214056 kb
Host smart-a88d142c-fe5a-4ed4-82f0-239eefc554d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154216779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2154216779
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3671966122
Short name T985
Test name
Test status
Simulation time 47392972 ps
CPU time 2.58 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213808 kb
Host smart-dd68aa8c-c780-4734-9a47-f4df85bf34ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671966122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3671966122
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.62768179
Short name T155
Test name
Test status
Simulation time 192782540 ps
CPU time 5.28 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 205908 kb
Host smart-3a412c3c-e362-4825-b63d-c568f3189e89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62768179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.62768179
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1374668589
Short name T1024
Test name
Test status
Simulation time 105944635 ps
CPU time 1.27 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 205616 kb
Host smart-aef444cb-557d-43c6-bc61-05efd38d4a05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374668589 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1374668589
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3587410043
Short name T968
Test name
Test status
Simulation time 41064563 ps
CPU time 0.89 seconds
Started Jul 03 05:20:15 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 205508 kb
Host smart-a4c3c537-5789-4866-8b13-ce1e4d6301d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587410043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3587410043
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.83200427
Short name T1012
Test name
Test status
Simulation time 38110400 ps
CPU time 0.8 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 205352 kb
Host smart-0f4462ac-b92f-4b9f-81ed-38dc056d41f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83200427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.83200427
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2178828446
Short name T1015
Test name
Test status
Simulation time 445959390 ps
CPU time 2.55 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:21 PM PDT 24
Peak memory 205560 kb
Host smart-e8589fa3-9bb5-4f69-89c0-a8e27ec3fcc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178828446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2178828446
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4166278173
Short name T999
Test name
Test status
Simulation time 540392901 ps
CPU time 3.18 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 214116 kb
Host smart-403322e5-a5c7-4a32-b647-7083804b1fc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166278173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4166278173
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.86562200
Short name T1084
Test name
Test status
Simulation time 1720260105 ps
CPU time 10.47 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 220524 kb
Host smart-36df8a56-833c-4665-964f-dc5564f1320a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86562200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.86562200
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1157449011
Short name T1066
Test name
Test status
Simulation time 1412181837 ps
CPU time 4.38 seconds
Started Jul 03 05:20:20 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 213512 kb
Host smart-090be04f-5f1e-49a2-a56a-737ad9f4bb86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157449011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1157449011
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.41648224
Short name T974
Test name
Test status
Simulation time 78529050 ps
CPU time 1.42 seconds
Started Jul 03 05:20:17 PM PDT 24
Finished Jul 03 05:20:19 PM PDT 24
Peak memory 213820 kb
Host smart-6b96a4f3-44dc-4e10-b946-ab3f66c73d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41648224 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.41648224
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3600894582
Short name T988
Test name
Test status
Simulation time 64833011 ps
CPU time 0.95 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 205516 kb
Host smart-03270dd6-6fde-4cfa-88bc-e0df6db35aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600894582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3600894582
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4116873938
Short name T930
Test name
Test status
Simulation time 68568691 ps
CPU time 0.85 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 205352 kb
Host smart-a85b5505-66ba-4e5d-8eab-7e045361827c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116873938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4116873938
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2278877662
Short name T1037
Test name
Test status
Simulation time 173967608 ps
CPU time 2.92 seconds
Started Jul 03 05:20:15 PM PDT 24
Finished Jul 03 05:20:18 PM PDT 24
Peak memory 205532 kb
Host smart-b0c8a740-3dab-4959-8081-db9df4b60e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278877662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2278877662
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2671329214
Short name T1035
Test name
Test status
Simulation time 122557838 ps
CPU time 3.47 seconds
Started Jul 03 05:20:13 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 214024 kb
Host smart-b787c5a2-f386-428e-bd4a-e0aead82a0be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671329214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2671329214
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3788148828
Short name T1021
Test name
Test status
Simulation time 727014938 ps
CPU time 14.07 seconds
Started Jul 03 05:20:21 PM PDT 24
Finished Jul 03 05:20:36 PM PDT 24
Peak memory 213992 kb
Host smart-fe49f11f-7966-4e4d-9dd6-5de07158c3f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788148828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3788148828
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.487145458
Short name T1048
Test name
Test status
Simulation time 162394791 ps
CPU time 5.26 seconds
Started Jul 03 05:20:18 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 213764 kb
Host smart-9fdb9e06-6a3c-49a6-98ed-348b4c8458ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487145458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.487145458
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2109513509
Short name T847
Test name
Test status
Simulation time 12657154 ps
CPU time 0.91 seconds
Started Jul 03 05:56:05 PM PDT 24
Finished Jul 03 05:56:06 PM PDT 24
Peak memory 206156 kb
Host smart-abd61222-927a-4c63-9238-1d40ab280221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109513509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2109513509
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1674287153
Short name T39
Test name
Test status
Simulation time 95785670 ps
CPU time 3.62 seconds
Started Jul 03 05:56:07 PM PDT 24
Finished Jul 03 05:56:11 PM PDT 24
Peak memory 218436 kb
Host smart-ce878a16-13d5-48b2-91d3-fea16d56a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674287153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1674287153
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2355776304
Short name T411
Test name
Test status
Simulation time 185860141 ps
CPU time 2.26 seconds
Started Jul 03 05:56:04 PM PDT 24
Finished Jul 03 05:56:07 PM PDT 24
Peak memory 210116 kb
Host smart-92646e42-cf42-4259-8b7d-494b1435bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355776304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2355776304
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.87732513
Short name T865
Test name
Test status
Simulation time 789628558 ps
CPU time 3.53 seconds
Started Jul 03 05:56:06 PM PDT 24
Finished Jul 03 05:56:10 PM PDT 24
Peak memory 214316 kb
Host smart-e6e05437-35f2-482c-bcf5-c32b9bc7ade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87732513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.87732513
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.157602632
Short name T323
Test name
Test status
Simulation time 713134337 ps
CPU time 2.64 seconds
Started Jul 03 05:56:08 PM PDT 24
Finished Jul 03 05:56:11 PM PDT 24
Peak memory 214300 kb
Host smart-82d3347c-1fab-41d5-a68e-3af853f8c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157602632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.157602632
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.85222940
Short name T659
Test name
Test status
Simulation time 71634623 ps
CPU time 3.84 seconds
Started Jul 03 05:56:03 PM PDT 24
Finished Jul 03 05:56:07 PM PDT 24
Peak memory 214144 kb
Host smart-f2c69e1a-922c-45cd-80b0-db423edcbbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85222940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.85222940
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2170442838
Short name T881
Test name
Test status
Simulation time 34005881 ps
CPU time 2.1 seconds
Started Jul 03 05:56:06 PM PDT 24
Finished Jul 03 05:56:09 PM PDT 24
Peak memory 206868 kb
Host smart-b77880bb-c0b2-4ddf-97a8-1c0f43e27950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170442838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2170442838
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.965522336
Short name T848
Test name
Test status
Simulation time 236890007 ps
CPU time 4.99 seconds
Started Jul 03 05:56:03 PM PDT 24
Finished Jul 03 05:56:08 PM PDT 24
Peak memory 208800 kb
Host smart-322feabb-d085-4451-a9ec-dcd9a5e2817f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965522336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.965522336
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2533298820
Short name T210
Test name
Test status
Simulation time 724976160 ps
CPU time 21.81 seconds
Started Jul 03 05:56:04 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 208140 kb
Host smart-3dd6a9ea-5a30-46c0-a849-309984efd6c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533298820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2533298820
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2321234953
Short name T212
Test name
Test status
Simulation time 85363728 ps
CPU time 3.18 seconds
Started Jul 03 05:56:06 PM PDT 24
Finished Jul 03 05:56:09 PM PDT 24
Peak memory 206900 kb
Host smart-882d6b7a-2344-4aca-9d3a-15577e9d2d20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321234953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2321234953
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1264644983
Short name T668
Test name
Test status
Simulation time 168550775 ps
CPU time 3 seconds
Started Jul 03 05:56:09 PM PDT 24
Finished Jul 03 05:56:12 PM PDT 24
Peak memory 214280 kb
Host smart-d5bd702f-7e99-4c17-955b-ff17c2ae549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264644983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1264644983
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2419731481
Short name T492
Test name
Test status
Simulation time 267716147 ps
CPU time 4.86 seconds
Started Jul 03 05:56:02 PM PDT 24
Finished Jul 03 05:56:07 PM PDT 24
Peak memory 206804 kb
Host smart-fc8fb773-68d7-4272-8a20-4f8db12b0aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419731481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2419731481
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3238526010
Short name T70
Test name
Test status
Simulation time 2525500882 ps
CPU time 21.42 seconds
Started Jul 03 05:56:05 PM PDT 24
Finished Jul 03 05:56:27 PM PDT 24
Peak memory 221548 kb
Host smart-f6a7f491-cff3-4109-9329-d8a1177a9519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238526010 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3238526010
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1855843496
Short name T315
Test name
Test status
Simulation time 540054862 ps
CPU time 10.99 seconds
Started Jul 03 05:56:07 PM PDT 24
Finished Jul 03 05:56:18 PM PDT 24
Peak memory 214424 kb
Host smart-ae3c9642-a489-4a72-b054-1160a52a95f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855843496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1855843496
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2148168500
Short name T35
Test name
Test status
Simulation time 198143938 ps
CPU time 3.68 seconds
Started Jul 03 05:56:09 PM PDT 24
Finished Jul 03 05:56:13 PM PDT 24
Peak memory 209916 kb
Host smart-008fd8c4-85e2-40bd-b946-e3a76abe97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148168500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2148168500
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3940284025
Short name T842
Test name
Test status
Simulation time 16265927 ps
CPU time 0.77 seconds
Started Jul 03 05:56:16 PM PDT 24
Finished Jul 03 05:56:17 PM PDT 24
Peak memory 206000 kb
Host smart-4f3b163b-3f79-4406-9c58-26dc04bb71ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940284025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3940284025
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1176916366
Short name T20
Test name
Test status
Simulation time 60735311 ps
CPU time 3.11 seconds
Started Jul 03 05:56:12 PM PDT 24
Finished Jul 03 05:56:16 PM PDT 24
Peak memory 214760 kb
Host smart-4e82af57-1b72-4a6d-bda4-c6ea75c0f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176916366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1176916366
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3967944099
Short name T898
Test name
Test status
Simulation time 43375731 ps
CPU time 2.26 seconds
Started Jul 03 05:56:08 PM PDT 24
Finished Jul 03 05:56:10 PM PDT 24
Peak memory 214344 kb
Host smart-5faf3435-d90f-4707-aed5-a22d4645f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967944099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3967944099
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3054610253
Short name T246
Test name
Test status
Simulation time 114679607 ps
CPU time 5.24 seconds
Started Jul 03 05:56:11 PM PDT 24
Finished Jul 03 05:56:17 PM PDT 24
Peak memory 214372 kb
Host smart-ac26443b-8811-46f4-b854-fc6728808c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054610253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3054610253
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.845032224
Short name T59
Test name
Test status
Simulation time 481962720 ps
CPU time 4.21 seconds
Started Jul 03 05:56:13 PM PDT 24
Finished Jul 03 05:56:18 PM PDT 24
Peak memory 219636 kb
Host smart-bc8e02d5-54ec-4f67-b2cd-9a8c551dc88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845032224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.845032224
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3156243258
Short name T117
Test name
Test status
Simulation time 87926983 ps
CPU time 2.27 seconds
Started Jul 03 05:56:11 PM PDT 24
Finished Jul 03 05:56:14 PM PDT 24
Peak memory 206156 kb
Host smart-301b2747-1ad2-4b33-b6a7-03866fc66180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156243258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3156243258
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2600877726
Short name T536
Test name
Test status
Simulation time 1481021252 ps
CPU time 15.05 seconds
Started Jul 03 05:56:11 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 214312 kb
Host smart-31374411-9dc6-4bae-886d-0c9b0bab9657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600877726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2600877726
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.423726383
Short name T44
Test name
Test status
Simulation time 1490364422 ps
CPU time 11.85 seconds
Started Jul 03 05:56:14 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 234136 kb
Host smart-9853382b-1767-4a73-ade5-493644907a55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423726383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.423726383
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3778496540
Short name T653
Test name
Test status
Simulation time 157807931 ps
CPU time 3.2 seconds
Started Jul 03 05:56:07 PM PDT 24
Finished Jul 03 05:56:11 PM PDT 24
Peak memory 206896 kb
Host smart-5e275f93-e3d1-48ed-9a8b-0761e63e8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778496540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3778496540
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2568207215
Short name T11
Test name
Test status
Simulation time 228455613 ps
CPU time 5.07 seconds
Started Jul 03 05:56:10 PM PDT 24
Finished Jul 03 05:56:15 PM PDT 24
Peak memory 208512 kb
Host smart-7fb2829b-2092-4cee-8b8f-19d879334f7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568207215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2568207215
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1944970608
Short name T264
Test name
Test status
Simulation time 429091018 ps
CPU time 5.34 seconds
Started Jul 03 05:56:08 PM PDT 24
Finished Jul 03 05:56:13 PM PDT 24
Peak memory 208776 kb
Host smart-b01cf28f-0e0f-42d3-8032-567274efede0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944970608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1944970608
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1002078342
Short name T572
Test name
Test status
Simulation time 97102295 ps
CPU time 3.22 seconds
Started Jul 03 05:56:15 PM PDT 24
Finished Jul 03 05:56:18 PM PDT 24
Peak memory 210064 kb
Host smart-ec0803b9-e4cc-49b1-969f-d47e24632c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002078342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1002078342
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1620868314
Short name T736
Test name
Test status
Simulation time 503926986 ps
CPU time 14.25 seconds
Started Jul 03 05:56:05 PM PDT 24
Finished Jul 03 05:56:19 PM PDT 24
Peak memory 208288 kb
Host smart-366e7386-66e9-4467-b11f-8a9a59e05b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620868314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1620868314
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1185159252
Short name T566
Test name
Test status
Simulation time 1404153506 ps
CPU time 6.81 seconds
Started Jul 03 05:56:12 PM PDT 24
Finished Jul 03 05:56:19 PM PDT 24
Peak memory 208300 kb
Host smart-96da12fd-1b48-470b-ae8f-f67b55a11036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185159252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1185159252
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2449561566
Short name T281
Test name
Test status
Simulation time 598688303 ps
CPU time 4.2 seconds
Started Jul 03 05:56:15 PM PDT 24
Finished Jul 03 05:56:20 PM PDT 24
Peak memory 214424 kb
Host smart-6720c4a3-4740-44d3-bf58-a6c3fb312746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449561566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2449561566
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.489219668
Short name T528
Test name
Test status
Simulation time 23553828 ps
CPU time 0.89 seconds
Started Jul 03 05:57:10 PM PDT 24
Finished Jul 03 05:57:11 PM PDT 24
Peak memory 206012 kb
Host smart-5a047715-22dd-4c40-bdef-1dff57f2e6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489219668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.489219668
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2531300185
Short name T381
Test name
Test status
Simulation time 74531916 ps
CPU time 4.44 seconds
Started Jul 03 05:57:13 PM PDT 24
Finished Jul 03 05:57:18 PM PDT 24
Peak memory 222508 kb
Host smart-3a8f2d10-70c2-4d96-903c-e8be6b410c5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531300185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2531300185
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.615768972
Short name T388
Test name
Test status
Simulation time 1003554141 ps
CPU time 5.61 seconds
Started Jul 03 05:57:07 PM PDT 24
Finished Jul 03 05:57:13 PM PDT 24
Peak memory 210612 kb
Host smart-431e3e6f-a01c-4ccf-b4d6-7af271568f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615768972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.615768972
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1684350737
Short name T782
Test name
Test status
Simulation time 143938846 ps
CPU time 2 seconds
Started Jul 03 05:57:08 PM PDT 24
Finished Jul 03 05:57:11 PM PDT 24
Peak memory 214336 kb
Host smart-9c38027d-7523-4600-b9b8-fa21bae98e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684350737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1684350737
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2385653839
Short name T849
Test name
Test status
Simulation time 85195947 ps
CPU time 4.05 seconds
Started Jul 03 05:57:09 PM PDT 24
Finished Jul 03 05:57:13 PM PDT 24
Peak memory 214296 kb
Host smart-fa8d9c2b-e6dc-4cb4-b1e1-3f5c752782a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385653839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2385653839
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.926645910
Short name T885
Test name
Test status
Simulation time 31631835 ps
CPU time 1.8 seconds
Started Jul 03 05:57:09 PM PDT 24
Finished Jul 03 05:57:11 PM PDT 24
Peak memory 219040 kb
Host smart-bfc3e8df-7b47-4de5-addc-e09b2ca528f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926645910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.926645910
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2365707831
Short name T199
Test name
Test status
Simulation time 50174454 ps
CPU time 3.45 seconds
Started Jul 03 05:57:08 PM PDT 24
Finished Jul 03 05:57:12 PM PDT 24
Peak memory 207244 kb
Host smart-39425c85-a36a-45ee-ada9-428f4fd278c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365707831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2365707831
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1761891265
Short name T692
Test name
Test status
Simulation time 1161621529 ps
CPU time 35.34 seconds
Started Jul 03 05:57:04 PM PDT 24
Finished Jul 03 05:57:40 PM PDT 24
Peak memory 208536 kb
Host smart-ee0b43d0-9bd7-42c8-aa73-1f4b176c6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761891265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1761891265
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3303535386
Short name T255
Test name
Test status
Simulation time 63808831 ps
CPU time 2.91 seconds
Started Jul 03 05:57:07 PM PDT 24
Finished Jul 03 05:57:10 PM PDT 24
Peak memory 208972 kb
Host smart-ab5a67bf-c47f-4fe5-a2f2-7a8574b3e4af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303535386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3303535386
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3565330036
Short name T864
Test name
Test status
Simulation time 75932635 ps
CPU time 2.9 seconds
Started Jul 03 05:57:07 PM PDT 24
Finished Jul 03 05:57:10 PM PDT 24
Peak memory 208632 kb
Host smart-971159fe-7bde-44c9-a095-2d4b88891dcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565330036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3565330036
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.976899203
Short name T785
Test name
Test status
Simulation time 29529661 ps
CPU time 2.32 seconds
Started Jul 03 05:57:06 PM PDT 24
Finished Jul 03 05:57:08 PM PDT 24
Peak memory 206836 kb
Host smart-615a3195-0b6e-422c-af8f-5006920c26a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976899203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.976899203
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.474965101
Short name T211
Test name
Test status
Simulation time 57730834 ps
CPU time 1.7 seconds
Started Jul 03 05:57:13 PM PDT 24
Finished Jul 03 05:57:15 PM PDT 24
Peak memory 215188 kb
Host smart-e5b3ee19-8f86-480f-99a5-273a646e6b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474965101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.474965101
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.489827225
Short name T816
Test name
Test status
Simulation time 1083714855 ps
CPU time 6.5 seconds
Started Jul 03 05:57:04 PM PDT 24
Finished Jul 03 05:57:11 PM PDT 24
Peak memory 208264 kb
Host smart-94a58f67-85d6-4c07-857a-b21dbaba9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489827225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.489827225
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3155095724
Short name T134
Test name
Test status
Simulation time 241848987 ps
CPU time 7.58 seconds
Started Jul 03 05:57:09 PM PDT 24
Finished Jul 03 05:57:17 PM PDT 24
Peak memory 219640 kb
Host smart-33fb942b-aef0-4450-ba03-a45c9a9a56d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155095724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3155095724
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4023154316
Short name T510
Test name
Test status
Simulation time 130523737 ps
CPU time 4.34 seconds
Started Jul 03 05:57:08 PM PDT 24
Finished Jul 03 05:57:13 PM PDT 24
Peak memory 218168 kb
Host smart-b6388022-db99-4608-b853-fc3b2f362899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023154316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4023154316
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3347493510
Short name T838
Test name
Test status
Simulation time 1512083017 ps
CPU time 11.99 seconds
Started Jul 03 05:57:11 PM PDT 24
Finished Jul 03 05:57:23 PM PDT 24
Peak memory 210360 kb
Host smart-7091514d-aabf-4b33-ada9-e1cce37a0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347493510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3347493510
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1472618320
Short name T497
Test name
Test status
Simulation time 14363128 ps
CPU time 0.81 seconds
Started Jul 03 05:57:17 PM PDT 24
Finished Jul 03 05:57:18 PM PDT 24
Peak memory 205988 kb
Host smart-cd778fae-2f45-4020-89e6-646a24c24d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472618320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1472618320
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.73419822
Short name T781
Test name
Test status
Simulation time 95585993 ps
CPU time 3.77 seconds
Started Jul 03 05:57:14 PM PDT 24
Finished Jul 03 05:57:18 PM PDT 24
Peak memory 210256 kb
Host smart-461bab03-18e7-4191-864a-f665f8dafee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73419822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.73419822
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3694156683
Short name T737
Test name
Test status
Simulation time 94312410 ps
CPU time 1.87 seconds
Started Jul 03 05:57:14 PM PDT 24
Finished Jul 03 05:57:16 PM PDT 24
Peak memory 207408 kb
Host smart-9546caa5-5181-44a3-81e6-8cc19b8dd2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694156683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3694156683
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.529508600
Short name T581
Test name
Test status
Simulation time 567758741 ps
CPU time 3.12 seconds
Started Jul 03 05:57:13 PM PDT 24
Finished Jul 03 05:57:16 PM PDT 24
Peak memory 222592 kb
Host smart-d725961f-75d4-48c5-b499-ab13fcd4982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529508600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.529508600
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3825507286
Short name T451
Test name
Test status
Simulation time 199570006 ps
CPU time 3.53 seconds
Started Jul 03 05:57:14 PM PDT 24
Finished Jul 03 05:57:18 PM PDT 24
Peak memory 214336 kb
Host smart-22bcd80b-b5d4-4420-a95e-bb649cab3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825507286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3825507286
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.775015791
Short name T786
Test name
Test status
Simulation time 356190671 ps
CPU time 3.57 seconds
Started Jul 03 05:57:13 PM PDT 24
Finished Jul 03 05:57:17 PM PDT 24
Peak memory 208688 kb
Host smart-70d59a9b-8c7c-4ee5-a307-52939631ce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775015791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.775015791
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3766318399
Short name T644
Test name
Test status
Simulation time 142270060 ps
CPU time 2.6 seconds
Started Jul 03 05:57:15 PM PDT 24
Finished Jul 03 05:57:18 PM PDT 24
Peak memory 208920 kb
Host smart-c4339e22-9e49-4aa6-820b-97b78f853d44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766318399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3766318399
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.235214865
Short name T352
Test name
Test status
Simulation time 204054330 ps
CPU time 8.56 seconds
Started Jul 03 05:57:15 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 208732 kb
Host smart-6dfdba0a-1d4f-4134-9213-a66f0c3b3171
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235214865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.235214865
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1921004251
Short name T427
Test name
Test status
Simulation time 53530022 ps
CPU time 3.02 seconds
Started Jul 03 05:57:12 PM PDT 24
Finished Jul 03 05:57:16 PM PDT 24
Peak memory 208672 kb
Host smart-738cebd9-8500-4833-aa6d-b7a802805923
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921004251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1921004251
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2962845332
Short name T12
Test name
Test status
Simulation time 53017237 ps
CPU time 2.18 seconds
Started Jul 03 05:57:19 PM PDT 24
Finished Jul 03 05:57:22 PM PDT 24
Peak memory 214332 kb
Host smart-7fd2b0b0-7cbb-4323-ade6-24f7d0834af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962845332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2962845332
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1955446699
Short name T734
Test name
Test status
Simulation time 407743886 ps
CPU time 2.62 seconds
Started Jul 03 05:57:16 PM PDT 24
Finished Jul 03 05:57:19 PM PDT 24
Peak memory 206828 kb
Host smart-f9b84f69-54cc-4072-b4a7-97c7fc395c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955446699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1955446699
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3651331807
Short name T679
Test name
Test status
Simulation time 693626741 ps
CPU time 25.02 seconds
Started Jul 03 05:57:19 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 215380 kb
Host smart-7583a8c6-3eaa-4f8c-ae73-52291853dcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651331807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3651331807
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1886135316
Short name T183
Test name
Test status
Simulation time 433902219 ps
CPU time 16.81 seconds
Started Jul 03 05:57:19 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 222564 kb
Host smart-d5fe43a7-09ba-4507-bc17-2a491bf2c211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886135316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1886135316
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2855032739
Short name T397
Test name
Test status
Simulation time 301745952 ps
CPU time 8.09 seconds
Started Jul 03 05:57:15 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 208148 kb
Host smart-e87f285a-4b92-4e07-90ca-0dd5358b46a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855032739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2855032739
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2977136696
Short name T179
Test name
Test status
Simulation time 195878298 ps
CPU time 3.47 seconds
Started Jul 03 05:57:19 PM PDT 24
Finished Jul 03 05:57:23 PM PDT 24
Peak memory 211008 kb
Host smart-336cace2-c93e-4a57-aebf-a80950bb3fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977136696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2977136696
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.30863703
Short name T574
Test name
Test status
Simulation time 44813686 ps
CPU time 0.71 seconds
Started Jul 03 05:57:25 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 205828 kb
Host smart-4e02dd2e-af82-45e2-bac8-2bab3de19000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30863703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.30863703
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1445843991
Short name T30
Test name
Test status
Simulation time 137072670 ps
CPU time 5.66 seconds
Started Jul 03 05:57:23 PM PDT 24
Finished Jul 03 05:57:29 PM PDT 24
Peak memory 218924 kb
Host smart-f13fa119-b44c-4e07-9674-883c5cfd6226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445843991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1445843991
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3462906713
Short name T499
Test name
Test status
Simulation time 313579243 ps
CPU time 4.33 seconds
Started Jul 03 05:57:21 PM PDT 24
Finished Jul 03 05:57:25 PM PDT 24
Peak memory 218404 kb
Host smart-b04e5abb-fabe-40a1-8207-03bf8a86af69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462906713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3462906713
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3432437772
Short name T107
Test name
Test status
Simulation time 918971888 ps
CPU time 18.77 seconds
Started Jul 03 05:57:26 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 219608 kb
Host smart-0af8d01e-28bf-49b4-b5a0-50147a45e109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432437772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3432437772
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.469928904
Short name T683
Test name
Test status
Simulation time 64595912 ps
CPU time 2.36 seconds
Started Jul 03 05:57:25 PM PDT 24
Finished Jul 03 05:57:27 PM PDT 24
Peak memory 219556 kb
Host smart-a1abd3c8-8294-430c-89b2-e21ad62a2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469928904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.469928904
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3245412781
Short name T834
Test name
Test status
Simulation time 90774170 ps
CPU time 1.79 seconds
Started Jul 03 05:57:24 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 206152 kb
Host smart-4f4488d7-4ced-43b0-9fdc-7dea6d6feb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245412781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3245412781
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1592461081
Short name T793
Test name
Test status
Simulation time 27041361 ps
CPU time 2.08 seconds
Started Jul 03 05:57:17 PM PDT 24
Finished Jul 03 05:57:19 PM PDT 24
Peak memory 208368 kb
Host smart-470c3fb0-da01-4698-95ec-84971accc5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592461081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1592461081
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1217142008
Short name T761
Test name
Test status
Simulation time 146901335 ps
CPU time 3.14 seconds
Started Jul 03 05:57:20 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 206964 kb
Host smart-a6037c72-b540-492e-bc68-8012d2640d42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217142008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1217142008
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1252046061
Short name T872
Test name
Test status
Simulation time 911110755 ps
CPU time 19.16 seconds
Started Jul 03 05:57:21 PM PDT 24
Finished Jul 03 05:57:41 PM PDT 24
Peak memory 208976 kb
Host smart-333e80c0-ed95-42b1-9e25-5a6fd3f32ab8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252046061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1252046061
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1122711678
Short name T295
Test name
Test status
Simulation time 3180563435 ps
CPU time 23.09 seconds
Started Jul 03 05:57:21 PM PDT 24
Finished Jul 03 05:57:44 PM PDT 24
Peak memory 209076 kb
Host smart-becafad2-5441-4c8f-9490-19f32ecfb6fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122711678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1122711678
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2807846914
Short name T198
Test name
Test status
Simulation time 1030307839 ps
CPU time 6.35 seconds
Started Jul 03 05:57:19 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 208832 kb
Host smart-5434f36e-1878-44c5-9622-dfc47e8f24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807846914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2807846914
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2642073728
Short name T81
Test name
Test status
Simulation time 422362070 ps
CPU time 17.02 seconds
Started Jul 03 05:57:25 PM PDT 24
Finished Jul 03 05:57:42 PM PDT 24
Peak memory 222632 kb
Host smart-cc4efb27-c4cf-445e-ad5b-8a8cd30743aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642073728 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2642073728
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2267813838
Short name T526
Test name
Test status
Simulation time 389543434 ps
CPU time 4.15 seconds
Started Jul 03 05:57:24 PM PDT 24
Finished Jul 03 05:57:28 PM PDT 24
Peak memory 207988 kb
Host smart-f0f38bbd-d7c7-4752-88ea-b4598846e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267813838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2267813838
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.612818416
Short name T628
Test name
Test status
Simulation time 75689364 ps
CPU time 2.07 seconds
Started Jul 03 05:57:25 PM PDT 24
Finished Jul 03 05:57:28 PM PDT 24
Peak memory 210204 kb
Host smart-5879d045-e20c-4c3f-8c9b-66b17a415979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612818416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.612818416
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1487836929
Short name T887
Test name
Test status
Simulation time 32650983 ps
CPU time 0.81 seconds
Started Jul 03 05:57:33 PM PDT 24
Finished Jul 03 05:57:34 PM PDT 24
Peak memory 205888 kb
Host smart-70abef80-fc90-43ed-914c-29ed946e26ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487836929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1487836929
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.238581669
Short name T379
Test name
Test status
Simulation time 639644587 ps
CPU time 8.54 seconds
Started Jul 03 05:57:30 PM PDT 24
Finished Jul 03 05:57:39 PM PDT 24
Peak memory 214288 kb
Host smart-31462efd-fb6b-445f-aa92-dc4f070dc55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238581669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.238581669
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3685862962
Short name T554
Test name
Test status
Simulation time 93489479 ps
CPU time 1.93 seconds
Started Jul 03 05:57:30 PM PDT 24
Finished Jul 03 05:57:32 PM PDT 24
Peak memory 214376 kb
Host smart-9773edf2-3786-4362-aef2-99e864433e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685862962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3685862962
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2949211412
Short name T823
Test name
Test status
Simulation time 55143410 ps
CPU time 2.43 seconds
Started Jul 03 05:57:30 PM PDT 24
Finished Jul 03 05:57:33 PM PDT 24
Peak memory 222012 kb
Host smart-ee291ce7-0393-42a2-8883-67e2d1acc89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949211412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2949211412
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.456520296
Short name T551
Test name
Test status
Simulation time 3379034702 ps
CPU time 21.48 seconds
Started Jul 03 05:57:29 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 208516 kb
Host smart-b9cf025e-6536-4d1a-8160-3dcef0ee3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456520296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.456520296
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1300027639
Short name T189
Test name
Test status
Simulation time 123602744 ps
CPU time 3.14 seconds
Started Jul 03 05:57:23 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 206984 kb
Host smart-70530e65-d181-44f2-9da9-965906049e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300027639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1300027639
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.94481532
Short name T93
Test name
Test status
Simulation time 30314559 ps
CPU time 2.19 seconds
Started Jul 03 05:57:26 PM PDT 24
Finished Jul 03 05:57:29 PM PDT 24
Peak memory 206976 kb
Host smart-9d94c078-3121-4a69-9aac-705be432e5ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94481532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.94481532
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4272977406
Short name T90
Test name
Test status
Simulation time 34475699 ps
CPU time 2.36 seconds
Started Jul 03 05:57:30 PM PDT 24
Finished Jul 03 05:57:32 PM PDT 24
Peak memory 207104 kb
Host smart-c45d5090-3a49-4e2b-bf52-4fb8769ae11b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272977406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4272977406
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2956719679
Short name T844
Test name
Test status
Simulation time 444120999 ps
CPU time 6.92 seconds
Started Jul 03 05:57:28 PM PDT 24
Finished Jul 03 05:57:36 PM PDT 24
Peak memory 208892 kb
Host smart-dbc61b0e-ade2-4cd4-85ef-ef04d2e3d411
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956719679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2956719679
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.498053633
Short name T655
Test name
Test status
Simulation time 140832342 ps
CPU time 4.05 seconds
Started Jul 03 05:57:27 PM PDT 24
Finished Jul 03 05:57:31 PM PDT 24
Peak memory 218296 kb
Host smart-3cb69ac3-0330-4346-9064-eac946b81fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498053633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.498053633
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2814254342
Short name T500
Test name
Test status
Simulation time 74424263 ps
CPU time 2.48 seconds
Started Jul 03 05:57:24 PM PDT 24
Finished Jul 03 05:57:27 PM PDT 24
Peak memory 208572 kb
Host smart-6661c38d-8174-4fa4-9176-b8b5df24cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814254342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2814254342
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2514658089
Short name T896
Test name
Test status
Simulation time 20286460339 ps
CPU time 125.14 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:59:38 PM PDT 24
Peak memory 218124 kb
Host smart-a8600a17-c5db-45c9-bad5-b6f24bc6900a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514658089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2514658089
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2699814875
Short name T437
Test name
Test status
Simulation time 204443653 ps
CPU time 7.94 seconds
Started Jul 03 05:57:28 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 209220 kb
Host smart-1a869108-b0dc-4c7e-bc64-a8615517da12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699814875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2699814875
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1862272188
Short name T609
Test name
Test status
Simulation time 36775117 ps
CPU time 1.78 seconds
Started Jul 03 05:57:28 PM PDT 24
Finished Jul 03 05:57:31 PM PDT 24
Peak memory 208436 kb
Host smart-b6c752a1-6290-41e8-be9c-79ca6a049501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862272188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1862272188
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.809216755
Short name T671
Test name
Test status
Simulation time 131210857 ps
CPU time 0.74 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 206184 kb
Host smart-c11f82de-a4b0-4e07-8793-2562f191b8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809216755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.809216755
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.109845382
Short name T633
Test name
Test status
Simulation time 50879465 ps
CPU time 2.56 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 217476 kb
Host smart-c40e916a-f5da-4d3a-8edd-62781587448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109845382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.109845382
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1110159378
Short name T779
Test name
Test status
Simulation time 47301000 ps
CPU time 2.88 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 214412 kb
Host smart-6a9b046a-a089-4f4f-a97c-951f2630534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110159378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1110159378
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.525354446
Short name T901
Test name
Test status
Simulation time 111515899 ps
CPU time 3.03 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 214340 kb
Host smart-3e04198f-43bf-4d66-ba81-ff3687d50bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525354446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.525354446
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2529469011
Short name T607
Test name
Test status
Simulation time 196875711 ps
CPU time 3.68 seconds
Started Jul 03 05:57:31 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 208380 kb
Host smart-7a857329-31f6-4b2b-a556-1ec69229c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529469011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2529469011
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2814652894
Short name T410
Test name
Test status
Simulation time 133243067 ps
CPU time 5.37 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 214356 kb
Host smart-7cfc4b1c-e5b1-4027-8ede-65f1661ead68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814652894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2814652894
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.20109168
Short name T201
Test name
Test status
Simulation time 1378138592 ps
CPU time 35.18 seconds
Started Jul 03 05:57:29 PM PDT 24
Finished Jul 03 05:58:04 PM PDT 24
Peak memory 208824 kb
Host smart-a3960122-cf26-41a1-8d9b-5a1b73f0532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20109168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.20109168
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1107774581
Short name T560
Test name
Test status
Simulation time 962324003 ps
CPU time 29.23 seconds
Started Jul 03 05:57:33 PM PDT 24
Finished Jul 03 05:58:02 PM PDT 24
Peak memory 208512 kb
Host smart-4006f457-7673-4ee2-8c54-f6fa7a2658c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107774581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1107774581
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3274960637
Short name T444
Test name
Test status
Simulation time 257251070 ps
CPU time 3.24 seconds
Started Jul 03 05:57:31 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 206948 kb
Host smart-8b60a7f8-8834-40d8-a776-f46770d18aa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274960637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3274960637
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1910214936
Short name T771
Test name
Test status
Simulation time 657236218 ps
CPU time 3 seconds
Started Jul 03 05:57:32 PM PDT 24
Finished Jul 03 05:57:35 PM PDT 24
Peak memory 206956 kb
Host smart-9c21d9ad-0f08-468c-80c9-2d315c4ee91e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910214936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1910214936
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1077095341
Short name T369
Test name
Test status
Simulation time 1198597462 ps
CPU time 11.61 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:46 PM PDT 24
Peak memory 214228 kb
Host smart-b207162b-aa90-4f1a-b777-b93d0ec6b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077095341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1077095341
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1505562681
Short name T400
Test name
Test status
Simulation time 56797053 ps
CPU time 2.36 seconds
Started Jul 03 05:57:31 PM PDT 24
Finished Jul 03 05:57:33 PM PDT 24
Peak memory 206828 kb
Host smart-c1326a70-04e4-4783-bb85-c17d7774900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505562681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1505562681
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2820527747
Short name T77
Test name
Test status
Simulation time 3334391753 ps
CPU time 34.48 seconds
Started Jul 03 05:57:36 PM PDT 24
Finished Jul 03 05:58:11 PM PDT 24
Peak memory 222544 kb
Host smart-4f63a991-ef4b-43ef-9e50-b6e2b2d2e7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820527747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2820527747
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1296117257
Short name T889
Test name
Test status
Simulation time 570943780 ps
CPU time 6.33 seconds
Started Jul 03 05:57:31 PM PDT 24
Finished Jul 03 05:57:38 PM PDT 24
Peak memory 209240 kb
Host smart-f461428c-72f1-494e-b997-5e244c6b47d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296117257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1296117257
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3939882997
Short name T571
Test name
Test status
Simulation time 151249984 ps
CPU time 2.43 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:36 PM PDT 24
Peak memory 210260 kb
Host smart-5215331a-0280-49a1-8fef-be5cb564e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939882997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3939882997
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1437603272
Short name T742
Test name
Test status
Simulation time 23637401 ps
CPU time 0.77 seconds
Started Jul 03 05:57:37 PM PDT 24
Finished Jul 03 05:57:38 PM PDT 24
Peak memory 205988 kb
Host smart-c090d820-0656-4cdb-aa38-96ff17be0329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437603272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1437603272
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1557828292
Short name T907
Test name
Test status
Simulation time 300531181 ps
CPU time 3.47 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:38 PM PDT 24
Peak memory 214440 kb
Host smart-01abef2c-77bd-4eeb-bd40-21ea37079c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557828292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1557828292
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3384517023
Short name T874
Test name
Test status
Simulation time 69751107 ps
CPU time 2.37 seconds
Started Jul 03 05:57:39 PM PDT 24
Finished Jul 03 05:57:42 PM PDT 24
Peak memory 214300 kb
Host smart-9b694684-02e0-4e6d-a3c6-0849ea10010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384517023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3384517023
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.597762760
Short name T539
Test name
Test status
Simulation time 48604089 ps
CPU time 2.34 seconds
Started Jul 03 05:57:38 PM PDT 24
Finished Jul 03 05:57:41 PM PDT 24
Peak memory 214292 kb
Host smart-b760d65d-b2b6-45c1-93e5-a017f76d0640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597762760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.597762760
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.927916589
Short name T608
Test name
Test status
Simulation time 217611740 ps
CPU time 6.14 seconds
Started Jul 03 05:57:37 PM PDT 24
Finished Jul 03 05:57:44 PM PDT 24
Peak memory 209408 kb
Host smart-27417045-0df9-4bb5-a33b-acc98614bee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927916589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.927916589
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1416774972
Short name T193
Test name
Test status
Simulation time 96233042 ps
CPU time 4.82 seconds
Started Jul 03 05:57:36 PM PDT 24
Finished Jul 03 05:57:41 PM PDT 24
Peak memory 218184 kb
Host smart-f1cf45a3-938b-4b04-9a14-7f6561232e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416774972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1416774972
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1576398051
Short name T650
Test name
Test status
Simulation time 95093507 ps
CPU time 3.45 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:38 PM PDT 24
Peak memory 208436 kb
Host smart-65973b43-3d53-411a-8e14-b173968fce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576398051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1576398051
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1739108666
Short name T522
Test name
Test status
Simulation time 175188152 ps
CPU time 2.45 seconds
Started Jul 03 05:57:35 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 208876 kb
Host smart-b06b9001-2a41-43e8-83cd-80617b0de93f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739108666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1739108666
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.144288109
Short name T699
Test name
Test status
Simulation time 457140387 ps
CPU time 5.72 seconds
Started Jul 03 05:57:35 PM PDT 24
Finished Jul 03 05:57:41 PM PDT 24
Peak memory 208772 kb
Host smart-14f672b5-56d0-4895-a84d-3d8e8c030530
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144288109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.144288109
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3237205097
Short name T517
Test name
Test status
Simulation time 548577414 ps
CPU time 2.52 seconds
Started Jul 03 05:57:34 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 209148 kb
Host smart-a681d50f-eb36-4a56-b936-f7dddc9b7e8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237205097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3237205097
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1122106822
Short name T284
Test name
Test status
Simulation time 810146066 ps
CPU time 5.71 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:46 PM PDT 24
Peak memory 207296 kb
Host smart-022313d2-c743-47bd-9317-aec84b719832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122106822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1122106822
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1908158857
Short name T490
Test name
Test status
Simulation time 383276048 ps
CPU time 3.08 seconds
Started Jul 03 05:57:33 PM PDT 24
Finished Jul 03 05:57:37 PM PDT 24
Peak memory 208716 kb
Host smart-d61866b8-1995-4fbc-850a-5db4d40fa033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908158857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1908158857
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2228306425
Short name T794
Test name
Test status
Simulation time 163917704 ps
CPU time 0.93 seconds
Started Jul 03 05:57:38 PM PDT 24
Finished Jul 03 05:57:39 PM PDT 24
Peak memory 206152 kb
Host smart-ebaa325a-d8ea-447a-8a31-961a7d0fb2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228306425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2228306425
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3788781680
Short name T208
Test name
Test status
Simulation time 162422879 ps
CPU time 5.2 seconds
Started Jul 03 05:57:39 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 214372 kb
Host smart-a80cf3e1-a7da-4e8e-8597-4805028f9601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788781680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3788781680
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3578257619
Short name T494
Test name
Test status
Simulation time 154843797 ps
CPU time 2 seconds
Started Jul 03 05:57:37 PM PDT 24
Finished Jul 03 05:57:39 PM PDT 24
Peak memory 210008 kb
Host smart-fb8d22a1-3997-4aa0-bbe1-0b516d20ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578257619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3578257619
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.297477065
Short name T482
Test name
Test status
Simulation time 17304742 ps
CPU time 0.82 seconds
Started Jul 03 05:57:44 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 205976 kb
Host smart-cf51c298-0cdc-4fb2-84c4-253e4d95f22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297477065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.297477065
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3233619322
Short name T311
Test name
Test status
Simulation time 743302331 ps
CPU time 10.76 seconds
Started Jul 03 05:57:41 PM PDT 24
Finished Jul 03 05:57:52 PM PDT 24
Peak memory 215584 kb
Host smart-0c32d953-7062-4df6-a82b-e8f13ae8e28c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233619322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3233619322
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.161102505
Short name T852
Test name
Test status
Simulation time 169016459 ps
CPU time 5.15 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 222640 kb
Host smart-7f84cf4c-625d-4b69-9d5f-e1ad568efe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161102505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.161102505
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1714568629
Short name T289
Test name
Test status
Simulation time 119065129 ps
CPU time 1.67 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:42 PM PDT 24
Peak memory 207868 kb
Host smart-1cf2d1f8-85fe-4cf2-9fba-ff5e0746907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714568629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1714568629
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3432893271
Short name T106
Test name
Test status
Simulation time 318197737 ps
CPU time 4.13 seconds
Started Jul 03 05:57:42 PM PDT 24
Finished Jul 03 05:57:47 PM PDT 24
Peak memory 209524 kb
Host smart-376abf77-db28-47a1-a722-11b47328ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432893271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3432893271
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4207126453
Short name T54
Test name
Test status
Simulation time 43225638 ps
CPU time 2.11 seconds
Started Jul 03 05:57:41 PM PDT 24
Finished Jul 03 05:57:43 PM PDT 24
Peak memory 214300 kb
Host smart-6afb1877-49cb-493a-9806-8d0066b701ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207126453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4207126453
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.3565638630
Short name T213
Test name
Test status
Simulation time 513231606 ps
CPU time 8.74 seconds
Started Jul 03 05:57:41 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 208184 kb
Host smart-ee736742-e2c8-4614-8cd0-8580c6564bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565638630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3565638630
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2652622266
Short name T524
Test name
Test status
Simulation time 163328456 ps
CPU time 4.61 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 206860 kb
Host smart-481ee20b-02f2-4629-87cb-06669d6e0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652622266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2652622266
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3662281552
Short name T883
Test name
Test status
Simulation time 1407157239 ps
CPU time 4.21 seconds
Started Jul 03 05:57:39 PM PDT 24
Finished Jul 03 05:57:43 PM PDT 24
Peak memory 208812 kb
Host smart-0c994b3a-94dd-4adc-a911-94d2cf3e2ce7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662281552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3662281552
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2406928577
Short name T391
Test name
Test status
Simulation time 32301426 ps
CPU time 2.26 seconds
Started Jul 03 05:57:36 PM PDT 24
Finished Jul 03 05:57:39 PM PDT 24
Peak memory 206972 kb
Host smart-53ca6710-456f-4833-abe8-0738e6e27b67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406928577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2406928577
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3986265644
Short name T440
Test name
Test status
Simulation time 1955975201 ps
CPU time 12.27 seconds
Started Jul 03 05:57:38 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 208036 kb
Host smart-f7905831-72ca-4092-9dc7-dca29623ac77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986265644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3986265644
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4234580523
Short name T757
Test name
Test status
Simulation time 191913837 ps
CPU time 2.75 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:43 PM PDT 24
Peak memory 214356 kb
Host smart-c230a4ef-45bf-49e7-b6ff-d6c4d5621156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234580523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4234580523
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2689143707
Short name T588
Test name
Test status
Simulation time 302805776 ps
CPU time 2.55 seconds
Started Jul 03 05:57:37 PM PDT 24
Finished Jul 03 05:57:40 PM PDT 24
Peak memory 206784 kb
Host smart-e0e86300-3154-46f8-a076-19d9cf1aef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689143707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2689143707
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4090514841
Short name T56
Test name
Test status
Simulation time 1882119213 ps
CPU time 11.21 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:57 PM PDT 24
Peak memory 221716 kb
Host smart-737c6126-3fad-400e-875c-6f4336ccbaba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090514841 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4090514841
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.20924182
Short name T618
Test name
Test status
Simulation time 470217843 ps
CPU time 14.03 seconds
Started Jul 03 05:57:42 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 209360 kb
Host smart-b8cb3157-afa0-4856-84b7-2e53dfe85df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20924182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.20924182
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1852377736
Short name T384
Test name
Test status
Simulation time 26073388 ps
CPU time 1.48 seconds
Started Jul 03 05:57:40 PM PDT 24
Finished Jul 03 05:57:42 PM PDT 24
Peak memory 210056 kb
Host smart-4e52e852-fedb-4890-8903-c0619efa8706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852377736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1852377736
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3509302033
Short name T845
Test name
Test status
Simulation time 65487825 ps
CPU time 0.9 seconds
Started Jul 03 05:57:48 PM PDT 24
Finished Jul 03 05:57:49 PM PDT 24
Peak memory 205964 kb
Host smart-d4294ba1-1fc0-461f-8b67-17bc9673966e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509302033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3509302033
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1881426959
Short name T254
Test name
Test status
Simulation time 621267777 ps
CPU time 29.11 seconds
Started Jul 03 05:57:47 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 215624 kb
Host smart-58d019ee-cf7b-4e09-ae88-821ff9b81f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881426959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1881426959
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1555823673
Short name T29
Test name
Test status
Simulation time 421365623 ps
CPU time 10.58 seconds
Started Jul 03 05:57:47 PM PDT 24
Finished Jul 03 05:57:58 PM PDT 24
Peak memory 222776 kb
Host smart-e0fb3c3f-2707-4e20-9575-6c4ceb8750ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555823673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1555823673
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1489228893
Short name T71
Test name
Test status
Simulation time 90272989 ps
CPU time 2.28 seconds
Started Jul 03 05:57:44 PM PDT 24
Finished Jul 03 05:57:46 PM PDT 24
Peak memory 207816 kb
Host smart-e0d73c0b-7c0b-4a44-b86b-8e1d200f456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489228893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1489228893
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3376814001
Short name T415
Test name
Test status
Simulation time 155737831 ps
CPU time 3.89 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 214324 kb
Host smart-d6874bef-f25d-4091-af92-38adef98fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376814001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3376814001
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.704363624
Short name T535
Test name
Test status
Simulation time 158994122 ps
CPU time 2.49 seconds
Started Jul 03 05:57:44 PM PDT 24
Finished Jul 03 05:57:46 PM PDT 24
Peak memory 222380 kb
Host smart-970116ee-1eb0-4390-9683-101f7860fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704363624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.704363624
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2406413249
Short name T417
Test name
Test status
Simulation time 238568787 ps
CPU time 3.55 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 208584 kb
Host smart-2914de34-017e-4881-99ab-2a3a4912b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406413249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2406413249
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3272600033
Short name T409
Test name
Test status
Simulation time 187999522 ps
CPU time 3.31 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 208016 kb
Host smart-b8b45fd1-cd0c-477c-a346-5ea6a4de0a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272600033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3272600033
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2798535020
Short name T350
Test name
Test status
Simulation time 2077907091 ps
CPU time 34.7 seconds
Started Jul 03 05:57:43 PM PDT 24
Finished Jul 03 05:58:18 PM PDT 24
Peak memory 208292 kb
Host smart-8843ed5c-2672-49df-a6b8-ce4920a31e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798535020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2798535020
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1218109233
Short name T749
Test name
Test status
Simulation time 201396250 ps
CPU time 2.38 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:48 PM PDT 24
Peak memory 207012 kb
Host smart-0d7de2fe-4fa7-4659-ad51-370f8c612200
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218109233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1218109233
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1914837330
Short name T669
Test name
Test status
Simulation time 356056456 ps
CPU time 8.24 seconds
Started Jul 03 05:57:45 PM PDT 24
Finished Jul 03 05:57:53 PM PDT 24
Peak memory 206940 kb
Host smart-73bfa70a-154d-4dc9-aa3f-c9cb95f514c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914837330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1914837330
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1997598240
Short name T840
Test name
Test status
Simulation time 582936364 ps
CPU time 5.86 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:53 PM PDT 24
Peak memory 208564 kb
Host smart-abf5ea51-47c8-4111-83b5-1f3999456ee7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997598240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1997598240
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2800274067
Short name T463
Test name
Test status
Simulation time 45850945 ps
CPU time 1.88 seconds
Started Jul 03 05:57:46 PM PDT 24
Finished Jul 03 05:57:49 PM PDT 24
Peak memory 208944 kb
Host smart-8ae2b745-002a-4e40-8ba9-d79d064f0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800274067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2800274067
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.193465858
Short name T903
Test name
Test status
Simulation time 22800789 ps
CPU time 1.67 seconds
Started Jul 03 05:57:43 PM PDT 24
Finished Jul 03 05:57:45 PM PDT 24
Peak memory 206728 kb
Host smart-1817f07d-d928-48eb-8f10-77bf0dd956ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193465858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.193465858
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.724256562
Short name T818
Test name
Test status
Simulation time 1054350285 ps
CPU time 9.51 seconds
Started Jul 03 05:57:43 PM PDT 24
Finished Jul 03 05:57:53 PM PDT 24
Peak memory 214328 kb
Host smart-ffcd24f1-c8cb-4ac7-83f8-4d57f32f9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724256562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.724256562
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3373897498
Short name T452
Test name
Test status
Simulation time 87560971 ps
CPU time 1.86 seconds
Started Jul 03 05:57:47 PM PDT 24
Finished Jul 03 05:57:49 PM PDT 24
Peak memory 210364 kb
Host smart-cce1d4be-c8cc-4ef1-9676-16938ff9b843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373897498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3373897498
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4212582393
Short name T543
Test name
Test status
Simulation time 59304814 ps
CPU time 0.91 seconds
Started Jul 03 05:57:56 PM PDT 24
Finished Jul 03 05:57:57 PM PDT 24
Peak memory 205828 kb
Host smart-2cb91096-ac1f-4cf6-bb30-9a100d3ba8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212582393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4212582393
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3364851729
Short name T145
Test name
Test status
Simulation time 136397616 ps
CPU time 3.01 seconds
Started Jul 03 05:57:53 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 215184 kb
Host smart-1c110f51-716b-4c5b-a0f0-a816a57aa11e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364851729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3364851729
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.25899020
Short name T675
Test name
Test status
Simulation time 183437711 ps
CPU time 3.48 seconds
Started Jul 03 05:57:52 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 214348 kb
Host smart-7fc2f742-f30f-4da3-9637-87ef503f95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25899020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.25899020
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.463315815
Short name T80
Test name
Test status
Simulation time 136027564 ps
CPU time 2.08 seconds
Started Jul 03 05:57:51 PM PDT 24
Finished Jul 03 05:57:54 PM PDT 24
Peak memory 209388 kb
Host smart-ceca7c12-c25a-45a5-ba0f-b33e06c4c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463315815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.463315815
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3908975298
Short name T763
Test name
Test status
Simulation time 305793363 ps
CPU time 6.76 seconds
Started Jul 03 05:57:52 PM PDT 24
Finished Jul 03 05:57:59 PM PDT 24
Peak memory 214312 kb
Host smart-936385c4-0645-4158-99db-1d0876a02a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908975298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3908975298
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1388238116
Short name T613
Test name
Test status
Simulation time 46609691 ps
CPU time 2.1 seconds
Started Jul 03 05:57:52 PM PDT 24
Finished Jul 03 05:57:54 PM PDT 24
Peak memory 214264 kb
Host smart-87d06737-7a6c-4559-afc4-eb22bdedc80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388238116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1388238116
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2311617220
Short name T674
Test name
Test status
Simulation time 1093147102 ps
CPU time 2.31 seconds
Started Jul 03 05:57:52 PM PDT 24
Finished Jul 03 05:57:55 PM PDT 24
Peak memory 207556 kb
Host smart-9e246799-f2bf-4eed-85f5-93119158ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311617220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2311617220
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.4273150239
Short name T590
Test name
Test status
Simulation time 94925610 ps
CPU time 4.7 seconds
Started Jul 03 05:57:51 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 208484 kb
Host smart-6b8e54ec-3367-4b4e-bdbf-a02e9451a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273150239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4273150239
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.576228562
Short name T862
Test name
Test status
Simulation time 130634851 ps
CPU time 2.04 seconds
Started Jul 03 05:57:48 PM PDT 24
Finished Jul 03 05:57:51 PM PDT 24
Peak memory 208416 kb
Host smart-a50bcbf4-bdfb-408c-b1fb-7f3ec17c43c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576228562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.576228562
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3590776394
Short name T87
Test name
Test status
Simulation time 464366036 ps
CPU time 10.74 seconds
Started Jul 03 05:57:51 PM PDT 24
Finished Jul 03 05:58:02 PM PDT 24
Peak memory 208116 kb
Host smart-48a60644-b3d0-4500-bb4b-faf14e013a5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590776394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3590776394
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.583300192
Short name T617
Test name
Test status
Simulation time 33062159 ps
CPU time 2.35 seconds
Started Jul 03 05:57:48 PM PDT 24
Finished Jul 03 05:57:51 PM PDT 24
Peak memory 207060 kb
Host smart-02d8470c-013f-42bd-b616-988e10868343
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583300192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.583300192
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1637002633
Short name T496
Test name
Test status
Simulation time 326229193 ps
CPU time 3.29 seconds
Started Jul 03 05:57:51 PM PDT 24
Finished Jul 03 05:57:54 PM PDT 24
Peak memory 206976 kb
Host smart-fea7fe11-bf2a-4721-b6b7-21f84bc2f7f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637002633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1637002633
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1909354376
Short name T707
Test name
Test status
Simulation time 84424300 ps
CPU time 2.05 seconds
Started Jul 03 05:57:51 PM PDT 24
Finished Jul 03 05:57:54 PM PDT 24
Peak memory 209748 kb
Host smart-d41852ec-597b-49f0-8147-f3f1af6c507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909354376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1909354376
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2139903017
Short name T622
Test name
Test status
Simulation time 534621992 ps
CPU time 2.28 seconds
Started Jul 03 05:57:48 PM PDT 24
Finished Jul 03 05:57:51 PM PDT 24
Peak memory 206732 kb
Host smart-df589b85-e9ea-48b6-a854-8c79e4dd79d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139903017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2139903017
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.698717749
Short name T719
Test name
Test status
Simulation time 144575291 ps
CPU time 5.44 seconds
Started Jul 03 05:57:52 PM PDT 24
Finished Jul 03 05:57:58 PM PDT 24
Peak memory 218440 kb
Host smart-fada79b5-4076-4bdc-8033-b7155ee5b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698717749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.698717749
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1728392473
Short name T634
Test name
Test status
Simulation time 11426929 ps
CPU time 0.85 seconds
Started Jul 03 05:57:56 PM PDT 24
Finished Jul 03 05:57:57 PM PDT 24
Peak memory 205968 kb
Host smart-ea141161-2cc1-4b15-8ea7-0e05400a25c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728392473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1728392473
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4140920226
Short name T248
Test name
Test status
Simulation time 172514350 ps
CPU time 3.83 seconds
Started Jul 03 05:57:58 PM PDT 24
Finished Jul 03 05:58:02 PM PDT 24
Peak memory 214884 kb
Host smart-d2d27db5-b1c4-491f-9889-bb19aa2c6017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140920226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4140920226
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3113824092
Short name T286
Test name
Test status
Simulation time 36030477 ps
CPU time 2.24 seconds
Started Jul 03 05:57:59 PM PDT 24
Finished Jul 03 05:58:02 PM PDT 24
Peak memory 206960 kb
Host smart-50cfdbaa-5102-4ed5-8d75-a4bceb67dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113824092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3113824092
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.124627604
Short name T105
Test name
Test status
Simulation time 28553654 ps
CPU time 2.18 seconds
Started Jul 03 05:57:58 PM PDT 24
Finished Jul 03 05:58:00 PM PDT 24
Peak memory 208692 kb
Host smart-ce9f99f6-c3a8-4848-8d59-1f8c8c22763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124627604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.124627604
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2184046553
Short name T453
Test name
Test status
Simulation time 328543862 ps
CPU time 3.42 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:05 PM PDT 24
Peak memory 214256 kb
Host smart-9192e07e-8a8e-4daf-9c79-1a2104f16125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184046553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2184046553
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2146455259
Short name T789
Test name
Test status
Simulation time 152827253 ps
CPU time 2.27 seconds
Started Jul 03 05:57:59 PM PDT 24
Finished Jul 03 05:58:01 PM PDT 24
Peak memory 214300 kb
Host smart-49cc616d-ddc8-4568-a7c3-6bf9cae09083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146455259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2146455259
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1099883822
Short name T285
Test name
Test status
Simulation time 225397193 ps
CPU time 4.44 seconds
Started Jul 03 05:57:55 PM PDT 24
Finished Jul 03 05:58:00 PM PDT 24
Peak memory 209088 kb
Host smart-51bcb1b7-16d2-469a-aff3-82d9b924a7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099883822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1099883822
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3471426971
Short name T473
Test name
Test status
Simulation time 248943661 ps
CPU time 2.96 seconds
Started Jul 03 05:57:53 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 206800 kb
Host smart-7c390e1b-ff65-410e-a35a-eb81f464916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471426971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3471426971
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1655368234
Short name T269
Test name
Test status
Simulation time 197955990 ps
CPU time 3.04 seconds
Started Jul 03 05:57:54 PM PDT 24
Finished Jul 03 05:57:57 PM PDT 24
Peak memory 206936 kb
Host smart-9246df0d-537c-4b3d-9afe-c3d807b11d8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655368234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1655368234
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.585445306
Short name T308
Test name
Test status
Simulation time 54558855 ps
CPU time 2.93 seconds
Started Jul 03 05:57:54 PM PDT 24
Finished Jul 03 05:57:57 PM PDT 24
Peak memory 208572 kb
Host smart-a673a940-e1d5-4c6e-9703-42afc62a06d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585445306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.585445306
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2580413847
Short name T637
Test name
Test status
Simulation time 43971702 ps
CPU time 1.93 seconds
Started Jul 03 05:57:54 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 207396 kb
Host smart-023f020a-1128-4ad7-ba5f-22e0402e27f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580413847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2580413847
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1141436653
Short name T640
Test name
Test status
Simulation time 31188257 ps
CPU time 1.92 seconds
Started Jul 03 05:57:57 PM PDT 24
Finished Jul 03 05:57:59 PM PDT 24
Peak memory 214344 kb
Host smart-b031bd50-fc74-452d-bdb9-9b6e36b0aaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141436653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1141436653
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2166117650
Short name T732
Test name
Test status
Simulation time 78846998 ps
CPU time 2.22 seconds
Started Jul 03 05:57:56 PM PDT 24
Finished Jul 03 05:57:59 PM PDT 24
Peak memory 208164 kb
Host smart-7eff701d-435f-4fb0-b902-bf3e6da4f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166117650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2166117650
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3653909181
Short name T194
Test name
Test status
Simulation time 1742667759 ps
CPU time 9.66 seconds
Started Jul 03 05:57:58 PM PDT 24
Finished Jul 03 05:58:08 PM PDT 24
Peak memory 208008 kb
Host smart-d4dd0e69-ced6-452a-852a-eaac323a1c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653909181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3653909181
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3602283313
Short name T130
Test name
Test status
Simulation time 3879930710 ps
CPU time 20.8 seconds
Started Jul 03 05:57:56 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 220620 kb
Host smart-83290462-b5b2-4933-9b4f-a4af4d7e82c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602283313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3602283313
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3095665764
Short name T298
Test name
Test status
Simulation time 1634024958 ps
CPU time 25.31 seconds
Started Jul 03 05:57:59 PM PDT 24
Finished Jul 03 05:58:25 PM PDT 24
Peak memory 222552 kb
Host smart-05e857c6-2ed0-4a72-936c-36c656959ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095665764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3095665764
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2127486468
Short name T481
Test name
Test status
Simulation time 133243473 ps
CPU time 2.01 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:03 PM PDT 24
Peak memory 210200 kb
Host smart-dda9f8cb-7ca8-4097-b132-5e56c08168d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127486468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2127486468
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2954996323
Short name T546
Test name
Test status
Simulation time 52158166 ps
CPU time 0.93 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:19 PM PDT 24
Peak memory 206028 kb
Host smart-accf5871-91b1-45ca-80fb-07c4a6dcf7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954996323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2954996323
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2734581413
Short name T728
Test name
Test status
Simulation time 44657566 ps
CPU time 3.41 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:22 PM PDT 24
Peak memory 214356 kb
Host smart-a49230bb-c34b-437f-82d6-b12659f8e654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734581413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2734581413
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3503970140
Short name T280
Test name
Test status
Simulation time 223401524 ps
CPU time 3.17 seconds
Started Jul 03 05:56:19 PM PDT 24
Finished Jul 03 05:56:22 PM PDT 24
Peak memory 218376 kb
Host smart-cda9816d-e27e-409c-ac35-d1b38f02440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503970140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3503970140
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4170427746
Short name T798
Test name
Test status
Simulation time 60187842 ps
CPU time 2.57 seconds
Started Jul 03 05:56:16 PM PDT 24
Finished Jul 03 05:56:19 PM PDT 24
Peak memory 216752 kb
Host smart-b65bd943-b27e-446e-9e90-ca4ef1230d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170427746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4170427746
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2614067468
Short name T552
Test name
Test status
Simulation time 1221174168 ps
CPU time 5.03 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:22 PM PDT 24
Peak memory 214336 kb
Host smart-faf58e6e-4a52-4d39-ae38-73a51fe0b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614067468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2614067468
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1249062011
Short name T288
Test name
Test status
Simulation time 14699805269 ps
CPU time 39.51 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:57 PM PDT 24
Peak memory 209256 kb
Host smart-58d9d86e-e7f8-4b1f-9d5c-601226be5dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249062011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1249062011
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1849952376
Short name T43
Test name
Test status
Simulation time 1323757216 ps
CPU time 6.2 seconds
Started Jul 03 05:56:16 PM PDT 24
Finished Jul 03 05:56:23 PM PDT 24
Peak memory 230184 kb
Host smart-5b2db352-3ce8-4948-85e1-4be584f19009
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849952376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1849952376
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2394661734
Short name T399
Test name
Test status
Simulation time 247238264 ps
CPU time 6.49 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:25 PM PDT 24
Peak memory 208556 kb
Host smart-238fbf65-58fc-4b8c-8c20-9b5fc8862848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394661734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2394661734
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2444412433
Short name T441
Test name
Test status
Simulation time 66398816 ps
CPU time 3.14 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:20 PM PDT 24
Peak memory 208268 kb
Host smart-9174418f-1c42-4564-95f5-98344c614962
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444412433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2444412433
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.238019917
Short name T877
Test name
Test status
Simulation time 650428542 ps
CPU time 3.92 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:21 PM PDT 24
Peak memory 208984 kb
Host smart-007b57bc-928a-4102-ae53-dc62aff9d70a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238019917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.238019917
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1121005429
Short name T472
Test name
Test status
Simulation time 66128264 ps
CPU time 3.1 seconds
Started Jul 03 05:56:15 PM PDT 24
Finished Jul 03 05:56:18 PM PDT 24
Peak memory 206972 kb
Host smart-691c7170-cff8-4b2b-8ce7-f9084ed2e328
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121005429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1121005429
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1816764454
Short name T642
Test name
Test status
Simulation time 314964694 ps
CPU time 4.07 seconds
Started Jul 03 05:56:19 PM PDT 24
Finished Jul 03 05:56:23 PM PDT 24
Peak memory 214296 kb
Host smart-fa54d858-0f2f-49f6-bf76-f32eba19ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816764454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1816764454
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1621311708
Short name T594
Test name
Test status
Simulation time 110545854 ps
CPU time 2.17 seconds
Started Jul 03 05:56:18 PM PDT 24
Finished Jul 03 05:56:21 PM PDT 24
Peak memory 206936 kb
Host smart-dd3d8fbc-bee7-4292-8b98-ff88810527f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621311708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1621311708
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1609106744
Short name T682
Test name
Test status
Simulation time 5138973602 ps
CPU time 21.6 seconds
Started Jul 03 05:56:20 PM PDT 24
Finished Jul 03 05:56:42 PM PDT 24
Peak memory 222720 kb
Host smart-e8ed0b74-2d97-4e9f-b7af-17fd67701d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609106744 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1609106744
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2169372392
Short name T783
Test name
Test status
Simulation time 11550266 ps
CPU time 0.75 seconds
Started Jul 03 05:58:04 PM PDT 24
Finished Jul 03 05:58:05 PM PDT 24
Peak memory 205976 kb
Host smart-283b35f3-c954-439c-9a42-64bfb13586a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169372392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2169372392
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.337163746
Short name T509
Test name
Test status
Simulation time 499943163 ps
CPU time 4.09 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:06 PM PDT 24
Peak memory 208904 kb
Host smart-c30e996f-9436-4386-b225-d113e3124548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337163746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.337163746
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2322831712
Short name T188
Test name
Test status
Simulation time 49000594 ps
CPU time 1.83 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:03 PM PDT 24
Peak memory 207760 kb
Host smart-dca136ae-c8e3-44c9-b2c7-db7d34965162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322831712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2322831712
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3868915848
Short name T368
Test name
Test status
Simulation time 274527214 ps
CPU time 6.5 seconds
Started Jul 03 05:58:02 PM PDT 24
Finished Jul 03 05:58:09 PM PDT 24
Peak memory 209300 kb
Host smart-a3539d87-aeb3-4d78-82aa-8d1c3fe46dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868915848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3868915848
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2944291664
Short name T304
Test name
Test status
Simulation time 176689268 ps
CPU time 3.01 seconds
Started Jul 03 05:58:02 PM PDT 24
Finished Jul 03 05:58:06 PM PDT 24
Peak memory 214472 kb
Host smart-c0cce8bf-5e1d-4ce2-b027-d8afd0139f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944291664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2944291664
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1372212508
Short name T62
Test name
Test status
Simulation time 677477776 ps
CPU time 3.85 seconds
Started Jul 03 05:58:01 PM PDT 24
Finished Jul 03 05:58:05 PM PDT 24
Peak memory 218992 kb
Host smart-42d97c48-e48e-49b8-b8c0-c060867c807d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372212508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1372212508
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2395711324
Short name T673
Test name
Test status
Simulation time 329429256 ps
CPU time 8.59 seconds
Started Jul 03 05:58:02 PM PDT 24
Finished Jul 03 05:58:11 PM PDT 24
Peak memory 214320 kb
Host smart-2a587dd2-57d6-4d00-97a4-ba085ca10c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395711324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2395711324
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1642330012
Short name T197
Test name
Test status
Simulation time 59760250 ps
CPU time 2.27 seconds
Started Jul 03 05:58:00 PM PDT 24
Finished Jul 03 05:58:03 PM PDT 24
Peak memory 206872 kb
Host smart-ecd9f441-074e-40b2-9acc-21bdb03d3f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642330012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1642330012
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3143196760
Short name T353
Test name
Test status
Simulation time 864690107 ps
CPU time 4.23 seconds
Started Jul 03 05:58:02 PM PDT 24
Finished Jul 03 05:58:06 PM PDT 24
Peak memory 208884 kb
Host smart-8fe4b435-451b-4884-b074-63dadfa1483a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143196760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3143196760
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.543816045
Short name T801
Test name
Test status
Simulation time 97365804 ps
CPU time 2.81 seconds
Started Jul 03 05:58:03 PM PDT 24
Finished Jul 03 05:58:06 PM PDT 24
Peak memory 207060 kb
Host smart-70485880-6adb-478c-b33d-90696377864d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543816045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.543816045
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.469274814
Short name T555
Test name
Test status
Simulation time 559458858 ps
CPU time 4.52 seconds
Started Jul 03 05:58:03 PM PDT 24
Finished Jul 03 05:58:08 PM PDT 24
Peak memory 208008 kb
Host smart-86b09662-52c9-4b30-a0d7-c59c25b34a08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469274814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.469274814
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1812838360
Short name T250
Test name
Test status
Simulation time 70637881 ps
CPU time 2.02 seconds
Started Jul 03 05:58:04 PM PDT 24
Finished Jul 03 05:58:07 PM PDT 24
Peak memory 208516 kb
Host smart-b96dd911-657c-4158-9a3e-4dab1822521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812838360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1812838360
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2338129534
Short name T908
Test name
Test status
Simulation time 426494689 ps
CPU time 5.76 seconds
Started Jul 03 05:57:58 PM PDT 24
Finished Jul 03 05:58:04 PM PDT 24
Peak memory 206812 kb
Host smart-605035a5-c16c-4b46-9f35-c7cf9ff6b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338129534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2338129534
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2625964119
Short name T511
Test name
Test status
Simulation time 90090632 ps
CPU time 3.88 seconds
Started Jul 03 05:58:07 PM PDT 24
Finished Jul 03 05:58:11 PM PDT 24
Peak memory 209188 kb
Host smart-253345b9-4896-40bf-a7a4-e6df45b709f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625964119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2625964119
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3175110333
Short name T301
Test name
Test status
Simulation time 225073845 ps
CPU time 6.87 seconds
Started Jul 03 05:58:02 PM PDT 24
Finished Jul 03 05:58:09 PM PDT 24
Peak memory 209492 kb
Host smart-3c1570ac-d04c-4448-8d2c-294052ab9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175110333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3175110333
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1417280375
Short name T159
Test name
Test status
Simulation time 233566366 ps
CPU time 1.93 seconds
Started Jul 03 05:58:06 PM PDT 24
Finished Jul 03 05:58:08 PM PDT 24
Peak memory 209812 kb
Host smart-1aa7e79b-9a12-4a52-a189-ef80cdfd2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417280375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1417280375
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3522969269
Short name T419
Test name
Test status
Simulation time 53114541 ps
CPU time 3.8 seconds
Started Jul 03 05:58:09 PM PDT 24
Finished Jul 03 05:58:13 PM PDT 24
Peak memory 215184 kb
Host smart-2f7e2005-48b6-4508-a4b4-2affe7d0aadb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522969269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3522969269
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1429363472
Short name T236
Test name
Test status
Simulation time 79578654 ps
CPU time 3.41 seconds
Started Jul 03 05:58:09 PM PDT 24
Finished Jul 03 05:58:13 PM PDT 24
Peak memory 210580 kb
Host smart-6142babe-4453-46a7-ab20-4488be4dde11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429363472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1429363472
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.95328130
Short name T833
Test name
Test status
Simulation time 51858426 ps
CPU time 2.47 seconds
Started Jul 03 05:58:08 PM PDT 24
Finished Jul 03 05:58:11 PM PDT 24
Peak memory 214368 kb
Host smart-4249406c-23d8-4951-80ac-8d61d7102ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95328130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.95328130
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2135355561
Short name T421
Test name
Test status
Simulation time 874793033 ps
CPU time 3.24 seconds
Started Jul 03 05:58:06 PM PDT 24
Finished Jul 03 05:58:10 PM PDT 24
Peak memory 214348 kb
Host smart-c86ba1b5-0daf-466d-8405-d4fc51209c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135355561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2135355561
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1862441148
Short name T778
Test name
Test status
Simulation time 440346105 ps
CPU time 5.83 seconds
Started Jul 03 05:58:06 PM PDT 24
Finished Jul 03 05:58:12 PM PDT 24
Peak memory 222384 kb
Host smart-2a25b86a-a0bd-4614-809b-406957297371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862441148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1862441148
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1965395328
Short name T272
Test name
Test status
Simulation time 352541511 ps
CPU time 4.5 seconds
Started Jul 03 05:58:09 PM PDT 24
Finished Jul 03 05:58:14 PM PDT 24
Peak memory 214296 kb
Host smart-33bda43a-d204-45aa-9e8e-133f368f0584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965395328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1965395328
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1572143513
Short name T589
Test name
Test status
Simulation time 267830214 ps
CPU time 3.04 seconds
Started Jul 03 05:58:03 PM PDT 24
Finished Jul 03 05:58:07 PM PDT 24
Peak memory 207308 kb
Host smart-e591f388-5817-46a4-af9c-598eb7ab54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572143513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1572143513
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.511394340
Short name T309
Test name
Test status
Simulation time 402860981 ps
CPU time 6.16 seconds
Started Jul 03 05:58:05 PM PDT 24
Finished Jul 03 05:58:11 PM PDT 24
Peak memory 208608 kb
Host smart-88083ebe-a4aa-47d3-acfa-81e9fbbdeca1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511394340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.511394340
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3909292260
Short name T727
Test name
Test status
Simulation time 324150030 ps
CPU time 3.02 seconds
Started Jul 03 05:58:04 PM PDT 24
Finished Jul 03 05:58:08 PM PDT 24
Peak memory 207396 kb
Host smart-2913626d-03ec-4ae5-bad8-dcb260d73c2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909292260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3909292260
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1137307480
Short name T457
Test name
Test status
Simulation time 663763449 ps
CPU time 7.07 seconds
Started Jul 03 05:58:03 PM PDT 24
Finished Jul 03 05:58:10 PM PDT 24
Peak memory 206984 kb
Host smart-efd37696-514d-492b-81e9-661e46bb96df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137307480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1137307480
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.237110603
Short name T251
Test name
Test status
Simulation time 106460863 ps
CPU time 4.58 seconds
Started Jul 03 05:58:07 PM PDT 24
Finished Jul 03 05:58:12 PM PDT 24
Peak memory 209760 kb
Host smart-486ec567-c8d9-4801-ab64-a62220797f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237110603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.237110603
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.121341054
Short name T488
Test name
Test status
Simulation time 625381718 ps
CPU time 3.32 seconds
Started Jul 03 05:58:04 PM PDT 24
Finished Jul 03 05:58:08 PM PDT 24
Peak memory 206696 kb
Host smart-a41a3a8d-41c1-4279-989d-f76c135fc16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121341054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.121341054
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3194620575
Short name T909
Test name
Test status
Simulation time 143675614 ps
CPU time 8.24 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:21 PM PDT 24
Peak memory 222744 kb
Host smart-40754c31-cf55-475e-86c1-b97c332731b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194620575 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3194620575
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.198934394
Short name T811
Test name
Test status
Simulation time 43756776 ps
CPU time 2.95 seconds
Started Jul 03 05:58:07 PM PDT 24
Finished Jul 03 05:58:10 PM PDT 24
Peak memory 208148 kb
Host smart-1ef57e4f-5abe-45ab-a3f5-fe7e63c549da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198934394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.198934394
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3762562785
Short name T383
Test name
Test status
Simulation time 37770505 ps
CPU time 1.54 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:14 PM PDT 24
Peak memory 209912 kb
Host smart-fb99d297-0d43-436f-8f76-7c7988f9a8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762562785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3762562785
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.246433431
Short name T824
Test name
Test status
Simulation time 93733649 ps
CPU time 0.87 seconds
Started Jul 03 05:58:16 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 206000 kb
Host smart-0094e278-1590-42d3-8c63-250d220d3556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246433431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.246433431
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1023184198
Short name T413
Test name
Test status
Simulation time 50037724 ps
CPU time 3.71 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 215704 kb
Host smart-5be1e250-3dc5-4f9a-b8d3-9f6199626d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023184198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1023184198
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2537192180
Short name T656
Test name
Test status
Simulation time 117838491 ps
CPU time 2.56 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:15 PM PDT 24
Peak memory 222708 kb
Host smart-00b14d3d-acb1-460b-a5b9-107f7cf4c040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537192180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2537192180
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2849047490
Short name T291
Test name
Test status
Simulation time 614498330 ps
CPU time 5.99 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 215496 kb
Host smart-95d43e43-4297-4d70-99a4-a30f2b3edf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849047490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2849047490
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2551923879
Short name T810
Test name
Test status
Simulation time 213887053 ps
CPU time 3.02 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:14 PM PDT 24
Peak memory 214356 kb
Host smart-e12f11ad-2e64-4126-b344-a0d2964668c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551923879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2551923879
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.38794385
Short name T688
Test name
Test status
Simulation time 789807812 ps
CPU time 3.11 seconds
Started Jul 03 05:58:13 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 218776 kb
Host smart-56629c09-88eb-4fdb-ad26-d099a692aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38794385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.38794385
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4165081817
Short name T799
Test name
Test status
Simulation time 59573120 ps
CPU time 2.9 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:14 PM PDT 24
Peak memory 207808 kb
Host smart-4bb49cfe-dcfc-4b67-9253-d006ffb137d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165081817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4165081817
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2324348463
Short name T745
Test name
Test status
Simulation time 58419243 ps
CPU time 2.83 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:15 PM PDT 24
Peak memory 206932 kb
Host smart-0f7c3032-b67b-48db-8360-29fccc16425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324348463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2324348463
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3404417584
Short name T696
Test name
Test status
Simulation time 359617605 ps
CPU time 3.66 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 208580 kb
Host smart-b1679aa0-b4a1-4d00-9c82-b55b94827ca3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404417584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3404417584
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.695202636
Short name T313
Test name
Test status
Simulation time 320215899 ps
CPU time 3.14 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 208908 kb
Host smart-91a85e16-bb93-4ef9-a2f2-aba27aeb5f07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695202636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.695202636
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.301222641
Short name T459
Test name
Test status
Simulation time 255906349 ps
CPU time 3.19 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:15 PM PDT 24
Peak memory 208604 kb
Host smart-e77f5b6b-acad-416e-beab-fa1de5e518d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301222641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.301222641
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.711265702
Short name T475
Test name
Test status
Simulation time 55764294 ps
CPU time 2.74 seconds
Started Jul 03 05:58:10 PM PDT 24
Finished Jul 03 05:58:13 PM PDT 24
Peak memory 216136 kb
Host smart-dc53516b-55f3-499b-a301-bf0a1d1131e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711265702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.711265702
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.485450188
Short name T203
Test name
Test status
Simulation time 42865898 ps
CPU time 1.85 seconds
Started Jul 03 05:58:11 PM PDT 24
Finished Jul 03 05:58:13 PM PDT 24
Peak memory 207096 kb
Host smart-12cce158-35a8-4208-a98b-567984132742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485450188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.485450188
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1357047164
Short name T51
Test name
Test status
Simulation time 606397502 ps
CPU time 6.86 seconds
Started Jul 03 05:58:16 PM PDT 24
Finished Jul 03 05:58:24 PM PDT 24
Peak memory 219536 kb
Host smart-add80e25-0397-4162-ac7f-34239edd82b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357047164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1357047164
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2545690582
Short name T181
Test name
Test status
Simulation time 294491100 ps
CPU time 11.02 seconds
Started Jul 03 05:58:13 PM PDT 24
Finished Jul 03 05:58:25 PM PDT 24
Peak memory 222544 kb
Host smart-1b56eea8-1367-4d5c-9ab4-c9f9b7ba8c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545690582 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2545690582
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1276337518
Short name T666
Test name
Test status
Simulation time 7986065111 ps
CPU time 95.86 seconds
Started Jul 03 05:58:13 PM PDT 24
Finished Jul 03 05:59:49 PM PDT 24
Peak memory 209504 kb
Host smart-2dd7a2a2-ddec-4e76-bb7f-4d2ec72091ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276337518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1276337518
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4159044976
Short name T562
Test name
Test status
Simulation time 316750950 ps
CPU time 2.39 seconds
Started Jul 03 05:58:12 PM PDT 24
Finished Jul 03 05:58:14 PM PDT 24
Peak memory 210312 kb
Host smart-93b68f43-bde3-4663-ada9-3ed79e948220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159044976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4159044976
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.483054045
Short name T565
Test name
Test status
Simulation time 40339856 ps
CPU time 0.85 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:26 PM PDT 24
Peak memory 206024 kb
Host smart-4d5a7a47-16d9-4898-8b49-710538cf4cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483054045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.483054045
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2516588547
Short name T306
Test name
Test status
Simulation time 2393139033 ps
CPU time 33.37 seconds
Started Jul 03 05:58:14 PM PDT 24
Finished Jul 03 05:58:47 PM PDT 24
Peak memory 222604 kb
Host smart-cc2da051-e887-4f46-8bbf-e01716cf1c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516588547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2516588547
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1713640958
Short name T564
Test name
Test status
Simulation time 102795233 ps
CPU time 4.06 seconds
Started Jul 03 05:58:19 PM PDT 24
Finished Jul 03 05:58:23 PM PDT 24
Peak memory 210052 kb
Host smart-10f6b116-962d-409d-a0be-f6a53c7a2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713640958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1713640958
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1088989118
Short name T836
Test name
Test status
Simulation time 289701561 ps
CPU time 4.77 seconds
Started Jul 03 05:58:17 PM PDT 24
Finished Jul 03 05:58:22 PM PDT 24
Peak memory 222548 kb
Host smart-9f33db69-2fbf-44e9-98a4-c69068c65cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088989118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1088989118
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1148163309
Short name T599
Test name
Test status
Simulation time 142109582 ps
CPU time 3.16 seconds
Started Jul 03 05:58:17 PM PDT 24
Finished Jul 03 05:58:21 PM PDT 24
Peak memory 214300 kb
Host smart-e1f26c79-3310-472f-aa4f-00ac7f1d2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148163309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1148163309
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4018302743
Short name T720
Test name
Test status
Simulation time 139700212 ps
CPU time 6.44 seconds
Started Jul 03 05:58:19 PM PDT 24
Finished Jul 03 05:58:26 PM PDT 24
Peak memory 222424 kb
Host smart-4d1719d3-a633-4714-bf5b-4f6fbaad5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018302743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4018302743
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3835738052
Short name T519
Test name
Test status
Simulation time 166234049 ps
CPU time 3.64 seconds
Started Jul 03 05:58:16 PM PDT 24
Finished Jul 03 05:58:19 PM PDT 24
Peak memory 219728 kb
Host smart-3d802bc1-0e44-404f-a835-9c26f38da917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835738052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3835738052
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2803143582
Short name T729
Test name
Test status
Simulation time 58028330 ps
CPU time 3.54 seconds
Started Jul 03 05:58:17 PM PDT 24
Finished Jul 03 05:58:21 PM PDT 24
Peak memory 208120 kb
Host smart-59dca6f8-a285-45a1-b98a-6137384d5ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803143582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2803143582
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2597588017
Short name T508
Test name
Test status
Simulation time 267458323 ps
CPU time 3.65 seconds
Started Jul 03 05:58:13 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 208260 kb
Host smart-aee7250a-7eaf-4d81-bf7c-083e80a6c4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597588017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2597588017
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1509028906
Short name T863
Test name
Test status
Simulation time 238364076 ps
CPU time 4.56 seconds
Started Jul 03 05:58:16 PM PDT 24
Finished Jul 03 05:58:21 PM PDT 24
Peak memory 208792 kb
Host smart-ddf3134c-83e6-43a1-af08-82d66076c568
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509028906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1509028906
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3506466575
Short name T454
Test name
Test status
Simulation time 30298961 ps
CPU time 2.23 seconds
Started Jul 03 05:58:14 PM PDT 24
Finished Jul 03 05:58:16 PM PDT 24
Peak memory 207036 kb
Host smart-75598b81-15fd-4a15-8b5a-071eb964880b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506466575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3506466575
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4257082610
Short name T435
Test name
Test status
Simulation time 460489737 ps
CPU time 5.41 seconds
Started Jul 03 05:58:14 PM PDT 24
Finished Jul 03 05:58:19 PM PDT 24
Peak memory 208268 kb
Host smart-58499ba8-bc1f-49a6-b07c-c7bd565f6299
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257082610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4257082610
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3672515338
Short name T586
Test name
Test status
Simulation time 201784002 ps
CPU time 2.95 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:23 PM PDT 24
Peak memory 209936 kb
Host smart-77100985-7758-4210-8cca-e14efc96f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672515338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3672515338
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.750308116
Short name T455
Test name
Test status
Simulation time 99163182 ps
CPU time 1.94 seconds
Started Jul 03 05:58:15 PM PDT 24
Finished Jul 03 05:58:17 PM PDT 24
Peak memory 208644 kb
Host smart-4a3926de-f83e-435a-b271-6f0b2ccdcbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750308116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.750308116
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3380386875
Short name T182
Test name
Test status
Simulation time 421841241 ps
CPU time 12.25 seconds
Started Jul 03 05:58:18 PM PDT 24
Finished Jul 03 05:58:30 PM PDT 24
Peak memory 222640 kb
Host smart-7fb7f43a-91fc-4962-a46f-af4db4ff7767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380386875 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3380386875
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3676529546
Short name T503
Test name
Test status
Simulation time 123181057 ps
CPU time 4.54 seconds
Started Jul 03 05:58:17 PM PDT 24
Finished Jul 03 05:58:22 PM PDT 24
Peak memory 207204 kb
Host smart-582610b6-b869-46c4-b97c-11037dcda5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676529546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3676529546
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.419345403
Short name T154
Test name
Test status
Simulation time 40156503 ps
CPU time 1.89 seconds
Started Jul 03 05:58:21 PM PDT 24
Finished Jul 03 05:58:23 PM PDT 24
Peak memory 209792 kb
Host smart-1f090ecb-9916-49b1-8642-f79e1b3cb8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419345403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.419345403
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2748793576
Short name T533
Test name
Test status
Simulation time 134837734 ps
CPU time 0.71 seconds
Started Jul 03 05:58:23 PM PDT 24
Finished Jul 03 05:58:24 PM PDT 24
Peak memory 205988 kb
Host smart-0bf0bd26-15ed-4b57-98a2-b28b3f6a9a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748793576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2748793576
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1463581502
Short name T249
Test name
Test status
Simulation time 38483787 ps
CPU time 2.8 seconds
Started Jul 03 05:58:21 PM PDT 24
Finished Jul 03 05:58:25 PM PDT 24
Peak memory 214312 kb
Host smart-741c9c19-03e0-402d-8b72-9f3a9981e948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463581502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1463581502
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.301908631
Short name T460
Test name
Test status
Simulation time 492898381 ps
CPU time 3.19 seconds
Started Jul 03 05:58:21 PM PDT 24
Finished Jul 03 05:58:25 PM PDT 24
Peak memory 209252 kb
Host smart-2eaa7a28-dc1c-4858-91c5-c31850b2a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301908631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.301908631
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2391990770
Short name T99
Test name
Test status
Simulation time 124403004 ps
CPU time 1.92 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:27 PM PDT 24
Peak memory 214452 kb
Host smart-c68dc32d-84ae-4e20-b86d-d2e1bc6b71c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391990770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2391990770
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1301086693
Short name T724
Test name
Test status
Simulation time 339210499 ps
CPU time 6.89 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:27 PM PDT 24
Peak memory 222480 kb
Host smart-b1094b28-e70b-4201-92cf-f9d9d3908d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301086693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1301086693
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1547506876
Short name T196
Test name
Test status
Simulation time 270550220 ps
CPU time 7.21 seconds
Started Jul 03 05:58:19 PM PDT 24
Finished Jul 03 05:58:27 PM PDT 24
Peak memory 208656 kb
Host smart-a2e0e3ec-35f7-4ded-b6d3-d48c2468cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547506876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1547506876
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2004446301
Short name T550
Test name
Test status
Simulation time 56700226 ps
CPU time 1.66 seconds
Started Jul 03 05:58:18 PM PDT 24
Finished Jul 03 05:58:20 PM PDT 24
Peak memory 206900 kb
Host smart-ea07aff3-9a85-431b-9d8b-1237cbf643bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004446301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2004446301
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3821267566
Short name T89
Test name
Test status
Simulation time 209536120 ps
CPU time 4.24 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:30 PM PDT 24
Peak memory 208800 kb
Host smart-eae0c244-0197-4d4d-8dc4-a7f1eea45b84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821267566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3821267566
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3455856860
Short name T809
Test name
Test status
Simulation time 768039178 ps
CPU time 8.41 seconds
Started Jul 03 05:58:21 PM PDT 24
Finished Jul 03 05:58:30 PM PDT 24
Peak memory 206952 kb
Host smart-0230d519-12dc-45a8-a278-f5a9db6da5db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455856860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3455856860
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3680853911
Short name T84
Test name
Test status
Simulation time 47688684 ps
CPU time 2.54 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:23 PM PDT 24
Peak memory 208556 kb
Host smart-49442642-0098-4783-a029-da10e7da61ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680853911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3680853911
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4099203683
Short name T626
Test name
Test status
Simulation time 585223712 ps
CPU time 12.76 seconds
Started Jul 03 05:58:22 PM PDT 24
Finished Jul 03 05:58:35 PM PDT 24
Peak memory 208948 kb
Host smart-f5f1ce71-dc3f-423e-b04d-062d172b90c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099203683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4099203683
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1992569674
Short name T532
Test name
Test status
Simulation time 703873488 ps
CPU time 2.78 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:23 PM PDT 24
Peak memory 207060 kb
Host smart-9e2fe7e9-d012-4499-b2f7-dd66cc97df64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992569674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1992569674
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2746643283
Short name T370
Test name
Test status
Simulation time 1799134381 ps
CPU time 21.33 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:42 PM PDT 24
Peak memory 220080 kb
Host smart-f86d06e6-eb31-4e10-b53b-0c8dbc5f021f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746643283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2746643283
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3726002158
Short name T636
Test name
Test status
Simulation time 1313433509 ps
CPU time 25.26 seconds
Started Jul 03 05:58:20 PM PDT 24
Finished Jul 03 05:58:45 PM PDT 24
Peak memory 209972 kb
Host smart-0a38fb74-e3ea-4ffd-be8f-0a850d25035e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726002158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3726002158
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1557221060
Short name T58
Test name
Test status
Simulation time 1465038981 ps
CPU time 2.06 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:27 PM PDT 24
Peak memory 210308 kb
Host smart-29d995b4-756c-4fc6-8723-eaa2cd918ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557221060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1557221060
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2038388264
Short name T540
Test name
Test status
Simulation time 20089027 ps
CPU time 0.76 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:27 PM PDT 24
Peak memory 205920 kb
Host smart-a0df1d21-4697-475d-9990-758503ef320a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038388264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2038388264
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.603346215
Short name T700
Test name
Test status
Simulation time 44605632 ps
CPU time 3.22 seconds
Started Jul 03 05:58:22 PM PDT 24
Finished Jul 03 05:58:26 PM PDT 24
Peak memory 215548 kb
Host smart-aca9b40e-f00c-4e5e-94ba-685a78951aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603346215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.603346215
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3808528527
Short name T660
Test name
Test status
Simulation time 147803078 ps
CPU time 5.19 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:32 PM PDT 24
Peak memory 214708 kb
Host smart-4d88fc76-771c-41a9-bec0-b24187f22ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808528527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3808528527
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.179792251
Short name T282
Test name
Test status
Simulation time 197365863 ps
CPU time 1.92 seconds
Started Jul 03 05:58:22 PM PDT 24
Finished Jul 03 05:58:24 PM PDT 24
Peak memory 209868 kb
Host smart-509c3696-be2d-4850-9f85-aab02a0b6810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179792251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.179792251
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.715244
Short name T788
Test name
Test status
Simulation time 277783212 ps
CPU time 3.81 seconds
Started Jul 03 05:58:27 PM PDT 24
Finished Jul 03 05:58:31 PM PDT 24
Peak memory 214328 kb
Host smart-182c3564-695b-4ab3-9bc5-0f92c3fdb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.715244
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2265861939
Short name T578
Test name
Test status
Simulation time 203306731 ps
CPU time 1.91 seconds
Started Jul 03 05:58:27 PM PDT 24
Finished Jul 03 05:58:29 PM PDT 24
Peak memory 214284 kb
Host smart-2e33b992-d8f2-4dd7-9b54-990b6f58f798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265861939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2265861939
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2771562328
Short name T57
Test name
Test status
Simulation time 118675731 ps
CPU time 3.28 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:29 PM PDT 24
Peak memory 214320 kb
Host smart-7ee1ef19-4f00-4beb-9f90-23195fbe0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771562328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2771562328
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1412520554
Short name T585
Test name
Test status
Simulation time 1612379244 ps
CPU time 16.21 seconds
Started Jul 03 05:58:24 PM PDT 24
Finished Jul 03 05:58:40 PM PDT 24
Peak memory 214328 kb
Host smart-a2d72322-8618-4ed8-9d98-34a5e9cfc30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412520554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1412520554
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2756306042
Short name T330
Test name
Test status
Simulation time 94883683 ps
CPU time 4.27 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:29 PM PDT 24
Peak memory 208432 kb
Host smart-345bd148-b2b3-420f-898d-61cfe002b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756306042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2756306042
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.128037519
Short name T495
Test name
Test status
Simulation time 381774363 ps
CPU time 5.39 seconds
Started Jul 03 05:58:23 PM PDT 24
Finished Jul 03 05:58:29 PM PDT 24
Peak memory 208684 kb
Host smart-374f534d-61b5-42c9-8ffc-ffd8b98a0c9f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128037519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.128037519
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1246068275
Short name T394
Test name
Test status
Simulation time 527283373 ps
CPU time 4.8 seconds
Started Jul 03 05:58:23 PM PDT 24
Finished Jul 03 05:58:28 PM PDT 24
Peak memory 207920 kb
Host smart-a5576b66-8509-49dd-a69c-f50655b496aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246068275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1246068275
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.814728199
Short name T597
Test name
Test status
Simulation time 183057362 ps
CPU time 6.6 seconds
Started Jul 03 05:58:24 PM PDT 24
Finished Jul 03 05:58:31 PM PDT 24
Peak memory 208752 kb
Host smart-c24d55b3-ec28-4424-8c38-7e1ef390c5a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814728199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.814728199
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1069331825
Short name T266
Test name
Test status
Simulation time 1850380091 ps
CPU time 12.01 seconds
Started Jul 03 05:58:25 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 214276 kb
Host smart-b0ff2f93-4891-4231-97c9-00c02829bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069331825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1069331825
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1872277779
Short name T470
Test name
Test status
Simulation time 28049840 ps
CPU time 2.06 seconds
Started Jul 03 05:58:22 PM PDT 24
Finished Jul 03 05:58:24 PM PDT 24
Peak memory 206968 kb
Host smart-d62f21ec-5e03-4d58-82fe-0e987d95e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872277779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1872277779
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3606578584
Short name T49
Test name
Test status
Simulation time 1522899781 ps
CPU time 17.6 seconds
Started Jul 03 05:58:24 PM PDT 24
Finished Jul 03 05:58:42 PM PDT 24
Peak memory 222420 kb
Host smart-a37131d8-4b17-455a-bd57-263ac245b962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606578584 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3606578584
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.653006207
Short name T563
Test name
Test status
Simulation time 1940642426 ps
CPU time 44.47 seconds
Started Jul 03 05:58:28 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 209308 kb
Host smart-f35a91bd-ece2-4ebe-8abf-06bae9820a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653006207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.653006207
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3394117953
Short name T523
Test name
Test status
Simulation time 133329671 ps
CPU time 2.97 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:29 PM PDT 24
Peak memory 210280 kb
Host smart-5c4242ab-f006-49f0-b6bd-c909d2d0d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394117953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3394117953
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3895368139
Short name T429
Test name
Test status
Simulation time 10767821 ps
CPU time 0.78 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:31 PM PDT 24
Peak memory 205956 kb
Host smart-8585ef01-d8a1-4007-8917-5e4d59354e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895368139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3895368139
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.120093219
Short name T652
Test name
Test status
Simulation time 141036241 ps
CPU time 3.48 seconds
Started Jul 03 05:58:28 PM PDT 24
Finished Jul 03 05:58:32 PM PDT 24
Peak memory 209888 kb
Host smart-8a6c34ab-b6a9-4417-9814-9c34f421129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120093219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.120093219
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4111703423
Short name T754
Test name
Test status
Simulation time 732444474 ps
CPU time 7.46 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 207500 kb
Host smart-061988d9-7d75-4624-80e9-f9c8cbb43e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111703423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4111703423
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.570474362
Short name T900
Test name
Test status
Simulation time 159811257 ps
CPU time 6.95 seconds
Started Jul 03 05:58:28 PM PDT 24
Finished Jul 03 05:58:36 PM PDT 24
Peak memory 215120 kb
Host smart-ea8e6384-afc6-441f-be56-39e220558940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570474362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.570474362
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.598641285
Short name T825
Test name
Test status
Simulation time 1611695669 ps
CPU time 8.05 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 207324 kb
Host smart-f5c2915a-07b7-41ae-b88e-58752a2f7628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598641285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.598641285
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1546494074
Short name T346
Test name
Test status
Simulation time 766527070 ps
CPU time 6.71 seconds
Started Jul 03 05:58:29 PM PDT 24
Finished Jul 03 05:58:37 PM PDT 24
Peak memory 214424 kb
Host smart-df319a26-f54c-4d22-a596-2bd6614c4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546494074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1546494074
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1301071365
Short name T691
Test name
Test status
Simulation time 196051195 ps
CPU time 6.64 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:37 PM PDT 24
Peak memory 214324 kb
Host smart-b77bcaf9-8ecc-402f-b96b-6cace51d7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301071365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1301071365
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.434285153
Short name T905
Test name
Test status
Simulation time 227971114 ps
CPU time 6.64 seconds
Started Jul 03 05:58:27 PM PDT 24
Finished Jul 03 05:58:34 PM PDT 24
Peak memory 208700 kb
Host smart-4e53bdbd-cb5e-4cf5-beee-054c261f90c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434285153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.434285153
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.4096112809
Short name T366
Test name
Test status
Simulation time 2896197249 ps
CPU time 21.01 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:47 PM PDT 24
Peak memory 209152 kb
Host smart-27cd1abb-a05c-47f3-b3fa-8f11df3e721d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096112809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4096112809
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3718221619
Short name T684
Test name
Test status
Simulation time 399794629 ps
CPU time 3.55 seconds
Started Jul 03 05:58:26 PM PDT 24
Finished Jul 03 05:58:30 PM PDT 24
Peak memory 208376 kb
Host smart-4a5d6fcd-e91b-4147-957e-928a6558e372
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718221619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3718221619
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3482405921
Short name T610
Test name
Test status
Simulation time 179725096 ps
CPU time 3.77 seconds
Started Jul 03 05:58:29 PM PDT 24
Finished Jul 03 05:58:34 PM PDT 24
Peak memory 209852 kb
Host smart-41856008-e9c2-42f5-b66d-3d338f2128d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482405921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3482405921
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4281376940
Short name T893
Test name
Test status
Simulation time 1762995881 ps
CPU time 10.05 seconds
Started Jul 03 05:58:28 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 208680 kb
Host smart-8a2b3ac8-b1d1-44f2-a980-12ad92913b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281376940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4281376940
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2626663760
Short name T831
Test name
Test status
Simulation time 76989999 ps
CPU time 4.12 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:34 PM PDT 24
Peak memory 207744 kb
Host smart-f1c23c2a-6825-4148-9b28-7ec97098d3f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626663760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2626663760
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.816019731
Short name T784
Test name
Test status
Simulation time 803304735 ps
CPU time 7.81 seconds
Started Jul 03 05:58:29 PM PDT 24
Finished Jul 03 05:58:37 PM PDT 24
Peak memory 218484 kb
Host smart-8b643907-29ed-4821-a078-a5bb7bf55632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816019731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.816019731
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2526980785
Short name T600
Test name
Test status
Simulation time 1173892519 ps
CPU time 27.89 seconds
Started Jul 03 05:58:29 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 210968 kb
Host smart-e34330e6-febf-465c-9677-7d70f914a656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526980785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2526980785
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2901182518
Short name T538
Test name
Test status
Simulation time 22029151 ps
CPU time 0.83 seconds
Started Jul 03 05:58:36 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 205988 kb
Host smart-89199040-e82b-4333-8a2c-f4a995a7e227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901182518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2901182518
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4216831293
Short name T140
Test name
Test status
Simulation time 96193242 ps
CPU time 5.35 seconds
Started Jul 03 05:58:32 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 214304 kb
Host smart-d826de76-a9b9-44d6-af90-88a1703f2559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216831293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4216831293
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3724067646
Short name T31
Test name
Test status
Simulation time 45801981 ps
CPU time 1.83 seconds
Started Jul 03 05:58:33 PM PDT 24
Finished Jul 03 05:58:36 PM PDT 24
Peak memory 214716 kb
Host smart-5ca618ec-412f-47c4-bdcd-a8a68fc2f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724067646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3724067646
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.296626865
Short name T268
Test name
Test status
Simulation time 109404480 ps
CPU time 2.22 seconds
Started Jul 03 05:58:32 PM PDT 24
Finished Jul 03 05:58:34 PM PDT 24
Peak memory 207568 kb
Host smart-0d94b637-7f9a-4866-9598-8a35514f3cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296626865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.296626865
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3224342291
Short name T112
Test name
Test status
Simulation time 79113683 ps
CPU time 4.38 seconds
Started Jul 03 05:58:33 PM PDT 24
Finished Jul 03 05:58:38 PM PDT 24
Peak memory 214236 kb
Host smart-f1d28766-2f62-40cb-bad1-f5829fbfdaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224342291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3224342291
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.429434594
Short name T744
Test name
Test status
Simulation time 81003445 ps
CPU time 2.62 seconds
Started Jul 03 05:58:33 PM PDT 24
Finished Jul 03 05:58:36 PM PDT 24
Peak memory 220268 kb
Host smart-06162589-971c-435a-8150-d5805d74ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429434594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.429434594
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2622489459
Short name T876
Test name
Test status
Simulation time 673919234 ps
CPU time 6.59 seconds
Started Jul 03 05:58:34 PM PDT 24
Finished Jul 03 05:58:41 PM PDT 24
Peak memory 209360 kb
Host smart-5355242e-f1e6-41d0-bb57-07d1f3688fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622489459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2622489459
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1910697299
Short name T561
Test name
Test status
Simulation time 79990070 ps
CPU time 3.83 seconds
Started Jul 03 05:58:31 PM PDT 24
Finished Jul 03 05:58:35 PM PDT 24
Peak memory 208544 kb
Host smart-c09a7602-fcbf-4468-ae95-aa9be2ef6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910697299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1910697299
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2233591101
Short name T598
Test name
Test status
Simulation time 2754352011 ps
CPU time 30.5 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:59:01 PM PDT 24
Peak memory 208972 kb
Host smart-a5acf295-99c0-4c8f-905d-3062c2029585
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233591101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2233591101
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4109178938
Short name T651
Test name
Test status
Simulation time 47630424 ps
CPU time 2.59 seconds
Started Jul 03 05:58:33 PM PDT 24
Finished Jul 03 05:58:36 PM PDT 24
Peak memory 206912 kb
Host smart-efa7d8e8-9be6-4949-a4e6-6990ea096197
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109178938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4109178938
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2464966073
Short name T297
Test name
Test status
Simulation time 202113214 ps
CPU time 3.78 seconds
Started Jul 03 05:58:35 PM PDT 24
Finished Jul 03 05:58:39 PM PDT 24
Peak memory 207380 kb
Host smart-0178fe56-9786-4b47-af99-0c994502b660
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464966073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2464966073
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1672755309
Short name T632
Test name
Test status
Simulation time 473969208 ps
CPU time 5.72 seconds
Started Jul 03 05:58:34 PM PDT 24
Finished Jul 03 05:58:40 PM PDT 24
Peak memory 209348 kb
Host smart-d0ba8aa0-107a-423e-9e29-de2aa9245ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672755309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1672755309
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2882848411
Short name T432
Test name
Test status
Simulation time 490635600 ps
CPU time 3.14 seconds
Started Jul 03 05:58:30 PM PDT 24
Finished Jul 03 05:58:33 PM PDT 24
Peak memory 208696 kb
Host smart-a44a5eb9-8a29-441b-8570-c540aa30dc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882848411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2882848411
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1922468822
Short name T639
Test name
Test status
Simulation time 239916479 ps
CPU time 7.15 seconds
Started Jul 03 05:58:31 PM PDT 24
Finished Jul 03 05:58:39 PM PDT 24
Peak memory 210400 kb
Host smart-58b6e36e-a6f7-45d0-b17f-397ce71be7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922468822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1922468822
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.968768794
Short name T689
Test name
Test status
Simulation time 146474991 ps
CPU time 2.81 seconds
Started Jul 03 05:58:36 PM PDT 24
Finished Jul 03 05:58:39 PM PDT 24
Peak memory 210256 kb
Host smart-9becc52b-ed2a-4c37-a4a9-a3e219469e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968768794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.968768794
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.337583869
Short name T576
Test name
Test status
Simulation time 37922337 ps
CPU time 0.81 seconds
Started Jul 03 05:58:43 PM PDT 24
Finished Jul 03 05:58:44 PM PDT 24
Peak memory 205972 kb
Host smart-6bdd5d4c-df5e-4ecd-9bfc-8808973065bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337583869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.337583869
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1597043764
Short name T387
Test name
Test status
Simulation time 214423037 ps
CPU time 4.02 seconds
Started Jul 03 05:58:41 PM PDT 24
Finished Jul 03 05:58:45 PM PDT 24
Peak memory 214344 kb
Host smart-c67068ab-ac7f-40eb-8871-95bc3146cece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597043764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1597043764
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.638892479
Short name T820
Test name
Test status
Simulation time 146504346 ps
CPU time 2.89 seconds
Started Jul 03 05:58:44 PM PDT 24
Finished Jul 03 05:58:48 PM PDT 24
Peak memory 221684 kb
Host smart-4ebe70f8-d647-4243-a41d-651b750cfac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638892479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.638892479
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4105334064
Short name T658
Test name
Test status
Simulation time 70550425 ps
CPU time 3.36 seconds
Started Jul 03 05:58:39 PM PDT 24
Finished Jul 03 05:58:43 PM PDT 24
Peak memory 210088 kb
Host smart-bf194ead-7cb0-43f5-a645-93dcb057ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105334064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4105334064
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2050950860
Short name T822
Test name
Test status
Simulation time 38301384 ps
CPU time 2.26 seconds
Started Jul 03 05:58:44 PM PDT 24
Finished Jul 03 05:58:47 PM PDT 24
Peak memory 214388 kb
Host smart-eb905852-e9ed-45fb-a32f-a9ae5899153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050950860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2050950860
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1534493130
Short name T344
Test name
Test status
Simulation time 367449357 ps
CPU time 3.32 seconds
Started Jul 03 05:58:41 PM PDT 24
Finished Jul 03 05:58:45 PM PDT 24
Peak memory 214264 kb
Host smart-e5923ad6-a4b4-47ab-ac76-beeacad68095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534493130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1534493130
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1637590851
Short name T217
Test name
Test status
Simulation time 315129650 ps
CPU time 4.4 seconds
Started Jul 03 05:58:38 PM PDT 24
Finished Jul 03 05:58:43 PM PDT 24
Peak memory 209688 kb
Host smart-177905d1-7188-4d27-9ced-adf6816ceaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637590851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1637590851
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.37749263
Short name T338
Test name
Test status
Simulation time 199022507 ps
CPU time 3.08 seconds
Started Jul 03 05:58:40 PM PDT 24
Finished Jul 03 05:58:43 PM PDT 24
Peak memory 207296 kb
Host smart-26f217a7-5650-476a-9ddf-7ea5416780c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37749263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.37749263
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1334890893
Short name T670
Test name
Test status
Simulation time 556399332 ps
CPU time 2.54 seconds
Started Jul 03 05:58:36 PM PDT 24
Finished Jul 03 05:58:39 PM PDT 24
Peak memory 206156 kb
Host smart-0a0cec28-0f33-49cd-ba7b-059d9d377bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334890893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1334890893
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.762571069
Short name T537
Test name
Test status
Simulation time 481549719 ps
CPU time 4.51 seconds
Started Jul 03 05:58:36 PM PDT 24
Finished Jul 03 05:58:41 PM PDT 24
Peak memory 207968 kb
Host smart-7d480cb1-dc52-481a-8685-36e691891792
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762571069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.762571069
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1935723263
Short name T790
Test name
Test status
Simulation time 79860047 ps
CPU time 3.01 seconds
Started Jul 03 05:58:37 PM PDT 24
Finished Jul 03 05:58:40 PM PDT 24
Peak memory 208720 kb
Host smart-1934753d-7a5a-444a-a8dd-a23dcc64c493
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935723263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1935723263
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1967826908
Short name T434
Test name
Test status
Simulation time 469772203 ps
CPU time 3.6 seconds
Started Jul 03 05:58:36 PM PDT 24
Finished Jul 03 05:58:40 PM PDT 24
Peak memory 209204 kb
Host smart-aa932179-3fb5-4023-ab84-c6712f29dc23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967826908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1967826908
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3367153617
Short name T464
Test name
Test status
Simulation time 280173635 ps
CPU time 3.03 seconds
Started Jul 03 05:58:41 PM PDT 24
Finished Jul 03 05:58:44 PM PDT 24
Peak memory 208696 kb
Host smart-25e61aec-b080-44d0-acc2-fd92547a3224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367153617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3367153617
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.191339267
Short name T635
Test name
Test status
Simulation time 190655994 ps
CPU time 4.02 seconds
Started Jul 03 05:58:38 PM PDT 24
Finished Jul 03 05:58:42 PM PDT 24
Peak memory 208580 kb
Host smart-8f711fce-cbbe-45f8-94fd-c3919cb11519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191339267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.191339267
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.783540900
Short name T358
Test name
Test status
Simulation time 188794958 ps
CPU time 9.62 seconds
Started Jul 03 05:58:39 PM PDT 24
Finished Jul 03 05:58:49 PM PDT 24
Peak memory 216916 kb
Host smart-17d8e72a-9c7e-471e-ba18-a8216e71e151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783540900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.783540900
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3280326419
Short name T606
Test name
Test status
Simulation time 190434690 ps
CPU time 5.25 seconds
Started Jul 03 05:58:44 PM PDT 24
Finished Jul 03 05:58:50 PM PDT 24
Peak memory 218064 kb
Host smart-d9d8d752-9832-4d57-a3a8-b2497b03d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280326419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3280326419
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.912286526
Short name T591
Test name
Test status
Simulation time 86555601 ps
CPU time 1.55 seconds
Started Jul 03 05:58:39 PM PDT 24
Finished Jul 03 05:58:40 PM PDT 24
Peak memory 210000 kb
Host smart-6bbee410-71d3-4d09-91ce-d3b1f39da8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912286526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.912286526
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3708536851
Short name T431
Test name
Test status
Simulation time 10940190 ps
CPU time 0.85 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 206036 kb
Host smart-819972f7-abc0-4599-a753-3b2972f1c2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708536851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3708536851
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3733288320
Short name T178
Test name
Test status
Simulation time 122182553 ps
CPU time 2.17 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:53 PM PDT 24
Peak memory 209064 kb
Host smart-061c204b-2be9-4f1d-8a25-db3ac4ae631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733288320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3733288320
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.75442959
Short name T787
Test name
Test status
Simulation time 743943770 ps
CPU time 2.23 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 208416 kb
Host smart-67f60a16-b4a7-4b6a-9f2e-94c81eb7b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75442959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.75442959
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3367312744
Short name T95
Test name
Test status
Simulation time 318590290 ps
CPU time 4.35 seconds
Started Jul 03 05:58:45 PM PDT 24
Finished Jul 03 05:58:50 PM PDT 24
Peak memory 214664 kb
Host smart-5910ea3e-460a-4440-a83d-1ca5a653d37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367312744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3367312744
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2032062692
Short name T740
Test name
Test status
Simulation time 68494216 ps
CPU time 2.34 seconds
Started Jul 03 05:58:42 PM PDT 24
Finished Jul 03 05:58:45 PM PDT 24
Peak memory 214288 kb
Host smart-d648a62a-1435-4c5c-942e-be12c1c4de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032062692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2032062692
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2082235636
Short name T47
Test name
Test status
Simulation time 549525112 ps
CPU time 2.66 seconds
Started Jul 03 05:58:45 PM PDT 24
Finished Jul 03 05:58:48 PM PDT 24
Peak memory 220100 kb
Host smart-cea709d2-f0f1-4129-af50-1b3f9f8fb43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082235636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2082235636
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1332709133
Short name T821
Test name
Test status
Simulation time 778243812 ps
CPU time 6.82 seconds
Started Jul 03 05:58:42 PM PDT 24
Finished Jul 03 05:58:49 PM PDT 24
Peak memory 210240 kb
Host smart-053174f3-34f6-4cdd-a77b-14cbf8374a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332709133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1332709133
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1424882898
Short name T765
Test name
Test status
Simulation time 106366763 ps
CPU time 2.88 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 206828 kb
Host smart-44b97288-4c65-4b12-9624-f82dd4ed64e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424882898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1424882898
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3408649875
Short name T878
Test name
Test status
Simulation time 53965756 ps
CPU time 1.67 seconds
Started Jul 03 05:58:55 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 206980 kb
Host smart-582241c9-360b-480e-b4db-99ff1263e9cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408649875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3408649875
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4099445827
Short name T92
Test name
Test status
Simulation time 63840570 ps
CPU time 3.26 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 206896 kb
Host smart-7d6e5483-9b52-4f8e-897b-9663590e2461
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099445827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4099445827
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.235563079
Short name T442
Test name
Test status
Simulation time 70285456 ps
CPU time 3.18 seconds
Started Jul 03 05:58:44 PM PDT 24
Finished Jul 03 05:58:47 PM PDT 24
Peak memory 206772 kb
Host smart-bcb150d0-f770-4a3a-b944-be19d1e32066
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235563079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.235563079
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3494845172
Short name T521
Test name
Test status
Simulation time 39250747 ps
CPU time 2.27 seconds
Started Jul 03 05:58:44 PM PDT 24
Finished Jul 03 05:58:47 PM PDT 24
Peak memory 214308 kb
Host smart-9d14012c-3e3b-4c32-a12c-3e303a5b2f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494845172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3494845172
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4219695922
Short name T501
Test name
Test status
Simulation time 116258979 ps
CPU time 4.43 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:51 PM PDT 24
Peak memory 208648 kb
Host smart-44bed3f0-44bd-425f-bb79-1288c2848095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219695922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4219695922
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3213898629
Short name T867
Test name
Test status
Simulation time 790921474 ps
CPU time 24.25 seconds
Started Jul 03 05:58:45 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 221420 kb
Host smart-983d76e3-2a3c-4f96-907e-bad403f9cdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213898629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3213898629
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4267722636
Short name T279
Test name
Test status
Simulation time 159364797 ps
CPU time 3.14 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:50 PM PDT 24
Peak memory 214340 kb
Host smart-27342236-7c97-4d0c-83a4-dbb95247bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267722636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4267722636
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1873499380
Short name T701
Test name
Test status
Simulation time 256322340 ps
CPU time 1.66 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:58 PM PDT 24
Peak memory 209872 kb
Host smart-2bbafbec-8148-4a69-ad9c-0879cb74d7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873499380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1873499380
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.83222922
Short name T13
Test name
Test status
Simulation time 27723927 ps
CPU time 0.79 seconds
Started Jul 03 05:56:24 PM PDT 24
Finished Jul 03 05:56:25 PM PDT 24
Peak memory 206016 kb
Host smart-d480bb41-dbbf-4c91-a1a4-4d7635287f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83222922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.83222922
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1594994344
Short name T404
Test name
Test status
Simulation time 45841403 ps
CPU time 3.41 seconds
Started Jul 03 05:56:22 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 215224 kb
Host smart-4039d8ed-be26-4195-82ba-9e368c0f60c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594994344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1594994344
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3397863593
Short name T748
Test name
Test status
Simulation time 85197508 ps
CPU time 4.32 seconds
Started Jul 03 05:56:23 PM PDT 24
Finished Jul 03 05:56:27 PM PDT 24
Peak memory 221028 kb
Host smart-ccdbd135-7810-49da-9352-6b9b77485cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397863593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3397863593
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4132596023
Short name T726
Test name
Test status
Simulation time 156578933 ps
CPU time 3.2 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:24 PM PDT 24
Peak memory 218348 kb
Host smart-e92032ef-3eec-45a1-bcce-b294cda9c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132596023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4132596023
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2520503435
Short name T506
Test name
Test status
Simulation time 109000536 ps
CPU time 3.12 seconds
Started Jul 03 05:56:23 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 214348 kb
Host smart-d0e4c260-3d85-416f-919b-4eb979f1e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520503435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2520503435
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1790327923
Short name T321
Test name
Test status
Simulation time 84359501 ps
CPU time 3.8 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:25 PM PDT 24
Peak memory 214244 kb
Host smart-034e6152-5e57-483e-8dea-01aa4b059e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790327923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1790327923
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.4121391892
Short name T205
Test name
Test status
Simulation time 470409784 ps
CPU time 8.87 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:30 PM PDT 24
Peak memory 209196 kb
Host smart-4d0035db-7525-4376-b0ff-21c4d9f3f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121391892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4121391892
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1572085111
Short name T570
Test name
Test status
Simulation time 568822568 ps
CPU time 7.06 seconds
Started Jul 03 05:56:22 PM PDT 24
Finished Jul 03 05:56:30 PM PDT 24
Peak memory 208248 kb
Host smart-091d8cd3-7f75-4c3d-a2c3-7b10d9c85a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572085111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1572085111
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1215904907
Short name T596
Test name
Test status
Simulation time 1173512924 ps
CPU time 5.75 seconds
Started Jul 03 05:56:22 PM PDT 24
Finished Jul 03 05:56:28 PM PDT 24
Peak memory 209100 kb
Host smart-9c81ff2d-f973-40c1-982c-b9446ba4e90e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215904907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1215904907
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3402263208
Short name T534
Test name
Test status
Simulation time 47422669 ps
CPU time 1.89 seconds
Started Jul 03 05:56:22 PM PDT 24
Finished Jul 03 05:56:24 PM PDT 24
Peak memory 207396 kb
Host smart-5ff32fd9-7ba8-4d2d-bd30-e306044a9970
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402263208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3402263208
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2390232422
Short name T549
Test name
Test status
Simulation time 120347301 ps
CPU time 2.32 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:24 PM PDT 24
Peak memory 206900 kb
Host smart-7de15b32-4599-4482-8b5d-cf93fcfbf04c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390232422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2390232422
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.877531057
Short name T721
Test name
Test status
Simulation time 91854983 ps
CPU time 2.77 seconds
Started Jul 03 05:56:23 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 209108 kb
Host smart-d5d36d79-37c0-420e-b9e3-07cedabdbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877531057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.877531057
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4098392088
Short name T525
Test name
Test status
Simulation time 135948763 ps
CPU time 3.22 seconds
Started Jul 03 05:56:17 PM PDT 24
Finished Jul 03 05:56:20 PM PDT 24
Peak memory 208456 kb
Host smart-ff5ed3bf-c4be-4d14-8f37-166a5af46393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098392088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4098392088
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1538831881
Short name T75
Test name
Test status
Simulation time 613664643 ps
CPU time 14.47 seconds
Started Jul 03 05:56:25 PM PDT 24
Finished Jul 03 05:56:39 PM PDT 24
Peak memory 215212 kb
Host smart-93d8e0ec-ab27-41e5-8d57-3945637b9a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538831881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1538831881
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.604484539
Short name T238
Test name
Test status
Simulation time 2496782018 ps
CPU time 22.07 seconds
Started Jul 03 05:56:24 PM PDT 24
Finished Jul 03 05:56:46 PM PDT 24
Peak memory 222692 kb
Host smart-b6231faa-2271-41c6-90da-e96a7ea1e546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604484539 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.604484539
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.615329366
Short name T531
Test name
Test status
Simulation time 129482408 ps
CPU time 3.64 seconds
Started Jul 03 05:56:23 PM PDT 24
Finished Jul 03 05:56:27 PM PDT 24
Peak memory 208076 kb
Host smart-54b81a0a-7a2f-4e40-9082-cc402897cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615329366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.615329366
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2013147922
Short name T704
Test name
Test status
Simulation time 171127055 ps
CPU time 2.75 seconds
Started Jul 03 05:56:21 PM PDT 24
Finished Jul 03 05:56:24 PM PDT 24
Peak memory 209888 kb
Host smart-dc344feb-2221-435a-975c-74b8c6dc4a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013147922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2013147922
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.836100186
Short name T520
Test name
Test status
Simulation time 70350011 ps
CPU time 0.99 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 05:58:55 PM PDT 24
Peak memory 206112 kb
Host smart-f0641b15-8c3d-4a7a-a3a3-6caf1b3694b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836100186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.836100186
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.181070057
Short name T837
Test name
Test status
Simulation time 227578157 ps
CPU time 3.37 seconds
Started Jul 03 05:58:47 PM PDT 24
Finished Jul 03 05:58:51 PM PDT 24
Peak memory 214308 kb
Host smart-0e2b5f8d-4620-47f0-bebc-c6d7f38e21ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181070057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.181070057
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.848408016
Short name T806
Test name
Test status
Simulation time 92207888 ps
CPU time 2.43 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:53 PM PDT 24
Peak memory 214788 kb
Host smart-2dba1f21-9d3d-439a-af18-072c1f0a4d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848408016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.848408016
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2770614136
Short name T527
Test name
Test status
Simulation time 904238389 ps
CPU time 3.46 seconds
Started Jul 03 05:58:48 PM PDT 24
Finished Jul 03 05:58:52 PM PDT 24
Peak memory 208580 kb
Host smart-6fd0a08b-68f8-4356-82eb-e09bb37adbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770614136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2770614136
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2193576959
Short name T686
Test name
Test status
Simulation time 515925587 ps
CPU time 5.46 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:52 PM PDT 24
Peak memory 214380 kb
Host smart-7fe32385-ec37-420f-b180-b8eda188352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193576959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2193576959
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3883115205
Short name T343
Test name
Test status
Simulation time 132934458 ps
CPU time 2.43 seconds
Started Jul 03 05:58:49 PM PDT 24
Finished Jul 03 05:58:51 PM PDT 24
Peak memory 214384 kb
Host smart-07db2875-287d-400a-a47c-d447d562a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883115205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3883115205
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.995722693
Short name T224
Test name
Test status
Simulation time 177888920 ps
CPU time 3.25 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 210436 kb
Host smart-9a2bd58b-c171-4099-87de-f9e945dc9d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995722693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.995722693
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2973007183
Short name T412
Test name
Test status
Simulation time 788837975 ps
CPU time 7.31 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 208348 kb
Host smart-e23fb30b-9d1e-4667-b46d-544ed612881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973007183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2973007183
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.282539666
Short name T34
Test name
Test status
Simulation time 175046252 ps
CPU time 4.98 seconds
Started Jul 03 05:58:47 PM PDT 24
Finished Jul 03 05:58:53 PM PDT 24
Peak memory 208528 kb
Host smart-0b5621c4-e03b-4882-8898-ee8e74682bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282539666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.282539666
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4066343293
Short name T706
Test name
Test status
Simulation time 44312558 ps
CPU time 2.33 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:49 PM PDT 24
Peak memory 206940 kb
Host smart-df7a4a73-fbab-42c3-8f1f-f7743fe0b4d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066343293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4066343293
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.479885364
Short name T573
Test name
Test status
Simulation time 329747284 ps
CPU time 3.47 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:50 PM PDT 24
Peak memory 208696 kb
Host smart-3e3aa05a-87b3-4c38-b226-569571b003cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479885364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.479885364
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2768290624
Short name T733
Test name
Test status
Simulation time 2348357239 ps
CPU time 23.77 seconds
Started Jul 03 05:58:47 PM PDT 24
Finished Jul 03 05:59:11 PM PDT 24
Peak memory 208640 kb
Host smart-4195cb63-7a72-4812-9808-716746901139
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768290624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2768290624
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4273305776
Short name T645
Test name
Test status
Simulation time 132945504 ps
CPU time 2.91 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 215780 kb
Host smart-545dc0e4-3425-4633-acd4-c8f172b4f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273305776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4273305776
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1471355679
Short name T449
Test name
Test status
Simulation time 57064631 ps
CPU time 2.48 seconds
Started Jul 03 05:58:46 PM PDT 24
Finished Jul 03 05:58:49 PM PDT 24
Peak memory 208048 kb
Host smart-b28f43da-d8f8-4cf3-b6c4-2236593efca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471355679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1471355679
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1117098001
Short name T274
Test name
Test status
Simulation time 13036010784 ps
CPU time 88.34 seconds
Started Jul 03 05:58:51 PM PDT 24
Finished Jul 03 06:00:20 PM PDT 24
Peak memory 215368 kb
Host smart-72202b88-f5d8-473d-a40e-82093e00b669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117098001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1117098001
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2782315862
Short name T712
Test name
Test status
Simulation time 230937632 ps
CPU time 3.99 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:55 PM PDT 24
Peak memory 218180 kb
Host smart-dd406cc7-1617-4e82-902e-04020c3fc5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782315862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2782315862
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2613515868
Short name T819
Test name
Test status
Simulation time 94753867 ps
CPU time 2.48 seconds
Started Jul 03 05:58:51 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 210776 kb
Host smart-094250d6-dbf4-4130-a2c5-ca51c15df964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613515868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2613515868
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3942009280
Short name T111
Test name
Test status
Simulation time 17905159 ps
CPU time 0.97 seconds
Started Jul 03 05:58:52 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 206112 kb
Host smart-284e87d4-962a-4a7c-8aa3-1d78517252a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942009280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3942009280
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1327832723
Short name T624
Test name
Test status
Simulation time 310101877 ps
CPU time 1.77 seconds
Started Jul 03 05:58:52 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 214212 kb
Host smart-df80ceb1-cfaa-4aa6-8c49-e15fda6a19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327832723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1327832723
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2533171171
Short name T73
Test name
Test status
Simulation time 992450382 ps
CPU time 5.58 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:03 PM PDT 24
Peak memory 210012 kb
Host smart-c2a02d7d-964b-4ac4-a304-bfb20f875a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533171171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2533171171
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1887208765
Short name T108
Test name
Test status
Simulation time 178574268 ps
CPU time 3.21 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 214328 kb
Host smart-db8661f1-d857-4f30-bc80-b4c2fb30d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887208765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1887208765
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1672827150
Short name T325
Test name
Test status
Simulation time 67676714 ps
CPU time 2.68 seconds
Started Jul 03 05:58:51 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 206064 kb
Host smart-b00e2bda-efb0-4cb8-b4e1-3051b67102ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672827150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1672827150
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.722901773
Short name T220
Test name
Test status
Simulation time 178365829 ps
CPU time 4.42 seconds
Started Jul 03 05:58:55 PM PDT 24
Finished Jul 03 05:59:00 PM PDT 24
Peak memory 210244 kb
Host smart-3eb567c5-976c-4ae2-983b-bcb243d29376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722901773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.722901773
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.202449248
Short name T750
Test name
Test status
Simulation time 333801602 ps
CPU time 4.77 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 208380 kb
Host smart-bc1dfd86-74b1-441e-a446-1e09633f0ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202449248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.202449248
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.397937529
Short name T756
Test name
Test status
Simulation time 432232220 ps
CPU time 4.31 seconds
Started Jul 03 05:58:48 PM PDT 24
Finished Jul 03 05:58:52 PM PDT 24
Peak memory 208488 kb
Host smart-e2315dc3-e367-4564-b70e-5f1bb8ed3e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397937529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.397937529
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4068892726
Short name T467
Test name
Test status
Simulation time 89452104 ps
CPU time 3.68 seconds
Started Jul 03 05:58:51 PM PDT 24
Finished Jul 03 05:58:55 PM PDT 24
Peak memory 208756 kb
Host smart-01941fe0-2689-4490-9cbf-d55bc7c9870f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068892726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4068892726
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3047111755
Short name T559
Test name
Test status
Simulation time 1350073315 ps
CPU time 23.69 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:59:20 PM PDT 24
Peak memory 208096 kb
Host smart-26acef3a-dcbb-4680-b6b2-8c7151687b54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047111755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3047111755
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3837172360
Short name T804
Test name
Test status
Simulation time 2997538786 ps
CPU time 16.48 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 208036 kb
Host smart-b387ec71-8622-4e87-ad7f-972d5b7b9240
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837172360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3837172360
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2903758548
Short name T498
Test name
Test status
Simulation time 81346790 ps
CPU time 2.61 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 207340 kb
Host smart-a4f09a55-3439-4185-89d6-3e4eff6f5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903758548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2903758548
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3074432700
Short name T436
Test name
Test status
Simulation time 86393930 ps
CPU time 2.27 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 05:58:55 PM PDT 24
Peak memory 206980 kb
Host smart-3af600c6-8a3c-4353-921e-bed385d5d3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074432700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3074432700
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2734680106
Short name T486
Test name
Test status
Simulation time 158552884 ps
CPU time 4.56 seconds
Started Jul 03 05:58:50 PM PDT 24
Finished Jul 03 05:58:56 PM PDT 24
Peak memory 208144 kb
Host smart-bbde228e-cac0-4534-8434-6cd62033ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734680106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2734680106
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.663286174
Short name T753
Test name
Test status
Simulation time 110933619 ps
CPU time 2.51 seconds
Started Jul 03 05:58:55 PM PDT 24
Finished Jul 03 05:58:58 PM PDT 24
Peak memory 210004 kb
Host smart-13ceb1e1-a045-40d7-8f51-a53d99ea0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663286174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.663286174
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4075742842
Short name T735
Test name
Test status
Simulation time 13246677 ps
CPU time 0.81 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:58:58 PM PDT 24
Peak memory 205908 kb
Host smart-5630f407-28ac-4415-bc23-b92cec3772d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075742842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4075742842
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.787382599
Short name T142
Test name
Test status
Simulation time 876216077 ps
CPU time 5.09 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:03 PM PDT 24
Peak memory 215232 kb
Host smart-f878c73d-c4f2-4451-8f1f-2badcdfeb2b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787382599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.787382599
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3074090450
Short name T759
Test name
Test status
Simulation time 391262671 ps
CPU time 5.31 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 216668 kb
Host smart-fb83172a-249d-4f52-b63d-1c6de30e1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074090450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3074090450
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2705696874
Short name T664
Test name
Test status
Simulation time 140783723 ps
CPU time 2.39 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:00 PM PDT 24
Peak memory 207640 kb
Host smart-da326526-ae8b-4e01-9fca-fb9933281c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705696874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2705696874
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1742858148
Short name T839
Test name
Test status
Simulation time 613954427 ps
CPU time 4.32 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 208764 kb
Host smart-6648879e-2704-40b7-9a32-73e85da256a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742858148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1742858148
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3414729982
Short name T587
Test name
Test status
Simulation time 42302645 ps
CPU time 2.15 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 217336 kb
Host smart-d3902d62-e2e3-4962-a574-0ae2bf9798a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414729982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3414729982
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.783830812
Short name T416
Test name
Test status
Simulation time 71895281 ps
CPU time 3.19 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 214828 kb
Host smart-4e097b70-f0cf-4ed7-9400-250084d8f2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783830812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.783830812
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.294826510
Short name T892
Test name
Test status
Simulation time 1006445483 ps
CPU time 4.16 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:58 PM PDT 24
Peak memory 207476 kb
Host smart-4a86640d-fdc3-4494-85d7-abc3a4ae6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294826510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.294826510
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.599586741
Short name T478
Test name
Test status
Simulation time 109375430 ps
CPU time 2.79 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 208136 kb
Host smart-8ead7f04-f04d-4503-9cd1-8b1d7c8ee5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599586741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.599586741
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1263128608
Short name T841
Test name
Test status
Simulation time 248849317 ps
CPU time 2.77 seconds
Started Jul 03 05:58:51 PM PDT 24
Finished Jul 03 05:58:54 PM PDT 24
Peak memory 207048 kb
Host smart-58b1d348-3c00-4e1c-af13-0325a286dbd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263128608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1263128608
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2348815915
Short name T616
Test name
Test status
Simulation time 47578019 ps
CPU time 2.39 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:57 PM PDT 24
Peak memory 207784 kb
Host smart-eb2998fc-2d69-4c19-a588-7f88632b2d7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348815915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2348815915
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.930438959
Short name T568
Test name
Test status
Simulation time 292236459 ps
CPU time 7.05 seconds
Started Jul 03 05:58:53 PM PDT 24
Finished Jul 03 05:59:01 PM PDT 24
Peak memory 208768 kb
Host smart-27f392b0-003f-4dce-80a1-2ab52dbd25f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930438959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.930438959
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3358107966
Short name T396
Test name
Test status
Simulation time 36416209 ps
CPU time 1.82 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 209568 kb
Host smart-d9c6198d-1664-4408-bee4-a403aea61aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358107966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3358107966
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3549657664
Short name T466
Test name
Test status
Simulation time 349863067 ps
CPU time 3.94 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:58 PM PDT 24
Peak memory 206828 kb
Host smart-a18af233-e9c0-4d9a-bb06-8eb6bbe51c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549657664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3549657664
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.659315827
Short name T6
Test name
Test status
Simulation time 2686040254 ps
CPU time 32.65 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:30 PM PDT 24
Peak memory 220488 kb
Host smart-4e90b474-ae55-4b21-9547-8609a1ca68f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659315827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.659315827
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2921075361
Short name T355
Test name
Test status
Simulation time 549195898 ps
CPU time 19.4 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:59:16 PM PDT 24
Peak memory 222372 kb
Host smart-e1e649ab-7fa8-4974-93a8-c3e4bcf103c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921075361 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2921075361
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2690367936
Short name T318
Test name
Test status
Simulation time 96947230 ps
CPU time 4.59 seconds
Started Jul 03 05:58:54 PM PDT 24
Finished Jul 03 05:58:59 PM PDT 24
Peak memory 218216 kb
Host smart-b1d40e61-f3da-4b01-8c3b-5c754bc88c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690367936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2690367936
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1826318643
Short name T469
Test name
Test status
Simulation time 77731947 ps
CPU time 2.18 seconds
Started Jul 03 05:58:58 PM PDT 24
Finished Jul 03 05:59:00 PM PDT 24
Peak memory 210152 kb
Host smart-3c698b10-a8b9-49df-9344-e79912a0f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826318643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1826318643
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.498667567
Short name T797
Test name
Test status
Simulation time 15650757 ps
CPU time 0.76 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 206020 kb
Host smart-9e76541d-15a1-412d-864d-f86f8505b71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498667567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.498667567
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1245367844
Short name T25
Test name
Test status
Simulation time 1220397067 ps
CPU time 5.52 seconds
Started Jul 03 05:59:02 PM PDT 24
Finished Jul 03 05:59:08 PM PDT 24
Peak memory 222884 kb
Host smart-f1f73e1d-3315-4cf7-a3cb-e0adf61b5e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245367844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1245367844
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.359299365
Short name T79
Test name
Test status
Simulation time 55814976 ps
CPU time 2.33 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:04 PM PDT 24
Peak memory 214424 kb
Host smart-069777d2-a8a7-4977-90a7-fc747a5a4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359299365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.359299365
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1337850066
Short name T303
Test name
Test status
Simulation time 141982628 ps
CPU time 2.56 seconds
Started Jul 03 05:58:59 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 214372 kb
Host smart-3b196f3d-cafc-47e1-8639-54e27f294936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337850066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1337850066
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1106937838
Short name T827
Test name
Test status
Simulation time 231413635 ps
CPU time 5.1 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:07 PM PDT 24
Peak memory 220408 kb
Host smart-5c741fbf-d030-4be6-a8f1-f359dfb74b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106937838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1106937838
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2342402550
Short name T257
Test name
Test status
Simulation time 258693504 ps
CPU time 3.29 seconds
Started Jul 03 05:58:58 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 209624 kb
Host smart-c8fba68a-f21d-4505-8d27-182dc53ceade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342402550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2342402550
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.4275680081
Short name T202
Test name
Test status
Simulation time 1230645976 ps
CPU time 8.38 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 214340 kb
Host smart-1832e44c-695b-42cd-845e-eba74c3f2383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275680081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.4275680081
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2810631329
Short name T676
Test name
Test status
Simulation time 1289778436 ps
CPU time 15.59 seconds
Started Jul 03 05:58:56 PM PDT 24
Finished Jul 03 05:59:12 PM PDT 24
Peak memory 207896 kb
Host smart-3e51661f-335d-47a0-b832-7c26018a82eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810631329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2810631329
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.63251745
Short name T772
Test name
Test status
Simulation time 167349584 ps
CPU time 3.47 seconds
Started Jul 03 05:58:58 PM PDT 24
Finished Jul 03 05:59:02 PM PDT 24
Peak memory 208964 kb
Host smart-b1fad6b1-ac4f-41ad-9206-e39729630ece
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63251745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.63251745
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.459380032
Short name T456
Test name
Test status
Simulation time 109136368 ps
CPU time 3.58 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:01 PM PDT 24
Peak memory 208452 kb
Host smart-8c5fa391-679e-4e13-8198-7d041f09b200
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459380032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.459380032
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.427604373
Short name T593
Test name
Test status
Simulation time 191960439 ps
CPU time 2.86 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:00 PM PDT 24
Peak memory 207008 kb
Host smart-05e4b118-bf2f-4512-b3a2-4341fba7532f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427604373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.427604373
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1897819087
Short name T646
Test name
Test status
Simulation time 81319310 ps
CPU time 1.6 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:03 PM PDT 24
Peak memory 218264 kb
Host smart-1a97f5c9-2d17-45ff-9a86-4503c7df8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897819087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1897819087
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3384150311
Short name T846
Test name
Test status
Simulation time 250455724 ps
CPU time 3.04 seconds
Started Jul 03 05:58:57 PM PDT 24
Finished Jul 03 05:59:01 PM PDT 24
Peak memory 207328 kb
Host smart-f75d8302-efda-42a9-a620-4b6ef57352f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384150311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3384150311
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4198853568
Short name T830
Test name
Test status
Simulation time 14106055587 ps
CPU time 40.14 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:42 PM PDT 24
Peak memory 222460 kb
Host smart-1896186b-c2df-4380-9e3a-f45c88dceab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198853568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4198853568
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2493388485
Short name T223
Test name
Test status
Simulation time 3535779378 ps
CPU time 11.32 seconds
Started Jul 03 05:59:01 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 220700 kb
Host smart-531914e0-2f29-43e2-9545-c177d2028c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493388485 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2493388485
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1631156756
Short name T851
Test name
Test status
Simulation time 185384981 ps
CPU time 4.5 seconds
Started Jul 03 05:58:58 PM PDT 24
Finished Jul 03 05:59:03 PM PDT 24
Peak memory 209544 kb
Host smart-e5d69be1-17e8-4b09-8bb1-a8ba586f1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631156756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1631156756
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2124502659
Short name T715
Test name
Test status
Simulation time 20882742 ps
CPU time 1.46 seconds
Started Jul 03 05:59:02 PM PDT 24
Finished Jul 03 05:59:04 PM PDT 24
Peak memory 209544 kb
Host smart-eb2e91e0-9bbf-4bb9-9cfe-a526aac12df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124502659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2124502659
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3637245799
Short name T428
Test name
Test status
Simulation time 46028848 ps
CPU time 0.89 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:09 PM PDT 24
Peak memory 205996 kb
Host smart-d50420c4-01b6-4da7-a008-44330e65c239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637245799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3637245799
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2111705388
Short name T83
Test name
Test status
Simulation time 512155804 ps
CPU time 3.29 seconds
Started Jul 03 05:59:04 PM PDT 24
Finished Jul 03 05:59:08 PM PDT 24
Peak memory 214340 kb
Host smart-465a4ce9-603e-4cc4-a594-9368f7e0f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111705388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2111705388
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3203569754
Short name T53
Test name
Test status
Simulation time 83162343 ps
CPU time 3.34 seconds
Started Jul 03 05:59:03 PM PDT 24
Finished Jul 03 05:59:07 PM PDT 24
Peak memory 214284 kb
Host smart-f2574cb7-6be9-411e-88bb-20a2911ebcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203569754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3203569754
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3307613189
Short name T261
Test name
Test status
Simulation time 80169584 ps
CPU time 2.46 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:12 PM PDT 24
Peak memory 207232 kb
Host smart-8f811465-557e-4cdf-9098-328c6c5a4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307613189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3307613189
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_random.2648261914
Short name T507
Test name
Test status
Simulation time 396901111 ps
CPU time 5.21 seconds
Started Jul 03 05:59:04 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 208256 kb
Host smart-63f92656-7e07-4ef4-a89c-22fc1622db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648261914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2648261914
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.164257247
Short name T803
Test name
Test status
Simulation time 532094698 ps
CPU time 2.8 seconds
Started Jul 03 05:59:07 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 208296 kb
Host smart-e5a69364-f484-4a85-92d9-5cc3cb47c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164257247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.164257247
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2360542806
Short name T705
Test name
Test status
Simulation time 384765728 ps
CPU time 5.91 seconds
Started Jul 03 05:59:03 PM PDT 24
Finished Jul 03 05:59:09 PM PDT 24
Peak memory 208636 kb
Host smart-b1f1010a-990d-4b84-9fd2-df9666c255d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360542806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2360542806
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.13535897
Short name T592
Test name
Test status
Simulation time 203023917 ps
CPU time 3.4 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:11 PM PDT 24
Peak memory 208116 kb
Host smart-4bcac7b7-d898-431f-9ef3-a7a1a0a5f2e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.13535897
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3293083406
Short name T888
Test name
Test status
Simulation time 1122581169 ps
CPU time 8.79 seconds
Started Jul 03 05:59:04 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 208560 kb
Host smart-29341fff-ed63-4894-9c6c-f7090075a478
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293083406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3293083406
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.900359384
Short name T614
Test name
Test status
Simulation time 158906523 ps
CPU time 2.32 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:10 PM PDT 24
Peak memory 218292 kb
Host smart-41cc4c5c-04ea-46e6-b116-2c3c734a03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900359384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.900359384
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.725805275
Short name T832
Test name
Test status
Simulation time 162786959 ps
CPU time 2.62 seconds
Started Jul 03 05:59:04 PM PDT 24
Finished Jul 03 05:59:07 PM PDT 24
Peak memory 206792 kb
Host smart-e01c4658-293c-4ed2-8bb2-09aff360f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725805275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.725805275
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2052888470
Short name T373
Test name
Test status
Simulation time 501231206 ps
CPU time 2.79 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 222492 kb
Host smart-f4a5b2ed-bd17-4050-89d6-6e2aca9d1a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052888470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2052888470
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4102462575
Short name T17
Test name
Test status
Simulation time 86905453 ps
CPU time 3.33 seconds
Started Jul 03 05:59:02 PM PDT 24
Finished Jul 03 05:59:06 PM PDT 24
Peak memory 210192 kb
Host smart-0415cab3-e2a3-47a4-b5da-76d3274c1127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102462575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4102462575
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2570380941
Short name T648
Test name
Test status
Simulation time 52502051 ps
CPU time 0.78 seconds
Started Jul 03 05:59:11 PM PDT 24
Finished Jul 03 05:59:12 PM PDT 24
Peak memory 205988 kb
Host smart-d7f51885-1a9a-4958-80fd-b4c4ad3224a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570380941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2570380941
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3970361659
Short name T418
Test name
Test status
Simulation time 110672060 ps
CPU time 6.15 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:23 PM PDT 24
Peak memory 215324 kb
Host smart-3e088295-6a82-4c3a-b718-5ba8e542e212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970361659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3970361659
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1776689984
Short name T275
Test name
Test status
Simulation time 327260954 ps
CPU time 2.85 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 209276 kb
Host smart-4490166c-8a4e-435a-9b61-a506a47f943e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776689984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1776689984
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2998718274
Short name T96
Test name
Test status
Simulation time 219819507 ps
CPU time 3.26 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 214852 kb
Host smart-4e33e009-3325-4105-ad82-183e3e64e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998718274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2998718274
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3965480980
Short name T100
Test name
Test status
Simulation time 168165898 ps
CPU time 2.45 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:19 PM PDT 24
Peak memory 214492 kb
Host smart-ac39c8fe-ddf7-4396-b288-0286a9295d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965480980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3965480980
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1400364644
Short name T5
Test name
Test status
Simulation time 444088726 ps
CPU time 2.85 seconds
Started Jul 03 05:59:17 PM PDT 24
Finished Jul 03 05:59:20 PM PDT 24
Peak memory 209304 kb
Host smart-5ef422b1-dc0c-45e0-81b9-755909a8bbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400364644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1400364644
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.822000549
Short name T204
Test name
Test status
Simulation time 1046894334 ps
CPU time 8.05 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:16 PM PDT 24
Peak memory 207480 kb
Host smart-bf904e78-20f8-4e3e-89c0-c8801ccaf84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822000549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.822000549
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1970700089
Short name T807
Test name
Test status
Simulation time 80919572 ps
CPU time 2.9 seconds
Started Jul 03 05:59:09 PM PDT 24
Finished Jul 03 05:59:12 PM PDT 24
Peak memory 208728 kb
Host smart-f9355104-0d04-45d6-b4cf-b2d85a5d3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970700089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1970700089
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.585526780
Short name T723
Test name
Test status
Simulation time 224126217 ps
CPU time 5.13 seconds
Started Jul 03 05:59:09 PM PDT 24
Finished Jul 03 05:59:14 PM PDT 24
Peak memory 206844 kb
Host smart-2e53073e-daa3-4208-96c5-06eb59f538dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585526780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.585526780
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3600267288
Short name T858
Test name
Test status
Simulation time 203506232 ps
CPU time 2.6 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:11 PM PDT 24
Peak memory 207000 kb
Host smart-33e4426a-f709-4e8f-8276-4441e0f17f05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600267288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3600267288
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1083864112
Short name T186
Test name
Test status
Simulation time 403609685 ps
CPU time 2.74 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 206988 kb
Host smart-9c440238-ad13-48ed-8470-0009ffa166d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083864112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1083864112
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.855838870
Short name T776
Test name
Test status
Simulation time 777269562 ps
CPU time 17.54 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 210244 kb
Host smart-1e2827d2-b1bb-4144-b483-26d222b14502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855838870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.855838870
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2342105588
Short name T390
Test name
Test status
Simulation time 357578840 ps
CPU time 7.33 seconds
Started Jul 03 05:59:08 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 209080 kb
Host smart-38474959-4667-46e9-a2d6-24de1bb4018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342105588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2342105588
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2382836731
Short name T667
Test name
Test status
Simulation time 969589291 ps
CPU time 14.04 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:26 PM PDT 24
Peak memory 214988 kb
Host smart-2dd5f80e-5944-475a-aaaf-011f4d7f1203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382836731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2382836731
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4173774258
Short name T389
Test name
Test status
Simulation time 119404235 ps
CPU time 5.47 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:22 PM PDT 24
Peak memory 207804 kb
Host smart-4d5abc9d-c0cc-45f5-a0da-d455ac559a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173774258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4173774258
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.372968349
Short name T1
Test name
Test status
Simulation time 131349285 ps
CPU time 2.84 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 210384 kb
Host smart-af1a34e7-8260-4486-882a-3be5de2d31e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372968349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.372968349
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.678894405
Short name T443
Test name
Test status
Simulation time 46421533 ps
CPU time 0.9 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:14 PM PDT 24
Peak memory 206004 kb
Host smart-212d305a-c97b-4a63-a6e2-916d266163d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678894405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.678894405
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3886818431
Short name T405
Test name
Test status
Simulation time 391734062 ps
CPU time 5.31 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:16 PM PDT 24
Peak memory 214308 kb
Host smart-3092d072-3158-4955-8989-7c00fdf52a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886818431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3886818431
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2301001700
Short name T504
Test name
Test status
Simulation time 75783005 ps
CPU time 3.33 seconds
Started Jul 03 05:59:13 PM PDT 24
Finished Jul 03 05:59:17 PM PDT 24
Peak memory 222760 kb
Host smart-3732aa8b-f744-45d7-aad9-01974ded83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301001700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2301001700
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3250013265
Short name T569
Test name
Test status
Simulation time 44342667 ps
CPU time 1.77 seconds
Started Jul 03 05:59:12 PM PDT 24
Finished Jul 03 05:59:14 PM PDT 24
Peak memory 214428 kb
Host smart-30a7fdf9-43e9-45b7-8723-1797726b9176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250013265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3250013265
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4135693823
Short name T94
Test name
Test status
Simulation time 958723222 ps
CPU time 5.09 seconds
Started Jul 03 05:59:20 PM PDT 24
Finished Jul 03 05:59:25 PM PDT 24
Peak memory 214344 kb
Host smart-04168050-9295-49c8-8a45-120bdef5b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135693823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4135693823
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1597044820
Short name T680
Test name
Test status
Simulation time 105837678 ps
CPU time 3.46 seconds
Started Jul 03 05:59:14 PM PDT 24
Finished Jul 03 05:59:18 PM PDT 24
Peak memory 210028 kb
Host smart-a5a7cd03-b620-4a0b-8e6f-3cfbb5129384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597044820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1597044820
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3758500224
Short name T300
Test name
Test status
Simulation time 467750513 ps
CPU time 5.65 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:22 PM PDT 24
Peak memory 209544 kb
Host smart-6d2fc050-3f22-49ad-b0eb-43b3fc917cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758500224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3758500224
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3495660810
Short name T207
Test name
Test status
Simulation time 353336018 ps
CPU time 4.1 seconds
Started Jul 03 05:59:11 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 206852 kb
Host smart-20a3bb20-71ca-4154-a59b-b251c726ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495660810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3495660810
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.670887321
Short name T774
Test name
Test status
Simulation time 146180382 ps
CPU time 2.35 seconds
Started Jul 03 05:59:10 PM PDT 24
Finished Jul 03 05:59:13 PM PDT 24
Peak memory 207000 kb
Host smart-1f902004-d9aa-40e6-8f87-293281bcf19d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670887321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.670887321
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1175360593
Short name T780
Test name
Test status
Simulation time 676661568 ps
CPU time 19.64 seconds
Started Jul 03 05:59:11 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 209060 kb
Host smart-fd2403a9-dba2-48fa-b177-d9abb8472657
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175360593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1175360593
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3229297627
Short name T861
Test name
Test status
Simulation time 53245302 ps
CPU time 2.79 seconds
Started Jul 03 05:59:11 PM PDT 24
Finished Jul 03 05:59:15 PM PDT 24
Peak memory 208844 kb
Host smart-7b3ad49d-004c-4777-a0e9-b799059c77e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229297627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3229297627
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2675682475
Short name T685
Test name
Test status
Simulation time 155279659 ps
CPU time 2.12 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:21 PM PDT 24
Peak memory 209496 kb
Host smart-e1ffb5ad-c6ba-44ec-b5f0-fef168275600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675682475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2675682475
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1539502467
Short name T392
Test name
Test status
Simulation time 40658968 ps
CPU time 1.77 seconds
Started Jul 03 05:59:14 PM PDT 24
Finished Jul 03 05:59:16 PM PDT 24
Peak memory 207312 kb
Host smart-e94a6db7-4adc-4002-ae47-85f29d995225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539502467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1539502467
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.289906450
Short name T234
Test name
Test status
Simulation time 10937363742 ps
CPU time 81.57 seconds
Started Jul 03 05:59:13 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 222528 kb
Host smart-3135fa8b-5e0f-4453-8ba9-e278910fecea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289906450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.289906450
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.612571848
Short name T374
Test name
Test status
Simulation time 1568144514 ps
CPU time 33.57 seconds
Started Jul 03 05:59:14 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 208668 kb
Host smart-3ac490d4-9a14-4cea-a634-1ed9ec834f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612571848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.612571848
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2312969770
Short name T739
Test name
Test status
Simulation time 43677537 ps
CPU time 2.19 seconds
Started Jul 03 05:59:15 PM PDT 24
Finished Jul 03 05:59:18 PM PDT 24
Peak memory 209868 kb
Host smart-2dcf8991-eb75-478d-a89b-bc8019859366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312969770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2312969770
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.349662270
Short name T695
Test name
Test status
Simulation time 25321891 ps
CPU time 0.76 seconds
Started Jul 03 05:59:23 PM PDT 24
Finished Jul 03 05:59:24 PM PDT 24
Peak memory 205984 kb
Host smart-dd6e9750-b3ba-4454-afd2-5a7e28e8845d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349662270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.349662270
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1698538857
Short name T19
Test name
Test status
Simulation time 82931429 ps
CPU time 1.92 seconds
Started Jul 03 05:59:19 PM PDT 24
Finished Jul 03 05:59:21 PM PDT 24
Peak memory 214704 kb
Host smart-48c57049-94b8-49c0-9d42-3685dda5fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698538857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1698538857
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3470251602
Short name T458
Test name
Test status
Simulation time 144812262 ps
CPU time 3.54 seconds
Started Jul 03 05:59:17 PM PDT 24
Finished Jul 03 05:59:20 PM PDT 24
Peak memory 214308 kb
Host smart-38b110fc-a0be-4274-8781-7ffc03595b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470251602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3470251602
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2319508385
Short name T324
Test name
Test status
Simulation time 208187359 ps
CPU time 2.83 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:19 PM PDT 24
Peak memory 214292 kb
Host smart-b70fc3db-64ad-47e4-ba44-b7c38de51ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319508385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2319508385
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4171499970
Short name T260
Test name
Test status
Simulation time 108832598 ps
CPU time 3.38 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:22 PM PDT 24
Peak memory 214272 kb
Host smart-b2d76c96-91fc-4da5-99b7-b8d2ba2bc809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171499970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4171499970
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3460323315
Short name T46
Test name
Test status
Simulation time 115567347 ps
CPU time 2.54 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:19 PM PDT 24
Peak memory 214288 kb
Host smart-a2be69bb-e0e6-45d2-8115-9a0b459d709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460323315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3460323315
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.585800567
Short name T641
Test name
Test status
Simulation time 107223658 ps
CPU time 4.56 seconds
Started Jul 03 05:59:13 PM PDT 24
Finished Jul 03 05:59:18 PM PDT 24
Peak memory 214320 kb
Host smart-86308212-d558-467a-94f7-1fcc5aeecf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585800567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.585800567
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2032589495
Short name T602
Test name
Test status
Simulation time 1340806142 ps
CPU time 13.64 seconds
Started Jul 03 05:59:21 PM PDT 24
Finished Jul 03 05:59:35 PM PDT 24
Peak memory 208456 kb
Host smart-18f6c342-f950-41c3-991d-d1696c1029ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032589495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2032589495
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1573225048
Short name T894
Test name
Test status
Simulation time 179320741 ps
CPU time 2.46 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:19 PM PDT 24
Peak memory 206936 kb
Host smart-2fb0d843-6e0a-4e83-8ce3-478281d9a328
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573225048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1573225048
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.583659181
Short name T621
Test name
Test status
Simulation time 36090286 ps
CPU time 2.59 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:21 PM PDT 24
Peak memory 207452 kb
Host smart-2f8d5319-408f-46ce-9182-4d481fa86a4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583659181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.583659181
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2455148785
Short name T327
Test name
Test status
Simulation time 8665337598 ps
CPU time 44.34 seconds
Started Jul 03 05:59:15 PM PDT 24
Finished Jul 03 05:59:59 PM PDT 24
Peak memory 208744 kb
Host smart-97bb2cbd-9d1d-439a-aa57-9585a87a84d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455148785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2455148785
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.358120905
Short name T710
Test name
Test status
Simulation time 224421305 ps
CPU time 3.02 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:21 PM PDT 24
Peak memory 214300 kb
Host smart-540eabca-b318-4109-871c-0387a1e91be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358120905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.358120905
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1487892036
Short name T483
Test name
Test status
Simulation time 223923418 ps
CPU time 2.74 seconds
Started Jul 03 05:59:16 PM PDT 24
Finished Jul 03 05:59:19 PM PDT 24
Peak memory 208744 kb
Host smart-20b95a9c-e1d2-4d83-b2e3-82064adef04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487892036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1487892036
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.368906141
Short name T709
Test name
Test status
Simulation time 322328336 ps
CPU time 4.99 seconds
Started Jul 03 05:59:23 PM PDT 24
Finished Jul 03 05:59:28 PM PDT 24
Peak memory 220984 kb
Host smart-1cef950a-af5d-4644-98ac-f4fab6750abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368906141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.368906141
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3273569443
Short name T132
Test name
Test status
Simulation time 230779621 ps
CPU time 8.94 seconds
Started Jul 03 05:59:21 PM PDT 24
Finished Jul 03 05:59:30 PM PDT 24
Peak memory 222616 kb
Host smart-714587cd-a7c8-4395-b212-03cac2abffd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273569443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3273569443
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2989021115
Short name T505
Test name
Test status
Simulation time 911364835 ps
CPU time 8.85 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:27 PM PDT 24
Peak memory 209364 kb
Host smart-e06f872f-03fe-4760-94ba-6964c3c613fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989021115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2989021115
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2395706351
Short name T491
Test name
Test status
Simulation time 230187791 ps
CPU time 4.14 seconds
Started Jul 03 05:59:22 PM PDT 24
Finished Jul 03 05:59:26 PM PDT 24
Peak memory 210460 kb
Host smart-1ca10650-b296-4b35-b115-9d77e711066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395706351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2395706351
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1132614196
Short name T542
Test name
Test status
Simulation time 29232342 ps
CPU time 0.8 seconds
Started Jul 03 05:59:25 PM PDT 24
Finished Jul 03 05:59:26 PM PDT 24
Peak memory 205964 kb
Host smart-ec38d4aa-e666-4e17-83a7-0ff3fff1a2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132614196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1132614196
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.904821753
Short name T38
Test name
Test status
Simulation time 56970251 ps
CPU time 1.73 seconds
Started Jul 03 05:59:28 PM PDT 24
Finished Jul 03 05:59:30 PM PDT 24
Peak memory 219840 kb
Host smart-6b914b97-8d92-41e2-a826-18ebbe1b7aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904821753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.904821753
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.445948294
Short name T360
Test name
Test status
Simulation time 120511834 ps
CPU time 2.99 seconds
Started Jul 03 05:59:20 PM PDT 24
Finished Jul 03 05:59:24 PM PDT 24
Peak memory 210372 kb
Host smart-324a89aa-85f0-4e19-a192-49edf8814e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445948294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.445948294
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2483797182
Short name T302
Test name
Test status
Simulation time 60538665 ps
CPU time 1.86 seconds
Started Jul 03 05:59:18 PM PDT 24
Finished Jul 03 05:59:20 PM PDT 24
Peak memory 214236 kb
Host smart-961fa8b0-a148-4339-8a82-d44aaf155e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483797182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2483797182
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3180265799
Short name T693
Test name
Test status
Simulation time 91702875 ps
CPU time 2.4 seconds
Started Jul 03 05:59:25 PM PDT 24
Finished Jul 03 05:59:28 PM PDT 24
Peak memory 214284 kb
Host smart-ab6cfb7e-3975-4c12-9ac4-33cf279a0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180265799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3180265799
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1461476957
Short name T228
Test name
Test status
Simulation time 182902578 ps
CPU time 3.12 seconds
Started Jul 03 05:59:22 PM PDT 24
Finished Jul 03 05:59:25 PM PDT 24
Peak memory 217856 kb
Host smart-36c3754d-c62b-4ff4-8c32-fc80b2057a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461476957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1461476957
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2045737700
Short name T371
Test name
Test status
Simulation time 363960340 ps
CPU time 4.95 seconds
Started Jul 03 05:59:23 PM PDT 24
Finished Jul 03 05:59:28 PM PDT 24
Peak memory 208080 kb
Host smart-8cb12689-1fdd-4133-8823-9b130cafed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045737700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2045737700
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.23339013
Short name T474
Test name
Test status
Simulation time 200570840 ps
CPU time 3.5 seconds
Started Jul 03 05:59:25 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 206868 kb
Host smart-59fd82a5-c2fe-44f9-84b3-2d40deb04450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23339013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.23339013
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1506463845
Short name T136
Test name
Test status
Simulation time 832752614 ps
CPU time 6.75 seconds
Started Jul 03 05:59:22 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 208092 kb
Host smart-851a89ce-6149-4771-9c41-972eb006ab27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506463845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1506463845
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3252068246
Short name T826
Test name
Test status
Simulation time 7173915102 ps
CPU time 73.07 seconds
Started Jul 03 05:59:22 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 208640 kb
Host smart-b9403532-249b-4282-8e46-9b2280b601fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252068246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3252068246
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2878203622
Short name T553
Test name
Test status
Simulation time 342801064 ps
CPU time 3.61 seconds
Started Jul 03 05:59:21 PM PDT 24
Finished Jul 03 05:59:25 PM PDT 24
Peak memory 206820 kb
Host smart-5d9b89fc-68a8-4111-8d8d-d116b8abd917
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878203622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2878203622
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3801696555
Short name T769
Test name
Test status
Simulation time 441856652 ps
CPU time 5.36 seconds
Started Jul 03 05:59:25 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 209392 kb
Host smart-6cfdc7cf-859b-468a-9bd6-fb87baab345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801696555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3801696555
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4246859267
Short name T899
Test name
Test status
Simulation time 247592272 ps
CPU time 2.83 seconds
Started Jul 03 05:59:23 PM PDT 24
Finished Jul 03 05:59:26 PM PDT 24
Peak memory 206788 kb
Host smart-fadc1ce7-7be2-44af-bf50-cb96fdcbfe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246859267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4246859267
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3721860807
Short name T310
Test name
Test status
Simulation time 574503385 ps
CPU time 22.84 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 222384 kb
Host smart-f7109a49-ab45-4d5d-9a39-63e6599ad6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721860807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3721860807
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2877124330
Short name T163
Test name
Test status
Simulation time 387296953 ps
CPU time 13.38 seconds
Started Jul 03 05:59:24 PM PDT 24
Finished Jul 03 05:59:38 PM PDT 24
Peak memory 222556 kb
Host smart-2b6fc1dd-daec-40dd-8504-daca9b848d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877124330 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2877124330
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3302797973
Short name T215
Test name
Test status
Simulation time 211388057 ps
CPU time 4.68 seconds
Started Jul 03 05:59:19 PM PDT 24
Finished Jul 03 05:59:24 PM PDT 24
Peak memory 207832 kb
Host smart-0c8534b9-09a9-4669-91d2-46dcc3772649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302797973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3302797973
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2626339401
Short name T681
Test name
Test status
Simulation time 213760602 ps
CPU time 2.01 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:28 PM PDT 24
Peak memory 210080 kb
Host smart-af549cfd-0739-4d03-9acb-fd4c97f081ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626339401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2626339401
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1166764041
Short name T450
Test name
Test status
Simulation time 56284120 ps
CPU time 0.87 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 206024 kb
Host smart-757b5916-9fc2-46fe-a83e-7c696c74ab27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166764041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1166764041
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1805034322
Short name T869
Test name
Test status
Simulation time 125919458 ps
CPU time 4.93 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:33 PM PDT 24
Peak memory 215456 kb
Host smart-7ba22129-12d0-4c05-96e4-76103fe2f1e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805034322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1805034322
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2648403743
Short name T800
Test name
Test status
Simulation time 216911763 ps
CPU time 2.83 seconds
Started Jul 03 05:59:29 PM PDT 24
Finished Jul 03 05:59:32 PM PDT 24
Peak memory 209992 kb
Host smart-640df427-b19b-4062-bc54-6becb929a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648403743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2648403743
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.11790139
Short name T904
Test name
Test status
Simulation time 56217586 ps
CPU time 1.77 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 207976 kb
Host smart-028e089c-3a63-4ad4-8d4e-60b7b3872d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11790139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.11790139
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.493256223
Short name T109
Test name
Test status
Simulation time 340229449 ps
CPU time 4.3 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 214356 kb
Host smart-fa3bf14d-801a-4fc8-a594-c7877d974448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493256223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.493256223
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.575289640
Short name T792
Test name
Test status
Simulation time 170445661 ps
CPU time 3.05 seconds
Started Jul 03 05:59:33 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 207848 kb
Host smart-c8d86b38-dfef-4ab2-b1e0-62f440aa520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575289640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.575289640
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.40868660
Short name T2
Test name
Test status
Simulation time 317845978 ps
CPU time 4.67 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 207832 kb
Host smart-3f737fee-f2c6-43fd-b246-75781c0e872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40868660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.40868660
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.235085462
Short name T337
Test name
Test status
Simulation time 787350931 ps
CPU time 14.9 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:42 PM PDT 24
Peak memory 208452 kb
Host smart-550ee7ff-b711-4063-b7c5-357ec1e577d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235085462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.235085462
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2293041979
Short name T545
Test name
Test status
Simulation time 139989177 ps
CPU time 5.11 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:32 PM PDT 24
Peak memory 207864 kb
Host smart-4635f3e9-1b08-4c75-b39a-6536291d4c10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293041979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2293041979
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3714500010
Short name T514
Test name
Test status
Simulation time 34510671 ps
CPU time 2.53 seconds
Started Jul 03 05:59:24 PM PDT 24
Finished Jul 03 05:59:27 PM PDT 24
Peak memory 207544 kb
Host smart-602c758d-e91e-400e-9b68-6944777b6277
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714500010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3714500010
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3524376127
Short name T359
Test name
Test status
Simulation time 637014281 ps
CPU time 13.27 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:41 PM PDT 24
Peak memory 208744 kb
Host smart-b38424fb-c4f3-43d8-83d4-367302b199ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524376127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3524376127
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3889366003
Short name T638
Test name
Test status
Simulation time 28881947 ps
CPU time 1.84 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:30 PM PDT 24
Peak memory 218188 kb
Host smart-11665c99-f173-4f92-ac9e-1ceab1b5354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889366003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3889366003
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2771147202
Short name T717
Test name
Test status
Simulation time 411807019 ps
CPU time 4.48 seconds
Started Jul 03 05:59:22 PM PDT 24
Finished Jul 03 05:59:26 PM PDT 24
Peak memory 207964 kb
Host smart-2fb924ce-7d43-46b3-a7c9-6ba2fc3e466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771147202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2771147202
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4120509601
Short name T619
Test name
Test status
Simulation time 2011124576 ps
CPU time 24.5 seconds
Started Jul 03 05:59:29 PM PDT 24
Finished Jul 03 05:59:53 PM PDT 24
Peak memory 219824 kb
Host smart-5f8f83ca-17d3-49b3-8bf6-b44f9693a647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120509601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4120509601
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.603107607
Short name T502
Test name
Test status
Simulation time 161111154 ps
CPU time 2.73 seconds
Started Jul 03 05:59:28 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 208564 kb
Host smart-cd7d12a9-b73f-43ca-999a-0b1725396cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603107607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.603107607
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2293137549
Short name T160
Test name
Test status
Simulation time 97086646 ps
CPU time 1.94 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:30 PM PDT 24
Peak memory 209924 kb
Host smart-8151e91f-9fda-4c3f-a10b-ec2ac5c410c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293137549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2293137549
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3022341671
Short name T743
Test name
Test status
Simulation time 39307116 ps
CPU time 0.78 seconds
Started Jul 03 05:56:37 PM PDT 24
Finished Jul 03 05:56:38 PM PDT 24
Peak memory 206000 kb
Host smart-29ff8ff4-ca0c-4fbe-a42c-d8095798214a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022341671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3022341671
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.222335875
Short name T14
Test name
Test status
Simulation time 50505734 ps
CPU time 3.36 seconds
Started Jul 03 05:56:27 PM PDT 24
Finished Jul 03 05:56:31 PM PDT 24
Peak memory 214880 kb
Host smart-ad8194b4-d9e8-4bea-8785-e70c0d606788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222335875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.222335875
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.388088177
Short name T751
Test name
Test status
Simulation time 153835117 ps
CPU time 2.4 seconds
Started Jul 03 05:56:28 PM PDT 24
Finished Jul 03 05:56:31 PM PDT 24
Peak memory 207268 kb
Host smart-449c7104-fdda-4a10-99dd-40031c672d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388088177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.388088177
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1214379545
Short name T110
Test name
Test status
Simulation time 51687645 ps
CPU time 3.01 seconds
Started Jul 03 05:56:31 PM PDT 24
Finished Jul 03 05:56:34 PM PDT 24
Peak memory 214356 kb
Host smart-bcae325d-12a5-4cb7-8c4c-1a7f5d2b69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214379545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1214379545
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1282899780
Short name T767
Test name
Test status
Simulation time 454802946 ps
CPU time 3.97 seconds
Started Jul 03 05:56:32 PM PDT 24
Finished Jul 03 05:56:37 PM PDT 24
Peak memory 215384 kb
Host smart-e36c4801-d920-444c-a81e-9ed3b5c52086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282899780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1282899780
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.679166356
Short name T448
Test name
Test status
Simulation time 133900236 ps
CPU time 2.66 seconds
Started Jul 03 05:56:32 PM PDT 24
Finished Jul 03 05:56:35 PM PDT 24
Peak memory 220036 kb
Host smart-0ca8795d-0b02-412a-a754-f8c29d375b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679166356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.679166356
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2229647352
Short name T657
Test name
Test status
Simulation time 81596415 ps
CPU time 3.7 seconds
Started Jul 03 05:56:29 PM PDT 24
Finished Jul 03 05:56:33 PM PDT 24
Peak memory 208140 kb
Host smart-53e0ce83-7e0f-461d-9bd1-3b1505b745c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229647352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2229647352
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2821818761
Short name T10
Test name
Test status
Simulation time 2486041773 ps
CPU time 6.55 seconds
Started Jul 03 05:56:40 PM PDT 24
Finished Jul 03 05:56:47 PM PDT 24
Peak memory 237240 kb
Host smart-8cae1902-1eab-40a3-aa83-0a225bb54669
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821818761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2821818761
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1473773647
Short name T265
Test name
Test status
Simulation time 781452942 ps
CPU time 6.5 seconds
Started Jul 03 05:56:28 PM PDT 24
Finished Jul 03 05:56:35 PM PDT 24
Peak memory 208704 kb
Host smart-d4e88ce9-c873-4e41-9eb3-becc9ad47dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473773647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1473773647
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2683515540
Short name T307
Test name
Test status
Simulation time 77541830 ps
CPU time 3.04 seconds
Started Jul 03 05:56:26 PM PDT 24
Finished Jul 03 05:56:29 PM PDT 24
Peak memory 209052 kb
Host smart-6e958811-567c-46b7-b6a7-79b05e93136a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683515540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2683515540
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2021738981
Short name T209
Test name
Test status
Simulation time 243717016 ps
CPU time 5.31 seconds
Started Jul 03 05:56:28 PM PDT 24
Finished Jul 03 05:56:34 PM PDT 24
Peak memory 208124 kb
Host smart-e657b70b-d8f8-4016-bc87-c10ca4542984
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021738981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2021738981
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1919582310
Short name T768
Test name
Test status
Simulation time 256767499 ps
CPU time 3.17 seconds
Started Jul 03 05:56:27 PM PDT 24
Finished Jul 03 05:56:31 PM PDT 24
Peak memory 207132 kb
Host smart-0d3781e4-e7e5-4ea0-8871-f099f35eb6bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919582310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1919582310
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1957467006
Short name T252
Test name
Test status
Simulation time 378097117 ps
CPU time 2.75 seconds
Started Jul 03 05:56:31 PM PDT 24
Finished Jul 03 05:56:35 PM PDT 24
Peak memory 208772 kb
Host smart-843fe25b-82a2-4462-bb96-afa4986c2360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957467006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1957467006
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.831505454
Short name T579
Test name
Test status
Simulation time 120813838 ps
CPU time 2.32 seconds
Started Jul 03 05:56:23 PM PDT 24
Finished Jul 03 05:56:26 PM PDT 24
Peak memory 207064 kb
Host smart-8a452853-8dc6-449a-840e-18fd21c8fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831505454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.831505454
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1104756087
Short name T584
Test name
Test status
Simulation time 72616530 ps
CPU time 3.63 seconds
Started Jul 03 05:56:33 PM PDT 24
Finished Jul 03 05:56:37 PM PDT 24
Peak memory 208684 kb
Host smart-59a1b9fb-5500-44bf-b5a0-453a13887bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104756087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1104756087
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3017815669
Short name T88
Test name
Test status
Simulation time 370049695 ps
CPU time 1.65 seconds
Started Jul 03 05:56:32 PM PDT 24
Finished Jul 03 05:56:34 PM PDT 24
Peak memory 210132 kb
Host smart-c2603fd4-012c-40a0-8074-66905727945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017815669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3017815669
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2133837294
Short name T829
Test name
Test status
Simulation time 11147088 ps
CPU time 0.79 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:31 PM PDT 24
Peak memory 205892 kb
Host smart-9bca1d49-b534-475a-9d03-da2e09eed5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133837294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2133837294
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1349540785
Short name T333
Test name
Test status
Simulation time 214424832 ps
CPU time 4 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 214372 kb
Host smart-d3f41170-7b8e-4678-8e57-c5e1e03ff25b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349540785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1349540785
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1344128811
Short name T465
Test name
Test status
Simulation time 115872795 ps
CPU time 2.48 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 220996 kb
Host smart-64d25fba-0576-4a98-9769-7ce11421f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344128811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1344128811
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1698980081
Short name T480
Test name
Test status
Simulation time 637040680 ps
CPU time 2.99 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 214356 kb
Host smart-39554f13-eadd-4fbc-99e4-c6e1209082fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698980081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1698980081
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3468765307
Short name T271
Test name
Test status
Simulation time 132972505 ps
CPU time 2.88 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 221312 kb
Host smart-42d42fdf-efd5-4228-880a-32abc44f08cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468765307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3468765307
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3172446663
Short name T886
Test name
Test status
Simulation time 330812550 ps
CPU time 3.89 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:35 PM PDT 24
Peak memory 222516 kb
Host smart-1439faa3-12e0-4355-b516-665e792495cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172446663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3172446663
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.131892032
Short name T741
Test name
Test status
Simulation time 1581638441 ps
CPU time 13.5 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:40 PM PDT 24
Peak memory 219816 kb
Host smart-f9f0f9f0-4b84-4f94-a934-f03976a4a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131892032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.131892032
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.917234049
Short name T850
Test name
Test status
Simulation time 159615205 ps
CPU time 5.93 seconds
Started Jul 03 05:59:28 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 208036 kb
Host smart-09e9c439-a442-483b-b691-54c2c9b52af4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917234049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.917234049
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1464965969
Short name T187
Test name
Test status
Simulation time 476739370 ps
CPU time 4.34 seconds
Started Jul 03 05:59:28 PM PDT 24
Finished Jul 03 05:59:33 PM PDT 24
Peak memory 207908 kb
Host smart-86701644-475f-4ef5-a61b-bed9b75ca317
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464965969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1464965969
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3716151474
Short name T654
Test name
Test status
Simulation time 59844812 ps
CPU time 2.33 seconds
Started Jul 03 05:59:27 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 206816 kb
Host smart-1ec1e219-ae7e-4468-ba79-f24e8b6fa22e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716151474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3716151474
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2719187431
Short name T446
Test name
Test status
Simulation time 499628126 ps
CPU time 1.72 seconds
Started Jul 03 05:59:32 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 207684 kb
Host smart-77783ce5-e56c-41cd-af8b-bcaaf601d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719187431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2719187431
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1938744826
Short name T897
Test name
Test status
Simulation time 97175334 ps
CPU time 2.89 seconds
Started Jul 03 05:59:26 PM PDT 24
Finished Jul 03 05:59:29 PM PDT 24
Peak memory 208236 kb
Host smart-79df8c48-4a72-42bc-9cf5-35782aa73847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938744826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1938744826
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2988171050
Short name T221
Test name
Test status
Simulation time 850884213 ps
CPU time 12.78 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 222540 kb
Host smart-1bd9a241-eed1-496b-ae12-424e9e837e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988171050 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2988171050
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3345981453
Short name T694
Test name
Test status
Simulation time 165097289 ps
CPU time 6.13 seconds
Started Jul 03 05:59:30 PM PDT 24
Finished Jul 03 05:59:36 PM PDT 24
Peak memory 207632 kb
Host smart-5292312a-c725-40a6-a5ab-cc8eb4fd0f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345981453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3345981453
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.574341548
Short name T711
Test name
Test status
Simulation time 78153605 ps
CPU time 2.54 seconds
Started Jul 03 05:59:29 PM PDT 24
Finished Jul 03 05:59:32 PM PDT 24
Peak memory 210360 kb
Host smart-fec16f4e-0a44-4771-bbba-dafa7efea6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574341548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.574341548
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2069162952
Short name T730
Test name
Test status
Simulation time 20578410 ps
CPU time 0.8 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:38 PM PDT 24
Peak memory 206016 kb
Host smart-3b13da2d-9b0e-4da4-be67-79db84646b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069162952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2069162952
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.650812135
Short name T144
Test name
Test status
Simulation time 30574028 ps
CPU time 2.47 seconds
Started Jul 03 05:59:33 PM PDT 24
Finished Jul 03 05:59:36 PM PDT 24
Peak memory 214356 kb
Host smart-b177dc93-5c38-4cf1-af85-5dd7e929968a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650812135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.650812135
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3930155168
Short name T26
Test name
Test status
Simulation time 73625622 ps
CPU time 2.45 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 209116 kb
Host smart-d44d9ffe-d521-430a-a6ea-400f59a73901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930155168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3930155168
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1878237976
Short name T649
Test name
Test status
Simulation time 394014577 ps
CPU time 3.11 seconds
Started Jul 03 05:59:32 PM PDT 24
Finished Jul 03 05:59:36 PM PDT 24
Peak memory 210008 kb
Host smart-e02b9922-77f9-4493-8cb9-3c60a663b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878237976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1878237976
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.370240852
Short name T377
Test name
Test status
Simulation time 98474337 ps
CPU time 2.21 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:36 PM PDT 24
Peak memory 214336 kb
Host smart-c141c822-3046-401f-8df1-c527b4fa483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370240852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.370240852
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1008790045
Short name T612
Test name
Test status
Simulation time 65114123 ps
CPU time 2.15 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:39 PM PDT 24
Peak memory 217048 kb
Host smart-45146a9e-ee2b-4c1a-b9d5-da11cd71f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008790045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1008790045
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2274773306
Short name T177
Test name
Test status
Simulation time 138290455 ps
CPU time 3.35 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:40 PM PDT 24
Peak memory 208132 kb
Host smart-8924b3aa-cf83-49ba-9201-361c6d961704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274773306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2274773306
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2030068497
Short name T775
Test name
Test status
Simulation time 585791820 ps
CPU time 15.56 seconds
Started Jul 03 05:59:35 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 210568 kb
Host smart-bbb93747-3ca2-4bb6-9ec4-41374747f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030068497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2030068497
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.918057547
Short name T354
Test name
Test status
Simulation time 52062406 ps
CPU time 1.82 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:33 PM PDT 24
Peak memory 206776 kb
Host smart-2144fe28-1efb-40ed-bdb1-a3f1c4191cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918057547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.918057547
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3233330602
Short name T567
Test name
Test status
Simulation time 2558088517 ps
CPU time 24.75 seconds
Started Jul 03 05:59:31 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 209240 kb
Host smart-900dd9db-834e-4866-b82f-91eae3773351
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233330602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3233330602
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.557098381
Short name T547
Test name
Test status
Simulation time 135842769 ps
CPU time 3.28 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 208312 kb
Host smart-60d13904-343f-443d-8d5a-275b423a12aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557098381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.557098381
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.509909017
Short name T479
Test name
Test status
Simulation time 342881403 ps
CPU time 3.41 seconds
Started Jul 03 05:59:32 PM PDT 24
Finished Jul 03 05:59:36 PM PDT 24
Peak memory 218100 kb
Host smart-8153aa6f-6136-43a9-b8c5-5eac3447cc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509909017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.509909017
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4200976688
Short name T662
Test name
Test status
Simulation time 120552965 ps
CPU time 2.25 seconds
Started Jul 03 05:59:32 PM PDT 24
Finished Jul 03 05:59:34 PM PDT 24
Peak memory 206876 kb
Host smart-340eed63-2127-4bf2-96d8-eee55fb2d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200976688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4200976688
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4290418365
Short name T256
Test name
Test status
Simulation time 1124346141 ps
CPU time 18.63 seconds
Started Jul 03 05:59:35 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 215020 kb
Host smart-4fd4198e-cb6c-4ae5-83ed-65fbc9a28fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290418365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4290418365
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3129559676
Short name T351
Test name
Test status
Simulation time 9458821305 ps
CPU time 107.67 seconds
Started Jul 03 05:59:33 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 209800 kb
Host smart-5ed0d879-4d45-49b2-9e47-bc0a50f78300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129559676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3129559676
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1502304878
Short name T828
Test name
Test status
Simulation time 78836815 ps
CPU time 1.57 seconds
Started Jul 03 05:59:38 PM PDT 24
Finished Jul 03 05:59:40 PM PDT 24
Peak memory 209780 kb
Host smart-74379524-a96c-4628-8d38-fa1320252cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502304878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1502304878
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2437081932
Short name T716
Test name
Test status
Simulation time 16643178 ps
CPU time 0.82 seconds
Started Jul 03 05:59:42 PM PDT 24
Finished Jul 03 05:59:44 PM PDT 24
Peak memory 205828 kb
Host smart-657012f5-322d-4d66-a028-eeb722e4462a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437081932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2437081932
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1188570456
Short name T233
Test name
Test status
Simulation time 75152606 ps
CPU time 3.54 seconds
Started Jul 03 05:59:39 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 208268 kb
Host smart-e8292ba3-9c9f-4a21-b6dc-a6f68353f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188570456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1188570456
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3983909617
Short name T376
Test name
Test status
Simulation time 110772460 ps
CPU time 3.74 seconds
Started Jul 03 05:59:37 PM PDT 24
Finished Jul 03 05:59:41 PM PDT 24
Peak memory 208816 kb
Host smart-afb61e83-eec4-4a30-b0bf-3743133aedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983909617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3983909617
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1039167680
Short name T341
Test name
Test status
Simulation time 1138067878 ps
CPU time 3.8 seconds
Started Jul 03 05:59:40 PM PDT 24
Finished Jul 03 05:59:44 PM PDT 24
Peak memory 222268 kb
Host smart-b25fd2d9-3de9-453b-8413-fbd7ed0bfe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039167680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1039167680
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2325101724
Short name T320
Test name
Test status
Simulation time 236262640 ps
CPU time 5.07 seconds
Started Jul 03 05:59:37 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 221040 kb
Host smart-b3f030a8-66a9-4e11-ab38-a9ddd1c0b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325101724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2325101724
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2807288668
Short name T631
Test name
Test status
Simulation time 254630920 ps
CPU time 3.74 seconds
Started Jul 03 05:59:37 PM PDT 24
Finished Jul 03 05:59:41 PM PDT 24
Peak memory 214332 kb
Host smart-c0748b12-4d0b-41d9-8797-956b66e6dae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807288668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2807288668
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2867965413
Short name T556
Test name
Test status
Simulation time 226748989 ps
CPU time 4.98 seconds
Started Jul 03 05:59:39 PM PDT 24
Finished Jul 03 05:59:45 PM PDT 24
Peak memory 207588 kb
Host smart-c6f8c9b2-f61e-4b07-81a1-fbb0e9bf6aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867965413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2867965413
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1759385855
Short name T601
Test name
Test status
Simulation time 70026216 ps
CPU time 2.94 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:39 PM PDT 24
Peak memory 208156 kb
Host smart-fd751ae7-2b73-4f46-8e0c-9b78b4f0c59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759385855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1759385855
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.338652979
Short name T860
Test name
Test status
Simulation time 391751243 ps
CPU time 2.56 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 206840 kb
Host smart-d25944d8-d0a0-4471-a116-7895554f9b24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338652979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.338652979
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.896617917
Short name T115
Test name
Test status
Simulation time 343191244 ps
CPU time 7.48 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:44 PM PDT 24
Peak memory 208172 kb
Host smart-3bbe1aed-a6c1-4e56-9a46-ea306bc41f7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896617917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.896617917
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.663924754
Short name T718
Test name
Test status
Simulation time 371829818 ps
CPU time 11.46 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:53 PM PDT 24
Peak memory 208540 kb
Host smart-5e619869-a8c2-4215-a38a-cf367d65ecb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663924754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.663924754
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4184599455
Short name T515
Test name
Test status
Simulation time 317445060 ps
CPU time 9.85 seconds
Started Jul 03 05:59:38 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 208204 kb
Host smart-0a542dcc-fc7d-4982-80e6-ceaac22f9cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184599455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4184599455
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3352230968
Short name T605
Test name
Test status
Simulation time 77476258 ps
CPU time 2.65 seconds
Started Jul 03 05:59:34 PM PDT 24
Finished Jul 03 05:59:37 PM PDT 24
Peak memory 208064 kb
Host smart-97fd12fc-307a-4a37-98ff-2ec6b28de23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352230968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3352230968
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2193240922
Short name T813
Test name
Test status
Simulation time 716717910 ps
CPU time 12.88 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 222648 kb
Host smart-54050299-9ba8-454e-8c9d-184292fee73e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193240922 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2193240922
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1874819958
Short name T843
Test name
Test status
Simulation time 255391980 ps
CPU time 6.8 seconds
Started Jul 03 05:59:36 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 208072 kb
Host smart-772546c1-3ece-4e7f-95cb-3043fb93c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874819958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1874819958
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3625146464
Short name T868
Test name
Test status
Simulation time 17347017 ps
CPU time 0.87 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:46 PM PDT 24
Peak memory 205972 kb
Host smart-258bbdeb-3f24-428a-822a-dfb00ece472a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625146464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3625146464
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4263609008
Short name T33
Test name
Test status
Simulation time 1794519074 ps
CPU time 4.64 seconds
Started Jul 03 05:59:46 PM PDT 24
Finished Jul 03 05:59:51 PM PDT 24
Peak memory 214716 kb
Host smart-474d62bb-a7b1-4d2d-9863-6415d5aa9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263609008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4263609008
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3309343477
Short name T259
Test name
Test status
Simulation time 131638850 ps
CPU time 1.47 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:46 PM PDT 24
Peak memory 209328 kb
Host smart-e1e525ea-d598-4b4b-a978-5164d07f94b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309343477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3309343477
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4118974759
Short name T97
Test name
Test status
Simulation time 375867565 ps
CPU time 4.87 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 05:59:53 PM PDT 24
Peak memory 214980 kb
Host smart-2f02dd4d-9cba-417b-b342-dd797485e3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118974759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4118974759
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3554838506
Short name T363
Test name
Test status
Simulation time 103734381 ps
CPU time 5.26 seconds
Started Jul 03 05:59:43 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 222424 kb
Host smart-7b6023f4-8047-476a-894b-982fd3646181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554838506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3554838506
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.468389642
Short name T484
Test name
Test status
Simulation time 452644555 ps
CPU time 4.46 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 215832 kb
Host smart-a700cb77-9cff-4304-8619-f3c98244fb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468389642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.468389642
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4257887206
Short name T395
Test name
Test status
Simulation time 852047181 ps
CPU time 23.25 seconds
Started Jul 03 05:59:47 PM PDT 24
Finished Jul 03 06:00:11 PM PDT 24
Peak memory 219840 kb
Host smart-a8d0245c-1b54-4745-9a19-90bdc6e3caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257887206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4257887206
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2485772413
Short name T890
Test name
Test status
Simulation time 975594327 ps
CPU time 16.07 seconds
Started Jul 03 05:59:42 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 208740 kb
Host smart-6f2638e8-e99f-48d6-ac97-23dbf5a70ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485772413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2485772413
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.30126382
Short name T773
Test name
Test status
Simulation time 177101705 ps
CPU time 2.69 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:44 PM PDT 24
Peak memory 206960 kb
Host smart-ea02e18f-c288-4303-95b2-03587c1076bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.30126382
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1268997417
Short name T760
Test name
Test status
Simulation time 26718040 ps
CPU time 1.96 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:43 PM PDT 24
Peak memory 207680 kb
Host smart-15ccbd3d-04c5-42d3-b4d0-e400e40a0f1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268997417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1268997417
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2318081791
Short name T766
Test name
Test status
Simulation time 459434584 ps
CPU time 3.62 seconds
Started Jul 03 05:59:42 PM PDT 24
Finished Jul 03 05:59:46 PM PDT 24
Peak memory 208116 kb
Host smart-0fce0c7e-8d37-4d7e-8e1a-342cd2f9af96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318081791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2318081791
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1191060533
Short name T493
Test name
Test status
Simulation time 161217504 ps
CPU time 2.2 seconds
Started Jul 03 05:59:47 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 208308 kb
Host smart-a87890ec-92ea-42a3-bbf4-d723374386c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191060533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1191060533
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1228441901
Short name T661
Test name
Test status
Simulation time 1302862786 ps
CPU time 6.91 seconds
Started Jul 03 05:59:41 PM PDT 24
Finished Jul 03 05:59:49 PM PDT 24
Peak memory 208532 kb
Host smart-f457232e-9084-4eb2-bfdd-feb9e6b9d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228441901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1228441901
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2735795763
Short name T287
Test name
Test status
Simulation time 8136399999 ps
CPU time 81.89 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 06:01:10 PM PDT 24
Peak memory 215428 kb
Host smart-2edc2aae-a583-4897-a782-1f98e542845d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735795763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2735795763
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2537018351
Short name T336
Test name
Test status
Simulation time 115039775 ps
CPU time 2.48 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:48 PM PDT 24
Peak memory 207756 kb
Host smart-1ff5f822-7eaf-4004-83a9-a5c29a15731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537018351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2537018351
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.366770203
Short name T487
Test name
Test status
Simulation time 31520968 ps
CPU time 0.7 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 206016 kb
Host smart-02f4ee72-70aa-4059-92bd-e0016811a456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366770203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.366770203
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4217382904
Short name T420
Test name
Test status
Simulation time 37632941 ps
CPU time 2.84 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 214348 kb
Host smart-c7b253b3-d939-4bff-9702-f7ba5ad79067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217382904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4217382904
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.789160977
Short name T72
Test name
Test status
Simulation time 2755727995 ps
CPU time 35.6 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 06:00:29 PM PDT 24
Peak memory 214772 kb
Host smart-ed4002f4-83df-44a3-a2f9-2ec585ee02ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789160977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.789160977
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.523510245
Short name T672
Test name
Test status
Simulation time 64319504 ps
CPU time 2.17 seconds
Started Jul 03 05:59:50 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 209140 kb
Host smart-735bbdab-1962-438e-aa37-079e43057f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523510245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.523510245
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2775707252
Short name T879
Test name
Test status
Simulation time 403395606 ps
CPU time 2.81 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 214348 kb
Host smart-82e65ce3-bb8e-439f-8c75-7e39392e462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775707252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2775707252
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.191953152
Short name T611
Test name
Test status
Simulation time 55836549 ps
CPU time 3.03 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 214356 kb
Host smart-568d8a00-bc2f-4709-bf26-0de6b224c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191953152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.191953152
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2786722365
Short name T239
Test name
Test status
Simulation time 51015641 ps
CPU time 3.51 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 220540 kb
Host smart-0678c16b-44f6-4b92-91b7-27f0cd4bf9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786722365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2786722365
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1951379319
Short name T489
Test name
Test status
Simulation time 129530681 ps
CPU time 5.1 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 208852 kb
Host smart-41d9a037-18bf-474a-a679-318802dcdd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951379319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1951379319
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1765343095
Short name T462
Test name
Test status
Simulation time 134519339 ps
CPU time 2.3 seconds
Started Jul 03 05:59:44 PM PDT 24
Finished Jul 03 05:59:47 PM PDT 24
Peak memory 206676 kb
Host smart-cba4de03-b740-4a12-819d-db0feb455071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765343095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1765343095
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1354378048
Short name T214
Test name
Test status
Simulation time 89391218 ps
CPU time 3.76 seconds
Started Jul 03 05:59:45 PM PDT 24
Finished Jul 03 05:59:49 PM PDT 24
Peak memory 208720 kb
Host smart-088bcd25-d19b-4585-8fb2-363caf2d94ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354378048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1354378048
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.369069030
Short name T854
Test name
Test status
Simulation time 766565043 ps
CPU time 8.26 seconds
Started Jul 03 05:59:46 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 208360 kb
Host smart-5d2470f1-cdce-4227-adc4-a12f031bdb03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369069030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.369069030
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2328142299
Short name T853
Test name
Test status
Simulation time 222253316 ps
CPU time 3.14 seconds
Started Jul 03 05:59:46 PM PDT 24
Finished Jul 03 05:59:49 PM PDT 24
Peak memory 208776 kb
Host smart-abc73518-09c7-4a77-b58c-c0634f6741bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328142299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2328142299
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2802705092
Short name T814
Test name
Test status
Simulation time 94395988 ps
CPU time 1.71 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 05:59:51 PM PDT 24
Peak memory 208668 kb
Host smart-25757ead-601d-452d-b8c4-a65de87651c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802705092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2802705092
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.49743400
Short name T447
Test name
Test status
Simulation time 87289422 ps
CPU time 3.51 seconds
Started Jul 03 05:59:46 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 207912 kb
Host smart-ffcffcc5-c1c9-47f3-8d79-131e9055d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49743400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.49743400
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3213761463
Short name T240
Test name
Test status
Simulation time 2785470288 ps
CPU time 37.5 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 06:00:27 PM PDT 24
Peak memory 216988 kb
Host smart-7e8c2d58-b223-4922-be1e-7810aa6fe724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213761463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3213761463
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3122883593
Short name T687
Test name
Test status
Simulation time 109021522 ps
CPU time 3.65 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 207200 kb
Host smart-a65dd3fd-690a-4dff-b3e7-a8b321c133a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122883593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3122883593
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4254584106
Short name T66
Test name
Test status
Simulation time 1211728292 ps
CPU time 3.23 seconds
Started Jul 03 05:59:50 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 209832 kb
Host smart-daf77fff-0525-491a-881c-53368d784ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254584106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4254584106
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.271395911
Short name T895
Test name
Test status
Simulation time 29997177 ps
CPU time 0.97 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 05:59:55 PM PDT 24
Peak memory 206128 kb
Host smart-7501f180-a6e0-4539-ae43-40d5d5ee3cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271395911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.271395911
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1174335795
Short name T408
Test name
Test status
Simulation time 87219839 ps
CPU time 4.92 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 05:59:55 PM PDT 24
Peak memory 215500 kb
Host smart-e4b23836-9a96-4e9d-8230-a1f75e49d978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174335795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1174335795
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3858477936
Short name T747
Test name
Test status
Simulation time 684605455 ps
CPU time 5.07 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 218368 kb
Host smart-e3b9c14c-4241-40c9-bbf9-06eed895e37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858477936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3858477936
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4033554239
Short name T103
Test name
Test status
Simulation time 2883972165 ps
CPU time 29.41 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 06:00:22 PM PDT 24
Peak memory 209436 kb
Host smart-b701d194-9c13-443c-beb9-e991d735e7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033554239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4033554239
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3029460110
Short name T770
Test name
Test status
Simulation time 115402858 ps
CPU time 3.03 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 221920 kb
Host smart-9dc9dcfb-6dc9-4d9b-b61d-1fe31a7efb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029460110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3029460110
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2456709258
Short name T143
Test name
Test status
Simulation time 42339285 ps
CPU time 2.88 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 05:59:53 PM PDT 24
Peak memory 220060 kb
Host smart-cf60b26c-68c8-4186-b53c-803d0c577ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456709258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2456709258
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3792041457
Short name T270
Test name
Test status
Simulation time 214996455 ps
CPU time 6.75 seconds
Started Jul 03 05:59:50 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 208484 kb
Host smart-5fc74447-bc4f-4efd-946d-a1cbb4d8d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792041457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3792041457
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3755900147
Short name T859
Test name
Test status
Simulation time 909430120 ps
CPU time 6.21 seconds
Started Jul 03 05:59:50 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 206920 kb
Host smart-3f82bc8c-3931-4b9c-9699-baa4d8eb732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755900147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3755900147
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3778937195
Short name T461
Test name
Test status
Simulation time 212367919 ps
CPU time 3.09 seconds
Started Jul 03 05:59:48 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 206876 kb
Host smart-3173409c-b211-4ddb-96ed-900cb466dff4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778937195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3778937195
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.583143284
Short name T802
Test name
Test status
Simulation time 40913996 ps
CPU time 1.96 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 05:59:51 PM PDT 24
Peak memory 207556 kb
Host smart-97f462b8-f6ab-40cd-b0f4-1cc8a01cb365
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583143284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.583143284
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3076943961
Short name T86
Test name
Test status
Simulation time 1097863484 ps
CPU time 6.64 seconds
Started Jul 03 05:59:54 PM PDT 24
Finished Jul 03 06:00:01 PM PDT 24
Peak memory 208624 kb
Host smart-4296f26e-07e3-4824-91c6-7aff1d1c30ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076943961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3076943961
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1778102031
Short name T902
Test name
Test status
Simulation time 126722896 ps
CPU time 2.1 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 05:59:57 PM PDT 24
Peak memory 218428 kb
Host smart-534ad8ee-5699-4598-bbd4-a9a2a652138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778102031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1778102031
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1286306673
Short name T884
Test name
Test status
Simulation time 39886414 ps
CPU time 2.62 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 05:59:52 PM PDT 24
Peak memory 208864 kb
Host smart-6a34b1c0-9eb3-4bb7-b829-611116230cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286306673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1286306673
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.182593746
Short name T378
Test name
Test status
Simulation time 146197618 ps
CPU time 6.12 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 217980 kb
Host smart-5c8cd66a-0389-4a3a-ac81-90412ba3efa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182593746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.182593746
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2389472708
Short name T76
Test name
Test status
Simulation time 254155903 ps
CPU time 12.19 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 222624 kb
Host smart-773202e9-7719-4ea4-a7ae-54d1dbb3c378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389472708 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2389472708
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2118334611
Short name T335
Test name
Test status
Simulation time 11457797447 ps
CPU time 31.25 seconds
Started Jul 03 05:59:49 PM PDT 24
Finished Jul 03 06:00:21 PM PDT 24
Peak memory 209908 kb
Host smart-374c6c00-c599-4763-86d3-82db40489d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118334611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2118334611
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2782244120
Short name T67
Test name
Test status
Simulation time 68945543 ps
CPU time 2.86 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 05:59:57 PM PDT 24
Peak memory 210408 kb
Host smart-fdd25737-5118-45a6-b9f2-9bb1b92ecd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782244120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2782244120
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4023049232
Short name T15
Test name
Test status
Simulation time 10557728 ps
CPU time 0.85 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 206024 kb
Host smart-eb84615c-c255-4a04-bbc3-27931c6977c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023049232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4023049232
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2096765316
Short name T402
Test name
Test status
Simulation time 92418197 ps
CPU time 4.87 seconds
Started Jul 03 05:59:57 PM PDT 24
Finished Jul 03 06:00:02 PM PDT 24
Peak memory 214656 kb
Host smart-214d7a22-649f-4e66-93a6-9280be552cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096765316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2096765316
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3497535993
Short name T725
Test name
Test status
Simulation time 133275344 ps
CPU time 3.12 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 214688 kb
Host smart-064ca330-c5d2-4be6-857b-5f65a5838dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497535993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3497535993
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2761208287
Short name T855
Test name
Test status
Simulation time 3096709171 ps
CPU time 30.16 seconds
Started Jul 03 05:59:56 PM PDT 24
Finished Jul 03 06:00:27 PM PDT 24
Peak memory 214400 kb
Host smart-ce7f651f-451d-4266-98dd-547cf6606fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761208287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2761208287
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.982424698
Short name T677
Test name
Test status
Simulation time 93372554 ps
CPU time 4.39 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 06:00:00 PM PDT 24
Peak memory 214256 kb
Host smart-e81214b2-9f65-49e5-bc0f-024cf4b447d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982424698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.982424698
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_random.3149895102
Short name T620
Test name
Test status
Simulation time 625330104 ps
CPU time 6.86 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 05:59:59 PM PDT 24
Peak memory 214308 kb
Host smart-cf3a81b0-2764-43bb-bad4-aabf6276c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149895102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3149895102
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.213388228
Short name T253
Test name
Test status
Simulation time 181942497 ps
CPU time 2.6 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 206904 kb
Host smart-167123a0-ca53-4899-ac72-e3f365c2d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213388228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.213388228
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1061195441
Short name T703
Test name
Test status
Simulation time 55481813 ps
CPU time 2.81 seconds
Started Jul 03 05:59:53 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 208208 kb
Host smart-6adb8147-bbad-4a1f-896f-c609ff886548
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061195441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1061195441
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1605880598
Short name T85
Test name
Test status
Simulation time 401380101 ps
CPU time 3.31 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 05:59:55 PM PDT 24
Peak memory 208808 kb
Host smart-4a5026d2-bbbf-442d-8279-6e205fd2d302
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605880598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1605880598
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2986343793
Short name T216
Test name
Test status
Simulation time 56325261 ps
CPU time 2.02 seconds
Started Jul 03 05:59:51 PM PDT 24
Finished Jul 03 05:59:53 PM PDT 24
Peak memory 206800 kb
Host smart-464eb988-2a75-45d2-8e8a-c982c76f2b16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986343793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2986343793
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4209561656
Short name T866
Test name
Test status
Simulation time 56790018 ps
CPU time 2.39 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 214300 kb
Host smart-f9a98b21-46e8-40ad-b1b3-aefe93e5429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209561656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4209561656
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.23755532
Short name T643
Test name
Test status
Simulation time 901587748 ps
CPU time 4.37 seconds
Started Jul 03 05:59:52 PM PDT 24
Finished Jul 03 05:59:56 PM PDT 24
Peak memory 206788 kb
Host smart-52e15edf-885a-43d3-8885-461cbbedd4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23755532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.23755532
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2395098823
Short name T230
Test name
Test status
Simulation time 12325079473 ps
CPU time 76.34 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:01:17 PM PDT 24
Peak memory 222556 kb
Host smart-5e912f2d-dec1-4a77-8ee6-b73da612ed96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395098823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2395098823
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3862046395
Short name T738
Test name
Test status
Simulation time 305114349 ps
CPU time 4.78 seconds
Started Jul 03 05:59:54 PM PDT 24
Finished Jul 03 05:59:59 PM PDT 24
Peak memory 209144 kb
Host smart-b07348a9-8d83-479b-a858-f2245dc0e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862046395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3862046395
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1643544800
Short name T424
Test name
Test status
Simulation time 12557560 ps
CPU time 0.88 seconds
Started Jul 03 06:00:02 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 206008 kb
Host smart-3b50aadf-7f7f-466b-a3b9-8adfffb0d6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643544800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1643544800
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.4177481026
Short name T815
Test name
Test status
Simulation time 73601808 ps
CPU time 2.78 seconds
Started Jul 03 05:59:59 PM PDT 24
Finished Jul 03 06:00:02 PM PDT 24
Peak memory 208388 kb
Host smart-bbfff1ab-2e01-44b2-9d8f-954c5afb9f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177481026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.4177481026
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3477910821
Short name T319
Test name
Test status
Simulation time 53000156 ps
CPU time 2.79 seconds
Started Jul 03 05:59:57 PM PDT 24
Finished Jul 03 06:00:00 PM PDT 24
Peak memory 214224 kb
Host smart-7b670c79-d0b5-493f-bcd2-7dfed6b8d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477910821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3477910821
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1825430876
Short name T243
Test name
Test status
Simulation time 242019303 ps
CPU time 3.34 seconds
Started Jul 03 05:59:58 PM PDT 24
Finished Jul 03 06:00:01 PM PDT 24
Peak memory 214224 kb
Host smart-a2f5dc49-436f-4794-9a52-f1a84fc15759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825430876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1825430876
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2393117972
Short name T200
Test name
Test status
Simulation time 127924212 ps
CPU time 3.07 seconds
Started Jul 03 05:59:59 PM PDT 24
Finished Jul 03 06:00:02 PM PDT 24
Peak memory 214272 kb
Host smart-c2b62d09-3081-45f0-ace8-b119ffe8f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393117972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2393117972
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.477468730
Short name T439
Test name
Test status
Simulation time 39686556 ps
CPU time 2.41 seconds
Started Jul 03 05:59:55 PM PDT 24
Finished Jul 03 05:59:58 PM PDT 24
Peak memory 206728 kb
Host smart-8386bfcf-c291-4bef-805d-67b2c2e4c8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477468730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.477468730
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2802674198
Short name T690
Test name
Test status
Simulation time 1186167743 ps
CPU time 5.3 seconds
Started Jul 03 05:59:56 PM PDT 24
Finished Jul 03 06:00:02 PM PDT 24
Peak memory 208516 kb
Host smart-94d1824b-9b5f-428a-8560-825702854f98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802674198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2802674198
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1394113955
Short name T796
Test name
Test status
Simulation time 73552398 ps
CPU time 1.83 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:05 PM PDT 24
Peak memory 206852 kb
Host smart-d73203ab-3c8f-4c6a-8443-9a4db71c20bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394113955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1394113955
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2556488925
Short name T708
Test name
Test status
Simulation time 115456505 ps
CPU time 2.41 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:02 PM PDT 24
Peak memory 207412 kb
Host smart-f71757ac-9f66-4eb7-ae51-146c14dd6635
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556488925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2556488925
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3766669644
Short name T398
Test name
Test status
Simulation time 455132744 ps
CPU time 3.92 seconds
Started Jul 03 05:59:59 PM PDT 24
Finished Jul 03 06:00:03 PM PDT 24
Peak memory 209168 kb
Host smart-f9e6f677-e9b2-4f5e-a0d8-8342d99e5823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766669644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3766669644
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.967514720
Short name T856
Test name
Test status
Simulation time 94896581 ps
CPU time 3.34 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 206908 kb
Host smart-819a12e5-efef-4ef1-8b28-ee6c86080dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967514720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.967514720
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.765016100
Short name T219
Test name
Test status
Simulation time 1950375306 ps
CPU time 20.16 seconds
Started Jul 03 05:59:58 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 215820 kb
Host smart-ff8f071a-a573-4f94-80ea-7467c29236ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765016100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.765016100
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2447084986
Short name T615
Test name
Test status
Simulation time 98476466 ps
CPU time 4.9 seconds
Started Jul 03 05:59:59 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 208668 kb
Host smart-0b99511a-00ec-41ce-b06e-21c83521431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447084986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2447084986
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1599403345
Short name T808
Test name
Test status
Simulation time 115991780 ps
CPU time 2 seconds
Started Jul 03 05:59:57 PM PDT 24
Finished Jul 03 06:00:00 PM PDT 24
Peak memory 210216 kb
Host smart-c326e6c7-67a9-4b52-9435-ae67ff1c0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599403345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1599403345
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2029613861
Short name T430
Test name
Test status
Simulation time 32166830 ps
CPU time 0.81 seconds
Started Jul 03 06:00:07 PM PDT 24
Finished Jul 03 06:00:08 PM PDT 24
Peak memory 205968 kb
Host smart-fafb3920-699c-4258-924f-a33fa2f03cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029613861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2029613861
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2131922209
Short name T835
Test name
Test status
Simulation time 1170095945 ps
CPU time 5.47 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:11 PM PDT 24
Peak memory 220660 kb
Host smart-23bda771-e86b-4d02-a7fd-82fe6bb5e5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131922209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2131922209
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.475922006
Short name T468
Test name
Test status
Simulation time 19673156 ps
CPU time 1.78 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:06 PM PDT 24
Peak memory 216452 kb
Host smart-82f1f4ea-715c-4e5f-9240-1d3df0914aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475922006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.475922006
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2321555656
Short name T292
Test name
Test status
Simulation time 83598845 ps
CPU time 3.33 seconds
Started Jul 03 06:00:06 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 214308 kb
Host smart-121def6e-d7fa-40af-876e-4136d74189c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321555656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2321555656
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.824696994
Short name T114
Test name
Test status
Simulation time 202183463 ps
CPU time 2.35 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:08 PM PDT 24
Peak memory 207352 kb
Host smart-87d1d90f-1b96-4b8f-af8f-48ba1c061193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824696994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.824696994
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1106699725
Short name T731
Test name
Test status
Simulation time 50738936 ps
CPU time 2.96 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:08 PM PDT 24
Peak memory 214324 kb
Host smart-bf43e754-779f-4697-8e71-304d7209513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106699725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1106699725
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2477986494
Short name T277
Test name
Test status
Simulation time 2718941939 ps
CPU time 20.17 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:23 PM PDT 24
Peak memory 218376 kb
Host smart-98a0be3b-ada4-4387-b5b4-f8f287f73e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477986494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2477986494
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.822269546
Short name T880
Test name
Test status
Simulation time 273261617 ps
CPU time 6.5 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 207932 kb
Host smart-c427f97a-f110-4aea-9293-e7713c99fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822269546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.822269546
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2802811496
Short name T577
Test name
Test status
Simulation time 132595832 ps
CPU time 2.19 seconds
Started Jul 03 06:00:04 PM PDT 24
Finished Jul 03 06:00:07 PM PDT 24
Peak memory 206872 kb
Host smart-0f08c317-0c30-40c4-9a5a-c6f892e7b5ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802811496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2802811496
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2160705442
Short name T702
Test name
Test status
Simulation time 201094566 ps
CPU time 3.77 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 208972 kb
Host smart-3e19f977-2d42-44b9-a9ad-f5d5685ff1c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160705442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2160705442
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1947064134
Short name T764
Test name
Test status
Simulation time 192149278 ps
CPU time 5.44 seconds
Started Jul 03 06:00:01 PM PDT 24
Finished Jul 03 06:00:07 PM PDT 24
Peak memory 208128 kb
Host smart-9d15b08a-9c66-4aa0-abb2-d37f26be70c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947064134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1947064134
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3036376709
Short name T530
Test name
Test status
Simulation time 68942821 ps
CPU time 3.39 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 218392 kb
Host smart-1e50e05b-da31-4e03-92ca-afe9c845d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036376709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3036376709
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.681417661
Short name T795
Test name
Test status
Simulation time 134469389 ps
CPU time 3.25 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:07 PM PDT 24
Peak memory 208624 kb
Host smart-33228ca2-f0b4-46e8-a1a2-cdf10fdac46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681417661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.681417661
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4226403673
Short name T78
Test name
Test status
Simulation time 1809825822 ps
CPU time 43.24 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 216512 kb
Host smart-74d2d519-735f-4299-84e0-dc8627ff12ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226403673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4226403673
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1465506096
Short name T137
Test name
Test status
Simulation time 207236164 ps
CPU time 5.76 seconds
Started Jul 03 06:00:03 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 208088 kb
Host smart-01f94dce-36d6-40d2-9d39-55e5fbec3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465506096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1465506096
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.755917187
Short name T42
Test name
Test status
Simulation time 305982078 ps
CPU time 3.54 seconds
Started Jul 03 06:00:00 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 210464 kb
Host smart-a358d449-26ef-4bd8-8104-17bdd297ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755917187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.755917187
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.692257460
Short name T580
Test name
Test status
Simulation time 14803622 ps
CPU time 0.79 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 206020 kb
Host smart-a9b6d38b-e40c-4080-b2ba-f8ac44755c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692257460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.692257460
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2469920038
Short name T698
Test name
Test status
Simulation time 138345267 ps
CPU time 4.63 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 222856 kb
Host smart-4c877081-92bf-4c0c-9537-5424dd61277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469920038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2469920038
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2471979822
Short name T52
Test name
Test status
Simulation time 755434470 ps
CPU time 5.77 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:20 PM PDT 24
Peak memory 218252 kb
Host smart-6fce351b-edd9-4014-ae89-5199e9d342c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471979822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2471979822
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.749813954
Short name T104
Test name
Test status
Simulation time 1372726014 ps
CPU time 9.24 seconds
Started Jul 03 06:00:04 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 214424 kb
Host smart-3449024f-9441-4b96-b974-4d61d3fbd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749813954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.749813954
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3917948199
Short name T345
Test name
Test status
Simulation time 106169864 ps
CPU time 4.56 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 214232 kb
Host smart-3c8cb5ff-cf7e-499f-b738-a1e6a44d288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917948199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3917948199
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2040663044
Short name T746
Test name
Test status
Simulation time 153228021 ps
CPU time 4.94 seconds
Started Jul 03 06:00:04 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 206164 kb
Host smart-0ea618f3-e753-4d51-b0e8-c30f77b38f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040663044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2040663044
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.54030313
Short name T604
Test name
Test status
Simulation time 324770675 ps
CPU time 4.48 seconds
Started Jul 03 06:00:04 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 218536 kb
Host smart-d09f5100-1164-4f7c-90d2-b3a3777f16ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54030313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.54030313
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.714340712
Short name T206
Test name
Test status
Simulation time 5133171272 ps
CPU time 35.46 seconds
Started Jul 03 06:00:14 PM PDT 24
Finished Jul 03 06:00:50 PM PDT 24
Peak memory 208448 kb
Host smart-37a57599-9cdd-4c10-b090-98665867a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714340712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.714340712
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1069044547
Short name T477
Test name
Test status
Simulation time 1209303466 ps
CPU time 5.52 seconds
Started Jul 03 06:00:14 PM PDT 24
Finished Jul 03 06:00:20 PM PDT 24
Peak memory 209180 kb
Host smart-8dc77c40-3706-43b8-9990-551e71337be8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069044547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1069044547
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3350349024
Short name T603
Test name
Test status
Simulation time 34911829 ps
CPU time 2.44 seconds
Started Jul 03 06:00:06 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 207248 kb
Host smart-d1232637-e78f-4963-8922-a280a1772634
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350349024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3350349024
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3452157954
Short name T870
Test name
Test status
Simulation time 73769568 ps
CPU time 3.27 seconds
Started Jul 03 06:00:05 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 207040 kb
Host smart-d2d726ad-587b-4236-bc4d-48b1f1680b33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452157954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3452157954
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2197626782
Short name T557
Test name
Test status
Simulation time 61251668 ps
CPU time 2.1 seconds
Started Jul 03 06:00:10 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 215136 kb
Host smart-789480eb-be2d-4f5e-9d7c-7f3c3e8def6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197626782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2197626782
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.618266387
Short name T752
Test name
Test status
Simulation time 83481063 ps
CPU time 1.75 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:15 PM PDT 24
Peak memory 206948 kb
Host smart-adf83bb0-5baa-4995-a888-895c5ce0f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618266387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.618266387
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2818002342
Short name T758
Test name
Test status
Simulation time 1955567619 ps
CPU time 61.95 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:01:16 PM PDT 24
Peak memory 215844 kb
Host smart-c640f854-15d1-41ec-83e2-3bd1a30bfa13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818002342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2818002342
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1059528445
Short name T627
Test name
Test status
Simulation time 103123226 ps
CPU time 4.76 seconds
Started Jul 03 06:00:06 PM PDT 24
Finished Jul 03 06:00:11 PM PDT 24
Peak memory 209272 kb
Host smart-89bd05a6-c3c6-4efe-94bb-31a211425f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059528445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1059528445
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3976872796
Short name T175
Test name
Test status
Simulation time 142654797 ps
CPU time 1.79 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:15 PM PDT 24
Peak memory 210444 kb
Host smart-2f59a3f0-e4bc-42a6-a537-9070629772c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976872796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3976872796
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1639504369
Short name T195
Test name
Test status
Simulation time 34537555 ps
CPU time 0.84 seconds
Started Jul 03 05:56:41 PM PDT 24
Finished Jul 03 05:56:42 PM PDT 24
Peak memory 206032 kb
Host smart-edc7d815-a0ef-45c6-bf3a-f629e5508122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639504369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1639504369
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.620671610
Short name T357
Test name
Test status
Simulation time 92837689 ps
CPU time 3.4 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 05:56:40 PM PDT 24
Peak memory 214300 kb
Host smart-41c85a55-fd1a-46e2-aa40-faf0d770b806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620671610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.620671610
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1486367210
Short name T314
Test name
Test status
Simulation time 227499898 ps
CPU time 3.2 seconds
Started Jul 03 05:56:42 PM PDT 24
Finished Jul 03 05:56:46 PM PDT 24
Peak memory 208156 kb
Host smart-595b048c-af67-460d-a3e6-8f51d66371ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486367210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1486367210
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1904859959
Short name T326
Test name
Test status
Simulation time 75779322 ps
CPU time 2.35 seconds
Started Jul 03 05:56:38 PM PDT 24
Finished Jul 03 05:56:41 PM PDT 24
Peak memory 209780 kb
Host smart-8393a95d-0386-4d93-a82c-dec5cd23ee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904859959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1904859959
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3380488616
Short name T873
Test name
Test status
Simulation time 153498907 ps
CPU time 3.96 seconds
Started Jul 03 05:56:40 PM PDT 24
Finished Jul 03 05:56:44 PM PDT 24
Peak memory 214388 kb
Host smart-667b1d0d-0e0a-4eec-91b0-b704b64394b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380488616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3380488616
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2031652788
Short name T583
Test name
Test status
Simulation time 210486219 ps
CPU time 2.76 seconds
Started Jul 03 05:56:42 PM PDT 24
Finished Jul 03 05:56:45 PM PDT 24
Peak memory 222256 kb
Host smart-68b7ffc2-bf80-4ca5-872b-bc2c15de29b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031652788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2031652788
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.453383954
Short name T305
Test name
Test status
Simulation time 1318583053 ps
CPU time 3.85 seconds
Started Jul 03 05:56:39 PM PDT 24
Finished Jul 03 05:56:44 PM PDT 24
Peak memory 219928 kb
Host smart-d75bf4c0-e8fa-4ec8-af04-ce4786873117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453383954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.453383954
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload.645751640
Short name T630
Test name
Test status
Simulation time 30006749 ps
CPU time 2.32 seconds
Started Jul 03 05:56:37 PM PDT 24
Finished Jul 03 05:56:39 PM PDT 24
Peak memory 206864 kb
Host smart-7f712cba-39ee-431a-bdcf-fa246fae0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645751640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.645751640
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1593559143
Short name T625
Test name
Test status
Simulation time 920737002 ps
CPU time 25.04 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 05:57:01 PM PDT 24
Peak memory 208304 kb
Host smart-8d8a8f90-013a-4e80-8ecc-63baf158b250
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593559143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1593559143
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1083145859
Short name T476
Test name
Test status
Simulation time 131731436 ps
CPU time 4.3 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 05:56:41 PM PDT 24
Peak memory 208284 kb
Host smart-a87ddeec-7783-484b-a438-b63384a9cc62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083145859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1083145859
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4122762013
Short name T139
Test name
Test status
Simulation time 470526138 ps
CPU time 4.21 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 05:56:41 PM PDT 24
Peak memory 206960 kb
Host smart-d8dd1be4-e54b-402d-81af-f6f48838b2f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122762013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4122762013
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3980254870
Short name T755
Test name
Test status
Simulation time 139681383 ps
CPU time 2.23 seconds
Started Jul 03 05:56:42 PM PDT 24
Finished Jul 03 05:56:44 PM PDT 24
Peak memory 215724 kb
Host smart-b2f8c6ab-aa81-46e4-bfae-4810f3a10648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980254870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3980254870
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.781520283
Short name T513
Test name
Test status
Simulation time 53912183 ps
CPU time 2.59 seconds
Started Jul 03 05:56:36 PM PDT 24
Finished Jul 03 05:56:39 PM PDT 24
Peak memory 208708 kb
Host smart-ea2603e1-e781-4815-bb3b-dcec8ffe1690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781520283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.781520283
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.813895572
Short name T629
Test name
Test status
Simulation time 416803658 ps
CPU time 8.15 seconds
Started Jul 03 05:56:42 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 210864 kb
Host smart-a650d8c2-1a8c-4c44-8d31-98c2828a4a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813895572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.813895572
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4132898183
Short name T516
Test name
Test status
Simulation time 22244080 ps
CPU time 0.87 seconds
Started Jul 03 05:56:54 PM PDT 24
Finished Jul 03 05:56:55 PM PDT 24
Peak memory 205976 kb
Host smart-1b4aaecd-0e44-4146-8eb8-8e1875ddf802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132898183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4132898183
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3425656230
Short name T27
Test name
Test status
Simulation time 274258870 ps
CPU time 4.35 seconds
Started Jul 03 05:56:51 PM PDT 24
Finished Jul 03 05:56:56 PM PDT 24
Peak memory 214344 kb
Host smart-da670e4f-3c4a-4aac-a3a8-b194d3dfd627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425656230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3425656230
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3219112452
Short name T875
Test name
Test status
Simulation time 205602282 ps
CPU time 6.46 seconds
Started Jul 03 05:56:45 PM PDT 24
Finished Jul 03 05:56:52 PM PDT 24
Peak memory 208564 kb
Host smart-d552f47a-6f66-4c3d-a52d-617569d5a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219112452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3219112452
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3424095556
Short name T762
Test name
Test status
Simulation time 70147585 ps
CPU time 3.67 seconds
Started Jul 03 05:56:50 PM PDT 24
Finished Jul 03 05:56:54 PM PDT 24
Peak memory 214288 kb
Host smart-da439daa-a2a9-4df8-adc0-2fa2d5811e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424095556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3424095556
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.713716158
Short name T663
Test name
Test status
Simulation time 86175274 ps
CPU time 1.32 seconds
Started Jul 03 05:56:49 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 206228 kb
Host smart-2a376256-d6dc-4a5a-b1b5-33e651f60d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713716158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.713716158
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3942282081
Short name T91
Test name
Test status
Simulation time 81299231 ps
CPU time 1.97 seconds
Started Jul 03 05:56:47 PM PDT 24
Finished Jul 03 05:56:50 PM PDT 24
Peak memory 207312 kb
Host smart-c7343ee4-85e2-478a-8563-6ed4bebf907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942282081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3942282081
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.393293971
Short name T433
Test name
Test status
Simulation time 801483022 ps
CPU time 5.6 seconds
Started Jul 03 05:56:45 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 207892 kb
Host smart-0f560f1c-4707-44ac-bcc1-4d51e7cf1bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393293971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.393293971
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4197305844
Short name T529
Test name
Test status
Simulation time 332659976 ps
CPU time 4.17 seconds
Started Jul 03 05:56:46 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 208536 kb
Host smart-c3b8356f-4a7b-4b41-ab14-05ca12900d38
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197305844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4197305844
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4244011141
Short name T541
Test name
Test status
Simulation time 173974678 ps
CPU time 2.46 seconds
Started Jul 03 05:56:46 PM PDT 24
Finished Jul 03 05:56:49 PM PDT 24
Peak memory 207016 kb
Host smart-61e063ba-74e2-4798-87e2-5eb89d608fe9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244011141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4244011141
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3882037173
Short name T518
Test name
Test status
Simulation time 1542111210 ps
CPU time 34.68 seconds
Started Jul 03 05:56:47 PM PDT 24
Finished Jul 03 05:57:22 PM PDT 24
Peak memory 207960 kb
Host smart-db41ede3-a95e-40a0-8d65-f181b374d5a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882037173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3882037173
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3827643922
Short name T791
Test name
Test status
Simulation time 56963639 ps
CPU time 2.87 seconds
Started Jul 03 05:56:49 PM PDT 24
Finished Jul 03 05:56:53 PM PDT 24
Peak memory 214376 kb
Host smart-2f5e2606-09c5-447b-9ff1-e9e155612b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827643922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3827643922
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3951349679
Short name T544
Test name
Test status
Simulation time 151713909 ps
CPU time 3.76 seconds
Started Jul 03 05:56:46 PM PDT 24
Finished Jul 03 05:56:50 PM PDT 24
Peak memory 208080 kb
Host smart-397c4a34-c1a8-4d6b-84dc-4774d4180ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951349679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3951349679
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3308506610
Short name T180
Test name
Test status
Simulation time 1254849929 ps
CPU time 23.76 seconds
Started Jul 03 05:56:50 PM PDT 24
Finished Jul 03 05:57:14 PM PDT 24
Peak memory 222456 kb
Host smart-f0fc95c6-a38b-401b-baae-772c05a25c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308506610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3308506610
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3766916262
Short name T3
Test name
Test status
Simulation time 43400059 ps
CPU time 2.51 seconds
Started Jul 03 05:56:50 PM PDT 24
Finished Jul 03 05:56:54 PM PDT 24
Peak memory 218404 kb
Host smart-542516da-2c59-4962-b938-53d264415c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766916262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3766916262
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3228610492
Short name T423
Test name
Test status
Simulation time 12251997 ps
CPU time 0.75 seconds
Started Jul 03 05:56:58 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 206008 kb
Host smart-cef9f99d-a3d5-407f-be8e-389897f6caab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228610492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3228610492
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3767175855
Short name T407
Test name
Test status
Simulation time 164268580 ps
CPU time 3.36 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 214312 kb
Host smart-d951a148-7f16-4d30-8115-d0f30a2ec727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767175855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3767175855
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1872196201
Short name T74
Test name
Test status
Simulation time 37883875 ps
CPU time 1.82 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:56:58 PM PDT 24
Peak memory 208176 kb
Host smart-27bf4ed9-a630-445d-b620-522db5fea780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872196201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1872196201
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1828661570
Short name T276
Test name
Test status
Simulation time 135926848 ps
CPU time 2.62 seconds
Started Jul 03 05:56:56 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 218664 kb
Host smart-3ff2e218-3d84-4a8b-88b0-e0c0a3f57609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828661570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1828661570
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.603526808
Short name T242
Test name
Test status
Simulation time 1268597695 ps
CPU time 34.94 seconds
Started Jul 03 05:56:51 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 209504 kb
Host smart-60a99f5b-dc40-4d66-81f6-62b2b7ccbbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603526808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.603526808
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3384226523
Short name T372
Test name
Test status
Simulation time 568275988 ps
CPU time 7.33 seconds
Started Jul 03 05:56:50 PM PDT 24
Finished Jul 03 05:56:58 PM PDT 24
Peak memory 210320 kb
Host smart-c3a644ca-c4d6-4af8-b8da-e701199948a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384226523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3384226523
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1791209309
Short name T283
Test name
Test status
Simulation time 103287965 ps
CPU time 3.31 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 208688 kb
Host smart-774fe843-c75b-4f19-9e68-15e18529d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791209309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1791209309
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.295216772
Short name T558
Test name
Test status
Simulation time 297543713 ps
CPU time 2.67 seconds
Started Jul 03 05:56:54 PM PDT 24
Finished Jul 03 05:56:57 PM PDT 24
Peak memory 207360 kb
Host smart-f8460f29-3612-481e-af12-02385b0337b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295216772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.295216772
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2721716203
Short name T445
Test name
Test status
Simulation time 34780763 ps
CPU time 2.32 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:56:58 PM PDT 24
Peak memory 206892 kb
Host smart-0ad9130d-0d17-4833-86d0-c85d5ca36ab8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721716203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2721716203
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2330027620
Short name T713
Test name
Test status
Simulation time 32948950 ps
CPU time 2.25 seconds
Started Jul 03 05:56:53 PM PDT 24
Finished Jul 03 05:56:56 PM PDT 24
Peak memory 206904 kb
Host smart-bd7092d7-04bb-456c-b75c-c56f1c4a8b2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330027620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2330027620
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3879360139
Short name T678
Test name
Test status
Simulation time 174779106 ps
CPU time 2.47 seconds
Started Jul 03 05:56:54 PM PDT 24
Finished Jul 03 05:56:57 PM PDT 24
Peak memory 207644 kb
Host smart-6ce9cf04-1a2b-4471-b365-f412bfa90f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879360139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3879360139
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1092419172
Short name T393
Test name
Test status
Simulation time 675802322 ps
CPU time 4.95 seconds
Started Jul 03 05:56:54 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 206848 kb
Host smart-77cb8910-0361-4b19-8607-13d696f49db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092419172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1092419172
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4219666808
Short name T190
Test name
Test status
Simulation time 1216985820 ps
CPU time 21.19 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:22 PM PDT 24
Peak memory 220516 kb
Host smart-82aa4a42-4e83-4281-bd3d-e7f5aa28e23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219666808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4219666808
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3745536855
Short name T131
Test name
Test status
Simulation time 1105910987 ps
CPU time 18.71 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:57:14 PM PDT 24
Peak memory 222980 kb
Host smart-9bf6d2f5-5c34-47d4-aa10-6b1a825a693a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745536855 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3745536855
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1916460987
Short name T805
Test name
Test status
Simulation time 730121247 ps
CPU time 9.27 seconds
Started Jul 03 05:56:53 PM PDT 24
Finished Jul 03 05:57:03 PM PDT 24
Peak memory 218196 kb
Host smart-5f950a86-664a-40f7-8acb-4c4d86421aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916460987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1916460987
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2106492876
Short name T382
Test name
Test status
Simulation time 717696874 ps
CPU time 2.9 seconds
Started Jul 03 05:56:52 PM PDT 24
Finished Jul 03 05:56:56 PM PDT 24
Peak memory 210572 kb
Host smart-a89d991e-4782-44ba-8ef2-351cdce1cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106492876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2106492876
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2066922417
Short name T548
Test name
Test status
Simulation time 10614857 ps
CPU time 0.74 seconds
Started Jul 03 05:56:59 PM PDT 24
Finished Jul 03 05:57:00 PM PDT 24
Peak memory 205980 kb
Host smart-d44548a7-2924-4044-9005-2da3fa10488a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066922417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2066922417
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.162263637
Short name T386
Test name
Test status
Simulation time 130988941 ps
CPU time 4.79 seconds
Started Jul 03 05:56:58 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 214352 kb
Host smart-4d53ac0e-1d08-430c-8ab9-087fdd898fe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162263637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.162263637
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2046250402
Short name T37
Test name
Test status
Simulation time 4700517376 ps
CPU time 21.58 seconds
Started Jul 03 05:56:59 PM PDT 24
Finished Jul 03 05:57:21 PM PDT 24
Peak memory 209648 kb
Host smart-d29f7788-27cc-4b01-b61a-637646f597bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046250402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2046250402
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3067827249
Short name T471
Test name
Test status
Simulation time 52936069 ps
CPU time 2.14 seconds
Started Jul 03 05:56:56 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 222612 kb
Host smart-8633c603-491c-4590-afff-0e5942a130d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067827249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3067827249
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1839530418
Short name T575
Test name
Test status
Simulation time 117221054 ps
CPU time 4.99 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:57:01 PM PDT 24
Peak memory 222496 kb
Host smart-e8b45d60-5cc2-44f8-b305-c23a2d3718ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839530418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1839530418
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1055669541
Short name T231
Test name
Test status
Simulation time 71380779 ps
CPU time 2.99 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 216044 kb
Host smart-49255692-82f1-45f8-9ace-83b5ed912339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055669541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1055669541
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4237193746
Short name T817
Test name
Test status
Simulation time 92491204 ps
CPU time 4.12 seconds
Started Jul 03 05:56:59 PM PDT 24
Finished Jul 03 05:57:03 PM PDT 24
Peak memory 209468 kb
Host smart-77e1f8b5-bcaf-43da-905f-0cfc45a247ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237193746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4237193746
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2075904670
Short name T714
Test name
Test status
Simulation time 462772859 ps
CPU time 3.56 seconds
Started Jul 03 05:56:56 PM PDT 24
Finished Jul 03 05:57:00 PM PDT 24
Peak memory 208540 kb
Host smart-44602e22-2b1f-4468-8472-c64857171db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075904670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2075904670
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.657487959
Short name T512
Test name
Test status
Simulation time 92600455 ps
CPU time 3.34 seconds
Started Jul 03 05:56:57 PM PDT 24
Finished Jul 03 05:57:00 PM PDT 24
Peak memory 207008 kb
Host smart-b6dc607e-01a8-4d33-a470-805f32f26325
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657487959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.657487959
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2785767275
Short name T595
Test name
Test status
Simulation time 197639666 ps
CPU time 5.79 seconds
Started Jul 03 05:56:58 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 208068 kb
Host smart-fdc39f19-d14f-4902-8870-f2dc4b4848fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785767275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2785767275
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1900818535
Short name T425
Test name
Test status
Simulation time 368716005 ps
CPU time 3.95 seconds
Started Jul 03 05:56:57 PM PDT 24
Finished Jul 03 05:57:01 PM PDT 24
Peak memory 209164 kb
Host smart-c4c32af3-0d16-4b4f-83d1-f8beffbf1d83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900818535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1900818535
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1655005655
Short name T665
Test name
Test status
Simulation time 240637341 ps
CPU time 6.95 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:07 PM PDT 24
Peak memory 208160 kb
Host smart-f9dab643-bba2-4979-9853-9e6e1e78bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655005655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1655005655
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1215113159
Short name T192
Test name
Test status
Simulation time 246175030 ps
CPU time 3.68 seconds
Started Jul 03 05:56:55 PM PDT 24
Finished Jul 03 05:56:59 PM PDT 24
Peak memory 208484 kb
Host smart-8363e563-2a3c-4655-b584-8f2c7339fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215113159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1215113159
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3622546893
Short name T226
Test name
Test status
Simulation time 1652131622 ps
CPU time 22.96 seconds
Started Jul 03 05:57:02 PM PDT 24
Finished Jul 03 05:57:25 PM PDT 24
Peak memory 215944 kb
Host smart-93c75d15-1bbf-4353-9d9d-37e6a7f02465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622546893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3622546893
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3914020118
Short name T891
Test name
Test status
Simulation time 118069595 ps
CPU time 7.38 seconds
Started Jul 03 05:57:03 PM PDT 24
Finished Jul 03 05:57:10 PM PDT 24
Peak memory 222656 kb
Host smart-16a4b6ab-0324-48f7-bf12-a903b2ea2e6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914020118 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3914020118
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1482728276
Short name T697
Test name
Test status
Simulation time 220673743 ps
CPU time 7.15 seconds
Started Jul 03 05:56:56 PM PDT 24
Finished Jul 03 05:57:03 PM PDT 24
Peak memory 216140 kb
Host smart-c899df44-ac3a-45d2-b216-44c4e4321b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482728276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1482728276
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3899648146
Short name T41
Test name
Test status
Simulation time 226758453 ps
CPU time 5.6 seconds
Started Jul 03 05:56:59 PM PDT 24
Finished Jul 03 05:57:05 PM PDT 24
Peak memory 210888 kb
Host smart-a98f584a-be6e-4a6d-b443-3b4b08c853fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899648146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3899648146
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2815793649
Short name T438
Test name
Test status
Simulation time 24537053 ps
CPU time 0.75 seconds
Started Jul 03 05:57:01 PM PDT 24
Finished Jul 03 05:57:02 PM PDT 24
Peak memory 206020 kb
Host smart-21933012-576b-44f3-93ef-42fb09e38ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815793649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2815793649
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4172024543
Short name T414
Test name
Test status
Simulation time 1625783216 ps
CPU time 8.62 seconds
Started Jul 03 05:57:01 PM PDT 24
Finished Jul 03 05:57:10 PM PDT 24
Peak memory 214680 kb
Host smart-00fdf9df-9047-4f25-9ffe-c1a662b35bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172024543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4172024543
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3589739701
Short name T882
Test name
Test status
Simulation time 1164873646 ps
CPU time 6.23 seconds
Started Jul 03 05:57:02 PM PDT 24
Finished Jul 03 05:57:09 PM PDT 24
Peak memory 218220 kb
Host smart-f4e7773f-d8cc-4b26-b2bd-e7625e30d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589739701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3589739701
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.679303078
Short name T375
Test name
Test status
Simulation time 998800444 ps
CPU time 20.08 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:20 PM PDT 24
Peak memory 208752 kb
Host smart-4e8f63dd-3772-4163-b916-64c2dbb4b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679303078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.679303078
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3206455360
Short name T340
Test name
Test status
Simulation time 107950568 ps
CPU time 3.26 seconds
Started Jul 03 05:57:01 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 214344 kb
Host smart-4db9e942-b128-47f5-972d-6fee2aa9e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206455360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3206455360
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2497817774
Short name T113
Test name
Test status
Simulation time 677126605 ps
CPU time 3.28 seconds
Started Jul 03 05:57:04 PM PDT 24
Finished Jul 03 05:57:07 PM PDT 24
Peak memory 214240 kb
Host smart-e581df46-a5df-4379-84da-8a1322f7c330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497817774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2497817774
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1084325088
Short name T623
Test name
Test status
Simulation time 48229908 ps
CPU time 3 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:03 PM PDT 24
Peak memory 207872 kb
Host smart-a79ac878-2ac9-43b2-83a6-cef2b16c1625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084325088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1084325088
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3936267355
Short name T582
Test name
Test status
Simulation time 909783840 ps
CPU time 6.5 seconds
Started Jul 03 05:57:00 PM PDT 24
Finished Jul 03 05:57:07 PM PDT 24
Peak memory 210116 kb
Host smart-36336c37-45c5-41fb-bff6-836366a62f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936267355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3936267355
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3896362739
Short name T329
Test name
Test status
Simulation time 857003342 ps
CPU time 6.89 seconds
Started Jul 03 05:57:02 PM PDT 24
Finished Jul 03 05:57:09 PM PDT 24
Peak memory 208876 kb
Host smart-5cea7f89-e0dd-487c-b4b8-20d12c33da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896362739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3896362739
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1719705593
Short name T185
Test name
Test status
Simulation time 644570106 ps
CPU time 4.45 seconds
Started Jul 03 05:56:59 PM PDT 24
Finished Jul 03 05:57:04 PM PDT 24
Peak memory 208156 kb
Host smart-81144924-e466-46f4-a341-1792812b5807
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719705593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1719705593
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2236650849
Short name T116
Test name
Test status
Simulation time 1644539301 ps
CPU time 42.08 seconds
Started Jul 03 05:57:01 PM PDT 24
Finished Jul 03 05:57:43 PM PDT 24
Peak memory 208100 kb
Host smart-4709835d-d42f-4b5e-9179-3d3b991e7b5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236650849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2236650849
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1623353750
Short name T722
Test name
Test status
Simulation time 140273816 ps
CPU time 3.5 seconds
Started Jul 03 05:57:04 PM PDT 24
Finished Jul 03 05:57:08 PM PDT 24
Peak memory 207052 kb
Host smart-abf78913-820e-43af-a9d5-328f2ec72b3d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623353750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1623353750
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2558011389
Short name T426
Test name
Test status
Simulation time 196044879 ps
CPU time 5.35 seconds
Started Jul 03 05:57:04 PM PDT 24
Finished Jul 03 05:57:10 PM PDT 24
Peak memory 218268 kb
Host smart-f38980a4-b349-47b3-b105-883db10a34bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558011389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2558011389
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2900274584
Short name T777
Test name
Test status
Simulation time 195292310 ps
CPU time 2.59 seconds
Started Jul 03 05:57:03 PM PDT 24
Finished Jul 03 05:57:06 PM PDT 24
Peak memory 208468 kb
Host smart-be70e692-0a04-4b08-9b7d-8024413666ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900274584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2900274584
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3788671095
Short name T332
Test name
Test status
Simulation time 4680825029 ps
CPU time 18.43 seconds
Started Jul 03 05:57:05 PM PDT 24
Finished Jul 03 05:57:24 PM PDT 24
Peak memory 216240 kb
Host smart-15870002-e233-4337-a632-3e7256c8b7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788671095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3788671095
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.600420100
Short name T647
Test name
Test status
Simulation time 201201414 ps
CPU time 3.81 seconds
Started Jul 03 05:57:01 PM PDT 24
Finished Jul 03 05:57:05 PM PDT 24
Peak memory 208200 kb
Host smart-1edf5a7e-039e-46d0-8fc2-eb25fbce6c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600420100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.600420100
Directory /workspace/9.keymgr_sw_invalid_input/latest
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