Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
59265 |
1 |
|
|
T1 |
139 |
|
T2 |
33 |
|
T3 |
147 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34045 |
1 |
|
|
T1 |
107 |
|
T3 |
65 |
|
T12 |
8 |
auto[1] |
25220 |
1 |
|
|
T1 |
32 |
|
T2 |
33 |
|
T3 |
82 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
29317 |
1 |
|
|
T1 |
70 |
|
T2 |
17 |
|
T3 |
83 |
auto[1] |
29948 |
1 |
|
|
T1 |
69 |
|
T2 |
16 |
|
T3 |
64 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16840 |
1 |
|
|
T1 |
54 |
|
T3 |
33 |
|
T14 |
3 |
all_values[0] |
auto[0] |
auto[1] |
17205 |
1 |
|
|
T1 |
53 |
|
T3 |
32 |
|
T12 |
8 |
all_values[0] |
auto[1] |
auto[0] |
12477 |
1 |
|
|
T1 |
16 |
|
T2 |
17 |
|
T3 |
50 |
all_values[0] |
auto[1] |
auto[1] |
12743 |
1 |
|
|
T1 |
16 |
|
T2 |
16 |
|
T3 |
32 |