SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
62.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 3 | 5 | 62.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 3 | 5 | 62.50 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 3 | 5 | 62.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OtpRootKeyInvalid] | 0 | 1 | 1 | |
auto[OtpRootKeyValidLow] | 0 | 1 | 1 | |
auto[FlashCreatorSeedInvalid] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[LcStateInvalid] | 132 | 1 | T23 | 48 | T183 | 24 | T184 | 24 | ||||
auto[OtpDevIdInvalid] | 48 | 1 | T23 | 12 | T183 | 36 | - | - | ||||
auto[RomDigestInvalid] | 24 | 1 | T185 | 24 | - | - | - | - | ||||
auto[RomDigestValidLow] | 96 | 1 | T183 | 12 | T92 | 12 | T87 | 36 | ||||
auto[FlashOwnerSeedInvalid] | 24 | 1 | T21 | 24 | - | - | - | - |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |