Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4925

1

T1

3

T2

6

T3

3

auto[1]

544

1

T4

8

T53

3

T77

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4925

1

T1

3

T2

6

T3

3

auto[1]

544

1

T4

8

T53

3

T77

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4868

1

T1

1

T2

6

T3

3

auto[1]

601

1

T1

2

T12

1

T16

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4868

1

T1

1

T2

6

T3

3

auto[1]

601

1

T1

2

T12

1

T16

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T4	2		T108	2		T178	3
auto[OpGenId]	1170	1			T1	1		T3	2		T12	3
auto[OpGenSwOut]	1195	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	2594	1			T1	1		T2	5		T12	1
auto[OpDisable]	76	1			T46	1		T62	1		T52	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T4	2		T108	2		T178	3
auto[OpGenId]	1170	1			T1	1		T3	2		T12	3
auto[OpGenSwOut]	1195	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	2594	1			T1	1		T2	5		T12	1
auto[OpDisable]	76	1			T46	1		T62	1		T52	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4889

1

T1

3

T2

5

T3

3

auto[1]

580

1

T2

1

T12

1

T15

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4889

1

T1

3

T2

5

T3

3

auto[1]

580

1

T2

1

T12

1

T15

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5177

1

T1

3

T2

6

T3

3

auto[1]

292

1

T108

9

T101

1

T121

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1814	1			T1	1		T2	2		T3	2
auto[1]	742	1			T1	1		T2	2		T3	1
auto[2]	752	1			T15	1		T16	1		T81	1
auto[3]	706	1			T1	1		T2	1		T15	1
auto[4]	367	1			T26	1		T81	2		T4	2
auto[5]	391	1			T12	1		T15	2		T16	1
auto[6]	359	1			T12	1		T17	1		T26	1
auto[7]	338	1			T2	1		T12	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1455	1			T2	1		T12	3		T15	3
clear_one[1]	742	1			T1	1		T2	2		T3	1
clear_one[2]	752	1			T15	1		T16	1		T81	1
clear_one[3]	706	1			T1	1		T2	1		T15	1
clear_none	1814	1			T1	1		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	996	1			T3	1		T12	3		T16	1
auto[StInit]	644	1			T1	1		T2	1		T3	2
auto[StCreatorRootKey]	614	1			T1	1		T2	1		T12	1
auto[StOwnerIntKey]	557	1			T2	1		T12	1		T15	1
auto[StOwnerKey]	468	1			T1	1		T2	1		T15	1
auto[StDisabled]	1925	1			T2	2		T12	2		T15	4
auto[StInvalid]	265	1			T26	5		T34	4		T47	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	996	1			T3	1		T12	3		T16	1
auto[StInit]	644	1			T1	1		T2	1		T3	2
auto[StCreatorRootKey]	614	1			T1	1		T2	1		T12	1
auto[StOwnerIntKey]	557	1			T2	1		T12	1		T15	1
auto[StOwnerKey]	468	1			T1	1		T2	1		T15	1
auto[StDisabled]	1925	1			T2	2		T12	2		T15	4
auto[StInvalid]	265	1			T26	5		T34	4		T47	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T101	1		T214	1		T215	1
auto[0]	auto[StReset]	auto[OpGenId]	164	1			T17	1		T82	1		T53	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	162	1			T3	1		T12	1		T16	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	253	1			T17	1		T4	1		T182	1
auto[0]	auto[StInit]	auto[OpAdvance]	56	1			T4	1		T178	1		T53	1
auto[0]	auto[StInit]	auto[OpGenId]	89	1			T1	1		T3	1		T4	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	74	1			T4	1		T53	2		T52	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	180	1			T2	1		T14	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	27	1			T122	1		T6	3		T216	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	59	1			T4	1		T54	1		T180	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	49	1			T4	1		T108	1		T53	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	88	1			T15	1		T4	2		T182	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T53	1		T217	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T218	1		T188	1		T122	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	37	1			T79	1		T101	1		T66	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T52	2		T134	1		T219	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T220	1		T200	1		T201	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T116	1		T221	1		T222	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T66	1		T218	1		T177	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T181	1		T75	1		T52	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	16	1			T52	1		T124	1		T223	1
auto[0]	auto[StDisabled]	auto[OpGenId]	66	1			T12	1		T102	1		T66	4
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T4	2		T53	1		T54	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T2	1		T15	1		T4	3
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T46	1		T52	1		T54	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T47	1		T224	1		T225	2
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T26	1		T60	1		T226	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	20	1			T26	1		T35	1		T227	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T26	1		T34	1		T48	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T12	2		T62	1		T189	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	26	1			T66	1		T83	1		T188	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	42	1			T62	1		T182	1		T48	1
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T228	1		T229	1		T51	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T3	1		T53	1		T230	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T23	1		T118	1		T230	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	14	1			T77	1		T52	2		T231	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T53	1		T232	1		T61	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T115	1		T230	1		T233	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T83	1		T234	1		T6	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T219	1		T235	1		T236	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T188	1		T6	1		T237	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T180	1		T238	1		T239	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T54	1		T45	1		T240	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T2	1		T81	1		T182	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T241	1		T87	1		T242	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T53	1		T76	1		T243	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T1	1		T122	1		T61	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T2	1		T66	1		T244	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T4	1		T108	2		T52	1
auto[1]	auto[StDisabled]	auto[OpGenId]	66	1			T108	1		T66	2		T188	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T4	1		T53	1		T102	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T46	1		T4	2		T108	3
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T70	1		T58	1		T189	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T24	1		T245	1		T246	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T245	1		T246	1		T226	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T35	1		T247	1		T248	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T48	1		T246	1		T249	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T125	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	20	1			T52	1		T188	2		T247	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T191	1		T71	1		T250	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	61	1			T182	1		T53	1		T77	1
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T68	1		T125	1		T61	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T53	1		T67	1		T115	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T66	1		T183	1		T251	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	30	1			T182	1		T23	2		T114	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T252	1		T253	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T66	1		T188	1		T254	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T54	1		T67	1		T114	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	50	1			T53	1		T75	1		T52	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T68	1		T60	1		T255	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T4	1		T213	2		T256	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T66	1		T117	1		T118	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T53	2		T99	1		T235	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T257	1		-	-		-	-
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T118	1		T258	1		T259	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T53	1		T260	1		T167	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T15	1		T99	1		T261	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	33	1			T178	1		T66	1		T188	2
auto[2]	auto[StDisabled]	auto[OpGenId]	67	1			T4	1		T178	1		T52	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T16	1		T4	1		T53	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T81	1		T4	1		T182	2
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T238	1		T262	1		T263	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T48	1		T248	1		T264	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T34	1		T245	1		T224	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T227	1		T245	1		T41	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T48	1		T85	1		T41	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T120	1		T67	1		T83	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	15	1			T188	2		T21	1		T265	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	33	1			T182	1		T188	2		T266	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T216	1		T200	1		T202	1
auto[3]	auto[StInit]	auto[OpGenId]	6	1			T72	2		T267	1		T268	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T76	1		T124	2		T61	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T4	1		T234	1		T266	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T269	1		T200	1		T202	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T4	1		T6	1		T116	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	22	1			T4	1		T70	1		T239	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T1	1		T98	1		T54	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T270	1		T213	1		T201	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T54	1		T188	1		T61	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T124	2		T61	1		T254	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T181	1		T271	1		T94	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T66	1		T188	1		T272	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T53	1		T6	1		T117	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T53	1		T102	1		T123	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T182	1		T74	1		T219	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	31	1			T52	1		T121	2		T116	1
auto[3]	auto[StDisabled]	auto[OpGenId]	70	1			T16	1		T52	1		T120	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T2	1		T4	1		T52	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T15	1		T81	1		T182	1
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T62	1		T66	1		T6	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T227	1		T249	1		T273	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T34	1		T227	1		T247	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T47	1		T245	1		T274	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T47	1		T48	1		T275	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T187	1		T85	1		T260	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T66	1		T254	1		T189	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	24	1			T77	1		T85	1		T27	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T268	1		T276	1		T277	1
auto[4]	auto[StInit]	auto[OpGenId]	1	1			T189	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T278	1		T237	1		T276	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	7	1			T279	1		T280	1		T281	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T282	1		T208	2		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T118	1		T283	1		T207	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T188	1		T284	1		T49	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T62	1		T99	1		T285	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T72	1		T286	1		T287	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T53	1		T66	1		T238	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T4	1		T102	1		T115	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T52	1		T98	1		T21	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T250	1		T200	1		T288	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T52	1		T210	1		T51	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T6	1		T116	1		T284	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T289	1		T290	1		T291	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T66	1		T188	1		T124	1
auto[4]	auto[StDisabled]	auto[OpGenId]	30	1			T114	1		T188	1		T292	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T4	1		T53	1		T52	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	88	1			T81	2		T75	1		T52	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T52	1		T243	1		T71	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T85	1		T293	1		T294	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T26	1		T34	1		T264	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T264	1		T295	1		T296	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T48	1		T297	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T298	1		T213	1		T299	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T120	1		T300	1		T49	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T181	1		T77	1		T301	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T27	1		T302	1		T303	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T218	1		T6	1		T263	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T66	1		T188	1		T89	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	23	1			T181	1		T99	1		T23	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T21	1		T6	1		T205	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T241	1		T304	1		T305	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T45	1		T189	1		T71	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T16	1		T74	1		T52	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T139	1		T51	1		T306	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T66	1		T115	1		T33	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T114	1		T188	1		T63	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T74	1		T77	1		T52	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T307	1		T308	1		T309	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T4	1		T114	1		T252	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T6	1		T198	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T77	1		T310	1		T83	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T83	1		T188	1		T223	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T4	1		T53	1		T66	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T12	1		T62	1		T53	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T15	2		T4	1		T181	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T238	1		T72	1		T213	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	7	1			T47	1		T85	1		T311	1
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T293	1		T312	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T84	1		T313	1		T314	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T224	1		T315	1		T316	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T82	1		T53	1		T189	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	9	1			T82	1		T189	1		T317	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T99	1		T102	1		T45	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T318	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T319	1		T320	1		T51	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T52	1		T86	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T310	1		T321	1		T322	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T323	1		T213	1		T324	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T325	1		T72	1		T175	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T21	1		T27	1		T51	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T17	1		T81	1		T189	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T6	1		T216	1		T323	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T52	1		T6	1		T116	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T188	1		T326	1		T327	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T12	1		T4	1		T53	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T61	1		T270	1		T175	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	12	1			T178	1		T188	1		T121	2
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T6	1		T45	1		T328	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T81	1		T52	1		T188	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T329	1		T61	1		T323	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T4	1		T79	1		T329	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T53	3		T66	1		T114	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T53	1		T52	1		T99	2
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T54	1		T330	1		T278	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T48	1		T331	1		T332	1
auto[6]	auto[StInvalid]	auto[OpGenId]	2	1			T246	1		T333	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T35	1		T334	1		T335	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T26	1		T85	1		T315	1
auto[7]	auto[StReset]	auto[OpGenId]	5	1			T213	1		T276	1		T336	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T61	1		T49	1		T337	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T321	1		T338	2		T339	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T340	1		T341	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T16	1		T188	1		T198	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T4	1		T167	1		T86	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	6	1			T289	1		T342	1		T343	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T134	1		T189	1		T344	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T52	1		T345	1		T213	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T12	1		T4	1		T53	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T2	1		T181	1		T266	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T346	1		-	-		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T66	1		T121	2		T71	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T62	1		T108	2		T61	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T15	1		T236	1		T49	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T347	2		T348	2		T194	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T349	1		T350	1		T351	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T134	1		T239	1		T346	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T115	1		T352	1		T342	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T178	1		T45	1		T353	1
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T53	1		T66	1		T68	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T354	1		T355	1		T6	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T74	2		T99	1		T66	1
auto[7]	auto[StDisabled]	auto[OpDisable]	1	1			T72	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T356	1		T357	1		T314	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T300	1		T265	1		T224	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T227	1		T273	1		T358	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T35	1		T248	1		T359	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1455

1

T2

1

T12

3

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

419

1

T2

2

T3

1

T12

2

clear_one[1]

auto[0]

auto[0]

auto[1]

128

1

T46

1

T108

4

T182

2

clear_one[1]

auto[0]

auto[1]

auto[0]

138

1

T1

1

T81

1

T74

1

clear_one[1]

auto[0]

auto[1]

auto[1]

57

1

T108

1

T66

1

T61

1

clear_one[2]

auto[0]

auto[0]

auto[0]

459

1

T16

1

T81

1

T4

2

clear_one[2]

auto[0]

auto[0]

auto[1]

129

1

T15

1

T182

2

T181

1

clear_one[2]

auto[1]

auto[0]

auto[0]

121

1

T53

2

T77

1

T52

1

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T4

2

T52

1

T360

1

clear_one[3]

auto[0]

auto[0]

auto[0]

405

1

T2

1

T15

1

T4

4

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T1

1

T16

1

T81

1

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T77

1

T52

2

T219

3

clear_one[3]

auto[1]

auto[1]

auto[0]

44

1

T66

1

T83

1

T68

1

clear_none

auto[0]

auto[0]

auto[0]

1296

1

T1

1

T2

1

T3

2

clear_none

auto[0]

auto[0]

auto[1]

136

1

T2

1

T15

2

T46

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T4

1

T53

1

T52

2

clear_none

auto[0]

auto[1]

auto[1]

28

1

T12

1

T223

1

T61

1

clear_none

auto[1]

auto[0]

auto[0]

122

1

T4

5

T53

1

T77

2

clear_none

auto[1]

auto[0]

auto[1]

28

1

T4

1

T119

1

T263

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T54

2

T6

1

T45

1

clear_none

auto[1]

auto[1]

auto[1]

31

1

T188

1

T6

1

T223

4

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1356	1			T2	1		T12	3		T15	3
clear_all	auto[1]	99	1			T108	1		T121	3		T329	1
clear_one[1]	auto[0]	689	1			T1	1		T2	2		T3	1
clear_one[1]	auto[1]	53	1			T108	6		T122	1		T125	6
clear_one[2]	auto[0]	730	1			T15	1		T16	1		T81	1
clear_one[2]	auto[1]	22	1			T122	3		T125	3		T228	1
clear_one[3]	auto[0]	659	1			T1	1		T2	1		T15	1
clear_one[3]	auto[1]	47	1			T121	4		T124	4		T125	2
clear_none	auto[0]	1743	1			T1	1		T2	2		T3	2
clear_none	auto[1]	71	1			T108	2		T101	1		T122	1