Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11534

1

T1

20

T2

6

T3

25

auto[Attestation]

8034

1

T1

17

T2

2

T3

21

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2810	1			T1	5		T2	1		T3	9
auto[Aes]	3618	1			T1	2		T2	4		T3	6
auto[Kmac]	3562	1			T1	8		T2	1		T3	7
auto[Otbn]	3446	1			T1	6		T2	1		T3	11

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8038	1			T1	32		T2	8		T3	16
auto[OpGenId]	6132	1			T1	16		T2	1		T3	13
auto[OpGenSwOut]	6287	1			T1	18		T2	2		T3	18
auto[OpGenHwOut]	7149	1			T1	3		T2	5		T3	15
auto[OpDisable]	149	1			T3	1		T46	1		T4	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11236

1

T1

32

T2

8

T3

22

auto[OpDoneFail]

16519

1

T1

37

T2

8

T3

41

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6488	1			T1	9		T2	1		T3	22
auto[StInit]	3798	1			T1	8		T2	2		T3	16
auto[StCreatorRootKey]	3370	1			T1	8		T2	2		T3	11
auto[StOwnerIntKey]	2943	1			T1	8		T2	2		T3	2
auto[StOwnerKey]	2644	1			T1	8		T2	2		T3	2
auto[StDisabled]	8512	1			T1	28		T2	7		T3	10

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	347	1			T3	1		T12	2		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T3	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T52	3		T177	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T1	1		T82	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T1	1		T4	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	267	1			T1	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	339	1			T82	1		T4	2		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	98	1			T12	1		T59	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	111	1			T18	1		T4	2		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T13	1		T17	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T4	1		T62	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	232	1			T2	1		T4	4		T52	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	307	1			T1	1		T3	3		T12	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T1	1		T13	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T1	1		T108	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T1	1		T18	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T4	2		T52	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	233	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	326	1			T1	1		T3	1		T17	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	105	1			T4	1		T76	1		T52	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T3	1		T4	5		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T13	1		T108	1		T178	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	71	1			T53	1		T52	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	230	1			T1	2		T12	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T4	1		T53	2		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	93	1			T3	1		T46	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	90	1			T3	1		T12	3		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T4	1		T178	1		T179	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	81	1			T4	1		T53	2		T52	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	233	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	84	1			T4	1		T53	3		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T19	1		T26	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T14	1		T19	2		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	84	1			T4	2		T53	1		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T1	1		T17	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	237	1			T1	1		T4	3		T53	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	84	1			T3	1		T53	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T19	1		T82	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T4	2		T178	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T4	1		T62	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	75	1			T178	1		T53	2		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	240	1			T1	2		T3	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T1	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T3	3		T13	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T1	1		T4	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T4	1		T62	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T1	1		T16	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	221	1			T3	1		T12	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	253	1			T82	4		T4	2		T62	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	76	1			T14	1		T26	1		T52	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T3	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T2	1		T59	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T52	2		T54	2		T180	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T1	1		T4	2		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	534	1			T3	2		T12	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T3	2		T4	2		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T2	1		T4	2		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T13	1		T4	2		T52	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	98	1			T2	1		T77	1		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	305	1			T46	1		T4	3		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	469	1			T17	2		T82	2		T53	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	110	1			T19	1		T81	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	123	1			T1	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T16	1		T81	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T17	1		T82	1		T178	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	269	1			T12	3		T81	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	449	1			T3	1		T13	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T15	1		T46	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T3	2		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T108	1		T59	1		T181	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	100	1			T17	1		T46	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	307	1			T2	1		T12	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T3	2		T52	2		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T4	1		T53	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T4	1		T53	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T12	1		T4	1		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T4	1		T52	2		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	178	1			T3	1		T4	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T4	2		T52	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	108	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T3	1		T13	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	125	1			T17	1		T4	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T17	2		T52	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	296	1			T82	1		T4	3		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T4	1		T53	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T4	1		T108	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	133	1			T3	1		T17	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T52	3		T54	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	98	1			T12	1		T17	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	318	1			T1	1		T81	3		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T3	1		T4	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T182	1		T181	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T14	1		T4	2		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T15	1		T182	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T15	1		T17	2		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	275	1			T15	2		T4	1		T108	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T1	2		T82	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	745	1			T1	1		T3	2		T12	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T13	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	694	1			T2	1		T12	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	225	1			T1	2		T18	1		T4	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	682	1			T1	2		T2	1		T3	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	221	1			T13	1		T4	5		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	682	1			T1	3		T3	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	217	1			T3	1		T12	3		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	422	1			T1	1		T3	2		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	221	1			T1	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	449	1			T1	1		T19	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	232	1			T4	3		T62	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	450	1			T1	2		T3	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T1	2		T16	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	436	1			T1	1		T3	5		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T2	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	528	1			T1	1		T14	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	286	1			T2	2		T13	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	973	1			T3	4		T12	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	292	1			T1	1		T14	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	867	1			T12	3		T17	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	289	1			T3	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	885	1			T2	1		T3	2		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T12	1		T4	2		T53	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	356	1			T3	3		T4	3		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	296	1			T3	1		T13	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	483	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	319	1			T3	1		T12	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	495	1			T1	1		T81	3		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	259	1			T14	1		T15	2		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	475	1			T3	1		T15	2		T4	4