Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33837

1

T1

89

T2

18

T3

71

auto[1]

298

1

T108

4

T101

4

T134

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33851	1			T1	89		T2	18		T3	71
auto[134217728:268435455]	11	1			T223	1		T241	2		T230	1
auto[268435456:402653183]	11	1			T101	1		T124	1		T125	2
auto[402653184:536870911]	7	1			T101	1		T121	1		T223	1
auto[536870912:671088639]	8	1			T223	1		T241	2		T323	1
auto[671088640:805306367]	5	1			T329	1		T270	1		T228	1
auto[805306368:939524095]	9	1			T124	1		T125	1		T223	1
auto[939524096:1073741823]	13	1			T121	1		T223	1		T280	1
auto[1073741824:1207959551]	7	1			T125	1		T390	1		T391	1
auto[1207959552:1342177279]	9	1			T122	1		T270	1		T233	2
auto[1342177280:1476395007]	11	1			T108	1		T121	1		T270	1
auto[1476395008:1610612735]	7	1			T223	1		T373	1		T346	1
auto[1610612736:1744830463]	6	1			T241	1		T230	1		T392	1
auto[1744830464:1879048191]	13	1			T223	1		T241	1		T270	2
auto[1879048192:2013265919]	11	1			T108	1		T241	1		T230	1
auto[2013265920:2147483647]	7	1			T121	1		T241	1		T280	1
auto[2147483648:2281701375]	13	1			T329	1		T122	1		T241	1
auto[2281701376:2415919103]	6	1			T392	1		T373	1		T391	1
auto[2415919104:2550136831]	9	1			T329	1		T241	1		T270	1
auto[2550136832:2684354559]	12	1			T134	2		T326	1		T241	1
auto[2684354560:2818572287]	7	1			T323	1		T393	1		T288	1
auto[2818572288:2952790015]	11	1			T125	2		T280	1		T373	1
auto[2952790016:3087007743]	7	1			T134	1		T124	1		T233	1
auto[3087007744:3221225471]	11	1			T101	1		T125	1		T326	1
auto[3221225472:3355443199]	5	1			T121	1		T124	1		T394	1
auto[3355443200:3489660927]	11	1			T241	1		T323	1		T233	2
auto[3489660928:3623878655]	10	1			T101	1		T124	2		T223	1
auto[3623878656:3758096383]	7	1			T122	1		T346	1		T228	1
auto[3758096384:3892314111]	7	1			T125	1		T270	1		T391	1
auto[3892314112:4026531839]	9	1			T230	1		T323	1		T233	2
auto[4026531840:4160749567]	14	1			T108	1		T122	1		T124	1
auto[4160749568:4294967295]	10	1			T326	1		T270	1		T392	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33837	1			T1	89		T2	18		T3	71
auto[0:134217727]	auto[1]	14	1			T108	1		T230	1		T270	1
auto[134217728:268435455]	auto[1]	11	1			T223	1		T241	2		T230	1
auto[268435456:402653183]	auto[1]	11	1			T101	1		T124	1		T125	2
auto[402653184:536870911]	auto[1]	7	1			T101	1		T121	1		T223	1
auto[536870912:671088639]	auto[1]	8	1			T223	1		T241	2		T323	1
auto[671088640:805306367]	auto[1]	5	1			T329	1		T270	1		T228	1
auto[805306368:939524095]	auto[1]	9	1			T124	1		T125	1		T223	1
auto[939524096:1073741823]	auto[1]	13	1			T121	1		T223	1		T280	1
auto[1073741824:1207959551]	auto[1]	7	1			T125	1		T390	1		T391	1
auto[1207959552:1342177279]	auto[1]	9	1			T122	1		T270	1		T233	2
auto[1342177280:1476395007]	auto[1]	11	1			T108	1		T121	1		T270	1
auto[1476395008:1610612735]	auto[1]	7	1			T223	1		T373	1		T346	1
auto[1610612736:1744830463]	auto[1]	6	1			T241	1		T230	1		T392	1
auto[1744830464:1879048191]	auto[1]	13	1			T223	1		T241	1		T270	2
auto[1879048192:2013265919]	auto[1]	11	1			T108	1		T241	1		T230	1
auto[2013265920:2147483647]	auto[1]	7	1			T121	1		T241	1		T280	1
auto[2147483648:2281701375]	auto[1]	13	1			T329	1		T122	1		T241	1
auto[2281701376:2415919103]	auto[1]	6	1			T392	1		T373	1		T391	1
auto[2415919104:2550136831]	auto[1]	9	1			T329	1		T241	1		T270	1
auto[2550136832:2684354559]	auto[1]	12	1			T134	2		T326	1		T241	1
auto[2684354560:2818572287]	auto[1]	7	1			T323	1		T393	1		T288	1
auto[2818572288:2952790015]	auto[1]	11	1			T125	2		T280	1		T373	1
auto[2952790016:3087007743]	auto[1]	7	1			T134	1		T124	1		T233	1
auto[3087007744:3221225471]	auto[1]	11	1			T101	1		T125	1		T326	1
auto[3221225472:3355443199]	auto[1]	5	1			T121	1		T124	1		T394	1
auto[3355443200:3489660927]	auto[1]	11	1			T241	1		T323	1		T233	2
auto[3489660928:3623878655]	auto[1]	10	1			T101	1		T124	2		T223	1
auto[3623878656:3758096383]	auto[1]	7	1			T122	1		T346	1		T228	1
auto[3758096384:3892314111]	auto[1]	7	1			T125	1		T270	1		T391	1
auto[3892314112:4026531839]	auto[1]	9	1			T230	1		T323	1		T233	2
auto[4026531840:4160749567]	auto[1]	14	1			T108	1		T122	1		T124	1
auto[4160749568:4294967295]	auto[1]	10	1			T326	1		T270	1		T392	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1621

1

T1

1

T3

2

T12

1

auto[1]

1837

1

T3

3

T12

3

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T1	1		T46	1		T4	1
auto[134217728:268435455]	131	1			T3	1		T12	1		T4	2
auto[268435456:402653183]	109	1			T3	1		T14	1		T26	1
auto[402653184:536870911]	105	1			T4	3		T62	1		T53	3
auto[536870912:671088639]	88	1			T53	1		T20	1		T34	1
auto[671088640:805306367]	111	1			T62	1		T119	1		T120	1
auto[805306368:939524095]	119	1			T17	1		T4	1		T53	1
auto[939524096:1073741823]	119	1			T19	1		T4	2		T178	1
auto[1073741824:1207959551]	127	1			T17	1		T46	1		T4	2
auto[1207959552:1342177279]	97	1			T17	1		T4	3		T52	1
auto[1342177280:1476395007]	105	1			T4	1		T62	1		T53	1
auto[1476395008:1610612735]	99	1			T12	1		T4	1		T79	1
auto[1610612736:1744830463]	116	1			T4	2		T53	1		T44	1
auto[1744830464:1879048191]	125	1			T17	1		T4	1		T53	3
auto[1879048192:2013265919]	116	1			T3	1		T4	1		T52	1
auto[2013265920:2147483647]	120	1			T4	1		T52	1		T79	1
auto[2147483648:2281701375]	111	1			T3	1		T4	1		T53	1
auto[2281701376:2415919103]	94	1			T108	1		T53	1		T52	1
auto[2415919104:2550136831]	95	1			T26	1		T4	2		T52	1
auto[2550136832:2684354559]	127	1			T3	1		T4	1		T108	1
auto[2684354560:2818572287]	92	1			T4	3		T53	2		T52	1
auto[2818572288:2952790015]	107	1			T4	2		T108	1		T52	1
auto[2952790016:3087007743]	80	1			T4	1		T52	1		T120	1
auto[3087007744:3221225471]	108	1			T4	1		T178	1		T53	2
auto[3221225472:3355443199]	97	1			T4	2		T53	2		T119	1
auto[3355443200:3489660927]	125	1			T4	3		T53	2		T52	1
auto[3489660928:3623878655]	103	1			T4	1		T53	1		T54	1
auto[3623878656:3758096383]	104	1			T12	2		T4	4		T53	1
auto[3758096384:3892314111]	116	1			T26	1		T4	1		T59	2
auto[3892314112:4026531839]	93	1			T53	1		T52	1		T100	1
auto[4026531840:4160749567]	125	1			T4	1		T178	1		T53	1
auto[4160749568:4294967295]	102	1			T4	2		T79	1		T119	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T1	1		T46	1		T4	1
auto[0:134217727]	auto[1]	43	1			T135	1		T67	1		T57	1
auto[134217728:268435455]	auto[0]	54	1			T54	1		T66	1		T395	1
auto[134217728:268435455]	auto[1]	77	1			T3	1		T12	1		T4	2
auto[268435456:402653183]	auto[0]	54	1			T3	1		T26	1		T4	1
auto[268435456:402653183]	auto[1]	55	1			T14	1		T101	1		T135	1
auto[402653184:536870911]	auto[0]	54	1			T4	1		T62	1		T53	1
auto[402653184:536870911]	auto[1]	51	1			T4	2		T53	2		T20	1
auto[536870912:671088639]	auto[0]	46	1			T34	1		T47	1		T395	1
auto[536870912:671088639]	auto[1]	42	1			T53	1		T20	1		T360	1
auto[671088640:805306367]	auto[0]	49	1			T119	1		T120	1		T66	1
auto[671088640:805306367]	auto[1]	62	1			T62	1		T66	4		T67	1
auto[805306368:939524095]	auto[0]	52	1			T4	1		T34	1		T44	1
auto[805306368:939524095]	auto[1]	67	1			T17	1		T53	1		T120	1
auto[939524096:1073741823]	auto[0]	48	1			T19	1		T4	1		T178	1
auto[939524096:1073741823]	auto[1]	71	1			T4	1		T53	1		T52	3
auto[1073741824:1207959551]	auto[0]	55	1			T46	1		T4	1		T53	1
auto[1073741824:1207959551]	auto[1]	72	1			T17	1		T4	1		T108	1
auto[1207959552:1342177279]	auto[0]	48	1			T4	2		T52	1		T47	1
auto[1207959552:1342177279]	auto[1]	49	1			T17	1		T4	1		T48	1
auto[1342177280:1476395007]	auto[0]	45	1			T4	1		T53	1		T44	1
auto[1342177280:1476395007]	auto[1]	60	1			T62	1		T100	1		T66	1
auto[1476395008:1610612735]	auto[0]	48	1			T12	1		T4	1		T79	1
auto[1476395008:1610612735]	auto[1]	51	1			T218	1		T58	1		T21	1
auto[1610612736:1744830463]	auto[0]	57	1			T4	1		T44	1		T23	1
auto[1610612736:1744830463]	auto[1]	59	1			T4	1		T53	1		T188	2
auto[1744830464:1879048191]	auto[0]	58	1			T17	1		T4	1		T53	2
auto[1744830464:1879048191]	auto[1]	67	1			T53	1		T66	1		T69	2
auto[1879048192:2013265919]	auto[0]	49	1			T24	1		T6	3		T64	1
auto[1879048192:2013265919]	auto[1]	67	1			T3	1		T4	1		T52	1
auto[2013265920:2147483647]	auto[0]	55	1			T79	1		T66	1		T35	1
auto[2013265920:2147483647]	auto[1]	65	1			T4	1		T52	1		T66	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T4	1		T52	2
auto[2147483648:2281701375]	auto[1]	58	1			T53	1		T66	1		T23	1
auto[2281701376:2415919103]	auto[0]	43	1			T108	1		T53	1		T52	1
auto[2281701376:2415919103]	auto[1]	51	1			T66	1		T135	1		T83	1
auto[2415919104:2550136831]	auto[0]	40	1			T26	1		T4	1		T54	1
auto[2415919104:2550136831]	auto[1]	55	1			T4	1		T52	1		T6	2
auto[2550136832:2684354559]	auto[0]	63	1			T4	1		T108	1		T53	1
auto[2550136832:2684354559]	auto[1]	64	1			T3	1		T54	1		T66	2
auto[2684354560:2818572287]	auto[0]	50	1			T4	3		T53	1		T52	1
auto[2684354560:2818572287]	auto[1]	42	1			T53	1		T66	1		T48	1
auto[2818572288:2952790015]	auto[0]	52	1			T4	1		T108	1		T54	1
auto[2818572288:2952790015]	auto[1]	55	1			T4	1		T52	1		T66	1
auto[2952790016:3087007743]	auto[0]	36	1			T120	1		T57	1		T188	2
auto[2952790016:3087007743]	auto[1]	44	1			T4	1		T52	1		T69	1
auto[3087007744:3221225471]	auto[0]	52	1			T4	1		T53	1		T52	1
auto[3087007744:3221225471]	auto[1]	56	1			T178	1		T53	1		T52	2
auto[3221225472:3355443199]	auto[0]	43	1			T4	2		T53	2		T119	1
auto[3221225472:3355443199]	auto[1]	54	1			T66	1		T68	1		T21	1
auto[3355443200:3489660927]	auto[0]	59	1			T4	3		T53	2		T44	2
auto[3355443200:3489660927]	auto[1]	66	1			T52	1		T135	2		T232	1
auto[3489660928:3623878655]	auto[0]	40	1			T4	1		T232	1		T85	1
auto[3489660928:3623878655]	auto[1]	63	1			T53	1		T54	1		T134	1
auto[3623878656:3758096383]	auto[0]	59	1			T4	3		T53	1		T188	1
auto[3623878656:3758096383]	auto[1]	45	1			T12	2		T4	1		T52	1
auto[3758096384:3892314111]	auto[0]	57	1			T4	1		T66	2		T188	2
auto[3758096384:3892314111]	auto[1]	59	1			T26	1		T59	2		T53	1
auto[3892314112:4026531839]	auto[0]	40	1			T53	1		T100	1		T188	1
auto[3892314112:4026531839]	auto[1]	53	1			T52	1		T47	1		T66	2
auto[4026531840:4160749567]	auto[0]	70	1			T178	1		T53	1		T54	1
auto[4026531840:4160749567]	auto[1]	55	1			T4	1		T52	2		T54	1
auto[4160749568:4294967295]	auto[0]	43	1			T119	1		T245	1		T123	2
auto[4160749568:4294967295]	auto[1]	59	1			T4	2		T79	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T1

1

T3

2

T12

1

auto[1]

1849

1

T3

3

T12

3

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	126	1			T3	1		T12	1		T4	2
auto[134217728:268435455]	96	1			T53	3		T52	2		T66	2
auto[268435456:402653183]	113	1			T4	2		T53	1		T66	5
auto[402653184:536870911]	99	1			T4	1		T53	2		T47	2
auto[536870912:671088639]	109	1			T3	1		T53	1		T52	1
auto[671088640:805306367]	98	1			T26	1		T4	1		T53	1
auto[805306368:939524095]	100	1			T12	1		T17	1		T4	3
auto[939524096:1073741823]	112	1			T26	1		T4	1		T62	1
auto[1073741824:1207959551]	120	1			T4	3		T108	1		T178	1
auto[1207959552:1342177279]	127	1			T79	1		T100	1		T44	1
auto[1342177280:1476395007]	119	1			T3	1		T4	3		T53	1
auto[1476395008:1610612735]	120	1			T4	1		T108	1		T119	1
auto[1610612736:1744830463]	130	1			T26	1		T53	2		T52	2
auto[1744830464:1879048191]	99	1			T52	2		T54	1		T66	1
auto[1879048192:2013265919]	110	1			T46	1		T4	3		T53	1
auto[2013265920:2147483647]	79	1			T4	1		T62	1		T53	2
auto[2147483648:2281701375]	109	1			T46	1		T4	4		T52	1
auto[2281701376:2415919103]	107	1			T17	1		T53	2		T52	2
auto[2415919104:2550136831]	112	1			T4	2		T119	1		T100	1
auto[2550136832:2684354559]	131	1			T3	1		T4	1		T108	1
auto[2684354560:2818572287]	105	1			T19	1		T4	3		T52	2
auto[2818572288:2952790015]	91	1			T108	1		T59	1		T53	1
auto[2952790016:3087007743]	102	1			T1	1		T3	1		T4	2
auto[3087007744:3221225471]	120	1			T17	1		T4	3		T53	1
auto[3221225472:3355443199]	110	1			T62	1		T52	2		T54	1
auto[3355443200:3489660927]	109	1			T17	1		T4	1		T59	1
auto[3489660928:3623878655]	99	1			T14	1		T4	2		T44	1
auto[3623878656:3758096383]	91	1			T12	1		T4	4		T59	1
auto[3758096384:3892314111]	86	1			T4	1		T178	1		T53	2
auto[3892314112:4026531839]	110	1			T53	2		T52	1		T120	1
auto[4026531840:4160749567]	100	1			T4	1		T53	1		T120	1
auto[4160749568:4294967295]	119	1			T12	1		T4	2		T53	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T53	1		T79	1		T66	1
auto[0:134217727]	auto[1]	68	1			T3	1		T12	1		T4	2
auto[134217728:268435455]	auto[0]	42	1			T66	1		T218	1		T124	1
auto[134217728:268435455]	auto[1]	54	1			T53	3		T52	2		T66	1
auto[268435456:402653183]	auto[0]	60	1			T4	1		T66	1		T85	1
auto[268435456:402653183]	auto[1]	53	1			T4	1		T53	1		T66	4
auto[402653184:536870911]	auto[0]	48	1			T4	1		T53	2		T47	2
auto[402653184:536870911]	auto[1]	51	1			T54	1		T67	1		T238	1
auto[536870912:671088639]	auto[0]	41	1			T134	1		T396	1		T188	1
auto[536870912:671088639]	auto[1]	68	1			T3	1		T53	1		T52	1
auto[671088640:805306367]	auto[0]	50	1			T26	1		T54	1		T67	1
auto[671088640:805306367]	auto[1]	48	1			T4	1		T53	1		T100	1
auto[805306368:939524095]	auto[0]	44	1			T12	1		T4	1		T66	1
auto[805306368:939524095]	auto[1]	56	1			T17	1		T4	2		T178	1
auto[939524096:1073741823]	auto[0]	54	1			T26	1		T4	1		T52	1
auto[939524096:1073741823]	auto[1]	58	1			T62	1		T178	1		T53	2
auto[1073741824:1207959551]	auto[0]	63	1			T4	3		T178	1		T66	1
auto[1073741824:1207959551]	auto[1]	57	1			T108	1		T66	1		T134	1
auto[1207959552:1342177279]	auto[0]	49	1			T100	1		T44	1		T66	1
auto[1207959552:1342177279]	auto[1]	78	1			T79	1		T360	1		T188	2
auto[1342177280:1476395007]	auto[0]	50	1			T4	2		T53	1		T44	2
auto[1342177280:1476395007]	auto[1]	69	1			T3	1		T4	1		T54	1
auto[1476395008:1610612735]	auto[0]	59	1			T108	1		T119	1		T5	1
auto[1476395008:1610612735]	auto[1]	61	1			T4	1		T66	1		T187	1
auto[1610612736:1744830463]	auto[0]	60	1			T26	1		T53	1		T52	1
auto[1610612736:1744830463]	auto[1]	70	1			T53	1		T52	1		T66	1
auto[1744830464:1879048191]	auto[0]	45	1			T54	1		T66	1		T85	1
auto[1744830464:1879048191]	auto[1]	54	1			T52	2		T135	1		T360	1
auto[1879048192:2013265919]	auto[0]	48	1			T4	2		T34	1		T54	1
auto[1879048192:2013265919]	auto[1]	62	1			T46	1		T4	1		T53	1
auto[2013265920:2147483647]	auto[0]	37	1			T53	1		T52	1		T119	1
auto[2013265920:2147483647]	auto[1]	42	1			T4	1		T62	1		T53	1
auto[2147483648:2281701375]	auto[0]	49	1			T46	1		T4	2		T188	3
auto[2147483648:2281701375]	auto[1]	60	1			T4	2		T52	1		T66	3
auto[2281701376:2415919103]	auto[0]	42	1			T54	1		T48	1		T85	1
auto[2281701376:2415919103]	auto[1]	65	1			T17	1		T53	2		T52	2
auto[2415919104:2550136831]	auto[0]	59	1			T4	2		T119	1		T23	1
auto[2415919104:2550136831]	auto[1]	53	1			T100	1		T66	1		T23	1
auto[2550136832:2684354559]	auto[0]	66	1			T3	1		T108	1		T52	1
auto[2550136832:2684354559]	auto[1]	65	1			T4	1		T54	1		T23	1
auto[2684354560:2818572287]	auto[0]	49	1			T19	1		T4	3		T52	2
auto[2684354560:2818572287]	auto[1]	56	1			T180	1		T177	1		T188	2
auto[2818572288:2952790015]	auto[0]	29	1			T57	1		T48	1		T245	1
auto[2818572288:2952790015]	auto[1]	62	1			T108	1		T59	1		T53	1
auto[2952790016:3087007743]	auto[0]	53	1			T1	1		T3	1		T4	2
auto[2952790016:3087007743]	auto[1]	49	1			T53	1		T52	2		T66	1
auto[3087007744:3221225471]	auto[0]	59	1			T17	1		T4	1		T34	1
auto[3087007744:3221225471]	auto[1]	61	1			T4	2		T53	1		T123	1
auto[3221225472:3355443199]	auto[0]	60	1			T62	1		T52	2		T395	1
auto[3221225472:3355443199]	auto[1]	50	1			T54	1		T66	1		T23	1
auto[3355443200:3489660927]	auto[0]	45	1			T44	1		T188	2		T24	2
auto[3355443200:3489660927]	auto[1]	64	1			T17	1		T4	1		T59	1
auto[3489660928:3623878655]	auto[0]	43	1			T4	2		T44	1		T69	1
auto[3489660928:3623878655]	auto[1]	56	1			T14	1		T101	1		T66	1
auto[3623878656:3758096383]	auto[0]	44	1			T4	3		T66	1		T188	2
auto[3623878656:3758096383]	auto[1]	47	1			T12	1		T4	1		T59	1
auto[3758096384:3892314111]	auto[0]	39	1			T4	1		T53	1		T6	1
auto[3758096384:3892314111]	auto[1]	47	1			T178	1		T53	1		T20	1
auto[3892314112:4026531839]	auto[0]	58	1			T53	1		T120	1		T67	1
auto[3892314112:4026531839]	auto[1]	52	1			T53	1		T52	1		T134	1
auto[4026531840:4160749567]	auto[0]	47	1			T4	1		T44	1		T188	2
auto[4026531840:4160749567]	auto[1]	53	1			T53	1		T120	1		T54	1
auto[4160749568:4294967295]	auto[0]	59	1			T4	2		T53	2		T52	1
auto[4160749568:4294967295]	auto[1]	60	1			T12	1		T52	1		T66	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T1

1

T3

2

T12

1

auto[1]

1854

1

T3

3

T12

3

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T17	1		T4	2		T53	2
auto[134217728:268435455]	96	1			T4	2		T52	1		T100	1
auto[268435456:402653183]	117	1			T4	1		T108	1		T59	1
auto[402653184:536870911]	114	1			T4	4		T79	1		T101	1
auto[536870912:671088639]	104	1			T12	1		T4	1		T53	1
auto[671088640:805306367]	108	1			T4	4		T62	1		T53	1
auto[805306368:939524095]	131	1			T4	2		T178	1		T53	2
auto[939524096:1073741823]	96	1			T12	1		T4	1		T62	1
auto[1073741824:1207959551]	115	1			T4	4		T52	2		T44	2
auto[1207959552:1342177279]	97	1			T46	1		T108	1		T52	2
auto[1342177280:1476395007]	119	1			T19	1		T4	2		T62	1
auto[1476395008:1610612735]	85	1			T12	1		T4	1		T44	1
auto[1610612736:1744830463]	107	1			T4	1		T100	1		T54	1
auto[1744830464:1879048191]	102	1			T4	2		T20	1		T52	1
auto[1879048192:2013265919]	109	1			T1	1		T4	1		T178	2
auto[2013265920:2147483647]	108	1			T4	1		T119	2		T54	1
auto[2147483648:2281701375]	115	1			T4	1		T53	2		T52	1
auto[2281701376:2415919103]	100	1			T4	1		T108	1		T53	3
auto[2415919104:2550136831]	113	1			T3	1		T17	1		T26	1
auto[2550136832:2684354559]	110	1			T4	1		T53	2		T52	1
auto[2684354560:2818572287]	99	1			T46	1		T120	1		T34	1
auto[2818572288:2952790015]	116	1			T4	2		T59	1		T52	1
auto[2952790016:3087007743]	112	1			T59	1		T53	1		T52	1
auto[3087007744:3221225471]	113	1			T3	1		T17	1		T53	2
auto[3221225472:3355443199]	98	1			T12	1		T17	1		T53	1
auto[3355443200:3489660927]	108	1			T3	1		T14	1		T4	1
auto[3489660928:3623878655]	109	1			T52	1		T120	1		T54	1
auto[3623878656:3758096383]	92	1			T4	2		T53	2		T44	1
auto[3758096384:3892314111]	109	1			T3	1		T4	3		T53	1
auto[3892314112:4026531839]	132	1			T3	1		T26	2		T4	5
auto[4026531840:4160749567]	111	1			T4	2		T53	1		T52	2
auto[4160749568:4294967295]	104	1			T52	2		T66	1		T395	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T17	1		T4	1		T53	1
auto[0:134217727]	auto[1]	54	1			T4	1		T53	1		T66	2
auto[134217728:268435455]	auto[0]	49	1			T4	2		T187	1		T180	1
auto[134217728:268435455]	auto[1]	47	1			T52	1		T100	1		T101	1
auto[268435456:402653183]	auto[0]	58	1			T4	1		T120	1		T66	1
auto[268435456:402653183]	auto[1]	59	1			T108	1		T59	1		T188	1
auto[402653184:536870911]	auto[0]	42	1			T4	2		T79	1		T35	1
auto[402653184:536870911]	auto[1]	72	1			T4	2		T101	1		T66	3
auto[536870912:671088639]	auto[0]	48	1			T4	1		T52	1		T54	1
auto[536870912:671088639]	auto[1]	56	1			T12	1		T53	1		T119	1
auto[671088640:805306367]	auto[0]	53	1			T4	3		T62	1		T53	1
auto[671088640:805306367]	auto[1]	55	1			T4	1		T54	1		T66	1
auto[805306368:939524095]	auto[0]	54	1			T4	2		T53	1		T66	2
auto[805306368:939524095]	auto[1]	77	1			T178	1		T53	1		T52	1
auto[939524096:1073741823]	auto[0]	38	1			T62	1		T178	1		T53	1
auto[939524096:1073741823]	auto[1]	58	1			T12	1		T4	1		T53	1
auto[1073741824:1207959551]	auto[0]	54	1			T4	3		T52	1		T44	2
auto[1073741824:1207959551]	auto[1]	61	1			T4	1		T52	1		T66	2
auto[1207959552:1342177279]	auto[0]	52	1			T46	1		T108	1		T119	1
auto[1207959552:1342177279]	auto[1]	45	1			T52	2		T100	2		T66	3
auto[1342177280:1476395007]	auto[0]	55	1			T4	2		T62	1		T79	1
auto[1342177280:1476395007]	auto[1]	64	1			T19	1		T53	1		T52	2
auto[1476395008:1610612735]	auto[0]	40	1			T4	1		T44	1		T66	1
auto[1476395008:1610612735]	auto[1]	45	1			T12	1		T66	1		T23	1
auto[1610612736:1744830463]	auto[0]	51	1			T4	1		T54	1		T187	1
auto[1610612736:1744830463]	auto[1]	56	1			T100	1		T134	2		T135	1
auto[1744830464:1879048191]	auto[0]	50	1			T4	2		T217	1		T123	2
auto[1744830464:1879048191]	auto[1]	52	1			T20	1		T52	1		T188	1
auto[1879048192:2013265919]	auto[0]	51	1			T1	1		T4	1		T53	1
auto[1879048192:2013265919]	auto[1]	58	1			T178	2		T187	1		T83	1
auto[2013265920:2147483647]	auto[0]	52	1			T119	2		T188	3		T329	1
auto[2013265920:2147483647]	auto[1]	56	1			T4	1		T54	1		T66	1
auto[2147483648:2281701375]	auto[0]	49	1			T44	1		T188	1		T24	1
auto[2147483648:2281701375]	auto[1]	66	1			T4	1		T53	2		T52	1
auto[2281701376:2415919103]	auto[0]	49	1			T4	1		T108	1		T53	2
auto[2281701376:2415919103]	auto[1]	51	1			T53	1		T66	2		T69	1
auto[2415919104:2550136831]	auto[0]	52	1			T26	1		T119	1		T85	2
auto[2415919104:2550136831]	auto[1]	61	1			T3	1		T17	1		T53	1
auto[2550136832:2684354559]	auto[0]	58	1			T4	1		T53	1		T52	1
auto[2550136832:2684354559]	auto[1]	52	1			T53	1		T135	1		T218	1
auto[2684354560:2818572287]	auto[0]	43	1			T46	1		T120	1		T34	1
auto[2684354560:2818572287]	auto[1]	56	1			T66	1		T135	1		T83	1
auto[2818572288:2952790015]	auto[0]	57	1			T4	1		T52	1		T119	1
auto[2818572288:2952790015]	auto[1]	59	1			T4	1		T59	1		T83	1
auto[2952790016:3087007743]	auto[0]	46	1			T66	1		T188	1		T24	1
auto[2952790016:3087007743]	auto[1]	66	1			T59	1		T53	1		T52	1
auto[3087007744:3221225471]	auto[0]	58	1			T53	1		T69	1		T218	1
auto[3087007744:3221225471]	auto[1]	55	1			T3	1		T17	1		T53	1
auto[3221225472:3355443199]	auto[0]	42	1			T12	1		T53	1		T34	1
auto[3221225472:3355443199]	auto[1]	56	1			T17	1		T54	1		T66	1
auto[3355443200:3489660927]	auto[0]	50	1			T3	1		T4	1		T53	1
auto[3355443200:3489660927]	auto[1]	58	1			T14	1		T53	1		T120	1
auto[3489660928:3623878655]	auto[0]	59	1			T120	1		T54	1		T395	1
auto[3489660928:3623878655]	auto[1]	50	1			T52	1		T66	2		T360	1
auto[3623878656:3758096383]	auto[0]	41	1			T4	1		T53	1		T44	1
auto[3623878656:3758096383]	auto[1]	51	1			T4	1		T53	1		T54	1
auto[3758096384:3892314111]	auto[0]	48	1			T3	1		T4	2		T53	1
auto[3758096384:3892314111]	auto[1]	61	1			T4	1		T66	1		T69	1
auto[3892314112:4026531839]	auto[0]	50	1			T26	2		T4	3		T44	1
auto[3892314112:4026531839]	auto[1]	82	1			T3	1		T4	2		T108	1
auto[4026531840:4160749567]	auto[0]	47	1			T4	1		T52	1		T66	1
auto[4026531840:4160749567]	auto[1]	64	1			T4	1		T53	1		T52	1
auto[4160749568:4294967295]	auto[0]	53	1			T52	1		T66	1		T395	1
auto[4160749568:4294967295]	auto[1]	51	1			T52	1		T188	2		T123	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1574

1

T1

1

T3

1

T12

1

auto[1]

1884

1

T3

4

T12

3

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T17	1		T4	2		T178	1
auto[134217728:268435455]	92	1			T4	1		T59	1		T53	2
auto[268435456:402653183]	101	1			T4	3		T178	1		T79	1
auto[402653184:536870911]	109	1			T19	1		T4	1		T53	1
auto[536870912:671088639]	117	1			T12	1		T4	1		T62	1
auto[671088640:805306367]	128	1			T4	5		T52	2		T79	1
auto[805306368:939524095]	102	1			T17	1		T52	1		T120	1
auto[939524096:1073741823]	93	1			T12	1		T46	1		T4	2
auto[1073741824:1207959551]	99	1			T3	1		T4	2		T53	1
auto[1207959552:1342177279]	101	1			T119	1		T54	3		T66	1
auto[1342177280:1476395007]	92	1			T26	1		T52	1		T66	1
auto[1476395008:1610612735]	114	1			T3	1		T4	2		T59	1
auto[1610612736:1744830463]	96	1			T4	1		T52	2		T119	1
auto[1744830464:1879048191]	87	1			T4	2		T53	1		T119	1
auto[1879048192:2013265919]	120	1			T17	1		T108	1		T53	2
auto[2013265920:2147483647]	101	1			T12	1		T4	3		T53	1
auto[2147483648:2281701375]	121	1			T46	1		T26	1		T108	1
auto[2281701376:2415919103]	116	1			T4	1		T53	3		T54	1
auto[2415919104:2550136831]	105	1			T4	2		T20	1		T52	2
auto[2550136832:2684354559]	126	1			T1	1		T3	1		T4	1
auto[2684354560:2818572287]	97	1			T53	1		T52	1		T66	1
auto[2818572288:2952790015]	116	1			T26	1		T4	1		T100	1
auto[2952790016:3087007743]	128	1			T4	1		T59	1		T53	4
auto[3087007744:3221225471]	108	1			T12	1		T4	1		T108	1
auto[3221225472:3355443199]	106	1			T4	2		T53	2		T5	1
auto[3355443200:3489660927]	108	1			T4	2		T62	1		T53	1
auto[3489660928:3623878655]	112	1			T17	1		T4	2		T53	1
auto[3623878656:3758096383]	118	1			T4	1		T52	1		T119	1
auto[3758096384:3892314111]	101	1			T14	1		T4	2		T108	1
auto[3892314112:4026531839]	119	1			T3	1		T4	3		T52	1
auto[4026531840:4160749567]	114	1			T3	1		T4	2		T52	3
auto[4160749568:4294967295]	95	1			T4	1		T62	1		T53	1