Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060

1

T1

1

T3

2

T12

4

auto[1]

302

1

T108

6

T101

3

T134

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T4	1		T108	1		T119	1
auto[134217728:268435455]	119	1			T17	1		T4	2		T120	1
auto[268435456:402653183]	105	1			T108	3		T52	2		T79	1
auto[402653184:536870911]	111	1			T53	1		T52	1		T120	1
auto[536870912:671088639]	121	1			T53	1		T52	2		T79	1
auto[671088640:805306367]	91	1			T53	1		T360	1		T48	2
auto[805306368:939524095]	105	1			T53	1		T100	1		T66	1
auto[939524096:1073741823]	100	1			T108	1		T53	1		T52	1
auto[1073741824:1207959551]	119	1			T4	2		T178	1		T52	1
auto[1207959552:1342177279]	93	1			T12	1		T66	2		T395	1
auto[1342177280:1476395007]	111	1			T46	1		T26	1		T108	1
auto[1476395008:1610612735]	88	1			T17	1		T108	1		T178	1
auto[1610612736:1744830463]	85	1			T52	2		T34	1		T101	1
auto[1744830464:1879048191]	104	1			T19	1		T4	1		T62	1
auto[1879048192:2013265919]	124	1			T4	1		T53	1		T52	1
auto[2013265920:2147483647]	91	1			T4	1		T53	1		T23	1
auto[2147483648:2281701375]	109	1			T12	1		T4	1		T59	1
auto[2281701376:2415919103]	117	1			T1	1		T12	1		T4	2
auto[2415919104:2550136831]	107	1			T4	2		T52	1		T119	1
auto[2550136832:2684354559]	92	1			T17	1		T4	2		T62	1
auto[2684354560:2818572287]	104	1			T66	3		T234	1		T70	1
auto[2818572288:2952790015]	96	1			T3	1		T14	1		T26	2
auto[2952790016:3087007743]	116	1			T3	1		T4	1		T108	1
auto[3087007744:3221225471]	119	1			T4	1		T108	1		T53	3
auto[3221225472:3355443199]	96	1			T17	1		T4	1		T53	1
auto[3355443200:3489660927]	108	1			T4	5		T178	1		T53	2
auto[3489660928:3623878655]	119	1			T108	1		T53	1		T20	1
auto[3623878656:3758096383]	97	1			T62	1		T53	1		T67	1
auto[3758096384:3892314111]	121	1			T4	1		T53	1		T34	1
auto[3892314112:4026531839]	87	1			T12	1		T4	1		T66	2
auto[4026531840:4160749567]	99	1			T46	1		T59	1		T53	1
auto[4160749568:4294967295]	107	1			T4	2		T52	1		T66	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T4	1		T119	1		T66	1
auto[0:134217727]	auto[1]	7	1			T108	1		T241	1		T323	1
auto[134217728:268435455]	auto[0]	111	1			T17	1		T4	2		T120	1
auto[134217728:268435455]	auto[1]	8	1			T124	1		T233	2		T288	1
auto[268435456:402653183]	auto[0]	93	1			T108	1		T52	2		T79	1
auto[268435456:402653183]	auto[1]	12	1			T108	2		T125	1		T223	1
auto[402653184:536870911]	auto[0]	101	1			T53	1		T52	1		T120	1
auto[402653184:536870911]	auto[1]	10	1			T122	1		T125	1		T223	1
auto[536870912:671088639]	auto[0]	108	1			T53	1		T52	2		T79	1
auto[536870912:671088639]	auto[1]	13	1			T122	1		T125	1		T326	1
auto[671088640:805306367]	auto[0]	85	1			T53	1		T360	1		T48	2
auto[671088640:805306367]	auto[1]	6	1			T223	1		T391	1		T405	1
auto[805306368:939524095]	auto[0]	96	1			T53	1		T100	1		T66	1
auto[805306368:939524095]	auto[1]	9	1			T122	1		T125	2		T323	1
auto[939524096:1073741823]	auto[0]	96	1			T53	1		T52	1		T66	2
auto[939524096:1073741823]	auto[1]	4	1			T108	1		T326	1		T406	1
auto[1073741824:1207959551]	auto[0]	103	1			T4	2		T178	1		T52	1
auto[1073741824:1207959551]	auto[1]	16	1			T134	1		T124	1		T223	1
auto[1207959552:1342177279]	auto[0]	83	1			T12	1		T66	2		T395	1
auto[1207959552:1342177279]	auto[1]	10	1			T134	1		T125	1		T241	2
auto[1342177280:1476395007]	auto[0]	101	1			T46	1		T26	1		T108	1
auto[1342177280:1476395007]	auto[1]	10	1			T125	1		T223	1		T346	1
auto[1476395008:1610612735]	auto[0]	81	1			T17	1		T178	1		T119	1
auto[1476395008:1610612735]	auto[1]	7	1			T108	1		T125	1		T223	1
auto[1610612736:1744830463]	auto[0]	76	1			T52	2		T34	1		T47	1
auto[1610612736:1744830463]	auto[1]	9	1			T101	1		T124	1		T214	1
auto[1744830464:1879048191]	auto[0]	92	1			T19	1		T4	1		T62	1
auto[1744830464:1879048191]	auto[1]	12	1			T125	1		T326	1		T230	1
auto[1879048192:2013265919]	auto[0]	109	1			T4	1		T53	1		T52	1
auto[1879048192:2013265919]	auto[1]	15	1			T121	1		T326	1		T241	1
auto[2013265920:2147483647]	auto[0]	84	1			T4	1		T53	1		T23	1
auto[2013265920:2147483647]	auto[1]	7	1			T125	1		T223	1		T276	1
auto[2147483648:2281701375]	auto[0]	104	1			T12	1		T4	1		T59	1
auto[2147483648:2281701375]	auto[1]	5	1			T124	1		T398	1		T347	1
auto[2281701376:2415919103]	auto[0]	109	1			T1	1		T12	1		T4	2
auto[2281701376:2415919103]	auto[1]	8	1			T223	1		T346	1		T228	1
auto[2415919104:2550136831]	auto[0]	94	1			T4	2		T52	1		T119	1
auto[2415919104:2550136831]	auto[1]	13	1			T125	1		T223	1		T270	1
auto[2550136832:2684354559]	auto[0]	85	1			T17	1		T4	2		T62	1
auto[2550136832:2684354559]	auto[1]	7	1			T122	1		T124	2		T270	1
auto[2684354560:2818572287]	auto[0]	90	1			T66	3		T234	1		T70	1
auto[2684354560:2818572287]	auto[1]	14	1			T125	2		T223	1		T326	1
auto[2818572288:2952790015]	auto[0]	87	1			T3	1		T14	1		T26	2
auto[2818572288:2952790015]	auto[1]	9	1			T122	2		T230	1		T407	1
auto[2952790016:3087007743]	auto[0]	102	1			T3	1		T4	1		T59	1
auto[2952790016:3087007743]	auto[1]	14	1			T108	1		T125	2		T223	1
auto[3087007744:3221225471]	auto[0]	111	1			T4	1		T108	1		T53	3
auto[3087007744:3221225471]	auto[1]	8	1			T392	2		T228	1		T405	1
auto[3221225472:3355443199]	auto[0]	89	1			T17	1		T4	1		T53	1
auto[3221225472:3355443199]	auto[1]	7	1			T223	1		T241	1		T230	1
auto[3355443200:3489660927]	auto[0]	101	1			T4	5		T178	1		T53	2
auto[3355443200:3489660927]	auto[1]	7	1			T101	1		T407	1		T401	1
auto[3489660928:3623878655]	auto[0]	110	1			T108	1		T53	1		T20	1
auto[3489660928:3623878655]	auto[1]	9	1			T124	1		T270	1		T392	1
auto[3623878656:3758096383]	auto[0]	88	1			T62	1		T53	1		T67	1
auto[3623878656:3758096383]	auto[1]	9	1			T223	1		T233	1		T403	1
auto[3758096384:3892314111]	auto[0]	108	1			T4	1		T53	1		T34	1
auto[3758096384:3892314111]	auto[1]	13	1			T101	1		T125	2		T270	1
auto[3892314112:4026531839]	auto[0]	76	1			T12	1		T4	1		T66	2
auto[3892314112:4026531839]	auto[1]	11	1			T125	1		T241	2		T230	1
auto[4026531840:4160749567]	auto[0]	93	1			T46	1		T59	1		T53	1
auto[4026531840:4160749567]	auto[1]	6	1			T124	1		T323	1		T392	1
auto[4160749568:4294967295]	auto[0]	100	1			T4	2		T52	1		T66	1
auto[4160749568:4294967295]	auto[1]	7	1			T228	1		T276	1		T400	2