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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T1 1 T3 1 T12 1
auto[1] 1858 1 T3 4 T12 3 T14 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 109 1 T4 4 T53 1 T52 2
auto[134217728:268435455] 105 1 T4 4 T119 1 T66 2
auto[268435456:402653183] 96 1 T52 3 T79 1 T66 1
auto[402653184:536870911] 92 1 T3 1 T4 1 T59 1
auto[536870912:671088639] 102 1 T4 1 T62 1 T53 1
auto[671088640:805306367] 114 1 T1 1 T3 1 T17 1
auto[805306368:939524095] 110 1 T3 1 T4 1 T52 1
auto[939524096:1073741823] 97 1 T14 1 T4 1 T119 1
auto[1073741824:1207959551] 103 1 T46 1 T4 1 T59 1
auto[1207959552:1342177279] 98 1 T4 2 T53 1 T52 1
auto[1342177280:1476395007] 112 1 T4 3 T53 1 T54 2
auto[1476395008:1610612735] 107 1 T3 1 T4 1 T108 1
auto[1610612736:1744830463] 106 1 T20 1 T119 1 T100 1
auto[1744830464:1879048191] 106 1 T46 1 T4 1 T108 1
auto[1879048192:2013265919] 109 1 T12 1 T4 3 T53 2
auto[2013265920:2147483647] 105 1 T4 2 T53 1 T52 1
auto[2147483648:2281701375] 119 1 T12 1 T4 3 T53 1
auto[2281701376:2415919103] 106 1 T12 1 T17 1 T26 1
auto[2415919104:2550136831] 102 1 T26 1 T4 3 T53 1
auto[2550136832:2684354559] 111 1 T4 1 T108 1 T52 2
auto[2684354560:2818572287] 122 1 T4 1 T120 1 T66 2
auto[2818572288:2952790015] 103 1 T12 1 T108 1 T52 2
auto[2952790016:3087007743] 127 1 T19 1 T53 3 T44 2
auto[3087007744:3221225471] 114 1 T4 1 T53 2 T54 1
auto[3221225472:3355443199] 98 1 T17 1 T4 3 T62 1
auto[3355443200:3489660927] 113 1 T4 2 T53 1 T52 5
auto[3489660928:3623878655] 111 1 T3 1 T4 1 T178 2
auto[3623878656:3758096383] 106 1 T4 1 T20 1 T66 1
auto[3758096384:3892314111] 91 1 T4 1 T53 3 T52 2
auto[3892314112:4026531839] 108 1 T4 1 T62 1 T59 1
auto[4026531840:4160749567] 126 1 T17 1 T26 1 T4 3
auto[4160749568:4294967295] 130 1 T4 1 T53 1 T101 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 51 1 T4 1 T53 1 T52 1
auto[0:134217727] auto[1] 58 1 T4 3 T52 1 T360 1
auto[134217728:268435455] auto[0] 54 1 T4 3 T119 1 T35 1
auto[134217728:268435455] auto[1] 51 1 T4 1 T66 2 T238 1
auto[268435456:402653183] auto[0] 54 1 T52 1 T69 1 T83 1
auto[268435456:402653183] auto[1] 42 1 T52 2 T79 1 T66 1
auto[402653184:536870911] auto[0] 40 1 T3 1 T53 1 T44 1
auto[402653184:536870911] auto[1] 52 1 T4 1 T59 1 T178 1
auto[536870912:671088639] auto[0] 47 1 T4 1 T62 1 T120 1
auto[536870912:671088639] auto[1] 55 1 T53 1 T52 1 T120 1
auto[671088640:805306367] auto[0] 34 1 T1 1 T44 1 T66 1
auto[671088640:805306367] auto[1] 80 1 T3 1 T17 1 T53 1
auto[805306368:939524095] auto[0] 57 1 T4 1 T34 1 T67 1
auto[805306368:939524095] auto[1] 53 1 T3 1 T52 1 T69 1
auto[939524096:1073741823] auto[0] 42 1 T4 1 T119 1 T57 1
auto[939524096:1073741823] auto[1] 55 1 T14 1 T66 1 T23 1
auto[1073741824:1207959551] auto[0] 52 1 T46 1 T66 1 T187 1
auto[1073741824:1207959551] auto[1] 51 1 T4 1 T59 1 T53 1
auto[1207959552:1342177279] auto[0] 41 1 T4 2 T48 2 T234 1
auto[1207959552:1342177279] auto[1] 57 1 T53 1 T52 1 T54 1
auto[1342177280:1476395007] auto[0] 52 1 T4 2 T53 1 T66 2
auto[1342177280:1476395007] auto[1] 60 1 T4 1 T54 2 T66 2
auto[1476395008:1610612735] auto[0] 50 1 T4 1 T108 1 T53 1
auto[1476395008:1610612735] auto[1] 57 1 T3 1 T360 1 T177 1
auto[1610612736:1744830463] auto[0] 52 1 T119 1 T232 1 T396 1
auto[1610612736:1744830463] auto[1] 54 1 T20 1 T100 1 T66 1
auto[1744830464:1879048191] auto[0] 40 1 T46 1 T44 1 T134 1
auto[1744830464:1879048191] auto[1] 66 1 T4 1 T108 1 T53 2
auto[1879048192:2013265919] auto[0] 51 1 T4 2 T53 2 T44 2
auto[1879048192:2013265919] auto[1] 58 1 T12 1 T4 1 T69 1
auto[2013265920:2147483647] auto[0] 43 1 T52 1 T120 1 T188 1
auto[2013265920:2147483647] auto[1] 62 1 T4 2 T53 1 T79 1
auto[2147483648:2281701375] auto[0] 56 1 T4 2 T52 2 T395 1
auto[2147483648:2281701375] auto[1] 63 1 T12 1 T4 1 T53 1
auto[2281701376:2415919103] auto[0] 52 1 T12 1 T26 1 T53 2
auto[2281701376:2415919103] auto[1] 54 1 T17 1 T135 1 T114 1
auto[2415919104:2550136831] auto[0] 44 1 T26 1 T4 3 T53 1
auto[2415919104:2550136831] auto[1] 58 1 T188 1 T354 1 T115 1
auto[2550136832:2684354559] auto[0] 48 1 T108 1 T52 1 T23 1
auto[2550136832:2684354559] auto[1] 63 1 T4 1 T52 1 T119 1
auto[2684354560:2818572287] auto[0] 60 1 T4 1 T66 1 T69 1
auto[2684354560:2818572287] auto[1] 62 1 T120 1 T66 1 T135 1
auto[2818572288:2952790015] auto[0] 53 1 T108 1 T119 1 T120 1
auto[2818572288:2952790015] auto[1] 50 1 T12 1 T52 2 T100 1
auto[2952790016:3087007743] auto[0] 60 1 T19 1 T53 1 T44 1
auto[2952790016:3087007743] auto[1] 67 1 T53 2 T44 1 T66 3
auto[3087007744:3221225471] auto[0] 57 1 T4 1 T53 1 T66 3
auto[3087007744:3221225471] auto[1] 57 1 T53 1 T54 1 T66 1
auto[3221225472:3355443199] auto[0] 47 1 T17 1 T4 1 T53 1
auto[3221225472:3355443199] auto[1] 51 1 T4 2 T62 1 T66 1
auto[3355443200:3489660927] auto[0] 60 1 T4 1 T53 1 T52 3
auto[3355443200:3489660927] auto[1] 53 1 T4 1 T52 2 T100 1
auto[3489660928:3623878655] auto[0] 44 1 T178 1 T52 1 T47 1
auto[3489660928:3623878655] auto[1] 67 1 T3 1 T4 1 T178 1
auto[3623878656:3758096383] auto[0] 42 1 T4 1 T66 1 T57 1
auto[3623878656:3758096383] auto[1] 64 1 T20 1 T134 1 T234 1
auto[3758096384:3892314111] auto[0] 46 1 T4 1 T53 2 T52 1
auto[3758096384:3892314111] auto[1] 45 1 T53 1 T52 1 T66 1
auto[3892314112:4026531839] auto[0] 52 1 T62 1 T66 2 T188 1
auto[3892314112:4026531839] auto[1] 56 1 T4 1 T59 1 T54 1
auto[4026531840:4160749567] auto[0] 53 1 T4 2 T47 1 T188 3
auto[4026531840:4160749567] auto[1] 73 1 T17 1 T26 1 T4 1
auto[4160749568:4294967295] auto[0] 66 1 T4 1 T53 1 T101 1
auto[4160749568:4294967295] auto[1] 64 1 T101 1 T66 1 T360 1

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