Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1573

1

T1

1

T3

2

T19

1

auto[1]

1885

1

T3

3

T12

4

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T1	1		T19	1		T4	2
auto[134217728:268435455]	104	1			T26	1		T4	4		T178	1
auto[268435456:402653183]	97	1			T4	3		T53	1		T187	1
auto[402653184:536870911]	101	1			T4	2		T108	1		T53	3
auto[536870912:671088639]	109	1			T17	1		T4	1		T108	1
auto[671088640:805306367]	118	1			T3	1		T4	1		T52	1
auto[805306368:939524095]	103	1			T17	1		T4	4		T59	1
auto[939524096:1073741823]	99	1			T3	1		T46	1		T4	1
auto[1073741824:1207959551]	110	1			T4	2		T108	1		T52	2
auto[1207959552:1342177279]	107	1			T53	1		T119	1		T44	1
auto[1342177280:1476395007]	121	1			T12	1		T46	1		T4	1
auto[1476395008:1610612735]	107	1			T14	1		T4	2		T53	1
auto[1610612736:1744830463]	106	1			T53	1		T52	2		T44	1
auto[1744830464:1879048191]	113	1			T12	1		T4	1		T53	2
auto[1879048192:2013265919]	98	1			T4	1		T59	1		T52	1
auto[2013265920:2147483647]	108	1			T12	2		T4	1		T62	1
auto[2147483648:2281701375]	106	1			T3	1		T4	2		T53	3
auto[2281701376:2415919103]	94	1			T4	2		T178	1		T53	1
auto[2415919104:2550136831]	124	1			T4	2		T178	1		T53	1
auto[2550136832:2684354559]	112	1			T4	1		T47	1		T54	1
auto[2684354560:2818572287]	126	1			T17	1		T4	2		T108	1
auto[2818572288:2952790015]	96	1			T17	1		T20	1		T79	1
auto[2952790016:3087007743]	112	1			T62	1		T53	1		T52	1
auto[3087007744:3221225471]	100	1			T26	1		T4	2		T53	3
auto[3221225472:3355443199]	115	1			T4	1		T62	1		T52	1
auto[3355443200:3489660927]	93	1			T4	1		T53	1		T52	2
auto[3489660928:3623878655]	110	1			T3	1		T4	3		T52	1
auto[3623878656:3758096383]	119	1			T3	1		T53	3		T20	1
auto[3758096384:3892314111]	110	1			T53	1		T52	1		T34	2
auto[3892314112:4026531839]	123	1			T4	2		T34	1		T54	1
auto[4026531840:4160749567]	108	1			T26	1		T4	2		T59	1
auto[4160749568:4294967295]	115	1			T4	1		T53	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35	1			T1	1		T19	1		T4	1
auto[0:134217727]	auto[1]	59	1			T4	1		T188	1		T6	4
auto[134217728:268435455]	auto[0]	56	1			T26	1		T4	3		T53	1
auto[134217728:268435455]	auto[1]	48	1			T4	1		T178	1		T52	1
auto[268435456:402653183]	auto[0]	44	1			T4	2		T53	1		T188	1
auto[268435456:402653183]	auto[1]	53	1			T4	1		T187	1		T218	1
auto[402653184:536870911]	auto[0]	42	1			T108	1		T53	1		T100	1
auto[402653184:536870911]	auto[1]	59	1			T4	2		T53	2		T52	1
auto[536870912:671088639]	auto[0]	51	1			T4	1		T53	1		T119	1
auto[536870912:671088639]	auto[1]	58	1			T17	1		T108	1		T52	1
auto[671088640:805306367]	auto[0]	48	1			T4	1		T69	1		T68	1
auto[671088640:805306367]	auto[1]	70	1			T3	1		T52	1		T135	1
auto[805306368:939524095]	auto[0]	42	1			T4	3		T67	1		T24	1
auto[805306368:939524095]	auto[1]	61	1			T17	1		T4	1		T59	1
auto[939524096:1073741823]	auto[0]	41	1			T46	1		T6	1		T239	1
auto[939524096:1073741823]	auto[1]	58	1			T3	1		T4	1		T178	1
auto[1073741824:1207959551]	auto[0]	47	1			T4	2		T108	1		T52	2
auto[1073741824:1207959551]	auto[1]	63	1			T54	1		T66	3		T69	1
auto[1207959552:1342177279]	auto[0]	51	1			T66	1		T395	1		T85	2
auto[1207959552:1342177279]	auto[1]	56	1			T53	1		T119	1		T44	1
auto[1342177280:1476395007]	auto[0]	53	1			T232	1		T180	1		T234	1
auto[1342177280:1476395007]	auto[1]	68	1			T12	1		T46	1		T4	1
auto[1476395008:1610612735]	auto[0]	50	1			T4	1		T119	1		T66	1
auto[1476395008:1610612735]	auto[1]	57	1			T14	1		T4	1		T53	1
auto[1610612736:1744830463]	auto[0]	50	1			T53	1		T52	1		T44	1
auto[1610612736:1744830463]	auto[1]	56	1			T52	1		T135	1		T188	1
auto[1744830464:1879048191]	auto[0]	53	1			T4	1		T53	1		T119	1
auto[1744830464:1879048191]	auto[1]	60	1			T12	1		T53	1		T120	1
auto[1879048192:2013265919]	auto[0]	49	1			T79	1		T57	1		T21	1
auto[1879048192:2013265919]	auto[1]	49	1			T4	1		T59	1		T52	1
auto[2013265920:2147483647]	auto[0]	49	1			T4	1		T62	1		T53	1
auto[2013265920:2147483647]	auto[1]	59	1			T12	2		T52	2		T54	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T4	2		T53	2
auto[2147483648:2281701375]	auto[1]	53	1			T53	1		T54	1		T66	1
auto[2281701376:2415919103]	auto[0]	47	1			T4	1		T178	1		T69	1
auto[2281701376:2415919103]	auto[1]	47	1			T4	1		T53	1		T100	1
auto[2415919104:2550136831]	auto[0]	72	1			T4	2		T52	1		T120	2
auto[2415919104:2550136831]	auto[1]	52	1			T178	1		T53	1		T52	1
auto[2550136832:2684354559]	auto[0]	48	1			T47	1		T66	1		T69	3
auto[2550136832:2684354559]	auto[1]	64	1			T4	1		T54	1		T66	1
auto[2684354560:2818572287]	auto[0]	65	1			T4	1		T120	1		T54	1
auto[2684354560:2818572287]	auto[1]	61	1			T17	1		T4	1		T108	1
auto[2818572288:2952790015]	auto[0]	45	1			T79	1		T44	1		T54	1
auto[2818572288:2952790015]	auto[1]	51	1			T17	1		T20	1		T66	1
auto[2952790016:3087007743]	auto[0]	56	1			T62	1		T53	1		T52	1
auto[2952790016:3087007743]	auto[1]	56	1			T101	1		T66	2		T67	1
auto[3087007744:3221225471]	auto[0]	42	1			T26	1		T4	2		T53	2
auto[3087007744:3221225471]	auto[1]	58	1			T53	1		T52	2		T79	1
auto[3221225472:3355443199]	auto[0]	54	1			T44	1		T35	1		T94	1
auto[3221225472:3355443199]	auto[1]	61	1			T4	1		T62	1		T52	1
auto[3355443200:3489660927]	auto[0]	39	1			T4	1		T52	1		T119	1
auto[3355443200:3489660927]	auto[1]	54	1			T53	1		T52	1		T66	1
auto[3489660928:3623878655]	auto[0]	49	1			T4	3		T52	1		T188	3
auto[3489660928:3623878655]	auto[1]	61	1			T3	1		T66	1		T177	1
auto[3623878656:3758096383]	auto[0]	40	1			T3	1		T53	2		T44	1
auto[3623878656:3758096383]	auto[1]	79	1			T53	1		T20	1		T54	1
auto[3758096384:3892314111]	auto[0]	52	1			T52	1		T34	2		T101	1
auto[3758096384:3892314111]	auto[1]	58	1			T53	1		T54	1		T66	2
auto[3892314112:4026531839]	auto[0]	50	1			T4	1		T34	1		T66	2
auto[3892314112:4026531839]	auto[1]	73	1			T4	1		T54	1		T66	2
auto[4026531840:4160749567]	auto[0]	46	1			T26	1		T4	1		T54	1
auto[4026531840:4160749567]	auto[1]	62	1			T4	1		T59	1		T53	1
auto[4160749568:4294967295]	auto[0]	54	1			T53	1		T44	1		T48	2
auto[4160749568:4294967295]	auto[1]	61	1			T4	1		T66	1		T135	1