Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7216

1

T1

1

T3

8

T12

16

auto[1]

282

1

T108

8

T101

1

T121

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2984	1			T3	2		T12	6		T17	3
auto[134217728:268435455]	182	1			T3	3		T17	1		T4	1
auto[268435456:402653183]	174	1			T12	1		T26	1		T4	1
auto[402653184:536870911]	162	1			T14	1		T4	3		T53	3
auto[536870912:671088639]	160	1			T12	1		T4	2		T178	1
auto[671088640:805306367]	148	1			T12	1		T52	1		T79	1
auto[805306368:939524095]	144	1			T4	2		T108	2		T59	1
auto[939524096:1073741823]	155	1			T4	2		T62	2		T108	2
auto[1073741824:1207959551]	141	1			T46	1		T4	1		T108	1
auto[1207959552:1342177279]	158	1			T4	1		T108	1		T79	1
auto[1342177280:1476395007]	165	1			T4	1		T44	1		T54	1
auto[1476395008:1610612735]	151	1			T12	1		T19	1		T4	1
auto[1610612736:1744830463]	135	1			T12	1		T4	2		T52	2
auto[1744830464:1879048191]	143	1			T4	3		T53	2		T52	2
auto[1879048192:2013265919]	146	1			T3	1		T178	1		T53	1
auto[2013265920:2147483647]	167	1			T1	1		T108	1		T52	1
auto[2147483648:2281701375]	121	1			T4	1		T59	1		T52	1
auto[2281701376:2415919103]	133	1			T3	1		T12	1		T19	1
auto[2415919104:2550136831]	140	1			T17	1		T62	1		T52	1
auto[2550136832:2684354559]	145	1			T12	1		T17	1		T178	1
auto[2684354560:2818572287]	127	1			T17	1		T4	1		T52	1
auto[2818572288:2952790015]	155	1			T4	2		T62	1		T108	3
auto[2952790016:3087007743]	148	1			T4	3		T108	1		T52	3
auto[3087007744:3221225471]	123	1			T12	1		T79	1		T100	1
auto[3221225472:3355443199]	135	1			T46	1		T4	2		T52	1
auto[3355443200:3489660927]	134	1			T12	1		T46	1		T108	1
auto[3489660928:3623878655]	122	1			T12	1		T26	2		T4	1
auto[3623878656:3758096383]	114	1			T4	2		T108	1		T52	1
auto[3758096384:3892314111]	146	1			T3	1		T26	1		T53	1
auto[3892314112:4026531839]	134	1			T4	3		T178	2		T52	1
auto[4026531840:4160749567]	155	1			T17	1		T4	4		T59	1
auto[4160749568:4294967295]	151	1			T4	6		T53	1		T52	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2976	1			T3	2		T12	6		T17	3
auto[0:134217727]	auto[1]	8	1			T124	1		T233	2		T346	1
auto[134217728:268435455]	auto[0]	173	1			T3	3		T17	1		T4	1
auto[134217728:268435455]	auto[1]	9	1			T270	1		T346	2		T214	1
auto[268435456:402653183]	auto[0]	170	1			T12	1		T26	1		T4	1
auto[268435456:402653183]	auto[1]	4	1			T270	1		T392	1		T397	1
auto[402653184:536870911]	auto[0]	153	1			T14	1		T4	3		T53	3
auto[402653184:536870911]	auto[1]	9	1			T329	1		T122	1		T125	1
auto[536870912:671088639]	auto[0]	158	1			T12	1		T4	2		T178	1
auto[536870912:671088639]	auto[1]	2	1			T280	1		T346	1		-	-
auto[671088640:805306367]	auto[0]	139	1			T12	1		T52	1		T79	1
auto[671088640:805306367]	auto[1]	9	1			T329	1		T241	1		T270	1
auto[805306368:939524095]	auto[0]	135	1			T4	2		T108	2		T59	1
auto[805306368:939524095]	auto[1]	9	1			T125	1		T270	1		T233	1
auto[939524096:1073741823]	auto[0]	145	1			T4	2		T62	2		T53	2
auto[939524096:1073741823]	auto[1]	10	1			T108	2		T101	1		T391	1
auto[1073741824:1207959551]	auto[0]	130	1			T46	1		T4	1		T52	1
auto[1073741824:1207959551]	auto[1]	11	1			T108	1		T373	1		T228	2
auto[1207959552:1342177279]	auto[0]	149	1			T4	1		T79	1		T100	1
auto[1207959552:1342177279]	auto[1]	9	1			T108	1		T223	1		T230	1
auto[1342177280:1476395007]	auto[0]	147	1			T4	1		T44	1		T54	1
auto[1342177280:1476395007]	auto[1]	18	1			T121	1		T124	1		T326	1
auto[1476395008:1610612735]	auto[0]	138	1			T12	1		T19	1		T4	1
auto[1476395008:1610612735]	auto[1]	13	1			T121	1		T125	1		T241	1
auto[1610612736:1744830463]	auto[0]	127	1			T12	1		T4	2		T52	2
auto[1610612736:1744830463]	auto[1]	8	1			T233	3		T398	1		T399	1
auto[1744830464:1879048191]	auto[0]	137	1			T4	3		T53	2		T52	2
auto[1744830464:1879048191]	auto[1]	6	1			T124	1		T233	1		T346	1
auto[1879048192:2013265919]	auto[0]	138	1			T3	1		T178	1		T53	1
auto[1879048192:2013265919]	auto[1]	8	1			T241	1		T270	1		T228	1
auto[2013265920:2147483647]	auto[0]	161	1			T1	1		T52	1		T79	1
auto[2013265920:2147483647]	auto[1]	6	1			T108	1		T121	1		T122	1
auto[2147483648:2281701375]	auto[0]	113	1			T4	1		T59	1		T52	1
auto[2147483648:2281701375]	auto[1]	8	1			T230	1		T228	1		T276	1
auto[2281701376:2415919103]	auto[0]	124	1			T3	1		T12	1		T19	1
auto[2281701376:2415919103]	auto[1]	9	1			T125	1		T230	2		T270	1
auto[2415919104:2550136831]	auto[0]	128	1			T17	1		T62	1		T52	1
auto[2415919104:2550136831]	auto[1]	12	1			T122	1		T233	1		T373	1
auto[2550136832:2684354559]	auto[0]	139	1			T12	1		T17	1		T178	1
auto[2550136832:2684354559]	auto[1]	6	1			T223	1		T392	2		T228	1
auto[2684354560:2818572287]	auto[0]	117	1			T17	1		T4	1		T52	1
auto[2684354560:2818572287]	auto[1]	10	1			T223	1		T230	2		T270	1
auto[2818572288:2952790015]	auto[0]	144	1			T4	2		T62	1		T108	2
auto[2818572288:2952790015]	auto[1]	11	1			T108	1		T326	1		T241	1
auto[2952790016:3087007743]	auto[0]	137	1			T4	3		T52	3		T120	1
auto[2952790016:3087007743]	auto[1]	11	1			T108	1		T122	1		T228	1
auto[3087007744:3221225471]	auto[0]	115	1			T12	1		T79	1		T100	1
auto[3087007744:3221225471]	auto[1]	8	1			T121	1		T122	1		T125	1
auto[3221225472:3355443199]	auto[0]	124	1			T46	1		T4	2		T52	1
auto[3221225472:3355443199]	auto[1]	11	1			T241	1		T270	2		T392	1
auto[3355443200:3489660927]	auto[0]	125	1			T12	1		T46	1		T53	1
auto[3355443200:3489660927]	auto[1]	9	1			T108	1		T124	1		T125	1
auto[3489660928:3623878655]	auto[0]	113	1			T12	1		T26	2		T4	1
auto[3489660928:3623878655]	auto[1]	9	1			T214	2		T276	2		T340	1
auto[3623878656:3758096383]	auto[0]	109	1			T4	2		T108	1		T52	1
auto[3623878656:3758096383]	auto[1]	5	1			T398	1		T340	1		T394	1
auto[3758096384:3892314111]	auto[0]	137	1			T3	1		T26	1		T53	1
auto[3758096384:3892314111]	auto[1]	9	1			T124	2		T230	1		T323	1
auto[3892314112:4026531839]	auto[0]	124	1			T4	3		T178	2		T52	1
auto[3892314112:4026531839]	auto[1]	10	1			T125	2		T270	1		T228	2
auto[4026531840:4160749567]	auto[0]	147	1			T17	1		T4	4		T59	1
auto[4026531840:4160749567]	auto[1]	8	1			T125	2		T230	1		T400	1
auto[4160749568:4294967295]	auto[0]	144	1			T4	6		T53	1		T52	2
auto[4160749568:4294967295]	auto[1]	7	1			T125	1		T346	1		T401	1