Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4552

1

T3

6

T12

4

T17

8

auto[1]

2364

1

T1

2

T3

4

T12

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	222	1			T14	2		T4	8		T59	2
auto[134217728:268435455]	206	1			T79	2		T120	2		T101	2
auto[268435456:402653183]	252	1			T4	2		T53	2		T52	2
auto[402653184:536870911]	188	1			T4	2		T108	2		T53	6
auto[536870912:671088639]	210	1			T12	2		T26	2		T53	2
auto[671088640:805306367]	262	1			T3	2		T4	8		T53	2
auto[805306368:939524095]	222	1			T17	2		T4	2		T108	2
auto[939524096:1073741823]	220	1			T46	2		T4	2		T53	2
auto[1073741824:1207959551]	212	1			T53	2		T79	2		T34	2
auto[1207959552:1342177279]	190	1			T3	2		T53	4		T52	2
auto[1342177280:1476395007]	226	1			T26	4		T4	4		T100	2
auto[1476395008:1610612735]	186	1			T3	2		T178	2		T53	2
auto[1610612736:1744830463]	202	1			T4	2		T53	2		T52	2
auto[1744830464:1879048191]	220	1			T1	2		T12	2		T4	6
auto[1879048192:2013265919]	222	1			T12	2		T4	4		T62	2
auto[2013265920:2147483647]	234	1			T4	4		T53	2		T52	2
auto[2147483648:2281701375]	180	1			T4	2		T62	2		T53	2
auto[2281701376:2415919103]	206	1			T4	4		T53	2		T66	2
auto[2415919104:2550136831]	246	1			T4	4		T20	2		T52	2
auto[2550136832:2684354559]	244	1			T19	2		T46	2		T120	4
auto[2684354560:2818572287]	198	1			T4	4		T52	4		T44	2
auto[2818572288:2952790015]	228	1			T4	6		T53	4		T20	2
auto[2952790016:3087007743]	204	1			T3	2		T17	2		T4	6
auto[3087007744:3221225471]	200	1			T17	2		T59	2		T52	2
auto[3221225472:3355443199]	224	1			T4	6		T108	2		T52	4
auto[3355443200:3489660927]	232	1			T4	6		T59	2		T53	2
auto[3489660928:3623878655]	186	1			T17	2		T4	4		T178	2
auto[3623878656:3758096383]	222	1			T4	4		T53	4		T52	2
auto[3758096384:3892314111]	222	1			T108	2		T53	2		T52	2
auto[3892314112:4026531839]	218	1			T12	2		T4	2		T62	2
auto[4026531840:4160749567]	210	1			T3	2		T53	4		T52	2
auto[4160749568:4294967295]	222	1			T4	2		T53	4		T395	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	144	1			T4	4		T178	2		T53	2
auto[0:134217727]	auto[1]	78	1			T14	2		T4	4		T59	2
auto[134217728:268435455]	auto[0]	134	1			T79	2		T120	2		T66	2
auto[134217728:268435455]	auto[1]	72	1			T101	2		T83	2		T123	4
auto[268435456:402653183]	auto[0]	166	1			T52	2		T119	2		T44	2
auto[268435456:402653183]	auto[1]	86	1			T4	2		T53	2		T100	2
auto[402653184:536870911]	auto[0]	138	1			T4	2		T53	6		T54	2
auto[402653184:536870911]	auto[1]	50	1			T108	2		T134	2		T48	2
auto[536870912:671088639]	auto[0]	148	1			T12	2		T26	2		T119	2
auto[536870912:671088639]	auto[1]	62	1			T53	2		T52	2		T232	2
auto[671088640:805306367]	auto[0]	164	1			T3	2		T4	6		T52	2
auto[671088640:805306367]	auto[1]	98	1			T4	2		T53	2		T54	2
auto[805306368:939524095]	auto[0]	144	1			T17	2		T4	2		T52	2
auto[805306368:939524095]	auto[1]	78	1			T108	2		T134	2		T234	2
auto[939524096:1073741823]	auto[0]	164	1			T46	2		T4	2		T53	2
auto[939524096:1073741823]	auto[1]	56	1			T52	4		T101	2		T188	2
auto[1073741824:1207959551]	auto[0]	118	1			T53	2		T79	2		T47	2
auto[1073741824:1207959551]	auto[1]	94	1			T34	2		T187	2		T177	2
auto[1207959552:1342177279]	auto[0]	108	1			T66	4		T58	2		T122	2
auto[1207959552:1342177279]	auto[1]	82	1			T3	2		T53	4		T52	2
auto[1342177280:1476395007]	auto[0]	148	1			T4	2		T100	2		T66	2
auto[1342177280:1476395007]	auto[1]	78	1			T26	4		T4	2		T54	2
auto[1476395008:1610612735]	auto[0]	118	1			T178	2		T66	2		T23	2
auto[1476395008:1610612735]	auto[1]	68	1			T3	2		T53	2		T21	2
auto[1610612736:1744830463]	auto[0]	136	1			T4	2		T52	2		T54	2
auto[1610612736:1744830463]	auto[1]	66	1			T53	2		T100	2		T44	2
auto[1744830464:1879048191]	auto[0]	150	1			T4	4		T66	2		T232	2
auto[1744830464:1879048191]	auto[1]	70	1			T1	2		T12	2		T4	2
auto[1879048192:2013265919]	auto[0]	166	1			T4	2		T62	2		T53	2
auto[1879048192:2013265919]	auto[1]	56	1			T12	2		T4	2		T54	2
auto[2013265920:2147483647]	auto[0]	152	1			T4	2		T53	2		T79	2
auto[2013265920:2147483647]	auto[1]	82	1			T4	2		T52	2		T100	2
auto[2147483648:2281701375]	auto[0]	114	1			T62	2		T53	2		T52	2
auto[2147483648:2281701375]	auto[1]	66	1			T4	2		T66	2		T188	2
auto[2281701376:2415919103]	auto[0]	144	1			T4	2		T53	2		T66	2
auto[2281701376:2415919103]	auto[1]	62	1			T4	2		T395	2		T188	4
auto[2415919104:2550136831]	auto[0]	150	1			T4	4		T52	2		T66	6
auto[2415919104:2550136831]	auto[1]	96	1			T20	2		T34	4		T395	2
auto[2550136832:2684354559]	auto[0]	164	1			T19	2		T46	2		T120	4
auto[2550136832:2684354559]	auto[1]	80	1			T23	2		T69	2		T67	4
auto[2684354560:2818572287]	auto[0]	126	1			T4	4		T52	4		T66	4
auto[2684354560:2818572287]	auto[1]	72	1			T44	2		T329	2		T238	2
auto[2818572288:2952790015]	auto[0]	146	1			T4	4		T53	4		T52	2
auto[2818572288:2952790015]	auto[1]	82	1			T4	2		T20	2		T67	2
auto[2952790016:3087007743]	auto[0]	130	1			T3	2		T17	2		T4	4
auto[2952790016:3087007743]	auto[1]	74	1			T4	2		T66	2		T48	2
auto[3087007744:3221225471]	auto[0]	132	1			T17	2		T59	2		T52	2
auto[3087007744:3221225471]	auto[1]	68	1			T67	2		T243	2		T123	2
auto[3221225472:3355443199]	auto[0]	160	1			T4	6		T108	2		T52	2
auto[3221225472:3355443199]	auto[1]	64	1			T52	2		T66	2		T245	2
auto[3355443200:3489660927]	auto[0]	148	1			T4	4		T52	2		T66	2
auto[3355443200:3489660927]	auto[1]	84	1			T4	2		T59	2		T53	2
auto[3489660928:3623878655]	auto[0]	132	1			T17	2		T4	4		T178	2
auto[3489660928:3623878655]	auto[1]	54	1			T52	2		T66	4		T70	2
auto[3623878656:3758096383]	auto[0]	146	1			T4	4		T53	2		T52	2
auto[3623878656:3758096383]	auto[1]	76	1			T53	2		T114	2		T188	2
auto[3758096384:3892314111]	auto[0]	138	1			T108	2		T52	2		T119	4
auto[3758096384:3892314111]	auto[1]	84	1			T53	2		T54	2		T69	2
auto[3892314112:4026531839]	auto[0]	140	1			T12	2		T178	2		T44	2
auto[3892314112:4026531839]	auto[1]	78	1			T4	2		T62	2		T53	2
auto[4026531840:4160749567]	auto[0]	134	1			T3	2		T53	4		T54	2
auto[4026531840:4160749567]	auto[1]	76	1			T52	2		T360	2		T217	2
auto[4160749568:4294967295]	auto[0]	150	1			T4	2		T53	2		T188	4
auto[4160749568:4294967295]	auto[1]	72	1			T53	2		T395	2		T188	4