Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 98.11 98.24 100.00 99.02 98.41 91.19


Total test records in report: 1089
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1009 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2332807748 Jul 04 05:07:09 PM PDT 24 Jul 04 05:07:11 PM PDT 24 91717901 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.54295440 Jul 04 05:06:50 PM PDT 24 Jul 04 05:06:53 PM PDT 24 134658842 ps
T1011 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2014197772 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:26 PM PDT 24 17501032 ps
T1012 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2555644074 Jul 04 05:06:56 PM PDT 24 Jul 04 05:07:04 PM PDT 24 339460879 ps
T1013 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2562734213 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:05 PM PDT 24 117467290 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1231985739 Jul 04 05:07:05 PM PDT 24 Jul 04 05:07:06 PM PDT 24 22087618 ps
T1015 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3948091804 Jul 04 05:07:18 PM PDT 24 Jul 04 05:07:19 PM PDT 24 14136592 ps
T1016 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.104453351 Jul 04 05:06:52 PM PDT 24 Jul 04 05:06:53 PM PDT 24 17635880 ps
T1017 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.228344676 Jul 04 05:07:12 PM PDT 24 Jul 04 05:07:14 PM PDT 24 31381344 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3518246578 Jul 04 05:06:50 PM PDT 24 Jul 04 05:07:04 PM PDT 24 2240467984 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.334740212 Jul 04 05:06:59 PM PDT 24 Jul 04 05:07:09 PM PDT 24 1403430258 ps
T1020 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.821174382 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:27 PM PDT 24 34910780 ps
T1021 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.896679082 Jul 04 05:07:20 PM PDT 24 Jul 04 05:07:22 PM PDT 24 467914184 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.203018487 Jul 04 05:06:52 PM PDT 24 Jul 04 05:07:00 PM PDT 24 1019053079 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1024542679 Jul 04 05:06:56 PM PDT 24 Jul 04 05:06:58 PM PDT 24 48892227 ps
T1024 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2678493692 Jul 04 05:07:11 PM PDT 24 Jul 04 05:07:13 PM PDT 24 10030605 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3265355046 Jul 04 05:06:49 PM PDT 24 Jul 04 05:06:59 PM PDT 24 667272785 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2188797345 Jul 04 05:06:50 PM PDT 24 Jul 04 05:06:53 PM PDT 24 375863891 ps
T1027 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1448686391 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:17 PM PDT 24 376974760 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3698744322 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:05 PM PDT 24 11691299 ps
T1029 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4048497694 Jul 04 05:07:21 PM PDT 24 Jul 04 05:07:22 PM PDT 24 14994824 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3759317512 Jul 04 05:06:58 PM PDT 24 Jul 04 05:06:59 PM PDT 24 9091262 ps
T1031 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2271390449 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:26 PM PDT 24 9584197 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3687736534 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:05 PM PDT 24 136187978 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2760251621 Jul 04 05:06:50 PM PDT 24 Jul 04 05:06:52 PM PDT 24 216901403 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.803854118 Jul 04 05:07:11 PM PDT 24 Jul 04 05:07:15 PM PDT 24 115255955 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1867486642 Jul 04 05:06:50 PM PDT 24 Jul 04 05:06:55 PM PDT 24 135594023 ps
T1036 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.478129171 Jul 04 05:06:58 PM PDT 24 Jul 04 05:07:05 PM PDT 24 258759282 ps
T1037 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.629484763 Jul 04 05:07:19 PM PDT 24 Jul 04 05:07:21 PM PDT 24 15014984 ps
T1038 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.612848420 Jul 04 05:07:20 PM PDT 24 Jul 04 05:07:21 PM PDT 24 49337621 ps
T160 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3362315735 Jul 04 05:07:01 PM PDT 24 Jul 04 05:07:12 PM PDT 24 326185854 ps
T1039 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1901430360 Jul 04 05:07:24 PM PDT 24 Jul 04 05:07:25 PM PDT 24 11943344 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4253054337 Jul 04 05:06:59 PM PDT 24 Jul 04 05:07:01 PM PDT 24 86214990 ps
T1041 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.575244658 Jul 04 05:07:18 PM PDT 24 Jul 04 05:07:21 PM PDT 24 102192548 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2708376043 Jul 04 05:07:23 PM PDT 24 Jul 04 05:07:24 PM PDT 24 17178483 ps
T1043 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2953324418 Jul 04 05:06:49 PM PDT 24 Jul 04 05:06:52 PM PDT 24 134918321 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1705145293 Jul 04 05:07:20 PM PDT 24 Jul 04 05:07:21 PM PDT 24 11707364 ps
T1045 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3671050673 Jul 04 05:06:56 PM PDT 24 Jul 04 05:07:00 PM PDT 24 286794430 ps
T1046 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.488853238 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:27 PM PDT 24 26874474 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3712277480 Jul 04 05:06:49 PM PDT 24 Jul 04 05:06:50 PM PDT 24 27364573 ps
T1048 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3925780025 Jul 04 05:06:59 PM PDT 24 Jul 04 05:07:00 PM PDT 24 33598983 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3214043090 Jul 04 05:06:50 PM PDT 24 Jul 04 05:06:51 PM PDT 24 14811685 ps
T150 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3533322606 Jul 04 05:07:23 PM PDT 24 Jul 04 05:07:30 PM PDT 24 908540456 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3823948201 Jul 04 05:07:19 PM PDT 24 Jul 04 05:07:29 PM PDT 24 373356342 ps
T1051 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.249635367 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:27 PM PDT 24 13802749 ps
T1052 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.794391794 Jul 04 05:06:56 PM PDT 24 Jul 04 05:07:03 PM PDT 24 364416280 ps
T1053 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2392978923 Jul 04 05:06:56 PM PDT 24 Jul 04 05:07:01 PM PDT 24 124480201 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2349952363 Jul 04 05:07:01 PM PDT 24 Jul 04 05:07:02 PM PDT 24 17877355 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3897946034 Jul 04 05:06:58 PM PDT 24 Jul 04 05:07:01 PM PDT 24 280939682 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4259532391 Jul 04 05:07:09 PM PDT 24 Jul 04 05:07:11 PM PDT 24 74195630 ps
T1057 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3338569094 Jul 04 05:06:56 PM PDT 24 Jul 04 05:06:58 PM PDT 24 124585611 ps
T1058 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2265010261 Jul 04 05:07:04 PM PDT 24 Jul 04 05:07:05 PM PDT 24 9634382 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2294592793 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:04 PM PDT 24 9673187 ps
T154 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3935383408 Jul 04 05:06:49 PM PDT 24 Jul 04 05:06:57 PM PDT 24 277204428 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3759919986 Jul 04 05:06:51 PM PDT 24 Jul 04 05:06:53 PM PDT 24 49388043 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2673869258 Jul 04 05:07:17 PM PDT 24 Jul 04 05:07:20 PM PDT 24 39040772 ps
T1062 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2832778125 Jul 04 05:07:06 PM PDT 24 Jul 04 05:07:08 PM PDT 24 46567773 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3747413964 Jul 04 05:06:42 PM PDT 24 Jul 04 05:06:44 PM PDT 24 121948461 ps
T1064 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2402305315 Jul 04 05:06:56 PM PDT 24 Jul 04 05:06:57 PM PDT 24 53127544 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3848603705 Jul 04 05:07:09 PM PDT 24 Jul 04 05:07:11 PM PDT 24 100204817 ps
T1066 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.89340390 Jul 04 05:06:57 PM PDT 24 Jul 04 05:07:00 PM PDT 24 253484276 ps
T1067 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3172345780 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 14807984 ps
T1068 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.891008725 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:27 PM PDT 24 9323576 ps
T165 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3524972746 Jul 04 05:07:21 PM PDT 24 Jul 04 05:07:32 PM PDT 24 293543278 ps
T151 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2039658351 Jul 04 05:06:45 PM PDT 24 Jul 04 05:06:49 PM PDT 24 117794656 ps
T147 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1029906146 Jul 04 05:06:44 PM PDT 24 Jul 04 05:06:47 PM PDT 24 194309957 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.770274227 Jul 04 05:07:01 PM PDT 24 Jul 04 05:07:04 PM PDT 24 191890028 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3077581557 Jul 04 05:07:03 PM PDT 24 Jul 04 05:07:05 PM PDT 24 65435894 ps
T1071 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3264894797 Jul 04 05:07:16 PM PDT 24 Jul 04 05:07:17 PM PDT 24 56439250 ps
T164 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3475144671 Jul 04 05:06:56 PM PDT 24 Jul 04 05:07:01 PM PDT 24 169887524 ps
T1072 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4165902972 Jul 04 05:07:12 PM PDT 24 Jul 04 05:07:15 PM PDT 24 266463822 ps
T1073 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3015833435 Jul 04 05:06:43 PM PDT 24 Jul 04 05:06:45 PM PDT 24 27977327 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4132842305 Jul 04 05:07:17 PM PDT 24 Jul 04 05:07:18 PM PDT 24 22368368 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4107379545 Jul 04 05:06:44 PM PDT 24 Jul 04 05:06:50 PM PDT 24 206958048 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3451086100 Jul 04 05:06:45 PM PDT 24 Jul 04 05:06:47 PM PDT 24 71828766 ps
T1077 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.834014889 Jul 04 05:06:59 PM PDT 24 Jul 04 05:07:17 PM PDT 24 533383698 ps
T1078 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.946731378 Jul 04 05:06:56 PM PDT 24 Jul 04 05:06:59 PM PDT 24 72209502 ps
T1079 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3395958742 Jul 04 05:07:02 PM PDT 24 Jul 04 05:07:03 PM PDT 24 232529963 ps
T1080 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2559557388 Jul 04 05:07:09 PM PDT 24 Jul 04 05:07:13 PM PDT 24 400704749 ps
T1081 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1696079571 Jul 04 05:07:21 PM PDT 24 Jul 04 05:07:23 PM PDT 24 15671995 ps
T1082 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4027544792 Jul 04 05:07:05 PM PDT 24 Jul 04 05:07:07 PM PDT 24 72508996 ps
T1083 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2238484134 Jul 04 05:07:20 PM PDT 24 Jul 04 05:07:21 PM PDT 24 11657432 ps
T157 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1113121443 Jul 04 05:07:10 PM PDT 24 Jul 04 05:07:16 PM PDT 24 265321679 ps
T1084 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4162319485 Jul 04 05:07:02 PM PDT 24 Jul 04 05:07:04 PM PDT 24 63098580 ps
T1085 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4129869066 Jul 04 05:06:51 PM PDT 24 Jul 04 05:06:54 PM PDT 24 260931735 ps
T1086 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.665455135 Jul 04 05:07:19 PM PDT 24 Jul 04 05:07:25 PM PDT 24 418677843 ps
T1087 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1328899184 Jul 04 05:07:24 PM PDT 24 Jul 04 05:07:25 PM PDT 24 13289672 ps
T1088 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1120267792 Jul 04 05:06:43 PM PDT 24 Jul 04 05:06:45 PM PDT 24 8489004 ps
T1089 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4278819540 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:27 PM PDT 24 13989776 ps

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.484802205
Short name T3
Test name
Test status
Simulation time 2566942847 ps
CPU time 14.64 seconds
Started Jul 04 06:47:11 PM PDT 24
Finished Jul 04 06:47:26 PM PDT 24
Peak memory 221532 kb
Host smart-5f139e89-512a-4ea2-bff5-efe4480e60db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484802205 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.484802205
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.577506628
Short name T66
Test name
Test status
Simulation time 1310407217 ps
CPU time 46.02 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:47:37 PM PDT 24
Peak memory 221964 kb
Host smart-75d957f6-47e9-4206-937d-427cba61b6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577506628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.577506628
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.439248890
Short name T4
Test name
Test status
Simulation time 12390713473 ps
CPU time 195.47 seconds
Started Jul 04 06:47:58 PM PDT 24
Finished Jul 04 06:51:14 PM PDT 24
Peak memory 221344 kb
Host smart-34f75723-ada4-4253-a98a-cf7f56764d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439248890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.439248890
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3945452246
Short name T10
Test name
Test status
Simulation time 2649813376 ps
CPU time 7 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:09 PM PDT 24
Peak memory 233316 kb
Host smart-a4ee77e5-5523-4c00-bb85-4e3ea44eca60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945452246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3945452246
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3508294670
Short name T106
Test name
Test status
Simulation time 168033560 ps
CPU time 3.19 seconds
Started Jul 04 05:06:55 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 213932 kb
Host smart-24bcb9ec-4e84-4096-a145-a31ca957227d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508294670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3508294670
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3318126473
Short name T6
Test name
Test status
Simulation time 5942078085 ps
CPU time 110.5 seconds
Started Jul 04 06:48:01 PM PDT 24
Finished Jul 04 06:49:52 PM PDT 24
Peak memory 215868 kb
Host smart-dfda1834-92af-4747-8f59-2694a77c416e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318126473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3318126473
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4268022563
Short name T48
Test name
Test status
Simulation time 110119038 ps
CPU time 3.61 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 214312 kb
Host smart-e0251186-247b-4049-99ec-cad7b9fcee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268022563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4268022563
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3854893100
Short name T241
Test name
Test status
Simulation time 122751411 ps
CPU time 7.18 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:30 PM PDT 24
Peak memory 215920 kb
Host smart-b2e68101-c8d8-4569-9b7b-2532a0cda1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854893100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3854893100
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.151879631
Short name T8
Test name
Test status
Simulation time 62274682 ps
CPU time 2.65 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 222956 kb
Host smart-27859d72-71d5-4f6f-9c07-1e026c759055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151879631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.151879631
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3906495656
Short name T188
Test name
Test status
Simulation time 632818445 ps
CPU time 33.24 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 222584 kb
Host smart-9ad7d9dc-6814-4c66-89a3-75964ebdb804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906495656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3906495656
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1951040673
Short name T125
Test name
Test status
Simulation time 228659715 ps
CPU time 12.36 seconds
Started Jul 04 06:46:43 PM PDT 24
Finished Jul 04 06:46:55 PM PDT 24
Peak memory 214464 kb
Host smart-1e75e1a3-d716-4ba6-bced-2ba5dd577bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951040673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1951040673
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1183706868
Short name T12
Test name
Test status
Simulation time 132383523 ps
CPU time 4.23 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:18 PM PDT 24
Peak memory 220240 kb
Host smart-38fd087a-638e-40b3-90af-6fe318c73ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183706868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1183706868
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.803920193
Short name T104
Test name
Test status
Simulation time 164339072 ps
CPU time 6.17 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 213932 kb
Host smart-681d34d9-927a-4a92-8480-77ccda094d83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803920193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.803920193
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2409586274
Short name T397
Test name
Test status
Simulation time 7582609372 ps
CPU time 29.62 seconds
Started Jul 04 06:50:11 PM PDT 24
Finished Jul 04 06:50:41 PM PDT 24
Peak memory 215856 kb
Host smart-3df8c6ce-4376-424b-a5f1-0676a10eb606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409586274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2409586274
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1468758033
Short name T20
Test name
Test status
Simulation time 92536488 ps
CPU time 1.75 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:10 PM PDT 24
Peak memory 209616 kb
Host smart-4ca360bf-e4cd-4fa6-b491-7d8f2b0d9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468758033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1468758033
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.719246447
Short name T124
Test name
Test status
Simulation time 777975288 ps
CPU time 10.95 seconds
Started Jul 04 06:48:58 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 215908 kb
Host smart-22345fa1-a8fd-4408-a008-e47c34b265ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719246447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.719246447
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1350004762
Short name T52
Test name
Test status
Simulation time 724770468 ps
CPU time 35.36 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 222468 kb
Host smart-45c94390-6667-4553-8dd3-c5e4c9cfdff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350004762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1350004762
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1588713542
Short name T347
Test name
Test status
Simulation time 1121730182 ps
CPU time 10.06 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:51 PM PDT 24
Peak memory 215568 kb
Host smart-57a6d80e-4150-463b-ae54-fa8346d851d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588713542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1588713542
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.4083629566
Short name T167
Test name
Test status
Simulation time 2266312431 ps
CPU time 22.65 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:49:06 PM PDT 24
Peak memory 222624 kb
Host smart-6b5729ea-0473-4947-9c74-b0d22d5c65b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083629566 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.4083629566
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4244426432
Short name T40
Test name
Test status
Simulation time 55864639 ps
CPU time 2.49 seconds
Started Jul 04 06:47:21 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 210276 kb
Host smart-0f5433e1-4270-430c-afc8-24dd46f7c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244426432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4244426432
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2508551489
Short name T324
Test name
Test status
Simulation time 1995632400 ps
CPU time 110.83 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:47:52 PM PDT 24
Peak memory 219344 kb
Host smart-72ade3f4-43df-4f0c-8b6d-6852e056102c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508551489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2508551489
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1041315072
Short name T21
Test name
Test status
Simulation time 116154161 ps
CPU time 5.49 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 214360 kb
Host smart-144d188c-2c15-4bd6-9a26-6dbd6f08dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041315072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1041315072
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1067448694
Short name T37
Test name
Test status
Simulation time 120317135 ps
CPU time 4.38 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:46 PM PDT 24
Peak memory 209984 kb
Host smart-dcc44664-30e3-4e5e-8eac-965384e75c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067448694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1067448694
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1356922476
Short name T23
Test name
Test status
Simulation time 52198625 ps
CPU time 3.35 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:24 PM PDT 24
Peak memory 214352 kb
Host smart-9a9ad8e6-1093-43e6-830a-e2059426253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356922476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1356922476
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3291089917
Short name T213
Test name
Test status
Simulation time 816953896 ps
CPU time 40.21 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 222516 kb
Host smart-0ffb6d89-3d18-4d5d-874b-cc385a75c6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291089917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3291089917
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2346673956
Short name T346
Test name
Test status
Simulation time 910548214 ps
CPU time 12.79 seconds
Started Jul 04 06:46:31 PM PDT 24
Finished Jul 04 06:46:44 PM PDT 24
Peak memory 214768 kb
Host smart-10679f00-4262-4bbf-a11e-056411d7ab4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346673956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2346673956
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4040960533
Short name T51
Test name
Test status
Simulation time 1844235206 ps
CPU time 55.4 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:49:37 PM PDT 24
Peak memory 222500 kb
Host smart-839c076d-52a0-46ca-a4aa-b88fdeb15b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040960533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4040960533
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1001773900
Short name T137
Test name
Test status
Simulation time 321697828 ps
CPU time 5.77 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:18 PM PDT 24
Peak memory 222696 kb
Host smart-3caa720e-d598-42bb-9c01-cda8d87a44ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001773900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1001773900
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2855503114
Short name T546
Test name
Test status
Simulation time 263234649 ps
CPU time 5.38 seconds
Started Jul 04 06:47:29 PM PDT 24
Finished Jul 04 06:47:34 PM PDT 24
Peak memory 210244 kb
Host smart-0be8f5bb-1175-4157-8ed6-79439be64371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855503114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2855503114
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.893645891
Short name T118
Test name
Test status
Simulation time 1518782120 ps
CPU time 23.46 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:49:05 PM PDT 24
Peak memory 222628 kb
Host smart-3bf079fb-decf-442b-b511-91398d736b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893645891 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.893645891
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2618491494
Short name T233
Test name
Test status
Simulation time 156919760 ps
CPU time 8.43 seconds
Started Jul 04 06:46:38 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 215156 kb
Host smart-d8c569d8-f211-4af5-927d-596037e1fa2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618491494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2618491494
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1906301269
Short name T53
Test name
Test status
Simulation time 2726361799 ps
CPU time 61.34 seconds
Started Jul 04 06:48:47 PM PDT 24
Finished Jul 04 06:49:48 PM PDT 24
Peak memory 216908 kb
Host smart-c65d7eb6-8ac8-4a03-b7af-f478026cafe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906301269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1906301269
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1266000538
Short name T286
Test name
Test status
Simulation time 471526302 ps
CPU time 9.82 seconds
Started Jul 04 06:48:23 PM PDT 24
Finished Jul 04 06:48:33 PM PDT 24
Peak memory 214328 kb
Host smart-cd31d64d-992f-40ad-a158-c7810c389a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266000538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1266000538
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4236592002
Short name T96
Test name
Test status
Simulation time 12562331 ps
CPU time 0.99 seconds
Started Jul 04 06:47:45 PM PDT 24
Finished Jul 04 06:47:47 PM PDT 24
Peak memory 206032 kb
Host smart-e2dc7a21-62dd-4e5e-a86d-982969e78389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236592002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4236592002
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3533322606
Short name T150
Test name
Test status
Simulation time 908540456 ps
CPU time 6.67 seconds
Started Jul 04 05:07:23 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 205484 kb
Host smart-a4d05257-98ac-4665-b3dc-9bc9120a8fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533322606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3533322606
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2656812694
Short name T312
Test name
Test status
Simulation time 313231870 ps
CPU time 3.03 seconds
Started Jul 04 06:47:34 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 214284 kb
Host smart-7585f0fe-c672-4dce-b095-02e305658b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656812694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2656812694
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1974212389
Short name T101
Test name
Test status
Simulation time 122012722 ps
CPU time 2.67 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 214400 kb
Host smart-5e717889-9e19-4056-b1cc-d14fd4eea5b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974212389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1974212389
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2239203591
Short name T985
Test name
Test status
Simulation time 274775420 ps
CPU time 1.52 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 214068 kb
Host smart-41e93ffc-b727-4019-98bf-ea6fc34ab673
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239203591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2239203591
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3935383408
Short name T154
Test name
Test status
Simulation time 277204428 ps
CPU time 7.34 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:06:57 PM PDT 24
Peak memory 205760 kb
Host smart-5e6a8a6e-fa56-41fe-af63-34316dfd2160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935383408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3935383408
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2980365260
Short name T189
Test name
Test status
Simulation time 2009337656 ps
CPU time 51.7 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 215836 kb
Host smart-1930e06a-e64e-488f-bef0-dba12d810a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980365260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2980365260
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2784422057
Short name T64
Test name
Test status
Simulation time 401199008 ps
CPU time 2.38 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 209312 kb
Host smart-d110f0af-ddad-447f-bb7f-7166c0bc7a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784422057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2784422057
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2732024729
Short name T145
Test name
Test status
Simulation time 654190608 ps
CPU time 5.48 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 213596 kb
Host smart-f3c293e9-383c-4bb6-89ae-17305c7dbf11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732024729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2732024729
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1322947289
Short name T200
Test name
Test status
Simulation time 12471755494 ps
CPU time 373.28 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 216092 kb
Host smart-b13b5784-a44f-4aec-be88-7dbd95810fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322947289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1322947289
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2438088876
Short name T921
Test name
Test status
Simulation time 153514819 ps
CPU time 9.17 seconds
Started Jul 04 06:49:23 PM PDT 24
Finished Jul 04 06:49:32 PM PDT 24
Peak memory 214376 kb
Host smart-bb5e1b77-9033-481f-928f-c3b1a9574e77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438088876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2438088876
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3307902772
Short name T340
Test name
Test status
Simulation time 158088581 ps
CPU time 5.11 seconds
Started Jul 04 06:46:15 PM PDT 24
Finished Jul 04 06:46:21 PM PDT 24
Peak memory 214816 kb
Host smart-4a9c7726-5887-48f1-8e8c-ff81d2bcaa74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307902772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3307902772
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.812685318
Short name T143
Test name
Test status
Simulation time 1696421527 ps
CPU time 5.02 seconds
Started Jul 04 05:06:48 PM PDT 24
Finished Jul 04 05:06:54 PM PDT 24
Peak memory 213636 kb
Host smart-fecf4963-92ed-4204-bd95-9773188d9eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812685318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
812685318
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1277654287
Short name T61
Test name
Test status
Simulation time 34950724840 ps
CPU time 75.06 seconds
Started Jul 04 06:47:46 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 222584 kb
Host smart-f037bd09-e2af-48df-be79-e12510a1377c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277654287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1277654287
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1357189031
Short name T273
Test name
Test status
Simulation time 68946562 ps
CPU time 2.2 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:44 PM PDT 24
Peak memory 214372 kb
Host smart-4f9b2000-042e-4e99-9017-62e5362c4c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357189031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1357189031
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2779437933
Short name T339
Test name
Test status
Simulation time 231238171 ps
CPU time 3.11 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 208672 kb
Host smart-7289696f-6a56-4d0a-9642-f82b602abed3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779437933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2779437933
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3070422448
Short name T83
Test name
Test status
Simulation time 314857680 ps
CPU time 8.35 seconds
Started Jul 04 06:47:05 PM PDT 24
Finished Jul 04 06:47:13 PM PDT 24
Peak memory 214360 kb
Host smart-ac4a4407-29ca-4516-a836-c07a48e3a96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070422448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3070422448
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1113121443
Short name T157
Test name
Test status
Simulation time 265321679 ps
CPU time 5.59 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:16 PM PDT 24
Peak memory 213520 kb
Host smart-aaff9abf-8fbf-4731-9b7f-b5c958215658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113121443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1113121443
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4203100758
Short name T159
Test name
Test status
Simulation time 375938499 ps
CPU time 5.4 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 213704 kb
Host smart-881f7911-ff68-4c7e-978e-a1d995ac097a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203100758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4203100758
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3361013625
Short name T166
Test name
Test status
Simulation time 1170598743 ps
CPU time 3.77 seconds
Started Jul 04 06:47:46 PM PDT 24
Finished Jul 04 06:47:50 PM PDT 24
Peak memory 215140 kb
Host smart-85502b00-ffb9-4a88-b105-3a61ae67ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361013625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3361013625
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4121646120
Short name T245
Test name
Test status
Simulation time 49147037 ps
CPU time 2.58 seconds
Started Jul 04 06:46:12 PM PDT 24
Finished Jul 04 06:46:14 PM PDT 24
Peak memory 214264 kb
Host smart-a7e168a5-cbca-4532-ba0e-2c2752e19ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121646120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4121646120
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1926052982
Short name T26
Test name
Test status
Simulation time 59277026 ps
CPU time 2.73 seconds
Started Jul 04 06:47:29 PM PDT 24
Finished Jul 04 06:47:32 PM PDT 24
Peak memory 219992 kb
Host smart-67e2a679-0cd7-4e60-b276-fe8376cdfa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926052982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1926052982
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4182785507
Short name T389
Test name
Test status
Simulation time 143260740 ps
CPU time 2.2 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:43 PM PDT 24
Peak memory 210536 kb
Host smart-bf07215a-f570-4e98-a14c-f2e44a874fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182785507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4182785507
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.965793855
Short name T108
Test name
Test status
Simulation time 1271842323 ps
CPU time 13.25 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:49:03 PM PDT 24
Peak memory 214312 kb
Host smart-af431ee8-f491-440a-9466-07893f15f6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965793855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.965793855
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.528819361
Short name T72
Test name
Test status
Simulation time 3719949441 ps
CPU time 44.01 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 216304 kb
Host smart-a4b6d387-df7a-4419-8b1e-76ce439c47b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528819361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.528819361
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1956239899
Short name T56
Test name
Test status
Simulation time 52089894 ps
CPU time 2.75 seconds
Started Jul 04 06:49:40 PM PDT 24
Finished Jul 04 06:49:43 PM PDT 24
Peak memory 210392 kb
Host smart-8dc51683-e4b2-4eac-a1f2-2d5751156e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956239899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1956239899
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.324129534
Short name T139
Test name
Test status
Simulation time 548746876 ps
CPU time 5.56 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:39 PM PDT 24
Peak memory 218344 kb
Host smart-b867d01f-5268-4484-9c20-32bf2cade7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324129534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.324129534
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3165575754
Short name T140
Test name
Test status
Simulation time 38411883 ps
CPU time 1.91 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 215876 kb
Host smart-a457fd09-d4fe-43b7-a08e-eef2672a3d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165575754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3165575754
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2631137350
Short name T138
Test name
Test status
Simulation time 110215254 ps
CPU time 3.08 seconds
Started Jul 04 06:48:22 PM PDT 24
Finished Jul 04 06:48:25 PM PDT 24
Peak memory 222672 kb
Host smart-0ad932de-376e-4df2-a672-8e94b7a9eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631137350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2631137350
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.803280071
Short name T136
Test name
Test status
Simulation time 34664374 ps
CPU time 1.84 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 217740 kb
Host smart-2a6f653c-87b8-481a-be6c-0253a21fb3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803280071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.803280071
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2427103472
Short name T892
Test name
Test status
Simulation time 110753735 ps
CPU time 3.12 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 214328 kb
Host smart-e65b1e98-4f61-425c-b80e-71b49ccdd216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427103472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2427103472
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2687241889
Short name T657
Test name
Test status
Simulation time 652962875 ps
CPU time 4.34 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 208596 kb
Host smart-70baddf0-d2e5-4ea3-81ad-83d9e3126db9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687241889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2687241889
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.996132704
Short name T405
Test name
Test status
Simulation time 201788622 ps
CPU time 4.11 seconds
Started Jul 04 06:47:05 PM PDT 24
Finished Jul 04 06:47:09 PM PDT 24
Peak memory 214340 kb
Host smart-eaf6acaa-f93e-4840-b55e-e1aaeef4dd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996132704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.996132704
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3338343535
Short name T310
Test name
Test status
Simulation time 59953633 ps
CPU time 3.11 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 208544 kb
Host smart-d01c61a9-1bc6-4947-b1b6-7e9003fb11b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338343535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3338343535
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2563619596
Short name T35
Test name
Test status
Simulation time 162530392 ps
CPU time 2.63 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:48:46 PM PDT 24
Peak memory 222368 kb
Host smart-a133ec71-7917-4bb9-ae30-691ccf1ac76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563619596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2563619596
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3312180075
Short name T45
Test name
Test status
Simulation time 3285283110 ps
CPU time 77.8 seconds
Started Jul 04 06:46:32 PM PDT 24
Finished Jul 04 06:47:50 PM PDT 24
Peak memory 222616 kb
Host smart-8535957b-47a4-4009-ae1d-a920b1b93c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312180075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3312180075
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3645923052
Short name T185
Test name
Test status
Simulation time 469460265 ps
CPU time 6.43 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:49:03 PM PDT 24
Peak memory 222336 kb
Host smart-a855781b-5531-4efa-bbc3-f256f9b7172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645923052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3645923052
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3599310537
Short name T237
Test name
Test status
Simulation time 880257465 ps
CPU time 12.44 seconds
Started Jul 04 06:49:37 PM PDT 24
Finished Jul 04 06:49:49 PM PDT 24
Peak memory 216588 kb
Host smart-2a618c43-fda2-4f51-bf6b-a5fff0df5f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599310537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3599310537
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3232287605
Short name T314
Test name
Test status
Simulation time 33359952 ps
CPU time 2.34 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 214424 kb
Host smart-7fca4b97-8f21-4a25-934c-f8b7fc229e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232287605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3232287605
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3818974118
Short name T596
Test name
Test status
Simulation time 781236927 ps
CPU time 3.89 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 208836 kb
Host smart-b8ce6556-8a41-4233-9f9b-d318f0a0144b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818974118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3818974118
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3948749419
Short name T43
Test name
Test status
Simulation time 1081101221 ps
CPU time 14.2 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:21 PM PDT 24
Peak memory 235328 kb
Host smart-b8ee9c5a-f79d-4313-ad3e-fc569829b590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948749419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3948749419
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2039658351
Short name T151
Test name
Test status
Simulation time 117794656 ps
CPU time 3.82 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:49 PM PDT 24
Peak memory 213708 kb
Host smart-5c9b9a2a-b9fa-47a0-8edf-3ab433aeca87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039658351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2039658351
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.542297702
Short name T661
Test name
Test status
Simulation time 784987901 ps
CPU time 6.46 seconds
Started Jul 04 06:46:00 PM PDT 24
Finished Jul 04 06:46:07 PM PDT 24
Peak memory 208480 kb
Host smart-7a618597-645b-41e8-a86c-c27419a6a792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542297702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.542297702
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1281611018
Short name T87
Test name
Test status
Simulation time 126248220 ps
CPU time 5.23 seconds
Started Jul 04 06:46:12 PM PDT 24
Finished Jul 04 06:46:17 PM PDT 24
Peak memory 214272 kb
Host smart-f804077b-fbba-4259-86bb-fa83c71ea53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281611018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1281611018
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2306099459
Short name T813
Test name
Test status
Simulation time 363697336 ps
CPU time 4.74 seconds
Started Jul 04 06:46:08 PM PDT 24
Finished Jul 04 06:46:13 PM PDT 24
Peak memory 220620 kb
Host smart-008c6ed5-8762-49d4-91ce-5e76cec9c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306099459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2306099459
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1064945721
Short name T333
Test name
Test status
Simulation time 61816385 ps
CPU time 2.21 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 222348 kb
Host smart-7dc4c0ee-404d-4fc7-b9b1-928b042bbb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064945721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1064945721
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2068289814
Short name T224
Test name
Test status
Simulation time 177479409 ps
CPU time 2.87 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:16 PM PDT 24
Peak memory 214304 kb
Host smart-9da9c111-0da8-4b93-83ea-0bbfd0d7ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068289814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2068289814
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1227521202
Short name T196
Test name
Test status
Simulation time 90507341 ps
CPU time 4.19 seconds
Started Jul 04 06:47:21 PM PDT 24
Finished Jul 04 06:47:25 PM PDT 24
Peak memory 219292 kb
Host smart-9442b000-64dd-4590-8d04-049d802e6bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227521202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1227521202
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1958605369
Short name T565
Test name
Test status
Simulation time 148879982 ps
CPU time 3.69 seconds
Started Jul 04 06:47:40 PM PDT 24
Finished Jul 04 06:47:43 PM PDT 24
Peak memory 208460 kb
Host smart-17432718-e8e5-4325-8f19-537589db1f64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958605369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1958605369
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3365987204
Short name T208
Test name
Test status
Simulation time 3517695442 ps
CPU time 28.15 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:48:10 PM PDT 24
Peak memory 222600 kb
Host smart-26bbda84-4390-4bac-9a91-f0d204ca5eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365987204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3365987204
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.191484524
Short name T204
Test name
Test status
Simulation time 802298374 ps
CPU time 22.8 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:48:16 PM PDT 24
Peak memory 216004 kb
Host smart-57af66b1-1469-49c1-9685-f1753ba85d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191484524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.191484524
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.912112536
Short name T293
Test name
Test status
Simulation time 78075814 ps
CPU time 3.62 seconds
Started Jul 04 06:46:15 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 222368 kb
Host smart-5d726c7f-35b7-4db7-bcf5-86f7320facad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912112536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.912112536
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4040166245
Short name T172
Test name
Test status
Simulation time 531251404 ps
CPU time 18.29 seconds
Started Jul 04 06:46:22 PM PDT 24
Finished Jul 04 06:46:41 PM PDT 24
Peak memory 222588 kb
Host smart-c48d4ae0-94b5-43be-a41d-a6ec1b791a1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040166245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4040166245
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2601479965
Short name T257
Test name
Test status
Simulation time 97021742 ps
CPU time 2.36 seconds
Started Jul 04 06:48:07 PM PDT 24
Finished Jul 04 06:48:09 PM PDT 24
Peak memory 207980 kb
Host smart-a30d63ba-433b-467f-b00e-e040b42bf7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601479965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2601479965
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3880667093
Short name T839
Test name
Test status
Simulation time 206369058 ps
CPU time 11.47 seconds
Started Jul 04 06:48:38 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 215908 kb
Host smart-3de236b2-0c0b-495a-a7cf-da0bf759777d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880667093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3880667093
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3813177157
Short name T199
Test name
Test status
Simulation time 73233916 ps
CPU time 2.96 seconds
Started Jul 04 06:46:25 PM PDT 24
Finished Jul 04 06:46:28 PM PDT 24
Peak memory 214336 kb
Host smart-3c74766b-e2c1-49ca-bb86-a69a35d27ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813177157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3813177157
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4076358158
Short name T192
Test name
Test status
Simulation time 1158872808 ps
CPU time 6.47 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:43 PM PDT 24
Peak memory 209824 kb
Host smart-23ce65fa-675d-4433-a579-d594643cb0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076358158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4076358158
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1333476194
Short name T318
Test name
Test status
Simulation time 70475027566 ps
CPU time 392.31 seconds
Started Jul 04 06:46:32 PM PDT 24
Finished Jul 04 06:53:05 PM PDT 24
Peak memory 222500 kb
Host smart-0076791c-ff9b-40c9-ac2e-13e598dac9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333476194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1333476194
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.157883498
Short name T65
Test name
Test status
Simulation time 706502040 ps
CPU time 3.87 seconds
Started Jul 04 06:49:40 PM PDT 24
Finished Jul 04 06:49:45 PM PDT 24
Peak memory 214708 kb
Host smart-0ed3575c-f827-4f97-b8d8-01281ba42b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157883498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.157883498
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_random.278903489
Short name T252
Test name
Test status
Simulation time 358053700 ps
CPU time 3.76 seconds
Started Jul 04 06:49:42 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 207628 kb
Host smart-7d38629a-869c-478d-af2f-404c87a96b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278903489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.278903489
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.5579218
Short name T974
Test name
Test status
Simulation time 1494465129 ps
CPU time 9.54 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:55 PM PDT 24
Peak memory 205468 kb
Host smart-b36363fa-1539-4522-9ec8-76e2cbd8e314
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5579218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.5579218
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1331088922
Short name T960
Test name
Test status
Simulation time 3312001485 ps
CPU time 8.85 seconds
Started Jul 04 05:06:43 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205584 kb
Host smart-320ff9cd-f17c-4dcd-aaa8-0dce6c5d3fa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331088922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
331088922
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2959842549
Short name T944
Test name
Test status
Simulation time 50144601 ps
CPU time 1.12 seconds
Started Jul 04 05:06:42 PM PDT 24
Finished Jul 04 05:06:43 PM PDT 24
Peak memory 205564 kb
Host smart-399bd3b9-4427-425b-9ac8-f016da2891e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959842549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
959842549
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3747413964
Short name T1063
Test name
Test status
Simulation time 121948461 ps
CPU time 1.95 seconds
Started Jul 04 05:06:42 PM PDT 24
Finished Jul 04 05:06:44 PM PDT 24
Peak memory 213780 kb
Host smart-c4f0f495-4fe7-4b84-abe7-1caaddc4a77b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747413964 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3747413964
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3451086100
Short name T1076
Test name
Test status
Simulation time 71828766 ps
CPU time 0.94 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 205344 kb
Host smart-41ccea43-9d87-4a10-8706-7f678740ef7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451086100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3451086100
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3655967387
Short name T929
Test name
Test status
Simulation time 45685633 ps
CPU time 0.87 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:46 PM PDT 24
Peak memory 205324 kb
Host smart-41a5bb8d-2587-4bb2-9111-0ba5ffc5e161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655967387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3655967387
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1067576337
Short name T970
Test name
Test status
Simulation time 58998719 ps
CPU time 2.33 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 205520 kb
Host smart-1d314ded-436f-46f7-a222-a27d7f2e3207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067576337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1067576337
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3000388699
Short name T967
Test name
Test status
Simulation time 232677795 ps
CPU time 7.34 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:51 PM PDT 24
Peak memory 213920 kb
Host smart-eaa04927-0e86-4248-b34f-a05f1306cb67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000388699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3000388699
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3582739054
Short name T954
Test name
Test status
Simulation time 50365783 ps
CPU time 3.1 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:48 PM PDT 24
Peak memory 213684 kb
Host smart-2116ba55-75d3-451f-8122-2cf0b72a5b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582739054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3582739054
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1029906146
Short name T147
Test name
Test status
Simulation time 194309957 ps
CPU time 3 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 213700 kb
Host smart-01148e50-80bb-4135-b5a7-fb0891841b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029906146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1029906146
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1019607815
Short name T966
Test name
Test status
Simulation time 146504475 ps
CPU time 9.28 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:55 PM PDT 24
Peak memory 205572 kb
Host smart-80278e6b-bbc1-4979-8fec-308be51a475d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019607815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
019607815
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3545483075
Short name T976
Test name
Test status
Simulation time 1813732877 ps
CPU time 23.76 seconds
Started Jul 04 05:06:42 PM PDT 24
Finished Jul 04 05:07:06 PM PDT 24
Peak memory 205524 kb
Host smart-6efa1609-be8b-444a-9dd1-f00a57515201
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545483075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
545483075
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2945594374
Short name T993
Test name
Test status
Simulation time 138485859 ps
CPU time 1.43 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:46 PM PDT 24
Peak memory 205500 kb
Host smart-de937e25-7365-4ec4-8e98-a3819e6704a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945594374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
945594374
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3759919986
Short name T1060
Test name
Test status
Simulation time 49388043 ps
CPU time 1.38 seconds
Started Jul 04 05:06:51 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 213780 kb
Host smart-81984ce9-ae89-443f-8a7e-6626976986cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759919986 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3759919986
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3015833435
Short name T1073
Test name
Test status
Simulation time 27977327 ps
CPU time 1.11 seconds
Started Jul 04 05:06:43 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 205504 kb
Host smart-bca5c170-06de-459a-9861-f5e9c6907747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015833435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3015833435
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1120267792
Short name T1088
Test name
Test status
Simulation time 8489004 ps
CPU time 0.73 seconds
Started Jul 04 05:06:43 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 205208 kb
Host smart-73a4f08c-812f-4fbb-b9db-ab46c265b1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120267792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1120267792
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.678272330
Short name T955
Test name
Test status
Simulation time 263191126 ps
CPU time 2.02 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:48 PM PDT 24
Peak memory 205448 kb
Host smart-073cb7d8-bb0f-450a-a066-499595be8d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678272330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.678272330
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4107379545
Short name T1075
Test name
Test status
Simulation time 206958048 ps
CPU time 5.18 seconds
Started Jul 04 05:06:44 PM PDT 24
Finished Jul 04 05:06:50 PM PDT 24
Peak memory 214004 kb
Host smart-ab3b5ed2-e837-4243-9d79-8a84155a7afe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107379545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4107379545
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1954217994
Short name T998
Test name
Test status
Simulation time 179458941 ps
CPU time 4.41 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:49 PM PDT 24
Peak memory 213952 kb
Host smart-e8275cd9-149f-4765-8336-ca4593f800f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954217994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1954217994
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.178059646
Short name T956
Test name
Test status
Simulation time 1830841276 ps
CPU time 4.24 seconds
Started Jul 04 05:06:45 PM PDT 24
Finished Jul 04 05:06:50 PM PDT 24
Peak memory 221764 kb
Host smart-954fd41c-060d-4618-8fb6-59642207229a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178059646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.178059646
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3750761164
Short name T938
Test name
Test status
Simulation time 31826266 ps
CPU time 2.33 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:06 PM PDT 24
Peak memory 213576 kb
Host smart-66650346-354f-48d7-9368-3fba15e54919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750761164 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3750761164
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2301955937
Short name T957
Test name
Test status
Simulation time 17729181 ps
CPU time 0.93 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 205468 kb
Host smart-f0841fa8-4720-40b1-999b-bf48988cd72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301955937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2301955937
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1231985739
Short name T1014
Test name
Test status
Simulation time 22087618 ps
CPU time 0.74 seconds
Started Jul 04 05:07:05 PM PDT 24
Finished Jul 04 05:07:06 PM PDT 24
Peak memory 205340 kb
Host smart-919ad964-169c-4081-b684-cb9b802b171c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231985739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1231985739
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2832778125
Short name T1062
Test name
Test status
Simulation time 46567773 ps
CPU time 2.15 seconds
Started Jul 04 05:07:06 PM PDT 24
Finished Jul 04 05:07:08 PM PDT 24
Peak memory 205588 kb
Host smart-424b9763-4a04-46e2-9d7d-f41d811be18c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832778125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2832778125
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3077581557
Short name T1070
Test name
Test status
Simulation time 65435894 ps
CPU time 1.78 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 213948 kb
Host smart-864d8f45-77a5-4886-a73f-08bfb01a3d5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077581557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3077581557
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.626547289
Short name T991
Test name
Test status
Simulation time 316338693 ps
CPU time 6.74 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:09 PM PDT 24
Peak memory 214016 kb
Host smart-ad216897-72c4-4ecc-9044-8f0a097bcaa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626547289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.626547289
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.770274227
Short name T1069
Test name
Test status
Simulation time 191890028 ps
CPU time 2.02 seconds
Started Jul 04 05:07:01 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 213616 kb
Host smart-97ae4fb9-3585-482b-a75c-4b15182e1eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770274227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.770274227
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3307829259
Short name T162
Test name
Test status
Simulation time 260844316 ps
CPU time 4.06 seconds
Started Jul 04 05:07:01 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205448 kb
Host smart-a1fc56bc-8fc0-4830-912f-c788c7f074ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307829259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3307829259
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2349952363
Short name T1054
Test name
Test status
Simulation time 17877355 ps
CPU time 1.07 seconds
Started Jul 04 05:07:01 PM PDT 24
Finished Jul 04 05:07:02 PM PDT 24
Peak memory 205432 kb
Host smart-1e3854fa-6dd5-4399-b4e4-47f0cf55d97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349952363 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2349952363
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3395958742
Short name T1079
Test name
Test status
Simulation time 232529963 ps
CPU time 1.27 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 205716 kb
Host smart-1dad75ab-ab89-4695-85c5-7edbe328abf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395958742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3395958742
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2265010261
Short name T1058
Test name
Test status
Simulation time 9634382 ps
CPU time 0.76 seconds
Started Jul 04 05:07:04 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205216 kb
Host smart-6f78a545-9373-4f46-b0ad-7736d77f1a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265010261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2265010261
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3687736534
Short name T1032
Test name
Test status
Simulation time 136187978 ps
CPU time 1.95 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205804 kb
Host smart-a78264c2-4640-4bfd-a355-1dab39a83285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687736534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3687736534
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3872632333
Short name T973
Test name
Test status
Simulation time 55051402 ps
CPU time 1.43 seconds
Started Jul 04 05:07:01 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 213816 kb
Host smart-02659533-8a87-4c1e-86f7-98cb3a486e76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872632333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3872632333
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3744242454
Short name T112
Test name
Test status
Simulation time 4620575665 ps
CPU time 8.77 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:11 PM PDT 24
Peak memory 214076 kb
Host smart-beea8397-d445-4e83-8508-bb4e1dadb622
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744242454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3744242454
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2562734213
Short name T1013
Test name
Test status
Simulation time 117467290 ps
CPU time 2.12 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 216084 kb
Host smart-697a16ba-98f3-4374-b44f-6638206a6a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562734213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2562734213
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3362315735
Short name T160
Test name
Test status
Simulation time 326185854 ps
CPU time 10.39 seconds
Started Jul 04 05:07:01 PM PDT 24
Finished Jul 04 05:07:12 PM PDT 24
Peak memory 205480 kb
Host smart-1f4d2226-46a6-4f54-a33a-a454b5cfa56e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362315735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3362315735
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.995622911
Short name T981
Test name
Test status
Simulation time 24720534 ps
CPU time 1.46 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 205484 kb
Host smart-56b80b87-4e9e-440c-a717-8adccb97c35b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995622911 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.995622911
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4259532391
Short name T1056
Test name
Test status
Simulation time 74195630 ps
CPU time 0.92 seconds
Started Jul 04 05:07:09 PM PDT 24
Finished Jul 04 05:07:11 PM PDT 24
Peak memory 205344 kb
Host smart-b64e84f9-93fd-4088-b6bf-99bf6aaa3a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259532391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4259532391
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1931515539
Short name T952
Test name
Test status
Simulation time 17059908 ps
CPU time 0.93 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:11 PM PDT 24
Peak memory 205388 kb
Host smart-ec721723-961f-446f-aca7-7b8376d0a3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931515539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1931515539
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4165902972
Short name T1072
Test name
Test status
Simulation time 266463822 ps
CPU time 2.54 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:15 PM PDT 24
Peak memory 205516 kb
Host smart-febafc36-b98a-4229-be9a-752700756f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165902972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4165902972
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.636368045
Short name T105
Test name
Test status
Simulation time 119269106 ps
CPU time 1.46 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 214080 kb
Host smart-bb3918f4-b5b3-4eef-baad-898fb7e012ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636368045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.636368045
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1448686391
Short name T1027
Test name
Test status
Simulation time 376974760 ps
CPU time 13.98 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:17 PM PDT 24
Peak memory 213820 kb
Host smart-1167e5ec-f341-4c32-9a7e-3627f16102fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448686391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1448686391
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1000426026
Short name T984
Test name
Test status
Simulation time 1173414209 ps
CPU time 2.83 seconds
Started Jul 04 05:07:05 PM PDT 24
Finished Jul 04 05:07:08 PM PDT 24
Peak memory 213496 kb
Host smart-9f147940-918f-402a-aab5-f6c545f43739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000426026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1000426026
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.134843440
Short name T149
Test name
Test status
Simulation time 500690552 ps
CPU time 5.8 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:17 PM PDT 24
Peak memory 213612 kb
Host smart-3f947e07-d045-46a6-8682-adef6e686991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134843440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.134843440
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3878012908
Short name T371
Test name
Test status
Simulation time 36951147 ps
CPU time 1.59 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:12 PM PDT 24
Peak memory 205316 kb
Host smart-66af2952-eaf2-4539-a7f8-293075be7e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878012908 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3878012908
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3822475463
Short name T983
Test name
Test status
Simulation time 52258960 ps
CPU time 1 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 205352 kb
Host smart-4372b35e-9247-4c88-a8f6-4000b0f33be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822475463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3822475463
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2131763299
Short name T988
Test name
Test status
Simulation time 39392797 ps
CPU time 0.8 seconds
Started Jul 04 05:07:09 PM PDT 24
Finished Jul 04 05:07:10 PM PDT 24
Peak memory 205248 kb
Host smart-5aae1113-5f68-40e7-99e7-93e9fc377a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131763299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2131763299
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3438186690
Short name T130
Test name
Test status
Simulation time 44036982 ps
CPU time 1.75 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 205472 kb
Host smart-05bb840a-1d33-48e8-96b1-45ca040add3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438186690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3438186690
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3992813234
Short name T969
Test name
Test status
Simulation time 571099820 ps
CPU time 1.85 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 213940 kb
Host smart-fdcb2c31-60d8-4705-8735-376c4afda4a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992813234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3992813234
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1091165471
Short name T964
Test name
Test status
Simulation time 1688323041 ps
CPU time 7.51 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:20 PM PDT 24
Peak memory 213944 kb
Host smart-dc2e65d6-72c3-4c01-97ef-d11b28e6c407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091165471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1091165471
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1473813946
Short name T965
Test name
Test status
Simulation time 52395938 ps
CPU time 1.66 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 214744 kb
Host smart-4a5e0dcd-3675-4c18-9a87-286b8d907a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473813946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1473813946
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.803854118
Short name T1034
Test name
Test status
Simulation time 115255955 ps
CPU time 3.95 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:15 PM PDT 24
Peak memory 213636 kb
Host smart-9f1caead-302a-4a06-9c14-d7ce6fb7395b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803854118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.803854118
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2332807748
Short name T1009
Test name
Test status
Simulation time 91717901 ps
CPU time 1.54 seconds
Started Jul 04 05:07:09 PM PDT 24
Finished Jul 04 05:07:11 PM PDT 24
Peak memory 213728 kb
Host smart-4d6361da-7153-4593-82a3-2d2c305f2f56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332807748 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2332807748
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3848603705
Short name T1065
Test name
Test status
Simulation time 100204817 ps
CPU time 1.47 seconds
Started Jul 04 05:07:09 PM PDT 24
Finished Jul 04 05:07:11 PM PDT 24
Peak memory 205468 kb
Host smart-120e820f-824b-420d-ad8a-330d2459a78b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848603705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3848603705
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2678493692
Short name T1024
Test name
Test status
Simulation time 10030605 ps
CPU time 0.83 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 205180 kb
Host smart-9a4c63dd-d024-4561-b032-40b703f47c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678493692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2678493692
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3794914065
Short name T995
Test name
Test status
Simulation time 60549005 ps
CPU time 2.05 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 205464 kb
Host smart-94026d01-0670-4ada-ad6a-721f35ffe578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794914065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3794914065
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2559557388
Short name T1080
Test name
Test status
Simulation time 400704749 ps
CPU time 4.06 seconds
Started Jul 04 05:07:09 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 213796 kb
Host smart-c676b176-2678-4acb-b6a2-b7217c9b841a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559557388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2559557388
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.485881771
Short name T996
Test name
Test status
Simulation time 87207815 ps
CPU time 4.85 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:17 PM PDT 24
Peak memory 222196 kb
Host smart-cf287f29-63c0-4495-8ad2-ea928227f355
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485881771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.485881771
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2957132964
Short name T941
Test name
Test status
Simulation time 317494326 ps
CPU time 2.25 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 213520 kb
Host smart-3a50c89f-4dfd-4401-aeb8-0a19454e1f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957132964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2957132964
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.228344676
Short name T1017
Test name
Test status
Simulation time 31381344 ps
CPU time 1.44 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 205304 kb
Host smart-371730c0-447e-4089-8bb9-04bccde41d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228344676 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.228344676
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.895979570
Short name T1004
Test name
Test status
Simulation time 13452443 ps
CPU time 0.99 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:12 PM PDT 24
Peak memory 205216 kb
Host smart-466cb76c-fcbc-407f-b1ab-ffc32791a76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895979570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.895979570
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1013307475
Short name T940
Test name
Test status
Simulation time 25581796 ps
CPU time 0.74 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:12 PM PDT 24
Peak memory 205320 kb
Host smart-171e1e3e-8144-4af5-a2ce-154f74bbbbb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013307475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1013307475
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1848052297
Short name T127
Test name
Test status
Simulation time 70796205 ps
CPU time 2.83 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:15 PM PDT 24
Peak memory 205396 kb
Host smart-24cd4d79-fe00-47db-b2f0-d8f8f8f9ae84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848052297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1848052297
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.556007471
Short name T1006
Test name
Test status
Simulation time 316394826 ps
CPU time 2.01 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 213928 kb
Host smart-e73eb00e-90a8-4ccc-9cc1-8d6430673313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556007471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.556007471
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.702359145
Short name T111
Test name
Test status
Simulation time 174123471 ps
CPU time 5.04 seconds
Started Jul 04 05:07:11 PM PDT 24
Finished Jul 04 05:07:16 PM PDT 24
Peak memory 220568 kb
Host smart-e347a408-d662-4d05-8f64-69cb36c21d2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702359145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.702359145
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.577739104
Short name T926
Test name
Test status
Simulation time 762992956 ps
CPU time 3 seconds
Started Jul 04 05:07:10 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 213736 kb
Host smart-4c3854d6-9fd8-4fa2-bb09-fb45ddd60958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577739104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.577739104
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1836789490
Short name T156
Test name
Test status
Simulation time 273465934 ps
CPU time 5.22 seconds
Started Jul 04 05:07:12 PM PDT 24
Finished Jul 04 05:07:18 PM PDT 24
Peak memory 213624 kb
Host smart-baa70a8d-0f49-46b6-80fa-98e8f71dd7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836789490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1836789490
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.575244658
Short name T1041
Test name
Test status
Simulation time 102192548 ps
CPU time 2.03 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 213792 kb
Host smart-e435811a-a7a8-47dc-aa26-16a29f410421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575244658 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.575244658
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1705145293
Short name T1044
Test name
Test status
Simulation time 11707364 ps
CPU time 1.03 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205440 kb
Host smart-6abae004-ebc9-4662-912e-fcd757dabfc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705145293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1705145293
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.612848420
Short name T1038
Test name
Test status
Simulation time 49337621 ps
CPU time 0.75 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205168 kb
Host smart-afa42309-6443-4f8d-8a25-cffffd22df48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612848420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.612848420
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2640642513
Short name T133
Test name
Test status
Simulation time 266496888 ps
CPU time 2.53 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205512 kb
Host smart-520598dc-1d93-45bc-83d6-b73de6d9eeb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640642513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2640642513
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.665455135
Short name T1086
Test name
Test status
Simulation time 418677843 ps
CPU time 5.63 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 213948 kb
Host smart-9b14ba5e-5ef4-4131-b429-897af99008aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665455135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.665455135
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3770371044
Short name T113
Test name
Test status
Simulation time 597165896 ps
CPU time 7.64 seconds
Started Jul 04 05:07:16 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 220052 kb
Host smart-b5704c3f-f48c-4ee4-a6c7-8751ba230d50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770371044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3770371044
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.66482062
Short name T937
Test name
Test status
Simulation time 471475421 ps
CPU time 3.55 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:23 PM PDT 24
Peak memory 213556 kb
Host smart-18bdb786-5500-409e-b397-f415ef358f42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66482062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.66482062
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3334931503
Short name T153
Test name
Test status
Simulation time 516211151 ps
CPU time 9.95 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 214868 kb
Host smart-33c68a9c-cab2-4e1c-ab58-36ceb4b601fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334931503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3334931503
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2334068880
Short name T978
Test name
Test status
Simulation time 20918902 ps
CPU time 1.8 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 213860 kb
Host smart-061ea2e2-f2b1-4713-b9e0-db6fdd086d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334068880 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2334068880
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4132842305
Short name T1074
Test name
Test status
Simulation time 22368368 ps
CPU time 1.04 seconds
Started Jul 04 05:07:17 PM PDT 24
Finished Jul 04 05:07:18 PM PDT 24
Peak memory 205308 kb
Host smart-3527c84c-3136-4880-b94b-192a11814e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132842305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4132842305
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2708376043
Short name T1042
Test name
Test status
Simulation time 17178483 ps
CPU time 0.71 seconds
Started Jul 04 05:07:23 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 205292 kb
Host smart-d6f4f7f6-fcf2-400e-961c-1a17d98f1f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708376043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2708376043
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2887677033
Short name T132
Test name
Test status
Simulation time 90047717 ps
CPU time 1.73 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205440 kb
Host smart-302a8cd7-31a3-4aca-aaf4-2f7b9bce3dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887677033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2887677033
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.970088386
Short name T109
Test name
Test status
Simulation time 422611401 ps
CPU time 2.32 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 213820 kb
Host smart-58cf653b-f38d-4bc1-8c1e-09ecafb2f2de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970088386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.970088386
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.546812953
Short name T939
Test name
Test status
Simulation time 398262658 ps
CPU time 2.79 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 213684 kb
Host smart-87d159a3-2bd3-4be3-9bfa-75596168f0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546812953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.546812953
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.629484763
Short name T1037
Test name
Test status
Simulation time 15014984 ps
CPU time 1.19 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205556 kb
Host smart-2ffea877-791a-4d02-8190-ac94c0fae4ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629484763 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.629484763
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2045226070
Short name T1001
Test name
Test status
Simulation time 25263722 ps
CPU time 1.54 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205520 kb
Host smart-8478ea5a-aed6-4376-ba14-88c6f19b6919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045226070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2045226070
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3101900029
Short name T968
Test name
Test status
Simulation time 79397477 ps
CPU time 0.97 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:19 PM PDT 24
Peak memory 205152 kb
Host smart-c8040bd6-c89e-4893-98ee-cb610f997be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101900029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3101900029
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3991553551
Short name T128
Test name
Test status
Simulation time 359952049 ps
CPU time 2.65 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205540 kb
Host smart-b955ec44-77b4-4cc3-a578-caa59cd96a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991553551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3991553551
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1071583404
Short name T951
Test name
Test status
Simulation time 111284972 ps
CPU time 2.38 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 213948 kb
Host smart-8c02924c-8c3b-4008-b20d-3f474d840818
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071583404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1071583404
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2673460509
Short name T962
Test name
Test status
Simulation time 533594597 ps
CPU time 8.76 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 213920 kb
Host smart-3c43ca65-d78c-41cf-b83c-d3bf85da7ef7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673460509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2673460509
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3314964863
Short name T982
Test name
Test status
Simulation time 186113960 ps
CPU time 1.75 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:20 PM PDT 24
Peak memory 213632 kb
Host smart-35c6f336-9ed4-47d3-80a5-15dd1b756816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314964863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3314964863
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3524972746
Short name T165
Test name
Test status
Simulation time 293543278 ps
CPU time 11.15 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:32 PM PDT 24
Peak memory 213604 kb
Host smart-e9c4c58e-7d03-4ec0-ae85-80585f084ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524972746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3524972746
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1555248816
Short name T948
Test name
Test status
Simulation time 25776608 ps
CPU time 1.16 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205504 kb
Host smart-cccc4ebd-a4db-46c2-ac06-cc6c847051cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555248816 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1555248816
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1696079571
Short name T1081
Test name
Test status
Simulation time 15671995 ps
CPU time 1.08 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:23 PM PDT 24
Peak memory 205504 kb
Host smart-65705876-58a1-4c6b-a145-432c644ece33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696079571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1696079571
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4106024405
Short name T949
Test name
Test status
Simulation time 11551677 ps
CPU time 0.72 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205228 kb
Host smart-9a68be55-20d2-42bd-b195-1ba5878006fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106024405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4106024405
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2673869258
Short name T1061
Test name
Test status
Simulation time 39040772 ps
CPU time 2.6 seconds
Started Jul 04 05:07:17 PM PDT 24
Finished Jul 04 05:07:20 PM PDT 24
Peak memory 205536 kb
Host smart-a82c9a5e-7e8f-4099-8b11-67898f9a6b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673869258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2673869258
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.896679082
Short name T1021
Test name
Test status
Simulation time 467914184 ps
CPU time 2.53 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 214028 kb
Host smart-cd8c4fde-5123-4697-96ff-546f93911b36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896679082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.896679082
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3823948201
Short name T1050
Test name
Test status
Simulation time 373356342 ps
CPU time 9.28 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 213876 kb
Host smart-1887394f-bd15-48ef-b754-0a7d2d06729c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823948201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3823948201
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1427255594
Short name T1000
Test name
Test status
Simulation time 353233680 ps
CPU time 1.58 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 213696 kb
Host smart-87c2f790-ffbd-4654-b6db-6fdf4f2a7c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427255594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1427255594
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1867486642
Short name T1035
Test name
Test status
Simulation time 135594023 ps
CPU time 4.67 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:55 PM PDT 24
Peak memory 205448 kb
Host smart-fc7841cf-e6ca-469c-9886-211f2af3d1d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867486642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
867486642
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2256978965
Short name T946
Test name
Test status
Simulation time 2660303213 ps
CPU time 31.64 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205572 kb
Host smart-f6a9d2ad-8b69-4081-a6b4-1244b9d21c16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256978965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
256978965
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.104453351
Short name T1016
Test name
Test status
Simulation time 17635880 ps
CPU time 1.06 seconds
Started Jul 04 05:06:52 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205284 kb
Host smart-5c5effb5-a947-462d-8157-4d1885553894
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104453351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.104453351
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3712277480
Short name T1047
Test name
Test status
Simulation time 27364573 ps
CPU time 1.02 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:06:50 PM PDT 24
Peak memory 205536 kb
Host smart-40c8ae82-84f1-4712-a2d7-5e059996f7bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712277480 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3712277480
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3779939374
Short name T986
Test name
Test status
Simulation time 14670143 ps
CPU time 1.18 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:51 PM PDT 24
Peak memory 205376 kb
Host smart-f5673ab9-4c9a-4ba4-aed0-16149e293436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779939374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3779939374
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2482259095
Short name T980
Test name
Test status
Simulation time 15294662 ps
CPU time 0.75 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:51 PM PDT 24
Peak memory 205172 kb
Host smart-53de8fbf-65f5-4767-8b8c-14f232c208da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482259095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2482259095
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2188797345
Short name T1026
Test name
Test status
Simulation time 375863891 ps
CPU time 1.99 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205392 kb
Host smart-5d5765d8-41d9-4ed0-b6c1-080fa3a535bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188797345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2188797345
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2760251621
Short name T1033
Test name
Test status
Simulation time 216901403 ps
CPU time 1.43 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:52 PM PDT 24
Peak memory 214076 kb
Host smart-25880c02-7b92-47be-9d24-b606877a391d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760251621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2760251621
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.979195746
Short name T994
Test name
Test status
Simulation time 438949633 ps
CPU time 14.55 seconds
Started Jul 04 05:06:48 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 213960 kb
Host smart-35d16f12-b2c1-4eaf-ac91-7f4ec806fc20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979195746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.979195746
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2145161827
Short name T947
Test name
Test status
Simulation time 98877045 ps
CPU time 1.65 seconds
Started Jul 04 05:06:46 PM PDT 24
Finished Jul 04 05:06:48 PM PDT 24
Peak memory 213636 kb
Host smart-4f5f3ec0-e88d-435b-8e2a-3579d84d4ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145161827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2145161827
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2261133222
Short name T144
Test name
Test status
Simulation time 350923233 ps
CPU time 4.28 seconds
Started Jul 04 05:06:48 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205412 kb
Host smart-e7848c38-3a0f-40de-befe-3f252f1e7e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261133222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2261133222
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.811269676
Short name T1005
Test name
Test status
Simulation time 108283678 ps
CPU time 0.79 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205244 kb
Host smart-9c767f9b-7343-4283-b1ce-8e53d001a5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811269676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.811269676
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2238484134
Short name T1083
Test name
Test status
Simulation time 11657432 ps
CPU time 0.71 seconds
Started Jul 04 05:07:20 PM PDT 24
Finished Jul 04 05:07:21 PM PDT 24
Peak memory 205200 kb
Host smart-e81e221a-8dca-4a70-bc5f-e784d27d69a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238484134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2238484134
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3948091804
Short name T1015
Test name
Test status
Simulation time 14136592 ps
CPU time 0.67 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:19 PM PDT 24
Peak memory 205136 kb
Host smart-8ba68388-4ebc-421c-a186-b27752212f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948091804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3948091804
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4048497694
Short name T1029
Test name
Test status
Simulation time 14994824 ps
CPU time 0.93 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205292 kb
Host smart-7aedf6b7-4902-423d-b427-43a75f30ffbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048497694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4048497694
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.551102107
Short name T932
Test name
Test status
Simulation time 19707437 ps
CPU time 0.84 seconds
Started Jul 04 05:07:23 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 205216 kb
Host smart-3ed1d096-5348-4298-9fd2-680e752f7140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551102107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.551102107
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3244243371
Short name T934
Test name
Test status
Simulation time 17454930 ps
CPU time 0.75 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:20 PM PDT 24
Peak memory 205188 kb
Host smart-03abfb51-b14a-475d-b9ab-e4407714da5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244243371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3244243371
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2978255409
Short name T987
Test name
Test status
Simulation time 10423545 ps
CPU time 0.78 seconds
Started Jul 04 05:07:17 PM PDT 24
Finished Jul 04 05:07:18 PM PDT 24
Peak memory 205324 kb
Host smart-2ab8b998-4b35-4410-8aa1-f947e17c28b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978255409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2978255409
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1533169860
Short name T999
Test name
Test status
Simulation time 12061446 ps
CPU time 0.87 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205152 kb
Host smart-b0729550-447a-4076-82fa-9be65ae6e691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533169860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1533169860
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1218209385
Short name T931
Test name
Test status
Simulation time 11690681 ps
CPU time 0.72 seconds
Started Jul 04 05:07:19 PM PDT 24
Finished Jul 04 05:07:20 PM PDT 24
Peak memory 205148 kb
Host smart-c466cc75-4a37-4f20-8518-324b41361c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218209385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1218209385
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3264894797
Short name T1071
Test name
Test status
Simulation time 56439250 ps
CPU time 0.71 seconds
Started Jul 04 05:07:16 PM PDT 24
Finished Jul 04 05:07:17 PM PDT 24
Peak memory 205176 kb
Host smart-86249a07-c16c-4bf8-aa5c-b7f05efbf898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264894797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3264894797
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.794391794
Short name T1052
Test name
Test status
Simulation time 364416280 ps
CPU time 5.75 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 205408 kb
Host smart-40dd19d8-7b74-479c-983c-17ff4a51e81c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794391794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.794391794
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1084265153
Short name T971
Test name
Test status
Simulation time 1353861314 ps
CPU time 16.62 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:07:06 PM PDT 24
Peak memory 205432 kb
Host smart-9da81abb-f340-4ffc-810b-30b9b5ad11c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084265153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
084265153
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2829807160
Short name T945
Test name
Test status
Simulation time 14768391 ps
CPU time 1.05 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205412 kb
Host smart-bbf68a38-fe1f-48ff-9e82-0d3e0b605be5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829807160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
829807160
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3152235044
Short name T142
Test name
Test status
Simulation time 87545152 ps
CPU time 1.4 seconds
Started Jul 04 05:06:52 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 213564 kb
Host smart-27dcf8ac-8edb-40d5-a8e1-d972c4859ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152235044 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3152235044
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.147507187
Short name T126
Test name
Test status
Simulation time 13043061 ps
CPU time 1.08 seconds
Started Jul 04 05:06:52 PM PDT 24
Finished Jul 04 05:06:54 PM PDT 24
Peak memory 205344 kb
Host smart-41851b52-fd03-49bb-9e2f-83e7d06737e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147507187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.147507187
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3214043090
Short name T1049
Test name
Test status
Simulation time 14811685 ps
CPU time 0.71 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:51 PM PDT 24
Peak memory 205148 kb
Host smart-3836c7fe-0298-4a57-b22d-f2e1d8263ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214043090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3214043090
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4129869066
Short name T1085
Test name
Test status
Simulation time 260931735 ps
CPU time 2.72 seconds
Started Jul 04 05:06:51 PM PDT 24
Finished Jul 04 05:06:54 PM PDT 24
Peak memory 205364 kb
Host smart-95bee5bd-d14c-4f81-b892-c85864fe4d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129869066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4129869066
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1588770676
Short name T107
Test name
Test status
Simulation time 58593031 ps
CPU time 2.32 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 214000 kb
Host smart-6b4cfa63-1008-44c6-95dc-59a06429cdbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588770676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1588770676
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.840818549
Short name T997
Test name
Test status
Simulation time 1341954803 ps
CPU time 7.42 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 213900 kb
Host smart-621096ea-bed2-4c93-83dd-dfd718ef6762
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840818549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.840818549
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.54295440
Short name T1010
Test name
Test status
Simulation time 134658842 ps
CPU time 2.3 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 213560 kb
Host smart-4988f454-2e5a-42d6-8c0e-e08bef29adc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54295440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.54295440
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3813270021
Short name T933
Test name
Test status
Simulation time 12335799 ps
CPU time 0.73 seconds
Started Jul 04 05:07:18 PM PDT 24
Finished Jul 04 05:07:19 PM PDT 24
Peak memory 205172 kb
Host smart-90bd4bfb-c592-44b5-b540-c02fa9d3270a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813270021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3813270021
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1484955119
Short name T979
Test name
Test status
Simulation time 89323758 ps
CPU time 0.73 seconds
Started Jul 04 05:07:21 PM PDT 24
Finished Jul 04 05:07:22 PM PDT 24
Peak memory 205300 kb
Host smart-f71cd934-5987-4d7f-8061-e35b4fd7b056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484955119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1484955119
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1901430360
Short name T1039
Test name
Test status
Simulation time 11943344 ps
CPU time 0.91 seconds
Started Jul 04 05:07:24 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 205324 kb
Host smart-7a7c946c-b38e-4090-b4d9-ea0f67502b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901430360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1901430360
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.249635367
Short name T1051
Test name
Test status
Simulation time 13802749 ps
CPU time 0.75 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205312 kb
Host smart-79f2f9a2-ace6-49eb-87be-3d32c7da670f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249635367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.249635367
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.652118857
Short name T943
Test name
Test status
Simulation time 9334191 ps
CPU time 0.74 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 205148 kb
Host smart-2a213284-cc6c-4fd2-9ee2-fedd467f91eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652118857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.652118857
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2271390449
Short name T1031
Test name
Test status
Simulation time 9584197 ps
CPU time 0.73 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 205192 kb
Host smart-17329b0e-0cf4-4425-9757-b22160ebad8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271390449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2271390449
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1686423525
Short name T990
Test name
Test status
Simulation time 19913261 ps
CPU time 0.72 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 205152 kb
Host smart-6ad30bbc-662a-436c-a287-3767bce54d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686423525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1686423525
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3172345780
Short name T1067
Test name
Test status
Simulation time 14807984 ps
CPU time 0.7 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 205128 kb
Host smart-f799f519-976f-414d-9aea-d816d6de7d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172345780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3172345780
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.821174382
Short name T1020
Test name
Test status
Simulation time 34910780 ps
CPU time 0.69 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205328 kb
Host smart-00ce576f-c7fc-4328-88c6-7f4865fe0db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821174382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.821174382
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.488853238
Short name T1046
Test name
Test status
Simulation time 26874474 ps
CPU time 0.8 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205324 kb
Host smart-fe6e0088-9e79-45c5-9e07-dcd02159e8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488853238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.488853238
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.203018487
Short name T1022
Test name
Test status
Simulation time 1019053079 ps
CPU time 7.79 seconds
Started Jul 04 05:06:52 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 205528 kb
Host smart-97fced07-e6ca-4b45-a1e5-5a716ad06e09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203018487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.203018487
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3265355046
Short name T1025
Test name
Test status
Simulation time 667272785 ps
CPU time 9.84 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 205376 kb
Host smart-29701579-b0af-4fbd-a8a9-dc2db5e37eb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265355046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
265355046
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1408853365
Short name T959
Test name
Test status
Simulation time 151044224 ps
CPU time 1.19 seconds
Started Jul 04 05:06:51 PM PDT 24
Finished Jul 04 05:06:52 PM PDT 24
Peak memory 205492 kb
Host smart-9c38d329-1173-4fef-9eb4-f13df07fb238
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408853365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
408853365
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4152867898
Short name T953
Test name
Test status
Simulation time 93595205 ps
CPU time 2.11 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 213684 kb
Host smart-28269724-2148-4779-a8d3-4f107441f2f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152867898 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4152867898
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3672298892
Short name T131
Test name
Test status
Simulation time 23089519 ps
CPU time 1.08 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:06:51 PM PDT 24
Peak memory 205480 kb
Host smart-b0fb1794-c2c5-4abe-95ab-c71f46568f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672298892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3672298892
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.38146534
Short name T928
Test name
Test status
Simulation time 36294568 ps
CPU time 0.75 seconds
Started Jul 04 05:06:52 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205148 kb
Host smart-63ebcb6d-dbd6-4e57-86a7-1b98019d878f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.38146534
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2541802900
Short name T961
Test name
Test status
Simulation time 57544181 ps
CPU time 1.62 seconds
Started Jul 04 05:06:51 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 205364 kb
Host smart-b70a5879-90ce-4ee2-8c67-1cbafb1bee71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541802900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2541802900
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4074830464
Short name T110
Test name
Test status
Simulation time 328936639 ps
CPU time 2.72 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 213980 kb
Host smart-5a54b8b9-075a-4300-a2ce-14aaeb86071d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074830464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.4074830464
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3518246578
Short name T1018
Test name
Test status
Simulation time 2240467984 ps
CPU time 13.38 seconds
Started Jul 04 05:06:50 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 214076 kb
Host smart-f1ec8632-78b8-4db4-994a-b140011647e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518246578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3518246578
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3087140735
Short name T942
Test name
Test status
Simulation time 164605399 ps
CPU time 4.43 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:06:54 PM PDT 24
Peak memory 213680 kb
Host smart-f716dd54-f2fe-4154-9559-8464b4dd59df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087140735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3087140735
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2014197772
Short name T1011
Test name
Test status
Simulation time 17501032 ps
CPU time 0.8 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 205320 kb
Host smart-7c144edc-b1e3-44b3-affb-c46fd5b16a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014197772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2014197772
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4278819540
Short name T1089
Test name
Test status
Simulation time 13989776 ps
CPU time 0.72 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205316 kb
Host smart-60edfac2-6e08-41b3-8942-862465ae7ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278819540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4278819540
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3343034687
Short name T930
Test name
Test status
Simulation time 16070542 ps
CPU time 0.93 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 205276 kb
Host smart-b8ee66e9-2654-487c-ab98-7265c9f9eb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343034687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3343034687
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2320536320
Short name T977
Test name
Test status
Simulation time 11254121 ps
CPU time 0.72 seconds
Started Jul 04 05:07:24 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 205224 kb
Host smart-c5bbd53c-122f-461e-b669-1d0116cff44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320536320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2320536320
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1328899184
Short name T1087
Test name
Test status
Simulation time 13289672 ps
CPU time 0.77 seconds
Started Jul 04 05:07:24 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 205112 kb
Host smart-ef478a97-4a00-46ca-bd16-4475f96535d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328899184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1328899184
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1273907042
Short name T935
Test name
Test status
Simulation time 38732608 ps
CPU time 0.71 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205248 kb
Host smart-81ab4e68-a084-4319-9065-a0ace8cde533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273907042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1273907042
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2715114740
Short name T927
Test name
Test status
Simulation time 24321529 ps
CPU time 0.78 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 205172 kb
Host smart-6f971d09-2928-4f72-836c-b18132ac1294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715114740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2715114740
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.138711986
Short name T963
Test name
Test status
Simulation time 35528715 ps
CPU time 0.82 seconds
Started Jul 04 05:07:24 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 205224 kb
Host smart-131253f8-58a1-45b7-8663-0e7b830cbb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138711986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.138711986
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.392152637
Short name T1007
Test name
Test status
Simulation time 18680159 ps
CPU time 0.85 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 205180 kb
Host smart-d292dd2c-005a-41b9-92de-7291034e22c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392152637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.392152637
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.891008725
Short name T1068
Test name
Test status
Simulation time 9323576 ps
CPU time 0.73 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 205252 kb
Host smart-155368eb-c011-4835-b435-c14872905d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891008725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.891008725
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4253054337
Short name T1040
Test name
Test status
Simulation time 86214990 ps
CPU time 1.54 seconds
Started Jul 04 05:06:59 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 213760 kb
Host smart-0c42a070-0cf2-4291-be80-79661e1c5198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253054337 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4253054337
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.778684717
Short name T370
Test name
Test status
Simulation time 114108310 ps
CPU time 1.02 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 205404 kb
Host smart-ff637863-6d9b-4f7e-8677-0303b705ceae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778684717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.778684717
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3759317512
Short name T1030
Test name
Test status
Simulation time 9091262 ps
CPU time 0.84 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 205160 kb
Host smart-32858a5a-5246-4642-b0ba-5594fe6adbf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759317512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3759317512
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4130125761
Short name T129
Test name
Test status
Simulation time 77774445 ps
CPU time 1.7 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 205512 kb
Host smart-aedde93b-3380-4e37-a8e6-98183b783518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130125761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4130125761
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2953324418
Short name T1043
Test name
Test status
Simulation time 134918321 ps
CPU time 2.88 seconds
Started Jul 04 05:06:49 PM PDT 24
Finished Jul 04 05:06:52 PM PDT 24
Peak memory 214008 kb
Host smart-31e32173-150a-4b09-a10e-ea1ff419e0bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953324418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2953324418
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.334740212
Short name T1019
Test name
Test status
Simulation time 1403430258 ps
CPU time 9.43 seconds
Started Jul 04 05:06:59 PM PDT 24
Finished Jul 04 05:07:09 PM PDT 24
Peak memory 213932 kb
Host smart-bdf43798-6ead-4fbb-a8cb-5d166301019b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334740212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.334740212
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1298910653
Short name T174
Test name
Test status
Simulation time 123731112 ps
CPU time 4.19 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 213776 kb
Host smart-d57f24cc-8bc1-4b3e-92ee-df906f13f4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298910653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1298910653
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3338569094
Short name T1057
Test name
Test status
Simulation time 124585611 ps
CPU time 1.27 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205396 kb
Host smart-523c0c5c-a6c7-45b4-a70d-69d55f95a062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338569094 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3338569094
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1024542679
Short name T1023
Test name
Test status
Simulation time 48892227 ps
CPU time 1 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205260 kb
Host smart-d535b84e-967e-41a7-b247-1efe6c7221c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024542679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1024542679
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3020218142
Short name T936
Test name
Test status
Simulation time 31857754 ps
CPU time 0.83 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205312 kb
Host smart-79878831-0c85-4d68-9a4f-cbb827ab89b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020218142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3020218142
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1085836369
Short name T1003
Test name
Test status
Simulation time 1165558725 ps
CPU time 4 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:07 PM PDT 24
Peak memory 205384 kb
Host smart-2d79a0a8-48cd-48bd-ac2f-0c5c2ada725f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085836369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1085836369
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3897946034
Short name T1055
Test name
Test status
Simulation time 280939682 ps
CPU time 3 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 214064 kb
Host smart-f119cbae-bbb9-4947-a3dd-7cba252c8e13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897946034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3897946034
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.834014889
Short name T1077
Test name
Test status
Simulation time 533383698 ps
CPU time 16.77 seconds
Started Jul 04 05:06:59 PM PDT 24
Finished Jul 04 05:07:17 PM PDT 24
Peak memory 213916 kb
Host smart-c4969e42-4c78-4832-8768-f5554e336e56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834014889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.834014889
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2392978923
Short name T1053
Test name
Test status
Simulation time 124480201 ps
CPU time 4.49 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 215784 kb
Host smart-127ae034-5767-4863-94c4-bba79262a39c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392978923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2392978923
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.517028588
Short name T155
Test name
Test status
Simulation time 429773890 ps
CPU time 3.34 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 205908 kb
Host smart-bd108a98-91e7-4bb4-b843-784854a88b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517028588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
517028588
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1601177521
Short name T958
Test name
Test status
Simulation time 17766101 ps
CPU time 1.61 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 213760 kb
Host smart-5abd76f0-7d1c-455f-9f93-b0c5272969fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601177521 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1601177521
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2472760758
Short name T975
Test name
Test status
Simulation time 27181711 ps
CPU time 1.21 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205452 kb
Host smart-60c05950-80c4-474e-a922-b649ad51809c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472760758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2472760758
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3925780025
Short name T1048
Test name
Test status
Simulation time 33598983 ps
CPU time 0.72 seconds
Started Jul 04 05:06:59 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 205136 kb
Host smart-a7c6a549-4d70-497a-8c01-d34769844dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925780025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3925780025
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.888214949
Short name T992
Test name
Test status
Simulation time 89196544 ps
CPU time 2.46 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205488 kb
Host smart-a3249bd0-17f5-4822-96e9-2893aaf658d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888214949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.888214949
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3715263375
Short name T103
Test name
Test status
Simulation time 70449996 ps
CPU time 2.86 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 214024 kb
Host smart-1e47ec7a-9075-4ae2-ba18-ce31df738df0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715263375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3715263375
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1629572315
Short name T1008
Test name
Test status
Simulation time 77873372 ps
CPU time 4.3 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 213944 kb
Host smart-833ee3ee-a4fd-432c-ab77-a08b63e6a129
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629572315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1629572315
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4162319485
Short name T1084
Test name
Test status
Simulation time 63098580 ps
CPU time 1.8 seconds
Started Jul 04 05:07:02 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 215748 kb
Host smart-2778f096-98b5-4d15-b3e7-67429c67efca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162319485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4162319485
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3475144671
Short name T164
Test name
Test status
Simulation time 169887524 ps
CPU time 4.74 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 215068 kb
Host smart-0a398b27-151a-41b6-878f-4c9e383648a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475144671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3475144671
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.89340390
Short name T1066
Test name
Test status
Simulation time 253484276 ps
CPU time 2.4 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 213804 kb
Host smart-10436df3-67e0-4fbe-ad3b-b3ed5ee9a9e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89340390 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.89340390
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2956720128
Short name T1002
Test name
Test status
Simulation time 63149117 ps
CPU time 0.95 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 205296 kb
Host smart-1cd320e8-046b-488d-87cc-170fd98089ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956720128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2956720128
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2402305315
Short name T1064
Test name
Test status
Simulation time 53127544 ps
CPU time 0.67 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:57 PM PDT 24
Peak memory 205312 kb
Host smart-fd8991b4-c816-40c2-b8c9-d6d29068f1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402305315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2402305315
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.946731378
Short name T1078
Test name
Test status
Simulation time 72209502 ps
CPU time 2 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 205512 kb
Host smart-e999ef9d-e76b-405f-959a-48616623b973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946731378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.946731378
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1611549688
Short name T972
Test name
Test status
Simulation time 1739892776 ps
CPU time 9.2 seconds
Started Jul 04 05:06:57 PM PDT 24
Finished Jul 04 05:07:07 PM PDT 24
Peak memory 213952 kb
Host smart-efb2a274-0d04-4d99-a66f-739c05892d5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611549688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1611549688
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3671050673
Short name T1045
Test name
Test status
Simulation time 286794430 ps
CPU time 2.78 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 213760 kb
Host smart-25519eea-2f65-4076-bc50-c6266cd058b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671050673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3671050673
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1464950410
Short name T146
Test name
Test status
Simulation time 666147257 ps
CPU time 3.25 seconds
Started Jul 04 05:06:59 PM PDT 24
Finished Jul 04 05:07:02 PM PDT 24
Peak memory 213748 kb
Host smart-2dbad02d-3b79-4acc-a16c-d71dcbc1553e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464950410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1464950410
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.387481167
Short name T372
Test name
Test status
Simulation time 87888530 ps
CPU time 1.15 seconds
Started Jul 04 05:07:04 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205556 kb
Host smart-38c626d9-b9c5-47f5-abea-23a1e986724d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387481167 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.387481167
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3698744322
Short name T1028
Test name
Test status
Simulation time 11691299 ps
CPU time 1.21 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 205392 kb
Host smart-7fe47e10-1c74-4247-ac6e-da876bdff2a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698744322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3698744322
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2294592793
Short name T1059
Test name
Test status
Simulation time 9673187 ps
CPU time 0.8 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 205144 kb
Host smart-70ae9c2e-94c3-436c-86f4-4fab6b1a113a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294592793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2294592793
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4027544792
Short name T1082
Test name
Test status
Simulation time 72508996 ps
CPU time 2.06 seconds
Started Jul 04 05:07:05 PM PDT 24
Finished Jul 04 05:07:07 PM PDT 24
Peak memory 205444 kb
Host smart-6479f2d8-695e-47b1-a5c3-bc5af8c53a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027544792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4027544792
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3892773801
Short name T989
Test name
Test status
Simulation time 60036109 ps
CPU time 1.26 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 213904 kb
Host smart-bf9f087e-f772-46e5-b021-e254c0dda229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892773801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3892773801
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2555644074
Short name T1012
Test name
Test status
Simulation time 339460879 ps
CPU time 7.57 seconds
Started Jul 04 05:06:56 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 213944 kb
Host smart-e035a87b-3b88-4584-bbec-8117bc7143a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555644074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2555644074
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.857851587
Short name T950
Test name
Test status
Simulation time 288928030 ps
CPU time 3.7 seconds
Started Jul 04 05:07:03 PM PDT 24
Finished Jul 04 05:07:07 PM PDT 24
Peak memory 216832 kb
Host smart-5dad9fd3-19c1-4f04-8eec-df44be7ccfae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857851587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.857851587
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.478129171
Short name T1036
Test name
Test status
Simulation time 258759282 ps
CPU time 6.84 seconds
Started Jul 04 05:06:58 PM PDT 24
Finished Jul 04 05:07:05 PM PDT 24
Peak memory 213592 kb
Host smart-d239a478-e6a7-4266-a5ef-e52e73ccbcaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478129171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
478129171
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4126587493
Short name T783
Test name
Test status
Simulation time 130115175 ps
CPU time 0.8 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 206036 kb
Host smart-c7a6bb1e-69cf-4e7f-927e-0ea20068a8c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126587493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4126587493
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.443722107
Short name T38
Test name
Test status
Simulation time 1683181195 ps
CPU time 7 seconds
Started Jul 04 06:46:03 PM PDT 24
Finished Jul 04 06:46:10 PM PDT 24
Peak memory 210196 kb
Host smart-6ba0505d-c959-4c54-a77e-d7100ac0fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443722107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.443722107
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3781623460
Short name T336
Test name
Test status
Simulation time 244662262 ps
CPU time 3.47 seconds
Started Jul 04 06:46:00 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 210292 kb
Host smart-073f51df-0b5c-41a7-b1b4-d0804a31c931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781623460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3781623460
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2942496457
Short name T824
Test name
Test status
Simulation time 90591321 ps
CPU time 4.6 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:04 PM PDT 24
Peak memory 222340 kb
Host smart-c3e013b7-e2c3-4d46-91bb-22346c0d8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942496457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2942496457
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2085408396
Short name T190
Test name
Test status
Simulation time 42903241 ps
CPU time 2.24 seconds
Started Jul 04 06:46:00 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 220032 kb
Host smart-72cbd33f-f8c7-4c2f-b904-52c8c207aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085408396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2085408396
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1230542231
Short name T644
Test name
Test status
Simulation time 119398927 ps
CPU time 3.17 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 207532 kb
Host smart-9baa94e9-7462-4670-af54-9a36fbd0d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230542231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1230542231
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1664396704
Short name T820
Test name
Test status
Simulation time 484733651 ps
CPU time 13.56 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:13 PM PDT 24
Peak memory 208000 kb
Host smart-d0d9c907-e9fe-4471-939f-4195a0ce363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664396704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1664396704
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1751527414
Short name T792
Test name
Test status
Simulation time 135580274 ps
CPU time 4.29 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 208404 kb
Host smart-6f8c1eef-8d8a-4a41-9259-53649bce9450
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751527414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1751527414
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2019658876
Short name T463
Test name
Test status
Simulation time 439790262 ps
CPU time 3.79 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 208600 kb
Host smart-240c13e5-eead-47bd-a02f-d15a1def8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019658876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2019658876
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3777517573
Short name T815
Test name
Test status
Simulation time 401933908 ps
CPU time 4.01 seconds
Started Jul 04 06:46:01 PM PDT 24
Finished Jul 04 06:46:05 PM PDT 24
Peak memory 208472 kb
Host smart-f83057e8-00e3-4b0f-b91f-74d602f781c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777517573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3777517573
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4229373409
Short name T284
Test name
Test status
Simulation time 386643229 ps
CPU time 11.1 seconds
Started Jul 04 06:45:59 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 216912 kb
Host smart-0db7bf5d-21ce-4a55-bc90-783e5aa597fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229373409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4229373409
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.488800983
Short name T309
Test name
Test status
Simulation time 1141972571 ps
CPU time 8.13 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 222596 kb
Host smart-557794ed-965e-4299-9504-c0a24b3250e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488800983 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.488800983
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.156866432
Short name T587
Test name
Test status
Simulation time 588269861 ps
CPU time 5.76 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:08 PM PDT 24
Peak memory 209280 kb
Host smart-6beb1d93-4322-4ac4-b07c-bec1d6c45d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156866432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.156866432
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3875188823
Short name T689
Test name
Test status
Simulation time 3147280946 ps
CPU time 18.43 seconds
Started Jul 04 06:46:04 PM PDT 24
Finished Jul 04 06:46:23 PM PDT 24
Peak memory 211308 kb
Host smart-3e881212-cafb-43dc-9f4e-758599bc5920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875188823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3875188823
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2382337130
Short name T676
Test name
Test status
Simulation time 70085573 ps
CPU time 0.85 seconds
Started Jul 04 06:46:09 PM PDT 24
Finished Jul 04 06:46:10 PM PDT 24
Peak memory 205992 kb
Host smart-055561e2-e078-444b-b834-6193a6f6df36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382337130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2382337130
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3645371410
Short name T134
Test name
Test status
Simulation time 33941602 ps
CPU time 2.76 seconds
Started Jul 04 06:46:08 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 214984 kb
Host smart-4a048fa6-a888-4983-99f6-3789f2a4c420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645371410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3645371410
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2910915776
Short name T627
Test name
Test status
Simulation time 123367204 ps
CPU time 3.14 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:10 PM PDT 24
Peak memory 209724 kb
Host smart-9ef9c697-5427-42f7-a5a2-5c1b23d7f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910915776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2910915776
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3128145380
Short name T828
Test name
Test status
Simulation time 2772951947 ps
CPU time 47.35 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 209660 kb
Host smart-5ac481f6-3121-461c-86fb-86b08e799833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128145380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3128145380
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_random.728958605
Short name T277
Test name
Test status
Simulation time 162251684 ps
CPU time 6.73 seconds
Started Jul 04 06:46:08 PM PDT 24
Finished Jul 04 06:46:15 PM PDT 24
Peak memory 214292 kb
Host smart-9c5745b8-329d-4e17-904a-b4c732db4a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728958605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.728958605
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1689505005
Short name T292
Test name
Test status
Simulation time 183477233 ps
CPU time 5.46 seconds
Started Jul 04 06:46:02 PM PDT 24
Finished Jul 04 06:46:08 PM PDT 24
Peak memory 207052 kb
Host smart-c08b8bc2-a9e0-42ed-8cfe-d57ca8978395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689505005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1689505005
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3346455339
Short name T219
Test name
Test status
Simulation time 692616969 ps
CPU time 9.06 seconds
Started Jul 04 06:46:06 PM PDT 24
Finished Jul 04 06:46:16 PM PDT 24
Peak memory 208144 kb
Host smart-b49193d3-1967-4e70-b905-10064df41682
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346455339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3346455339
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2459460473
Short name T281
Test name
Test status
Simulation time 123506057 ps
CPU time 3.21 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 208620 kb
Host smart-5784c5ec-1bf9-409b-913e-842f97a01682
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459460473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2459460473
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1814327746
Short name T500
Test name
Test status
Simulation time 532329590 ps
CPU time 4.13 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 206816 kb
Host smart-3493ef6d-dcfc-4227-9918-680a14afb4ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814327746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1814327746
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4004300397
Short name T663
Test name
Test status
Simulation time 191221990 ps
CPU time 5.38 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:13 PM PDT 24
Peak memory 209544 kb
Host smart-f10e7e98-8403-4ebc-a863-3c3201594f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004300397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4004300397
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1237166287
Short name T522
Test name
Test status
Simulation time 2866461207 ps
CPU time 30.73 seconds
Started Jul 04 06:46:04 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 209052 kb
Host smart-618acba4-7241-4bac-9f81-a5d01b269fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237166287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1237166287
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3128709787
Short name T198
Test name
Test status
Simulation time 1272281661 ps
CPU time 46.96 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:55 PM PDT 24
Peak memory 216128 kb
Host smart-273ef3be-5f2a-4335-a23d-75b133c0924c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128709787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3128709787
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3440164726
Short name T63
Test name
Test status
Simulation time 450670830 ps
CPU time 9.28 seconds
Started Jul 04 06:46:06 PM PDT 24
Finished Jul 04 06:46:15 PM PDT 24
Peak memory 219700 kb
Host smart-865ae445-7135-4433-a1f3-616d99f27804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440164726 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3440164726
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2477191722
Short name T352
Test name
Test status
Simulation time 110670227 ps
CPU time 5.1 seconds
Started Jul 04 06:46:06 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 210596 kb
Host smart-feee35e7-1553-420f-981a-7171796a619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477191722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2477191722
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2811046274
Short name T39
Test name
Test status
Simulation time 295023453 ps
CPU time 3.26 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:11 PM PDT 24
Peak memory 210456 kb
Host smart-d18e6bb2-7b25-463a-a9c8-f2e40f72939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811046274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2811046274
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2944205306
Short name T842
Test name
Test status
Simulation time 13402420 ps
CPU time 0.85 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:14 PM PDT 24
Peak memory 205992 kb
Host smart-1b7d5038-d523-4194-bf53-d0ab3b5e6be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944205306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2944205306
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4080025224
Short name T70
Test name
Test status
Simulation time 3344708146 ps
CPU time 7 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:10 PM PDT 24
Peak memory 209408 kb
Host smart-c6ff948e-39c2-4f99-905e-b1770ad9900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080025224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4080025224
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2193516310
Short name T335
Test name
Test status
Simulation time 28255228 ps
CPU time 2.07 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:14 PM PDT 24
Peak memory 214652 kb
Host smart-698f6b44-9084-4bbf-bc08-a4278913565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193516310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2193516310
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1125223826
Short name T206
Test name
Test status
Simulation time 380078145 ps
CPU time 5.07 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:08 PM PDT 24
Peak memory 209828 kb
Host smart-aacd1a27-002f-4d65-a42c-b55eb881bf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125223826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1125223826
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.56072473
Short name T450
Test name
Test status
Simulation time 28423958 ps
CPU time 2.37 seconds
Started Jul 04 06:47:04 PM PDT 24
Finished Jul 04 06:47:07 PM PDT 24
Peak memory 216364 kb
Host smart-169ea511-ec81-4862-b0a7-c6318e85fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56072473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.56072473
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1932096440
Short name T428
Test name
Test status
Simulation time 890740076 ps
CPU time 23.27 seconds
Started Jul 04 06:47:02 PM PDT 24
Finished Jul 04 06:47:26 PM PDT 24
Peak memory 208052 kb
Host smart-1e427d39-b00c-418a-a3fd-977f551fed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932096440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1932096440
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2658293803
Short name T726
Test name
Test status
Simulation time 234314877 ps
CPU time 5 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:08 PM PDT 24
Peak memory 208696 kb
Host smart-2112ebd1-d98f-4005-a771-ebb82f75685c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658293803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2658293803
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3508880321
Short name T857
Test name
Test status
Simulation time 131600404 ps
CPU time 2.43 seconds
Started Jul 04 06:47:02 PM PDT 24
Finished Jul 04 06:47:05 PM PDT 24
Peak memory 206840 kb
Host smart-a6b91aad-78be-4f84-9778-d93c31175719
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508880321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3508880321
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3793865748
Short name T342
Test name
Test status
Simulation time 303371643 ps
CPU time 2.82 seconds
Started Jul 04 06:47:02 PM PDT 24
Finished Jul 04 06:47:05 PM PDT 24
Peak memory 208680 kb
Host smart-685d8d01-19f4-43b7-9d0a-8dc2ea3a2032
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793865748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3793865748
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3797966236
Short name T507
Test name
Test status
Simulation time 181165069 ps
CPU time 2.51 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 206924 kb
Host smart-3e4e7037-7a5d-4a28-a245-23e587107f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797966236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3797966236
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2137794862
Short name T384
Test name
Test status
Simulation time 2856791142 ps
CPU time 18.4 seconds
Started Jul 04 06:47:06 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 208768 kb
Host smart-87148e23-5286-4338-b319-330b7380b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137794862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2137794862
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2749427117
Short name T175
Test name
Test status
Simulation time 3762043430 ps
CPU time 51.67 seconds
Started Jul 04 06:47:11 PM PDT 24
Finished Jul 04 06:48:03 PM PDT 24
Peak memory 216288 kb
Host smart-8466dc2a-691d-487b-8a77-eabe30fe43b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749427117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2749427117
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1116956314
Short name T852
Test name
Test status
Simulation time 195699652 ps
CPU time 6.98 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:10 PM PDT 24
Peak memory 208012 kb
Host smart-fdfa33db-fecb-4934-bb9b-64b3c74be63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116956314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1116956314
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2786875462
Short name T740
Test name
Test status
Simulation time 101954663 ps
CPU time 2.47 seconds
Started Jul 04 06:47:14 PM PDT 24
Finished Jul 04 06:47:16 PM PDT 24
Peak memory 210176 kb
Host smart-bdfd6d70-b322-4559-ba9d-a0a8371eb8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786875462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2786875462
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3481450249
Short name T562
Test name
Test status
Simulation time 15601912 ps
CPU time 0.73 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:21 PM PDT 24
Peak memory 206016 kb
Host smart-a04e18dc-6aa1-440d-8352-1a2cc48c3af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481450249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3481450249
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2675129305
Short name T400
Test name
Test status
Simulation time 1058759743 ps
CPU time 51.07 seconds
Started Jul 04 06:47:16 PM PDT 24
Finished Jul 04 06:48:07 PM PDT 24
Peak memory 214720 kb
Host smart-e9119e68-ffd9-4733-a29d-d8bacae3b1ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675129305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2675129305
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3096448110
Short name T5
Test name
Test status
Simulation time 161757788 ps
CPU time 5.35 seconds
Started Jul 04 06:47:14 PM PDT 24
Finished Jul 04 06:47:19 PM PDT 24
Peak memory 217992 kb
Host smart-30d5dfbc-0647-4a26-92b5-fbcf0e158292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096448110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3096448110
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.58452316
Short name T664
Test name
Test status
Simulation time 271422173 ps
CPU time 4.24 seconds
Started Jul 04 06:47:11 PM PDT 24
Finished Jul 04 06:47:16 PM PDT 24
Peak memory 209220 kb
Host smart-84c3f1a3-2124-4e2c-a237-7c0bde63a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58452316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.58452316
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3674336475
Short name T551
Test name
Test status
Simulation time 291057929 ps
CPU time 3.94 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:17 PM PDT 24
Peak memory 208244 kb
Host smart-8f793526-ba43-4443-9549-8fff1f13daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674336475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3674336475
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1770764189
Short name T810
Test name
Test status
Simulation time 330747912 ps
CPU time 3.18 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 206908 kb
Host smart-092bddf1-92e2-4866-8a0d-829e58182ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770764189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1770764189
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.998766668
Short name T793
Test name
Test status
Simulation time 899622474 ps
CPU time 15.16 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 219952 kb
Host smart-be391d1a-ff43-44ce-af94-9c202d1824bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998766668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.998766668
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3728838268
Short name T707
Test name
Test status
Simulation time 74145126 ps
CPU time 2.75 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:16 PM PDT 24
Peak memory 208508 kb
Host smart-f090f9c4-fe16-4caa-ae92-67a6ec1e0062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728838268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3728838268
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3051586579
Short name T742
Test name
Test status
Simulation time 58549688 ps
CPU time 3.03 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:16 PM PDT 24
Peak memory 207072 kb
Host smart-b27585b6-5608-438c-923a-dd19ab8e11a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051586579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3051586579
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.958212587
Short name T516
Test name
Test status
Simulation time 150331469 ps
CPU time 4.64 seconds
Started Jul 04 06:47:13 PM PDT 24
Finished Jul 04 06:47:18 PM PDT 24
Peak memory 208836 kb
Host smart-ae9f9e5a-6888-4ccf-a414-ad7ef0f23946
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958212587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.958212587
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3075791592
Short name T584
Test name
Test status
Simulation time 289039439 ps
CPU time 4.2 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 215816 kb
Host smart-83822ac6-eb86-43f5-95e6-a51b4fbd7abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075791592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3075791592
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3141136311
Short name T452
Test name
Test status
Simulation time 236649148 ps
CPU time 2.91 seconds
Started Jul 04 06:47:12 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 208492 kb
Host smart-11c8cae8-8a2e-44f1-bcd2-5f72db1d24be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141136311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3141136311
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.934318827
Short name T330
Test name
Test status
Simulation time 318751190 ps
CPU time 8.62 seconds
Started Jul 04 06:47:19 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 220328 kb
Host smart-67c61dcb-5cda-49f0-bafd-df50961185be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934318827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.934318827
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.863549965
Short name T242
Test name
Test status
Simulation time 3468869460 ps
CPU time 20.99 seconds
Started Jul 04 06:47:21 PM PDT 24
Finished Jul 04 06:47:43 PM PDT 24
Peak memory 222700 kb
Host smart-a7373eaf-0cd8-49af-bf4e-d8a827c9220e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863549965 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.863549965
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2013351395
Short name T590
Test name
Test status
Simulation time 288333266 ps
CPU time 9.52 seconds
Started Jul 04 06:47:11 PM PDT 24
Finished Jul 04 06:47:21 PM PDT 24
Peak memory 208540 kb
Host smart-2334c1e6-8163-4b3d-b1a3-584e6cc6e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013351395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2013351395
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1600269032
Short name T865
Test name
Test status
Simulation time 15991830 ps
CPU time 0.74 seconds
Started Jul 04 06:47:24 PM PDT 24
Finished Jul 04 06:47:25 PM PDT 24
Peak memory 206024 kb
Host smart-dc2e9b67-0af0-4473-81dc-bf0c92e13756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600269032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1600269032
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1976414522
Short name T406
Test name
Test status
Simulation time 911389341 ps
CPU time 12.53 seconds
Started Jul 04 06:47:19 PM PDT 24
Finished Jul 04 06:47:32 PM PDT 24
Peak memory 214324 kb
Host smart-0518afb5-f3cb-4a3a-b69f-9ba377a19969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976414522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1976414522
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.410107025
Short name T648
Test name
Test status
Simulation time 35027564 ps
CPU time 1.82 seconds
Started Jul 04 06:47:19 PM PDT 24
Finished Jul 04 06:47:21 PM PDT 24
Peak memory 207528 kb
Host smart-8698c21f-af7b-46ce-92bb-3d06f44e92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410107025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.410107025
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2324420798
Short name T88
Test name
Test status
Simulation time 577539792 ps
CPU time 5.23 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 209684 kb
Host smart-e9018b55-a1b8-454e-8cad-6f4fb216ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324420798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2324420798
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_random.2876957566
Short name T473
Test name
Test status
Simulation time 874955848 ps
CPU time 8.9 seconds
Started Jul 04 06:47:19 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 215192 kb
Host smart-ce86b6bc-c824-444f-b0b2-cffb538ec902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876957566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2876957566
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3421004078
Short name T880
Test name
Test status
Simulation time 103567325 ps
CPU time 2.89 seconds
Started Jul 04 06:47:21 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 206876 kb
Host smart-1e4e67e5-7f64-4648-9c3e-3a2a2a87b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421004078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3421004078
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.287994714
Short name T99
Test name
Test status
Simulation time 227085814 ps
CPU time 8.52 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 208752 kb
Host smart-ea4bfc92-7346-4338-80a7-6996a9799dd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287994714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.287994714
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2857289822
Short name T847
Test name
Test status
Simulation time 387638503 ps
CPU time 3.78 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 208732 kb
Host smart-05e0c7c2-e246-4025-8c25-2223f55e3ca5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857289822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2857289822
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.756674598
Short name T600
Test name
Test status
Simulation time 314290470 ps
CPU time 7 seconds
Started Jul 04 06:47:24 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 208032 kb
Host smart-baa850ac-7361-4f5b-97da-50e66b391898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756674598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.756674598
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4198321135
Short name T777
Test name
Test status
Simulation time 234595571 ps
CPU time 2.18 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 215808 kb
Host smart-2cde40fe-ea20-4c61-be5c-5f639908caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198321135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4198321135
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1413761107
Short name T831
Test name
Test status
Simulation time 118205784 ps
CPU time 2.77 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:23 PM PDT 24
Peak memory 206772 kb
Host smart-7dd6323f-77a6-4399-a435-2ec0a5658b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413761107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1413761107
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.91047692
Short name T492
Test name
Test status
Simulation time 306662386 ps
CPU time 4.07 seconds
Started Jul 04 06:47:20 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 210404 kb
Host smart-632d448f-7053-4adb-bec1-f8c27a26c886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91047692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.91047692
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1171625078
Short name T817
Test name
Test status
Simulation time 36154044 ps
CPU time 2.11 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 209732 kb
Host smart-e56413bf-6b28-4d74-993d-56b73c5958da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171625078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1171625078
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2084652410
Short name T441
Test name
Test status
Simulation time 9312275 ps
CPU time 0.78 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 205988 kb
Host smart-cddf114a-cc72-4f28-b6fc-73fee60570ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084652410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2084652410
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1319472184
Short name T288
Test name
Test status
Simulation time 2530542512 ps
CPU time 89.26 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:48:56 PM PDT 24
Peak memory 215912 kb
Host smart-60793550-f719-455d-a182-9080c7e46201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319472184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1319472184
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.394382037
Short name T580
Test name
Test status
Simulation time 28003826 ps
CPU time 1.62 seconds
Started Jul 04 06:47:28 PM PDT 24
Finished Jul 04 06:47:30 PM PDT 24
Peak memory 208432 kb
Host smart-73db3d35-eafe-46ed-891c-eda07d071094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394382037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.394382037
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1647419028
Short name T899
Test name
Test status
Simulation time 333145910 ps
CPU time 4.77 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:32 PM PDT 24
Peak memory 209816 kb
Host smart-b5eea330-dba4-4928-8c59-83381e3525ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647419028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1647419028
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2056033223
Short name T745
Test name
Test status
Simulation time 31637586 ps
CPU time 2.7 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 214928 kb
Host smart-02a6f1ca-0988-403d-9e9c-77454216271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056033223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2056033223
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2259817032
Short name T247
Test name
Test status
Simulation time 89294007 ps
CPU time 2.96 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 221008 kb
Host smart-b2c89e2f-ae57-458e-b1ec-290cde010c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259817032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2259817032
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1565270773
Short name T453
Test name
Test status
Simulation time 261823956 ps
CPU time 3.65 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:30 PM PDT 24
Peak memory 209324 kb
Host smart-5a4fb22e-23ba-4fb4-8f1a-1ecca85cd6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565270773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1565270773
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1647761220
Short name T528
Test name
Test status
Simulation time 1099480518 ps
CPU time 7.06 seconds
Started Jul 04 06:47:28 PM PDT 24
Finished Jul 04 06:47:36 PM PDT 24
Peak memory 218380 kb
Host smart-387d1db4-1355-45a7-8ad9-167b4b538ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647761220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1647761220
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1504844158
Short name T436
Test name
Test status
Simulation time 402237370 ps
CPU time 5 seconds
Started Jul 04 06:47:24 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 208664 kb
Host smart-37f7989f-cca0-4a66-bb85-b26fdd7a5344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504844158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1504844158
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3515712259
Short name T871
Test name
Test status
Simulation time 122906080 ps
CPU time 3.26 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 209072 kb
Host smart-9da3b971-ff8d-4926-907b-e5c8376dde8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515712259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3515712259
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3108819987
Short name T887
Test name
Test status
Simulation time 32524072 ps
CPU time 2.46 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 207292 kb
Host smart-5d4d7b69-0797-4a33-b2b5-8ee5a32df7ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108819987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3108819987
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1033498367
Short name T780
Test name
Test status
Simulation time 410261152 ps
CPU time 3.77 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:30 PM PDT 24
Peak memory 208552 kb
Host smart-0172430d-96de-43be-b4ab-368cdce29f0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033498367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1033498367
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3152515954
Short name T320
Test name
Test status
Simulation time 159006111 ps
CPU time 2.68 seconds
Started Jul 04 06:47:25 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 218308 kb
Host smart-21aa1785-ff48-4ee8-aff1-c431acddc92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152515954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3152515954
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.111066357
Short name T863
Test name
Test status
Simulation time 821366641 ps
CPU time 5.75 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:32 PM PDT 24
Peak memory 206928 kb
Host smart-1017303f-2405-4cdd-9e84-ba8ee1052da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111066357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.111066357
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1050479202
Short name T923
Test name
Test status
Simulation time 1831029493 ps
CPU time 35.31 seconds
Started Jul 04 06:47:25 PM PDT 24
Finished Jul 04 06:48:01 PM PDT 24
Peak memory 222480 kb
Host smart-09e6a918-fa85-4695-836c-6d1f811ed748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050479202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1050479202
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4222712774
Short name T170
Test name
Test status
Simulation time 1119024406 ps
CPU time 10.8 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 219724 kb
Host smart-57d26a6e-ece6-4360-ba2d-65e859165c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222712774 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4222712774
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3821767579
Short name T640
Test name
Test status
Simulation time 456388425 ps
CPU time 4.75 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 207044 kb
Host smart-7429c3b8-7a7c-49da-b7c0-536a25ab7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821767579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3821767579
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1162390085
Short name T898
Test name
Test status
Simulation time 175170650 ps
CPU time 2.15 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 210024 kb
Host smart-adc498eb-a913-4244-9ba8-bccbb43b63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162390085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1162390085
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2928695478
Short name T548
Test name
Test status
Simulation time 24057752 ps
CPU time 0.74 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:34 PM PDT 24
Peak memory 206012 kb
Host smart-b8509812-fdc7-48ba-a80f-7bd5c3d42f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928695478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2928695478
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3721162111
Short name T329
Test name
Test status
Simulation time 32648120 ps
CPU time 2.62 seconds
Started Jul 04 06:47:31 PM PDT 24
Finished Jul 04 06:47:34 PM PDT 24
Peak memory 215084 kb
Host smart-c1ec130c-3bd8-4125-9da2-f1fb235ab545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721162111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3721162111
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2644598060
Short name T504
Test name
Test status
Simulation time 84277628 ps
CPU time 2.49 seconds
Started Jul 04 06:47:32 PM PDT 24
Finished Jul 04 06:47:34 PM PDT 24
Peak memory 207692 kb
Host smart-42e5ccf7-d00d-484d-bcca-da1666f08fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644598060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2644598060
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1592525502
Short name T747
Test name
Test status
Simulation time 163658352 ps
CPU time 4.72 seconds
Started Jul 04 06:47:36 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 209408 kb
Host smart-4130eb69-3b79-4e05-a044-6c8b285bb663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592525502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1592525502
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3811963057
Short name T357
Test name
Test status
Simulation time 76074401 ps
CPU time 2.14 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:36 PM PDT 24
Peak memory 214308 kb
Host smart-aa333e14-376a-457c-8887-908302bc24e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811963057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3811963057
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.679612350
Short name T711
Test name
Test status
Simulation time 450528229 ps
CPU time 2.82 seconds
Started Jul 04 06:47:34 PM PDT 24
Finished Jul 04 06:47:37 PM PDT 24
Peak memory 206344 kb
Host smart-516854d3-f42f-4351-b086-add03fbe1747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679612350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.679612350
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3146390128
Short name T287
Test name
Test status
Simulation time 763819494 ps
CPU time 5.9 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:32 PM PDT 24
Peak memory 214320 kb
Host smart-4994c0c4-56fb-47e9-a642-1a3b1c4d362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146390128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3146390128
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2710570983
Short name T2
Test name
Test status
Simulation time 201054292 ps
CPU time 3.08 seconds
Started Jul 04 06:47:25 PM PDT 24
Finished Jul 04 06:47:28 PM PDT 24
Peak memory 206876 kb
Host smart-9727d067-253c-4594-8a7f-09d7f833110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710570983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2710570983
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1931303117
Short name T610
Test name
Test status
Simulation time 76426306 ps
CPU time 3.54 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:30 PM PDT 24
Peak memory 208700 kb
Host smart-63d11e14-0885-4986-8b7c-88d3592aac9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931303117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1931303117
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2023973280
Short name T290
Test name
Test status
Simulation time 363985281 ps
CPU time 3.73 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:29 PM PDT 24
Peak memory 206828 kb
Host smart-7fb0424c-0842-4735-bad9-fda006038f3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023973280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2023973280
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3472081637
Short name T98
Test name
Test status
Simulation time 575955938 ps
CPU time 4.82 seconds
Started Jul 04 06:47:26 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 208040 kb
Host smart-23654190-98a5-48ae-ab8d-db754ce80852
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472081637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3472081637
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1856906090
Short name T306
Test name
Test status
Simulation time 1107723218 ps
CPU time 6.86 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:40 PM PDT 24
Peak memory 214272 kb
Host smart-bc48f3e1-52a8-4cab-9c09-c79d4aa24036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856906090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1856906090
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.513892995
Short name T438
Test name
Test status
Simulation time 803927653 ps
CPU time 14.51 seconds
Started Jul 04 06:47:27 PM PDT 24
Finished Jul 04 06:47:42 PM PDT 24
Peak memory 208072 kb
Host smart-916870d4-4802-47ed-81a0-bda2c35caaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513892995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.513892995
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2873424574
Short name T327
Test name
Test status
Simulation time 2217087173 ps
CPU time 26.69 seconds
Started Jul 04 06:47:32 PM PDT 24
Finished Jul 04 06:47:59 PM PDT 24
Peak memory 220168 kb
Host smart-ae88a85d-49df-40f2-92bd-0beadb27a441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873424574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2873424574
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2696618809
Short name T180
Test name
Test status
Simulation time 163185105 ps
CPU time 6.39 seconds
Started Jul 04 06:47:35 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 209392 kb
Host smart-79bfd861-f04d-4902-8e8f-735722f24719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696618809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2696618809
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.454388462
Short name T367
Test name
Test status
Simulation time 90760569 ps
CPU time 2.04 seconds
Started Jul 04 06:47:38 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 209904 kb
Host smart-aba21b40-f1e2-42b3-b438-45dd19879cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454388462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.454388462
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.921565634
Short name T837
Test name
Test status
Simulation time 34626925 ps
CPU time 0.82 seconds
Started Jul 04 06:47:40 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 206004 kb
Host smart-a06160a9-2ec5-4760-a1f6-2cc310ba28f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921565634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.921565634
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.145410840
Short name T393
Test name
Test status
Simulation time 43373572 ps
CPU time 3.28 seconds
Started Jul 04 06:47:32 PM PDT 24
Finished Jul 04 06:47:36 PM PDT 24
Peak memory 215348 kb
Host smart-68d3a0a9-de23-4d51-9e48-4a967a8abc6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145410840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.145410840
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3617043336
Short name T595
Test name
Test status
Simulation time 130632327 ps
CPU time 3.83 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:37 PM PDT 24
Peak memory 209992 kb
Host smart-8bb54c31-e304-4d4b-aade-32aaf94a9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617043336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3617043336
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.312901146
Short name T639
Test name
Test status
Simulation time 79607585 ps
CPU time 1.43 seconds
Started Jul 04 06:47:32 PM PDT 24
Finished Jul 04 06:47:34 PM PDT 24
Peak memory 207272 kb
Host smart-d80f9978-4060-4654-a4da-f267972c0fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312901146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.312901146
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3405078864
Short name T889
Test name
Test status
Simulation time 663678974 ps
CPU time 3.73 seconds
Started Jul 04 06:47:34 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 214412 kb
Host smart-bb4c758d-94cc-4248-a345-04d24cd0984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405078864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3405078864
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2039875286
Short name T808
Test name
Test status
Simulation time 108156854 ps
CPU time 2.27 seconds
Started Jul 04 06:47:38 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 209832 kb
Host smart-9b12eeb4-616d-43aa-a53b-c9018fe9dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039875286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2039875286
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3693271477
Short name T514
Test name
Test status
Simulation time 129726139 ps
CPU time 3.71 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:37 PM PDT 24
Peak memory 207780 kb
Host smart-68eadaa3-6f63-4ad0-a238-d587e4670740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693271477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3693271477
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.662824552
Short name T770
Test name
Test status
Simulation time 296726128 ps
CPU time 4.1 seconds
Started Jul 04 06:47:34 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 208496 kb
Host smart-99796460-7ea6-4fff-8ae2-ef577bfbf9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662824552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.662824552
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.401630452
Short name T576
Test name
Test status
Simulation time 149243680 ps
CPU time 2.79 seconds
Started Jul 04 06:47:38 PM PDT 24
Finished Jul 04 06:47:41 PM PDT 24
Peak memory 208652 kb
Host smart-3ade8c1d-5d4f-4c49-986f-7fc426e7f638
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401630452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.401630452
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3725683903
Short name T460
Test name
Test status
Simulation time 780931994 ps
CPU time 6.5 seconds
Started Jul 04 06:47:32 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 208128 kb
Host smart-ba301615-600e-400f-afb2-4033243d6201
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725683903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3725683903
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1037032154
Short name T462
Test name
Test status
Simulation time 36807688 ps
CPU time 1.89 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:35 PM PDT 24
Peak memory 208796 kb
Host smart-7955e495-acb8-463d-aaa7-828a8e6ffe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037032154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1037032154
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4262619503
Short name T78
Test name
Test status
Simulation time 664514523 ps
CPU time 4.71 seconds
Started Jul 04 06:47:33 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 208512 kb
Host smart-9079c9f0-109f-422a-86b2-bf8aae0e704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262619503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4262619503
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1400367615
Short name T485
Test name
Test status
Simulation time 2439343180 ps
CPU time 25.38 seconds
Started Jul 04 06:47:40 PM PDT 24
Finished Jul 04 06:48:06 PM PDT 24
Peak memory 222652 kb
Host smart-f98a2488-b8b8-46da-9c56-c15cec9e24c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400367615 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1400367615
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.414198716
Short name T178
Test name
Test status
Simulation time 7314742758 ps
CPU time 51.57 seconds
Started Jul 04 06:47:36 PM PDT 24
Finished Jul 04 06:48:28 PM PDT 24
Peak memory 220016 kb
Host smart-62a0a833-31b9-4a4f-bae7-a6ea22b0289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414198716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.414198716
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.394206169
Short name T361
Test name
Test status
Simulation time 442473056 ps
CPU time 2.97 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:47:45 PM PDT 24
Peak memory 210680 kb
Host smart-da7ca576-7b28-4aae-823b-b908dd870554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394206169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.394206169
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.690831965
Short name T398
Test name
Test status
Simulation time 491313732 ps
CPU time 14.23 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 214848 kb
Host smart-d4aee9ba-9ddf-42ba-8e54-1a6718e01df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690831965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.690831965
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3023137663
Short name T795
Test name
Test status
Simulation time 535695517 ps
CPU time 4.55 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:45 PM PDT 24
Peak memory 218308 kb
Host smart-defed46b-bc80-4cbd-8ff6-b21dd1def3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023137663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3023137663
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3710797748
Short name T313
Test name
Test status
Simulation time 77564360 ps
CPU time 3.93 seconds
Started Jul 04 06:47:40 PM PDT 24
Finished Jul 04 06:47:44 PM PDT 24
Peak memory 214376 kb
Host smart-f792179c-ad58-4527-b933-27d92752e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710797748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3710797748
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.852738729
Short name T637
Test name
Test status
Simulation time 221536625 ps
CPU time 3.49 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:45 PM PDT 24
Peak memory 208380 kb
Host smart-1d24542c-8051-4d4b-b18d-675e555144dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852738729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.852738729
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1839447978
Short name T569
Test name
Test status
Simulation time 1986438348 ps
CPU time 7.05 seconds
Started Jul 04 06:47:46 PM PDT 24
Finished Jul 04 06:47:53 PM PDT 24
Peak memory 207320 kb
Host smart-9ecd772c-79d5-4353-8a10-fa3a45fbb8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839447978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1839447978
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1124362293
Short name T82
Test name
Test status
Simulation time 90632559 ps
CPU time 4.59 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:47:46 PM PDT 24
Peak memory 208616 kb
Host smart-292c2122-ee6d-4f22-9ded-e838f022785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124362293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1124362293
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.563492315
Short name T279
Test name
Test status
Simulation time 188456887 ps
CPU time 4.43 seconds
Started Jul 04 06:47:40 PM PDT 24
Finished Jul 04 06:47:45 PM PDT 24
Peak memory 208780 kb
Host smart-73618d47-4d58-4f81-b362-fdcce80b6dd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563492315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.563492315
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3161844286
Short name T698
Test name
Test status
Simulation time 236756087 ps
CPU time 5.19 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:46 PM PDT 24
Peak memory 208824 kb
Host smart-1fb6321d-10cf-46cb-8f4c-440437f7e17f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161844286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3161844286
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.828918589
Short name T688
Test name
Test status
Simulation time 132274495 ps
CPU time 3.86 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:47:46 PM PDT 24
Peak memory 207852 kb
Host smart-ec97db35-0e76-4351-be2b-f24592578ed6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828918589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.828918589
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2030683470
Short name T446
Test name
Test status
Simulation time 96379730 ps
CPU time 2.14 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:43 PM PDT 24
Peak memory 214332 kb
Host smart-202f0c89-5ef4-47bc-a3d3-53cc95b67888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030683470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2030683470
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2737499454
Short name T383
Test name
Test status
Simulation time 71441732 ps
CPU time 2.23 seconds
Started Jul 04 06:47:41 PM PDT 24
Finished Jul 04 06:47:43 PM PDT 24
Peak memory 208136 kb
Host smart-b6faa822-85f6-4771-952d-37ce38d465b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737499454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2737499454
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4025935942
Short name T891
Test name
Test status
Simulation time 468317363 ps
CPU time 20.68 seconds
Started Jul 04 06:47:48 PM PDT 24
Finished Jul 04 06:48:09 PM PDT 24
Peak memory 222668 kb
Host smart-7fea0d90-d7f9-4d1b-8be2-b4b392a0866a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025935942 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4025935942
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1762004336
Short name T807
Test name
Test status
Simulation time 662365736 ps
CPU time 5.65 seconds
Started Jul 04 06:47:42 PM PDT 24
Finished Jul 04 06:47:48 PM PDT 24
Peak memory 207740 kb
Host smart-483b8e8c-3926-417b-8271-c28372c1b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762004336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1762004336
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3614453538
Short name T95
Test name
Test status
Simulation time 9395217 ps
CPU time 0.74 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:54 PM PDT 24
Peak memory 205992 kb
Host smart-7b0b74da-f351-483d-ad86-5f67dde758c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614453538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3614453538
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4286662041
Short name T374
Test name
Test status
Simulation time 299907789 ps
CPU time 2.17 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 214348 kb
Host smart-bbd44ceb-d055-4dff-b0de-2b8a1fae706a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286662041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4286662041
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3619076679
Short name T525
Test name
Test status
Simulation time 8670985960 ps
CPU time 26.33 seconds
Started Jul 04 06:47:47 PM PDT 24
Finished Jul 04 06:48:13 PM PDT 24
Peak memory 219528 kb
Host smart-a3db2e25-3e62-461b-b0f8-6e5208e80122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619076679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3619076679
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1849072650
Short name T251
Test name
Test status
Simulation time 105139475 ps
CPU time 5.59 seconds
Started Jul 04 06:47:47 PM PDT 24
Finished Jul 04 06:47:52 PM PDT 24
Peak memory 214364 kb
Host smart-0bb62771-2c52-4db3-909c-fabf0f2d234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849072650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1849072650
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3247813974
Short name T632
Test name
Test status
Simulation time 188438599 ps
CPU time 4.91 seconds
Started Jul 04 06:47:46 PM PDT 24
Finished Jul 04 06:47:51 PM PDT 24
Peak memory 220408 kb
Host smart-044281f5-3fa5-4fde-b10a-18021430132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247813974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3247813974
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1021620409
Short name T210
Test name
Test status
Simulation time 72744469 ps
CPU time 3.68 seconds
Started Jul 04 06:47:47 PM PDT 24
Finished Jul 04 06:47:51 PM PDT 24
Peak memory 209416 kb
Host smart-fe93da6f-e9cc-4f5f-8abf-9be05c2369c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021620409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1021620409
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2023741947
Short name T529
Test name
Test status
Simulation time 209541160 ps
CPU time 7.4 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:48:02 PM PDT 24
Peak memory 208816 kb
Host smart-9e9ff2ce-0af5-4de0-b65d-89cf86ac5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023741947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2023741947
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1629978706
Short name T803
Test name
Test status
Simulation time 9877328554 ps
CPU time 83.08 seconds
Started Jul 04 06:47:48 PM PDT 24
Finished Jul 04 06:49:11 PM PDT 24
Peak memory 208596 kb
Host smart-816c0e28-4aff-41b4-b873-0d3814bd410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629978706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1629978706
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3760079228
Short name T873
Test name
Test status
Simulation time 322388821 ps
CPU time 3.42 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:58 PM PDT 24
Peak memory 206976 kb
Host smart-3f0ed930-ff1e-438e-9174-de7efd540cf7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760079228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3760079228
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.806865334
Short name T515
Test name
Test status
Simulation time 209333140 ps
CPU time 2.97 seconds
Started Jul 04 06:47:47 PM PDT 24
Finished Jul 04 06:47:50 PM PDT 24
Peak memory 207024 kb
Host smart-7a5ab272-9e2c-4f19-aabf-19ec3ae52952
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806865334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.806865334
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2279142020
Short name T643
Test name
Test status
Simulation time 117980560 ps
CPU time 3.68 seconds
Started Jul 04 06:47:48 PM PDT 24
Finished Jul 04 06:47:52 PM PDT 24
Peak memory 208440 kb
Host smart-ab5b5360-3efb-4c25-adb4-01f5be451963
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279142020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2279142020
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1093056010
Short name T119
Test name
Test status
Simulation time 318782375 ps
CPU time 5.61 seconds
Started Jul 04 06:47:58 PM PDT 24
Finished Jul 04 06:48:03 PM PDT 24
Peak memory 209872 kb
Host smart-0000854f-5f61-4d9a-a8ef-348528a40c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093056010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1093056010
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3693132411
Short name T860
Test name
Test status
Simulation time 124685142 ps
CPU time 3 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 208456 kb
Host smart-46cd45de-4f7f-41bd-9ba3-275ad352c5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693132411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3693132411
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2692987902
Short name T116
Test name
Test status
Simulation time 744783969 ps
CPU time 12.28 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:48:06 PM PDT 24
Peak memory 222440 kb
Host smart-6c0bf846-a21a-4ae6-b048-7cca6aa04ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692987902 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2692987902
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1462627517
Short name T864
Test name
Test status
Simulation time 53902545 ps
CPU time 2.86 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 218348 kb
Host smart-934b6e8a-909c-4130-95e0-ee81eea474f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462627517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1462627517
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2969933849
Short name T362
Test name
Test status
Simulation time 99638910 ps
CPU time 3.01 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 210456 kb
Host smart-bae09b30-e572-4c3b-8f98-3db391f030f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969933849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2969933849
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.332449268
Short name T798
Test name
Test status
Simulation time 10974219 ps
CPU time 0.82 seconds
Started Jul 04 06:48:01 PM PDT 24
Finished Jul 04 06:48:03 PM PDT 24
Peak memory 206028 kb
Host smart-ece4e71e-41ea-4fe9-baf1-47e27adf3ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332449268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.332449268
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2926726211
Short name T399
Test name
Test status
Simulation time 83723396 ps
CPU time 3.32 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 215688 kb
Host smart-344005f3-b0e5-447f-a919-c0d368f130ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926726211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2926726211
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2725742442
Short name T360
Test name
Test status
Simulation time 412443977 ps
CPU time 3.27 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 218376 kb
Host smart-b0a4686e-d5ed-4f54-ba5e-e7da4a24ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725742442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2725742442
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1832136875
Short name T316
Test name
Test status
Simulation time 291971387 ps
CPU time 3.41 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 214316 kb
Host smart-091a6c25-f237-43bf-90f0-a90609830fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832136875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1832136875
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1677017866
Short name T331
Test name
Test status
Simulation time 36647699 ps
CPU time 1.88 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 220900 kb
Host smart-e77a2cab-de4c-42b4-9dc9-0a8d215efd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677017866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1677017866
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1833608830
Short name T577
Test name
Test status
Simulation time 208051882 ps
CPU time 2.8 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 209484 kb
Host smart-96044562-d3da-4016-a067-06e6620a88ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833608830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1833608830
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.960343308
Short name T607
Test name
Test status
Simulation time 856808766 ps
CPU time 6.44 seconds
Started Jul 04 06:47:57 PM PDT 24
Finished Jul 04 06:48:04 PM PDT 24
Peak memory 207644 kb
Host smart-3a558272-2d3d-4af3-ac94-1d5a5aecf6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960343308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.960343308
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.920013187
Short name T617
Test name
Test status
Simulation time 57141053 ps
CPU time 2.86 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:47:56 PM PDT 24
Peak memory 206928 kb
Host smart-5a28b0ef-90d3-4938-a663-992a37ba4e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920013187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.920013187
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2353576351
Short name T653
Test name
Test status
Simulation time 818678474 ps
CPU time 6 seconds
Started Jul 04 06:47:55 PM PDT 24
Finished Jul 04 06:48:01 PM PDT 24
Peak memory 209020 kb
Host smart-8e8b2e53-b66e-4179-974b-5312f8f33c53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353576351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2353576351
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1852161474
Short name T74
Test name
Test status
Simulation time 1000223144 ps
CPU time 6.21 seconds
Started Jul 04 06:47:52 PM PDT 24
Finished Jul 04 06:47:59 PM PDT 24
Peak memory 207948 kb
Host smart-11904576-fccf-453c-a220-ce786efaa7a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852161474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1852161474
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.512194013
Short name T301
Test name
Test status
Simulation time 575803896 ps
CPU time 6.69 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:48:00 PM PDT 24
Peak memory 208644 kb
Host smart-348c3c89-6b38-4b06-8cc3-a2969bde60b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512194013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.512194013
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4240927052
Short name T304
Test name
Test status
Simulation time 776587675 ps
CPU time 20 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 209744 kb
Host smart-6ec76863-522a-4582-981e-c2b3fc4cd074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240927052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4240927052
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2157720842
Short name T662
Test name
Test status
Simulation time 56814791 ps
CPU time 2.57 seconds
Started Jul 04 06:47:55 PM PDT 24
Finished Jul 04 06:47:57 PM PDT 24
Peak memory 208776 kb
Host smart-47e9c180-b09b-42b7-8628-af9da240983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157720842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2157720842
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3141087243
Short name T114
Test name
Test status
Simulation time 117079971 ps
CPU time 7.42 seconds
Started Jul 04 06:47:53 PM PDT 24
Finished Jul 04 06:48:01 PM PDT 24
Peak memory 222620 kb
Host smart-27674cd2-05f0-4a5c-8887-192967223dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141087243 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3141087243
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.361956234
Short name T258
Test name
Test status
Simulation time 282048992 ps
CPU time 8.03 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:48:03 PM PDT 24
Peak memory 209436 kb
Host smart-6f0472b5-5ae4-418e-9193-3393cced9857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361956234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.361956234
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3852835977
Short name T750
Test name
Test status
Simulation time 299333755 ps
CPU time 3.09 seconds
Started Jul 04 06:47:54 PM PDT 24
Finished Jul 04 06:47:58 PM PDT 24
Peak memory 210320 kb
Host smart-68c39070-adad-4997-a469-d81b2d0124c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852835977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3852835977
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1437508547
Short name T539
Test name
Test status
Simulation time 16582145 ps
CPU time 0.76 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 205996 kb
Host smart-6e01848e-5d92-41de-98f3-d077e5fcafa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437508547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1437508547
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3672011810
Short name T394
Test name
Test status
Simulation time 215603406 ps
CPU time 4.18 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:08 PM PDT 24
Peak memory 214796 kb
Host smart-a684d979-8349-43b0-9db3-37eefd523950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672011810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3672011810
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2154882564
Short name T36
Test name
Test status
Simulation time 443464119 ps
CPU time 3.58 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:08 PM PDT 24
Peak memory 210340 kb
Host smart-5dad985d-3cb5-4e5c-ba6e-63c7d4818d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154882564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2154882564
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1925117881
Short name T738
Test name
Test status
Simulation time 75985606 ps
CPU time 1.95 seconds
Started Jul 04 06:48:01 PM PDT 24
Finished Jul 04 06:48:04 PM PDT 24
Peak memory 214340 kb
Host smart-eb164256-c37e-4e5e-bb7c-606297e1dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925117881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1925117881
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1232979656
Short name T754
Test name
Test status
Simulation time 125692484 ps
CPU time 3.39 seconds
Started Jul 04 06:48:06 PM PDT 24
Finished Jul 04 06:48:09 PM PDT 24
Peak memory 214460 kb
Host smart-20bce2a7-c9e6-425e-a260-3fb4830c2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232979656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1232979656
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3133296655
Short name T684
Test name
Test status
Simulation time 187500829 ps
CPU time 3.4 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:07 PM PDT 24
Peak memory 214228 kb
Host smart-c09ffd42-df06-4bb6-ad6f-301b00066085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133296655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3133296655
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2295518497
Short name T634
Test name
Test status
Simulation time 85852427 ps
CPU time 1.95 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:05 PM PDT 24
Peak memory 208584 kb
Host smart-3119cd05-64ad-479f-9acc-2d7ff40eaa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295518497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2295518497
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2650800328
Short name T524
Test name
Test status
Simulation time 2198952013 ps
CPU time 17.25 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 209720 kb
Host smart-8bb62239-757a-4b54-b69e-ed4a8f3fac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650800328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2650800328
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4048952724
Short name T16
Test name
Test status
Simulation time 183910147 ps
CPU time 6.03 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:09 PM PDT 24
Peak memory 208348 kb
Host smart-b82a4f51-2679-4365-8cf0-ba1c762d8d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048952724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4048952724
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4038335539
Short name T680
Test name
Test status
Simulation time 33475435 ps
CPU time 2.29 seconds
Started Jul 04 06:48:04 PM PDT 24
Finished Jul 04 06:48:06 PM PDT 24
Peak memory 206992 kb
Host smart-69a97fbc-435c-4a8c-9d19-d4e095a6b18c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038335539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4038335539
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4058384
Short name T872
Test name
Test status
Simulation time 408079159 ps
CPU time 2.93 seconds
Started Jul 04 06:48:01 PM PDT 24
Finished Jul 04 06:48:04 PM PDT 24
Peak memory 206964 kb
Host smart-a3c089f4-53bc-46c5-9664-013a5d2e2de7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4058384
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4184625195
Short name T244
Test name
Test status
Simulation time 684027453 ps
CPU time 6.19 seconds
Started Jul 04 06:48:02 PM PDT 24
Finished Jul 04 06:48:08 PM PDT 24
Peak memory 206984 kb
Host smart-985c37c7-d028-4e22-84a3-9a703288f6cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184625195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4184625195
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3628313531
Short name T918
Test name
Test status
Simulation time 51197272 ps
CPU time 2.29 seconds
Started Jul 04 06:48:01 PM PDT 24
Finished Jul 04 06:48:04 PM PDT 24
Peak memory 210032 kb
Host smart-8f44dedc-7450-48f6-a8ba-4844d700d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628313531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3628313531
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.623379406
Short name T560
Test name
Test status
Simulation time 129242901 ps
CPU time 2.99 seconds
Started Jul 04 06:48:05 PM PDT 24
Finished Jul 04 06:48:08 PM PDT 24
Peak memory 208588 kb
Host smart-cc4763df-0e7b-4f1d-834a-e690141d06b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623379406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.623379406
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3393525416
Short name T409
Test name
Test status
Simulation time 89855966 ps
CPU time 4.54 seconds
Started Jul 04 06:48:03 PM PDT 24
Finished Jul 04 06:48:08 PM PDT 24
Peak memory 209332 kb
Host smart-f686b054-9d6f-44b4-bdd8-478d81517fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393525416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3393525416
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.386365935
Short name T364
Test name
Test status
Simulation time 50522248 ps
CPU time 1.58 seconds
Started Jul 04 06:48:02 PM PDT 24
Finished Jul 04 06:48:04 PM PDT 24
Peak memory 209992 kb
Host smart-263dc8f3-0e27-4d1c-89fd-dad80401bb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386365935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.386365935
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.95145818
Short name T97
Test name
Test status
Simulation time 89964999 ps
CPU time 0.82 seconds
Started Jul 04 06:46:21 PM PDT 24
Finished Jul 04 06:46:22 PM PDT 24
Peak memory 205996 kb
Host smart-35c5d6a4-6648-43b2-8378-5e70dffba23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95145818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.95145818
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3223038140
Short name T19
Test name
Test status
Simulation time 549317792 ps
CPU time 3.52 seconds
Started Jul 04 06:46:17 PM PDT 24
Finished Jul 04 06:46:20 PM PDT 24
Peak memory 218788 kb
Host smart-714342be-1814-4d73-b8b2-eccec0a27670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223038140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3223038140
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.991639016
Short name T437
Test name
Test status
Simulation time 778351869 ps
CPU time 6.94 seconds
Started Jul 04 06:46:17 PM PDT 24
Finished Jul 04 06:46:24 PM PDT 24
Peak memory 209036 kb
Host smart-83f2521c-aacc-46f8-a6bf-00b4da1d4257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991639016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.991639016
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3661477108
Short name T183
Test name
Test status
Simulation time 513793252 ps
CPU time 6.78 seconds
Started Jul 04 06:46:16 PM PDT 24
Finished Jul 04 06:46:23 PM PDT 24
Peak memory 214344 kb
Host smart-d829f842-6f0e-46a9-9429-4a3506d5628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661477108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3661477108
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.712147765
Short name T187
Test name
Test status
Simulation time 105740740 ps
CPU time 4.97 seconds
Started Jul 04 06:46:16 PM PDT 24
Finished Jul 04 06:46:21 PM PDT 24
Peak memory 214376 kb
Host smart-173cb353-f463-4f9f-91ca-69903e2231d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712147765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.712147765
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3171314271
Short name T912
Test name
Test status
Simulation time 2384781608 ps
CPU time 15.76 seconds
Started Jul 04 06:46:16 PM PDT 24
Finished Jul 04 06:46:32 PM PDT 24
Peak memory 218232 kb
Host smart-4de364b7-bf8b-45e8-8b3d-d726f93c499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171314271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3171314271
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4143306627
Short name T42
Test name
Test status
Simulation time 1948155265 ps
CPU time 17.05 seconds
Started Jul 04 06:46:24 PM PDT 24
Finished Jul 04 06:46:41 PM PDT 24
Peak memory 238656 kb
Host smart-ad00a8ea-8f9e-4b1a-b959-32d20798b745
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143306627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4143306627
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1596732177
Short name T739
Test name
Test status
Simulation time 532959064 ps
CPU time 4.22 seconds
Started Jul 04 06:46:08 PM PDT 24
Finished Jul 04 06:46:12 PM PDT 24
Peak memory 208676 kb
Host smart-5e36202c-38f4-428d-b3c3-c200f9d3173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596732177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1596732177
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.52824362
Short name T800
Test name
Test status
Simulation time 240863192 ps
CPU time 6.24 seconds
Started Jul 04 06:46:12 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 208916 kb
Host smart-bb08f9ea-2125-4882-b68c-14c7f87ddf61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52824362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.52824362
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2867584458
Short name T543
Test name
Test status
Simulation time 1355541935 ps
CPU time 29.44 seconds
Started Jul 04 06:46:07 PM PDT 24
Finished Jul 04 06:46:37 PM PDT 24
Peak memory 209196 kb
Host smart-e6c2429f-c398-43a7-bdef-f33a5e857a60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867584458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2867584458
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.274998569
Short name T611
Test name
Test status
Simulation time 97440683 ps
CPU time 1.94 seconds
Started Jul 04 06:46:16 PM PDT 24
Finished Jul 04 06:46:18 PM PDT 24
Peak memory 206928 kb
Host smart-66d0495f-c014-47e3-bf5e-2b70e81b0022
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274998569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.274998569
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.684550909
Short name T757
Test name
Test status
Simulation time 138989463 ps
CPU time 2.18 seconds
Started Jul 04 06:46:17 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 218488 kb
Host smart-8f5499e8-3bd3-427b-9f5d-3aee3ca2bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684550909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.684550909
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.518545209
Short name T414
Test name
Test status
Simulation time 95785791 ps
CPU time 3.71 seconds
Started Jul 04 06:46:08 PM PDT 24
Finished Jul 04 06:46:12 PM PDT 24
Peak memory 208800 kb
Host smart-58727794-0c88-4323-9436-c139395fbafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518545209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.518545209
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1600975556
Short name T499
Test name
Test status
Simulation time 4898127978 ps
CPU time 34.81 seconds
Started Jul 04 06:46:17 PM PDT 24
Finished Jul 04 06:46:52 PM PDT 24
Peak memory 208964 kb
Host smart-706b229b-5bb6-41d6-9842-09610a3fdb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600975556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1600975556
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.613352119
Short name T712
Test name
Test status
Simulation time 120354065 ps
CPU time 3.44 seconds
Started Jul 04 06:46:15 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 210444 kb
Host smart-639bda24-1327-4824-b6ea-6a8f29242c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613352119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.613352119
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.195577720
Short name T477
Test name
Test status
Simulation time 17917676 ps
CPU time 0.97 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 206152 kb
Host smart-550e1d23-146c-44d5-bbb6-53de01d0b7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195577720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.195577720
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1456689979
Short name T373
Test name
Test status
Simulation time 173376748 ps
CPU time 3.6 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 214344 kb
Host smart-13d3411c-8987-43cc-a60c-ae7f070caf85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456689979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1456689979
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2704407252
Short name T677
Test name
Test status
Simulation time 55400361 ps
CPU time 2.52 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:11 PM PDT 24
Peak memory 209096 kb
Host smart-1a8e820d-8ea5-4947-a5d2-fcdb7e08eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704407252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2704407252
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.105735643
Short name T184
Test name
Test status
Simulation time 756019479 ps
CPU time 6.2 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:16 PM PDT 24
Peak memory 219368 kb
Host smart-7d08e487-1ef5-4a9e-b9f5-7c35010548cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105735643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.105735643
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2914608812
Short name T490
Test name
Test status
Simulation time 156920248 ps
CPU time 3.15 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 218728 kb
Host smart-65a72fec-e9cd-4dd2-818b-363d7f9ea25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914608812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2914608812
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2425166481
Short name T881
Test name
Test status
Simulation time 481286713 ps
CPU time 4.2 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:13 PM PDT 24
Peak memory 214352 kb
Host smart-bc3e42db-67cc-45a4-b374-899a5824a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425166481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2425166481
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2654817062
Short name T120
Test name
Test status
Simulation time 437499574 ps
CPU time 5.43 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:15 PM PDT 24
Peak memory 214300 kb
Host smart-d4085b34-8f0e-497d-a55b-2eefe97902c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654817062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2654817062
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1927880582
Short name T718
Test name
Test status
Simulation time 102305887 ps
CPU time 3.9 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 206896 kb
Host smart-6734f873-d177-4777-939a-509a425d9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927880582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1927880582
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1434915491
Short name T458
Test name
Test status
Simulation time 194459101 ps
CPU time 5.59 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:17 PM PDT 24
Peak memory 207972 kb
Host smart-e2632b36-12e0-4c87-af41-ce63993532a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434915491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1434915491
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1817409228
Short name T533
Test name
Test status
Simulation time 286411984 ps
CPU time 5.75 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:16 PM PDT 24
Peak memory 207964 kb
Host smart-4c8df184-b878-4911-b2a8-4e340c15c8fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817409228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1817409228
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1417761601
Short name T17
Test name
Test status
Simulation time 164178559 ps
CPU time 3.09 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 214392 kb
Host smart-dd1246aa-c230-4431-afdc-bb841d0f028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417761601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1417761601
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.124508605
Short name T877
Test name
Test status
Simulation time 2737843027 ps
CPU time 24.76 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:34 PM PDT 24
Peak memory 208764 kb
Host smart-e529e746-8407-4541-a94b-b88af5d4c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124508605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.124508605
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1038440079
Short name T774
Test name
Test status
Simulation time 3048353657 ps
CPU time 15.35 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:26 PM PDT 24
Peak memory 209008 kb
Host smart-e62405d5-a7ed-4fcc-99a2-3729042524a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038440079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1038440079
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3945240742
Short name T171
Test name
Test status
Simulation time 1108062092 ps
CPU time 9.88 seconds
Started Jul 04 06:48:07 PM PDT 24
Finished Jul 04 06:48:17 PM PDT 24
Peak memory 222648 kb
Host smart-e7af0f90-5473-4c61-a7e3-1b1a76bbacdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945240742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3945240742
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.53471269
Short name T457
Test name
Test status
Simulation time 132855012 ps
CPU time 6.16 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:15 PM PDT 24
Peak memory 209316 kb
Host smart-0fd5c602-d99d-4f3e-8b4a-c587f3e18c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53471269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.53471269
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3574171520
Short name T809
Test name
Test status
Simulation time 609534701 ps
CPU time 6.67 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:15 PM PDT 24
Peak memory 210864 kb
Host smart-6831d984-e9bf-4db5-a4e5-a33a76b4fafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574171520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3574171520
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2807076124
Short name T649
Test name
Test status
Simulation time 23708688 ps
CPU time 0.86 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:11 PM PDT 24
Peak memory 206020 kb
Host smart-c48d60c3-82b9-482a-890d-8358d87e4b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807076124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2807076124
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.77366365
Short name T348
Test name
Test status
Simulation time 185469095 ps
CPU time 10.02 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:19 PM PDT 24
Peak memory 214668 kb
Host smart-c9a6f857-bc72-4b14-afb4-60192039f0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77366365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.77366365
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3161852574
Short name T32
Test name
Test status
Simulation time 63939496 ps
CPU time 3.31 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:13 PM PDT 24
Peak memory 214720 kb
Host smart-77a22080-92b7-43a7-a5e4-4fb7148d4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161852574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3161852574
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3040843231
Short name T262
Test name
Test status
Simulation time 83854944 ps
CPU time 2.9 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 208160 kb
Host smart-5151b939-62f0-4849-9d3f-504ef3581741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040843231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3040843231
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1988631559
Short name T86
Test name
Test status
Simulation time 33082833 ps
CPU time 2.24 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:11 PM PDT 24
Peak memory 208792 kb
Host smart-35b71f00-b999-4d69-871e-beb84ec7cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988631559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1988631559
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2910182815
Short name T41
Test name
Test status
Simulation time 424171001 ps
CPU time 2.71 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 214304 kb
Host smart-e1718ab7-6083-4fef-a261-f72ae44d1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910182815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2910182815
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3351844775
Short name T694
Test name
Test status
Simulation time 107781559 ps
CPU time 2.89 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 216116 kb
Host smart-73f80889-0e4f-44f0-a237-481de341c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351844775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3351844775
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.507356490
Short name T240
Test name
Test status
Simulation time 335589992 ps
CPU time 10.19 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:18 PM PDT 24
Peak memory 214308 kb
Host smart-020082a3-450c-4302-b632-28ba84583347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507356490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.507356490
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3607912535
Short name T345
Test name
Test status
Simulation time 597641687 ps
CPU time 5 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:15 PM PDT 24
Peak memory 207944 kb
Host smart-48a734ad-c90f-488d-a2fc-62aeda36d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607912535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3607912535
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3114973611
Short name T379
Test name
Test status
Simulation time 59430240 ps
CPU time 2.49 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 207032 kb
Host smart-eb3fa44c-6b19-49ad-9f29-e0e9c1d934f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114973611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3114973611
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.190473130
Short name T386
Test name
Test status
Simulation time 751480793 ps
CPU time 5.12 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 207832 kb
Host smart-857ed03c-05db-4e5e-980f-1914ef6d07b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190473130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.190473130
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4242477099
Short name T693
Test name
Test status
Simulation time 346866543 ps
CPU time 3.08 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 206964 kb
Host smart-dc1fb0a2-ea61-4ab0-b8c4-495eca6f4727
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242477099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4242477099
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1428746104
Short name T256
Test name
Test status
Simulation time 156258467 ps
CPU time 4.07 seconds
Started Jul 04 06:48:09 PM PDT 24
Finished Jul 04 06:48:13 PM PDT 24
Peak memory 215280 kb
Host smart-86d02018-3310-4961-872d-d2428e6a3b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428746104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1428746104
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3511633528
Short name T411
Test name
Test status
Simulation time 49665340 ps
CPU time 2.4 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:12 PM PDT 24
Peak memory 207968 kb
Host smart-8151cfb6-495e-4f15-b927-dbcec21d9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511633528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3511633528
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1821739764
Short name T71
Test name
Test status
Simulation time 2532235261 ps
CPU time 50.36 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 222608 kb
Host smart-b1b7fbbf-ed46-493d-a88d-a5329861e5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821739764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1821739764
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3156495119
Short name T703
Test name
Test status
Simulation time 371430081 ps
CPU time 22.14 seconds
Started Jul 04 06:48:10 PM PDT 24
Finished Jul 04 06:48:32 PM PDT 24
Peak memory 222860 kb
Host smart-1727d62b-66c4-48c2-8f53-1556f9b1efa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156495119 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3156495119
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3427494175
Short name T493
Test name
Test status
Simulation time 54950694 ps
CPU time 2.66 seconds
Started Jul 04 06:48:11 PM PDT 24
Finished Jul 04 06:48:14 PM PDT 24
Peak memory 210076 kb
Host smart-68e05fb4-3adf-4e0f-91da-0181b6921d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427494175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3427494175
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3535279939
Short name T433
Test name
Test status
Simulation time 12768481 ps
CPU time 0.86 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:17 PM PDT 24
Peak memory 205988 kb
Host smart-92f894d9-0dd2-438e-b1af-80e5c47c3896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535279939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3535279939
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2353513233
Short name T270
Test name
Test status
Simulation time 263606818 ps
CPU time 13.84 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:31 PM PDT 24
Peak memory 214312 kb
Host smart-438511b5-9337-49d6-9766-c856a3006b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353513233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2353513233
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1857652332
Short name T593
Test name
Test status
Simulation time 301198474 ps
CPU time 4.94 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:23 PM PDT 24
Peak memory 214760 kb
Host smart-bddea670-fe0f-45c7-9fa1-e1b8e5ca7907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857652332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1857652332
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1167557986
Short name T415
Test name
Test status
Simulation time 387946640 ps
CPU time 2.8 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 214356 kb
Host smart-fc675149-4b28-4b58-90c6-614b8ffbd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167557986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1167557986
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3725713253
Short name T294
Test name
Test status
Simulation time 190010454 ps
CPU time 2.19 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 214348 kb
Host smart-4cde3abb-4bd6-4afa-af37-95ea88b76d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725713253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3725713253
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1044667821
Short name T910
Test name
Test status
Simulation time 48707372 ps
CPU time 1.71 seconds
Started Jul 04 06:48:14 PM PDT 24
Finished Jul 04 06:48:16 PM PDT 24
Peak memory 214276 kb
Host smart-29c8113c-10e1-4fc5-926d-0a94bcebf968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044667821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1044667821
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3620713610
Short name T851
Test name
Test status
Simulation time 48557347 ps
CPU time 3.35 seconds
Started Jul 04 06:48:13 PM PDT 24
Finished Jul 04 06:48:16 PM PDT 24
Peak memory 209848 kb
Host smart-9a071cd8-dfb3-4fc9-89bf-4d34a0985443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620713610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3620713610
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2228718258
Short name T904
Test name
Test status
Simulation time 226456550 ps
CPU time 5.04 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 208672 kb
Host smart-7be227a0-78ff-49b0-b71d-c96858d2bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228718258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2228718258
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1959914481
Short name T542
Test name
Test status
Simulation time 49862503 ps
CPU time 2.81 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 206940 kb
Host smart-e098d482-6583-4250-afbc-7ac9e905621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959914481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1959914481
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2123643905
Short name T646
Test name
Test status
Simulation time 170360713 ps
CPU time 4.94 seconds
Started Jul 04 06:48:15 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 208748 kb
Host smart-15c1261f-c480-4d8d-8104-4051f8fc9a54
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123643905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2123643905
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.296201172
Short name T557
Test name
Test status
Simulation time 95196968 ps
CPU time 2.79 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 207056 kb
Host smart-d0a8b049-af4c-471a-be62-17c584e7b089
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296201172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.296201172
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3459513887
Short name T850
Test name
Test status
Simulation time 28986366 ps
CPU time 2.27 seconds
Started Jul 04 06:48:15 PM PDT 24
Finished Jul 04 06:48:17 PM PDT 24
Peak memory 208596 kb
Host smart-e3259db5-23d5-4568-a58f-6251ada93bd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459513887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3459513887
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.452241103
Short name T908
Test name
Test status
Simulation time 3404389246 ps
CPU time 28.8 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 218496 kb
Host smart-927cb212-12b9-4819-b7a4-ce095eb7e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452241103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.452241103
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.886290770
Short name T179
Test name
Test status
Simulation time 990705815 ps
CPU time 2.74 seconds
Started Jul 04 06:48:08 PM PDT 24
Finished Jul 04 06:48:11 PM PDT 24
Peak memory 207172 kb
Host smart-5789d2fa-7043-401e-9066-fc4c014fec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886290770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.886290770
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3761099617
Short name T44
Test name
Test status
Simulation time 1521945338 ps
CPU time 6.64 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:24 PM PDT 24
Peak memory 222520 kb
Host smart-6ddf3290-cd10-49cf-92ba-6e05ee296664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761099617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3761099617
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1397445444
Short name T876
Test name
Test status
Simulation time 2021876045 ps
CPU time 5.34 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:24 PM PDT 24
Peak memory 222364 kb
Host smart-818dd65c-e854-446d-99da-ab6d53f64217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397445444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1397445444
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3972843203
Short name T163
Test name
Test status
Simulation time 371640969 ps
CPU time 2.86 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 210112 kb
Host smart-785ef0c3-c030-4076-88cd-843eb254b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972843203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3972843203
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3997376027
Short name T426
Test name
Test status
Simulation time 20941551 ps
CPU time 1 seconds
Started Jul 04 06:48:22 PM PDT 24
Finished Jul 04 06:48:23 PM PDT 24
Peak memory 206176 kb
Host smart-30f67717-d416-4a95-9bc1-d3e3894876d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997376027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3997376027
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1387265624
Short name T230
Test name
Test status
Simulation time 119483607 ps
CPU time 4.4 seconds
Started Jul 04 06:48:15 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 222504 kb
Host smart-8da5c03e-c6b3-427b-9a5f-5829de178d24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387265624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1387265624
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3803841119
Short name T534
Test name
Test status
Simulation time 250369420 ps
CPU time 2.22 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:18 PM PDT 24
Peak memory 207604 kb
Host smart-fd7cb29a-b6d7-4d7e-bb18-fa743bf9f488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803841119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3803841119
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1499195985
Short name T521
Test name
Test status
Simulation time 563119345 ps
CPU time 3.58 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 214416 kb
Host smart-2cca250d-d2a3-4971-b8d3-f4612bdecef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499195985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1499195985
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2913061385
Short name T356
Test name
Test status
Simulation time 97743532 ps
CPU time 2.53 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 214288 kb
Host smart-fc7eab70-40fa-4c16-ac95-6bba44c92422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913061385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2913061385
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1696727122
Short name T890
Test name
Test status
Simulation time 222996292 ps
CPU time 6.23 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:22 PM PDT 24
Peak memory 220196 kb
Host smart-ccc378a1-0eb8-4263-bcad-670579ead7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696727122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1696727122
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2883305832
Short name T254
Test name
Test status
Simulation time 1509865119 ps
CPU time 8.2 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:26 PM PDT 24
Peak memory 218352 kb
Host smart-b8c3e4f1-5159-464c-a6f5-7650e489cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883305832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2883305832
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4088891170
Short name T582
Test name
Test status
Simulation time 528873299 ps
CPU time 4.79 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:22 PM PDT 24
Peak memory 206840 kb
Host smart-5b03e1f8-d70b-4bdc-9eb4-25ebfc3190b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088891170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4088891170
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2650975313
Short name T785
Test name
Test status
Simulation time 1829017818 ps
CPU time 26.73 seconds
Started Jul 04 06:48:18 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 208752 kb
Host smart-c74cd925-5a6b-452c-8016-0ace711d4c0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650975313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2650975313
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4160200252
Short name T235
Test name
Test status
Simulation time 229799025 ps
CPU time 7.13 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:23 PM PDT 24
Peak memory 208056 kb
Host smart-e7fbd003-b58a-4c29-89ea-efcb809d31f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160200252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4160200252
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1707752854
Short name T616
Test name
Test status
Simulation time 653481392 ps
CPU time 3.55 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 207020 kb
Host smart-3be0f36e-4786-403a-acd1-ca62898c25f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707752854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1707752854
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1967742747
Short name T471
Test name
Test status
Simulation time 192187339 ps
CPU time 2.29 seconds
Started Jul 04 06:48:24 PM PDT 24
Finished Jul 04 06:48:26 PM PDT 24
Peak memory 214780 kb
Host smart-e36a7889-d9cb-4cf7-9b97-9c529fa75e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967742747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1967742747
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1403869502
Short name T575
Test name
Test status
Simulation time 1232965118 ps
CPU time 5.72 seconds
Started Jul 04 06:48:17 PM PDT 24
Finished Jul 04 06:48:22 PM PDT 24
Peak memory 206852 kb
Host smart-b08cbb64-2d7b-49c8-a9bb-29d7de61df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403869502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1403869502
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.5371936
Short name T581
Test name
Test status
Simulation time 145093894 ps
CPU time 4.62 seconds
Started Jul 04 06:48:16 PM PDT 24
Finished Jul 04 06:48:21 PM PDT 24
Peak memory 208000 kb
Host smart-e048950e-4837-405f-823a-90b6de64e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5371936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.5371936
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1443408550
Short name T832
Test name
Test status
Simulation time 88989698 ps
CPU time 3.14 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:25 PM PDT 24
Peak memory 209960 kb
Host smart-b6b45622-e2cd-40b2-b152-d6d22c6fb6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443408550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1443408550
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1176589208
Short name T430
Test name
Test status
Simulation time 22295692 ps
CPU time 0.87 seconds
Started Jul 04 06:48:29 PM PDT 24
Finished Jul 04 06:48:30 PM PDT 24
Peak memory 206028 kb
Host smart-f04c090a-2c4f-441e-82ac-bd080979305e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176589208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1176589208
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3512310600
Short name T31
Test name
Test status
Simulation time 563313235 ps
CPU time 5.09 seconds
Started Jul 04 06:48:32 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 221636 kb
Host smart-3ddff3fc-ef70-4aea-b1c2-ac26967fcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512310600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3512310600
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.711330439
Short name T218
Test name
Test status
Simulation time 105321268 ps
CPU time 4.06 seconds
Started Jul 04 06:48:22 PM PDT 24
Finished Jul 04 06:48:26 PM PDT 24
Peak memory 219808 kb
Host smart-501d4256-a656-425e-a8f3-e1c4b01e4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711330439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.711330439
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2000214817
Short name T265
Test name
Test status
Simulation time 94075142 ps
CPU time 3.16 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:24 PM PDT 24
Peak memory 214296 kb
Host smart-c06bc33f-a6ee-470b-89ef-cbf6929e7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000214817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2000214817
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3550887162
Short name T642
Test name
Test status
Simulation time 77505250 ps
CPU time 2.95 seconds
Started Jul 04 06:48:22 PM PDT 24
Finished Jul 04 06:48:25 PM PDT 24
Peak memory 218672 kb
Host smart-c0f1a446-ff43-4a6b-9c3d-598b67b77629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550887162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3550887162
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.404255526
Short name T221
Test name
Test status
Simulation time 1857412951 ps
CPU time 31.01 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 209528 kb
Host smart-d13d9daa-9547-409c-9528-c011c6659a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404255526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.404255526
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.831933815
Short name T844
Test name
Test status
Simulation time 653637941 ps
CPU time 12.23 seconds
Started Jul 04 06:48:20 PM PDT 24
Finished Jul 04 06:48:33 PM PDT 24
Peak memory 207988 kb
Host smart-ec6d9e37-1af3-497b-a5ab-7509c17e7a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831933815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.831933815
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.70022113
Short name T445
Test name
Test status
Simulation time 372939302 ps
CPU time 7.9 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:29 PM PDT 24
Peak memory 208764 kb
Host smart-b2a188d1-af15-486f-a746-cc3d1eb5fca8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70022113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.70022113
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2108928763
Short name T558
Test name
Test status
Simulation time 134759110 ps
CPU time 3.77 seconds
Started Jul 04 06:48:21 PM PDT 24
Finished Jul 04 06:48:25 PM PDT 24
Peak memory 208448 kb
Host smart-7a85233e-3bb5-49bf-9f8f-887d1348602d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108928763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2108928763
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3436274196
Short name T506
Test name
Test status
Simulation time 2082220909 ps
CPU time 19.74 seconds
Started Jul 04 06:48:24 PM PDT 24
Finished Jul 04 06:48:44 PM PDT 24
Peak memory 208276 kb
Host smart-f95be438-3081-4dad-bd2a-a1b9eda2eace
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436274196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3436274196
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1957744508
Short name T721
Test name
Test status
Simulation time 226870165 ps
CPU time 3.01 seconds
Started Jul 04 06:48:30 PM PDT 24
Finished Jul 04 06:48:33 PM PDT 24
Peak memory 210076 kb
Host smart-f91ed097-c8ca-4a1e-bea0-6fc5c9bd4398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957744508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1957744508
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3777791906
Short name T425
Test name
Test status
Simulation time 52385687 ps
CPU time 2.31 seconds
Started Jul 04 06:48:20 PM PDT 24
Finished Jul 04 06:48:23 PM PDT 24
Peak memory 208040 kb
Host smart-79d005a8-9a0e-477a-81cf-e9ee4c66b819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777791906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3777791906
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.456683471
Short name T123
Test name
Test status
Simulation time 927588641 ps
CPU time 8.81 seconds
Started Jul 04 06:48:30 PM PDT 24
Finished Jul 04 06:48:38 PM PDT 24
Peak memory 216928 kb
Host smart-f8a9ba39-4919-4e11-bce2-cd6bdddc3981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456683471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.456683471
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.173006103
Short name T797
Test name
Test status
Simulation time 289985703 ps
CPU time 8.57 seconds
Started Jul 04 06:48:22 PM PDT 24
Finished Jul 04 06:48:31 PM PDT 24
Peak memory 209300 kb
Host smart-c393302b-85fa-49d6-a7c7-57e996d1a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173006103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.173006103
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1167817419
Short name T843
Test name
Test status
Simulation time 155463125 ps
CPU time 2.4 seconds
Started Jul 04 06:48:29 PM PDT 24
Finished Jul 04 06:48:32 PM PDT 24
Peak memory 210652 kb
Host smart-30861261-dad7-459b-b5b5-2955c82cc033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167817419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1167817419
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1290334775
Short name T417
Test name
Test status
Simulation time 45418570 ps
CPU time 0.88 seconds
Started Jul 04 06:48:35 PM PDT 24
Finished Jul 04 06:48:36 PM PDT 24
Peak memory 206016 kb
Host smart-377ac366-24cc-486e-8194-cf4724179228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290334775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1290334775
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3891050343
Short name T392
Test name
Test status
Simulation time 451010687 ps
CPU time 4.24 seconds
Started Jul 04 06:48:29 PM PDT 24
Finished Jul 04 06:48:34 PM PDT 24
Peak memory 214320 kb
Host smart-b7f6d34a-ee1e-4178-94c3-f311c05c8d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891050343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3891050343
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3506137831
Short name T606
Test name
Test status
Simulation time 169769297 ps
CPU time 5.01 seconds
Started Jul 04 06:48:33 PM PDT 24
Finished Jul 04 06:48:38 PM PDT 24
Peak memory 211192 kb
Host smart-9fd47679-30c0-47cd-99f5-0a0217027449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506137831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3506137831
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1628318073
Short name T234
Test name
Test status
Simulation time 274664492 ps
CPU time 2.51 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 214328 kb
Host smart-03aa42db-9ec5-49b6-92c1-bde98dfaf0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628318073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1628318073
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1060422020
Short name T791
Test name
Test status
Simulation time 129534833 ps
CPU time 2.62 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 222484 kb
Host smart-a54af0ce-4e2e-48c6-95af-0596aed07a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060422020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1060422020
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2384797083
Short name T249
Test name
Test status
Simulation time 398475953 ps
CPU time 4.35 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:39 PM PDT 24
Peak memory 214288 kb
Host smart-ecdccca4-e57f-4976-8e10-77e0aa92cbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384797083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2384797083
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2932710533
Short name T554
Test name
Test status
Simulation time 148543206 ps
CPU time 1.78 seconds
Started Jul 04 06:48:35 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 206132 kb
Host smart-6482c800-3fce-4d2d-a2c9-58141345ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932710533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2932710533
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1306837829
Short name T549
Test name
Test status
Simulation time 2005605933 ps
CPU time 9.48 seconds
Started Jul 04 06:48:29 PM PDT 24
Finished Jul 04 06:48:39 PM PDT 24
Peak memory 207532 kb
Host smart-d5f41737-13d5-4171-bfdc-52fbcaed0ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306837829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1306837829
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1651082677
Short name T623
Test name
Test status
Simulation time 242944590 ps
CPU time 3.64 seconds
Started Jul 04 06:48:30 PM PDT 24
Finished Jul 04 06:48:33 PM PDT 24
Peak memory 206824 kb
Host smart-d81fbb53-9931-441e-a02c-92793053ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651082677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1651082677
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3361345556
Short name T758
Test name
Test status
Simulation time 1342752120 ps
CPU time 25.04 seconds
Started Jul 04 06:48:28 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 208272 kb
Host smart-c6740c1b-4ed5-4d14-b4ed-6ab9fff6885f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361345556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3361345556
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.844321316
Short name T633
Test name
Test status
Simulation time 1551980763 ps
CPU time 6.74 seconds
Started Jul 04 06:48:30 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 208780 kb
Host smart-9bb29856-4860-4eab-8d0a-c7747f435542
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844321316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.844321316
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1352140145
Short name T744
Test name
Test status
Simulation time 82858667 ps
CPU time 3.42 seconds
Started Jul 04 06:48:33 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 206956 kb
Host smart-92cf0d2c-e229-4f4c-81ed-08286fcb8179
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352140145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1352140145
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1440243202
Short name T920
Test name
Test status
Simulation time 1422284521 ps
CPU time 8.89 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 209892 kb
Host smart-2ead1b8c-46f6-4bdf-ac5b-d9edd74e1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440243202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1440243202
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.319307258
Short name T796
Test name
Test status
Simulation time 3811410838 ps
CPU time 20.31 seconds
Started Jul 04 06:48:30 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 208652 kb
Host smart-a7ea71c6-788a-4d4b-8bb0-a3bd61852e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319307258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.319307258
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.369196526
Short name T705
Test name
Test status
Simulation time 137087919 ps
CPU time 7.33 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:42 PM PDT 24
Peak memory 222552 kb
Host smart-655761d9-567d-4e81-a727-fc239ed2599d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369196526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.369196526
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3427814592
Short name T239
Test name
Test status
Simulation time 129838297 ps
CPU time 5.09 seconds
Started Jul 04 06:48:38 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 207716 kb
Host smart-03c01b1b-b33f-4a30-877a-fff5e8a563f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427814592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3427814592
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2372230120
Short name T161
Test name
Test status
Simulation time 312434673 ps
CPU time 2.89 seconds
Started Jul 04 06:48:35 PM PDT 24
Finished Jul 04 06:48:38 PM PDT 24
Peak memory 209856 kb
Host smart-a83f8e82-7eef-4fc5-a640-a830b9eb664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372230120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2372230120
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.889159244
Short name T866
Test name
Test status
Simulation time 16713890 ps
CPU time 0.94 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 206084 kb
Host smart-6237a383-5590-4918-846c-42ff4f46f92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889159244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.889159244
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3028052220
Short name T805
Test name
Test status
Simulation time 60536123 ps
CPU time 2.96 seconds
Started Jul 04 06:48:35 PM PDT 24
Finished Jul 04 06:48:38 PM PDT 24
Peak memory 221776 kb
Host smart-d4fe717a-f569-4ebc-a753-2a2cc5126512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028052220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3028052220
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1612321506
Short name T897
Test name
Test status
Simulation time 100224061 ps
CPU time 1.69 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:36 PM PDT 24
Peak memory 207436 kb
Host smart-f548f20a-f95a-42f8-9e7a-b139e969aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612321506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1612321506
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3977229832
Short name T781
Test name
Test status
Simulation time 274091113 ps
CPU time 6.82 seconds
Started Jul 04 06:48:35 PM PDT 24
Finished Jul 04 06:48:42 PM PDT 24
Peak memory 208556 kb
Host smart-5f8a2541-cf25-4e95-9232-39d8ec187dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977229832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3977229832
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2417821393
Short name T573
Test name
Test status
Simulation time 2889778532 ps
CPU time 10.07 seconds
Started Jul 04 06:48:33 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 222472 kb
Host smart-d50251bb-d882-4442-bdf3-25b8353e6fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417821393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2417821393
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2153321009
Short name T681
Test name
Test status
Simulation time 385761594 ps
CPU time 5.19 seconds
Started Jul 04 06:48:38 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 220336 kb
Host smart-fe95cc79-8924-40a2-976c-b105086292a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153321009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2153321009
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1688218123
Short name T508
Test name
Test status
Simulation time 7888749581 ps
CPU time 28.53 seconds
Started Jul 04 06:48:38 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 218252 kb
Host smart-6bf5d3d0-c9c0-4d86-a48e-383b7cdd6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688218123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1688218123
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.251392501
Short name T782
Test name
Test status
Simulation time 1807142529 ps
CPU time 19.65 seconds
Started Jul 04 06:48:38 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 208120 kb
Host smart-861c10f1-66c1-4d02-8240-7fcfd036aaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251392501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.251392501
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1691150164
Short name T734
Test name
Test status
Simulation time 195726208 ps
CPU time 4.75 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:39 PM PDT 24
Peak memory 208960 kb
Host smart-56bb0cb4-13af-45b8-adb6-76ceeb6ca3a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691150164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1691150164
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1392065611
Short name T849
Test name
Test status
Simulation time 3078484429 ps
CPU time 7.06 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:41 PM PDT 24
Peak memory 207964 kb
Host smart-7972bf13-aa17-414c-a000-519d881c7dbb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392065611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1392065611
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1564505750
Short name T925
Test name
Test status
Simulation time 527844706 ps
CPU time 4.45 seconds
Started Jul 04 06:48:33 PM PDT 24
Finished Jul 04 06:48:38 PM PDT 24
Peak memory 208544 kb
Host smart-284e6ad9-4ced-4f5e-b5fa-806a66dcec0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564505750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1564505750
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.315787625
Short name T802
Test name
Test status
Simulation time 201819131 ps
CPU time 4.35 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:46 PM PDT 24
Peak memory 218352 kb
Host smart-ed863fc2-f99b-43c8-af1d-353546ac9846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315787625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.315787625
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3781390240
Short name T451
Test name
Test status
Simulation time 1022175550 ps
CPU time 9.87 seconds
Started Jul 04 06:48:37 PM PDT 24
Finished Jul 04 06:48:47 PM PDT 24
Peak memory 208304 kb
Host smart-3dbedae8-3544-49e6-8504-ab1452a2d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781390240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3781390240
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3495189212
Short name T612
Test name
Test status
Simulation time 205625183 ps
CPU time 3.06 seconds
Started Jul 04 06:48:34 PM PDT 24
Finished Jul 04 06:48:37 PM PDT 24
Peak memory 208140 kb
Host smart-d15f56fd-88bf-4488-87a6-f9f7f3507df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495189212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3495189212
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2911441542
Short name T365
Test name
Test status
Simulation time 150065521 ps
CPU time 2.16 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 210156 kb
Host smart-3a1f8354-3cc5-48a3-96ff-f7cd9b888e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911441542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2911441542
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.33658568
Short name T827
Test name
Test status
Simulation time 13182983 ps
CPU time 0.88 seconds
Started Jul 04 06:48:40 PM PDT 24
Finished Jul 04 06:48:42 PM PDT 24
Peak memory 205972 kb
Host smart-5161d8b8-4aa5-4868-bd18-6c6a894548bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33658568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.33658568
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1051732901
Short name T404
Test name
Test status
Simulation time 66714135 ps
CPU time 2.61 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:48:46 PM PDT 24
Peak memory 214924 kb
Host smart-12252bd1-e43f-4105-aa15-5008d5b53ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051732901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1051732901
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3275079878
Short name T46
Test name
Test status
Simulation time 100925311 ps
CPU time 2.08 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 207708 kb
Host smart-4b5a73fe-908e-4ec2-8fa4-59e252002b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275079878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3275079878
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3194341085
Short name T92
Test name
Test status
Simulation time 7203439807 ps
CPU time 36.74 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:49:19 PM PDT 24
Peak memory 222552 kb
Host smart-a30a12d8-4149-4f87-beae-c23dc604b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194341085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3194341085
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4278013575
Short name T598
Test name
Test status
Simulation time 68622775 ps
CPU time 2.09 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:44 PM PDT 24
Peak memory 214884 kb
Host smart-7f66344e-ba33-4023-9b34-0ac6d5df38f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278013575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4278013575
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4020507657
Short name T250
Test name
Test status
Simulation time 79191187 ps
CPU time 3.86 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 210576 kb
Host smart-7cc93410-1291-4ed0-8adf-b6c8f113304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020507657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4020507657
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3787518332
Short name T755
Test name
Test status
Simulation time 33474488 ps
CPU time 2.31 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:48:44 PM PDT 24
Peak memory 206984 kb
Host smart-3d75a579-3f51-4a7e-88e2-f61c36a86060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787518332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3787518332
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3923152761
Short name T563
Test name
Test status
Simulation time 205312909 ps
CPU time 2.98 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:48:44 PM PDT 24
Peak memory 207064 kb
Host smart-1ae57532-06e2-4b1e-974a-ef46f6943800
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923152761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3923152761
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3436764650
Short name T629
Test name
Test status
Simulation time 2452446970 ps
CPU time 26.59 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 208224 kb
Host smart-6c482d0b-07e2-4d7e-9784-9304383bd9dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436764650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3436764650
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1581680258
Short name T599
Test name
Test status
Simulation time 90477106 ps
CPU time 3.66 seconds
Started Jul 04 06:48:43 PM PDT 24
Finished Jul 04 06:48:47 PM PDT 24
Peak memory 206920 kb
Host smart-587b9dbf-3fe2-4232-bf52-6a2fe85c3db9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581680258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1581680258
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.39396387
Short name T806
Test name
Test status
Simulation time 583248347 ps
CPU time 3.58 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:45 PM PDT 24
Peak memory 218492 kb
Host smart-93000943-80a8-45bc-867a-191d8d48c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39396387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.39396387
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1900797327
Short name T732
Test name
Test status
Simulation time 693238369 ps
CPU time 5.01 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:47 PM PDT 24
Peak memory 208372 kb
Host smart-303bac2b-ffd7-40d9-8a86-e76affb69b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900797327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1900797327
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3392944642
Short name T896
Test name
Test status
Simulation time 8002602899 ps
CPU time 82.29 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:50:04 PM PDT 24
Peak memory 217688 kb
Host smart-93da033f-48dd-4886-9558-3d9eb471672c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392944642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3392944642
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2960886575
Short name T177
Test name
Test status
Simulation time 1209703647 ps
CPU time 4.9 seconds
Started Jul 04 06:48:42 PM PDT 24
Finished Jul 04 06:48:47 PM PDT 24
Peak memory 207296 kb
Host smart-b6594db4-deb1-42d1-bfdf-cbc22fa67d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960886575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2960886575
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1355625593
Short name T875
Test name
Test status
Simulation time 41317767 ps
CPU time 2.38 seconds
Started Jul 04 06:48:41 PM PDT 24
Finished Jul 04 06:48:43 PM PDT 24
Peak memory 210076 kb
Host smart-89311f54-de0b-455b-b4e9-8d093a5abfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355625593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1355625593
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3365161140
Short name T835
Test name
Test status
Simulation time 29679732 ps
CPU time 0.68 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 206216 kb
Host smart-a5d7e811-752c-4d69-842b-f8230737652b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365161140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3365161140
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1755302890
Short name T401
Test name
Test status
Simulation time 208731656 ps
CPU time 3.78 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:54 PM PDT 24
Peak memory 214368 kb
Host smart-e602595c-48a6-473d-b2e5-1989d8fa8136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755302890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1755302890
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1164363143
Short name T341
Test name
Test status
Simulation time 347997192 ps
CPU time 2.56 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 209868 kb
Host smart-65a6c8ef-1c89-4287-ac33-e0b6884ab969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164363143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1164363143
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1399142989
Short name T423
Test name
Test status
Simulation time 179090207 ps
CPU time 1.79 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 208200 kb
Host smart-1901b259-a9c0-4f09-aaac-234226c06b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399142989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1399142989
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4101948465
Short name T660
Test name
Test status
Simulation time 203746395 ps
CPU time 4.74 seconds
Started Jul 04 06:48:47 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 214396 kb
Host smart-6a46c36a-2b1c-4187-9740-946b3c9ecad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101948465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4101948465
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2437427369
Short name T84
Test name
Test status
Simulation time 54986558 ps
CPU time 2.11 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 222360 kb
Host smart-1d62afd0-41ac-4dad-924d-0af35c11dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437427369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2437427369
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2718909143
Short name T211
Test name
Test status
Simulation time 215943086 ps
CPU time 3.13 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 214344 kb
Host smart-85b7ec11-a729-4927-8b12-fca9c03f70dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718909143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2718909143
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2661857094
Short name T302
Test name
Test status
Simulation time 1518203680 ps
CPU time 5.51 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:55 PM PDT 24
Peak memory 214440 kb
Host smart-b13dce15-a9c9-4d1b-884c-acdde5921638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661857094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2661857094
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2537750665
Short name T449
Test name
Test status
Simulation time 527631534 ps
CPU time 13.68 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:49:03 PM PDT 24
Peak memory 208712 kb
Host smart-85814d7e-e825-4787-998b-41c6076bd220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537750665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2537750665
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.862847553
Short name T834
Test name
Test status
Simulation time 2315393540 ps
CPU time 22.65 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:49:13 PM PDT 24
Peak memory 208220 kb
Host smart-ca9d9e73-324a-4173-a602-3865e16cffe0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862847553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.862847553
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2722078523
Short name T564
Test name
Test status
Simulation time 164875958 ps
CPU time 5.36 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 207844 kb
Host smart-120268ad-c8e9-4735-afb9-980bb028ff9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722078523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2722078523
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2186351262
Short name T650
Test name
Test status
Simulation time 2302394286 ps
CPU time 6.27 seconds
Started Jul 04 06:48:51 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 209060 kb
Host smart-bf49f799-a08a-4a4a-be91-ac0123a2194f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186351262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2186351262
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1435661739
Short name T444
Test name
Test status
Simulation time 95439301 ps
CPU time 1.65 seconds
Started Jul 04 06:48:52 PM PDT 24
Finished Jul 04 06:48:54 PM PDT 24
Peak memory 207440 kb
Host smart-63a304b6-6c63-4441-89a5-cb8e8203f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435661739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1435661739
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1214900871
Short name T501
Test name
Test status
Simulation time 865069869 ps
CPU time 3.33 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 208572 kb
Host smart-8cfdba16-0321-4a7d-9f22-698e5c35aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214900871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1214900871
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.587208423
Short name T169
Test name
Test status
Simulation time 646868815 ps
CPU time 26.03 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:49:17 PM PDT 24
Peak memory 222616 kb
Host smart-758459ca-edae-4b51-aa8b-f3b8de0f4d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587208423 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.587208423
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2003750762
Short name T376
Test name
Test status
Simulation time 33008083 ps
CPU time 2.43 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:51 PM PDT 24
Peak memory 208300 kb
Host smart-1188c91f-da12-4038-a8c1-33b121db31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003750762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2003750762
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1163144060
Short name T152
Test name
Test status
Simulation time 446790358 ps
CPU time 2.07 seconds
Started Jul 04 06:48:47 PM PDT 24
Finished Jul 04 06:48:49 PM PDT 24
Peak memory 210152 kb
Host smart-3d262296-b2b6-4eb1-9834-83e7f627560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163144060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1163144060
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.292932701
Short name T749
Test name
Test status
Simulation time 18250405 ps
CPU time 0.8 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 206012 kb
Host smart-96388df1-3f8d-4090-a02c-25d7db1076a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292932701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.292932701
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4040994040
Short name T733
Test name
Test status
Simulation time 178874544 ps
CPU time 2.29 seconds
Started Jul 04 06:48:51 PM PDT 24
Finished Jul 04 06:48:54 PM PDT 24
Peak memory 221424 kb
Host smart-669362ac-1ef1-4944-9270-7403ed9babd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040994040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4040994040
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.247967044
Short name T675
Test name
Test status
Simulation time 345268180 ps
CPU time 2.19 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 218292 kb
Host smart-3003658d-aea4-4eb6-8535-aaed26a0630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247967044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.247967044
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2274278465
Short name T89
Test name
Test status
Simulation time 62973764 ps
CPU time 3.52 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 209124 kb
Host smart-be6d46cb-5238-4f1d-a83d-17a92e9a9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274278465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2274278465
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4049339641
Short name T651
Test name
Test status
Simulation time 94049477 ps
CPU time 2.77 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 205984 kb
Host smart-515ed7af-97cd-4d13-ae1a-023a3452702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049339641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4049339641
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2270131753
Short name T205
Test name
Test status
Simulation time 572969404 ps
CPU time 4.44 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 217880 kb
Host smart-58d8412d-5cd1-49b5-9027-e32984014944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270131753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2270131753
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4238989367
Short name T826
Test name
Test status
Simulation time 128662274 ps
CPU time 3.16 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 209432 kb
Host smart-e9e8a760-f69a-46d3-bc51-802862a4052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238989367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4238989367
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.48771782
Short name T879
Test name
Test status
Simulation time 94950532 ps
CPU time 2.58 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 208224 kb
Host smart-3f6be542-738d-44ee-ae8d-f7250491aad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48771782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.48771782
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.464900978
Short name T878
Test name
Test status
Simulation time 145351059 ps
CPU time 2.49 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 207192 kb
Host smart-3902eb79-dcd7-467f-b77b-c6cdeefa996e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464900978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.464900978
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.206507084
Short name T915
Test name
Test status
Simulation time 119416223 ps
CPU time 3.93 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 206896 kb
Host smart-725d3b9c-238d-4975-bf64-fd86c90ca532
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206507084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.206507084
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3560997477
Short name T765
Test name
Test status
Simulation time 282324677 ps
CPU time 2.51 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:51 PM PDT 24
Peak memory 208524 kb
Host smart-c6d273df-a8ff-44b8-bfac-8a13b9ef68bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560997477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3560997477
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3662254905
Short name T729
Test name
Test status
Simulation time 439288616 ps
CPU time 3.85 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 214300 kb
Host smart-36d691ee-f77f-4ee0-8c60-f426d7c03173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662254905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3662254905
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.446026701
Short name T427
Test name
Test status
Simulation time 54323304 ps
CPU time 2.3 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 207892 kb
Host smart-5af00828-b751-4304-acc4-f94078b9f8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446026701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.446026701
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4228576980
Short name T902
Test name
Test status
Simulation time 746062463 ps
CPU time 18.15 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 208804 kb
Host smart-3280c24b-3915-42fa-8d27-a1d027187f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228576980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4228576980
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1026918703
Short name T776
Test name
Test status
Simulation time 178337825 ps
CPU time 2.78 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 210316 kb
Host smart-b3d34464-25e4-4baa-8050-dbb76f3114aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026918703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1026918703
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1815210107
Short name T420
Test name
Test status
Simulation time 156419317 ps
CPU time 0.91 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:31 PM PDT 24
Peak memory 206264 kb
Host smart-2d7970e2-1d0c-4ce1-9690-947a064cb94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815210107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1815210107
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2258885800
Short name T25
Test name
Test status
Simulation time 191702506 ps
CPU time 2.13 seconds
Started Jul 04 06:46:21 PM PDT 24
Finished Jul 04 06:46:23 PM PDT 24
Peak memory 217676 kb
Host smart-575cb2bc-d7ce-4918-ae47-84ef064cead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258885800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2258885800
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1869682689
Short name T838
Test name
Test status
Simulation time 27858168 ps
CPU time 1.71 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:25 PM PDT 24
Peak memory 209328 kb
Host smart-77bc1d54-dcd2-489a-a5bf-25bc30e42167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869682689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1869682689
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2340993072
Short name T442
Test name
Test status
Simulation time 28571071 ps
CPU time 2.05 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:25 PM PDT 24
Peak memory 214384 kb
Host smart-ff7d7d7c-f5ff-4f71-be35-91ef3c397a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340993072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2340993072
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2949128253
Short name T359
Test name
Test status
Simulation time 445312567 ps
CPU time 5.12 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:29 PM PDT 24
Peak memory 214264 kb
Host smart-bb024e23-bbe2-4c58-b678-74ddea452e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949128253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2949128253
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.3929460616
Short name T351
Test name
Test status
Simulation time 105968049 ps
CPU time 3.72 seconds
Started Jul 04 06:46:21 PM PDT 24
Finished Jul 04 06:46:25 PM PDT 24
Peak memory 209472 kb
Host smart-9720bd24-660a-469d-a4f1-755c7a6cae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929460616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3929460616
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.897534595
Short name T9
Test name
Test status
Simulation time 1081273845 ps
CPU time 14.07 seconds
Started Jul 04 06:46:32 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 232380 kb
Host smart-224f1b39-c62c-42e6-9495-a047db26816f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897534595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.897534595
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1158301776
Short name T764
Test name
Test status
Simulation time 55789855 ps
CPU time 3.08 seconds
Started Jul 04 06:46:25 PM PDT 24
Finished Jul 04 06:46:29 PM PDT 24
Peak memory 206964 kb
Host smart-11b81986-7e49-4806-b9b5-947972739a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158301776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1158301776
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2128840428
Short name T647
Test name
Test status
Simulation time 68311772 ps
CPU time 3.02 seconds
Started Jul 04 06:46:26 PM PDT 24
Finished Jul 04 06:46:29 PM PDT 24
Peak memory 208096 kb
Host smart-221422c9-a18d-421a-bfb7-30b795468867
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128840428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2128840428
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4269428023
Short name T461
Test name
Test status
Simulation time 887666783 ps
CPU time 13.21 seconds
Started Jul 04 06:46:22 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 208776 kb
Host smart-bdbd0821-38c6-468d-a4a5-d40ad30f5b3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269428023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4269428023
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2894228261
Short name T641
Test name
Test status
Simulation time 37505643 ps
CPU time 1.81 seconds
Started Jul 04 06:46:25 PM PDT 24
Finished Jul 04 06:46:27 PM PDT 24
Peak memory 206952 kb
Host smart-0ad13980-aaed-43c6-991c-f85ac03a9cdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894228261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2894228261
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1396996191
Short name T439
Test name
Test status
Simulation time 375443887 ps
CPU time 2.24 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:26 PM PDT 24
Peak memory 209088 kb
Host smart-e9918552-101b-470e-b159-8c991faa8dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396996191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1396996191
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4137565445
Short name T474
Test name
Test status
Simulation time 249124328 ps
CPU time 2.41 seconds
Started Jul 04 06:46:23 PM PDT 24
Finished Jul 04 06:46:26 PM PDT 24
Peak memory 206880 kb
Host smart-8ee75cef-8d10-4b83-bb62-c8e70c556c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137565445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4137565445
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3274351099
Short name T503
Test name
Test status
Simulation time 337913165 ps
CPU time 4.39 seconds
Started Jul 04 06:46:22 PM PDT 24
Finished Jul 04 06:46:27 PM PDT 24
Peak memory 207908 kb
Host smart-6c5a84fd-00d9-48f2-9a8a-0fba85ce7cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274351099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3274351099
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2231155139
Short name T706
Test name
Test status
Simulation time 52734467 ps
CPU time 1.52 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:32 PM PDT 24
Peak memory 208608 kb
Host smart-72978d1d-2046-44f4-b551-29d75b6564e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231155139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2231155139
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3372825109
Short name T513
Test name
Test status
Simulation time 44758313 ps
CPU time 0.75 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 206008 kb
Host smart-b082ee39-a260-4f27-9d4e-0a8c2d2ffb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372825109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3372825109
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4151897201
Short name T215
Test name
Test status
Simulation time 150662994 ps
CPU time 8.54 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 214356 kb
Host smart-a3a6e0d0-221e-4723-9b00-26987423eb8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151897201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4151897201
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3987478417
Short name T30
Test name
Test status
Simulation time 116654593 ps
CPU time 1.53 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 214700 kb
Host smart-7f525cde-04a3-4641-9cf3-c39545e4d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987478417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3987478417
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1214592409
Short name T59
Test name
Test status
Simulation time 149021879 ps
CPU time 2.29 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 207880 kb
Host smart-2835c2c9-888f-4e9d-b5dc-bcebf92c0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214592409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1214592409
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.610616764
Short name T296
Test name
Test status
Simulation time 227538491 ps
CPU time 4.01 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 214248 kb
Host smart-cf14d70f-c551-4530-b77f-06476e4ec6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610616764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.610616764
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3050364915
Short name T761
Test name
Test status
Simulation time 313964196 ps
CPU time 4.92 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 214396 kb
Host smart-d6e8df25-f622-456e-9d61-0b12ed6a7e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050364915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3050364915
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4044597099
Short name T743
Test name
Test status
Simulation time 129104167 ps
CPU time 5.53 seconds
Started Jul 04 06:48:48 PM PDT 24
Finished Jul 04 06:48:54 PM PDT 24
Peak memory 214312 kb
Host smart-a51431b7-8747-4b07-bada-a53f5049902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044597099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4044597099
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3377120623
Short name T481
Test name
Test status
Simulation time 346884918 ps
CPU time 2.95 seconds
Started Jul 04 06:48:50 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 207044 kb
Host smart-74b55cec-bb83-41ff-ba0b-c32b78699a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377120623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3377120623
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2405025245
Short name T768
Test name
Test status
Simulation time 93396881 ps
CPU time 2.68 seconds
Started Jul 04 06:48:47 PM PDT 24
Finished Jul 04 06:48:50 PM PDT 24
Peak memory 207008 kb
Host smart-ffa05456-7054-4e02-b1a7-c874e2fc07e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405025245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2405025245
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.288696202
Short name T722
Test name
Test status
Simulation time 108684772 ps
CPU time 2.89 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 208888 kb
Host smart-dbe07f7d-fb03-4e4e-8e19-34de070df65a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288696202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.288696202
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1550869228
Short name T708
Test name
Test status
Simulation time 93897572 ps
CPU time 2.11 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 208984 kb
Host smart-7ff75fb0-9f23-47bd-ad47-82b263b455c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550869228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1550869228
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1038636685
Short name T410
Test name
Test status
Simulation time 87621453 ps
CPU time 2.6 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:00 PM PDT 24
Peak memory 208256 kb
Host smart-3826cfcf-463c-4233-b11b-0bfa41e0e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038636685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1038636685
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3498991011
Short name T18
Test name
Test status
Simulation time 104584736 ps
CPU time 3.29 seconds
Started Jul 04 06:48:49 PM PDT 24
Finished Jul 04 06:48:53 PM PDT 24
Peak memory 206952 kb
Host smart-e1f6fa0d-9f3b-49e6-83b4-e4a00c8112c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498991011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3498991011
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3768608343
Short name T238
Test name
Test status
Simulation time 1650560804 ps
CPU time 14.38 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 222440 kb
Host smart-a1fdf13f-d3e4-46a3-a140-13dd936bc2b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768608343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3768608343
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2635661928
Short name T282
Test name
Test status
Simulation time 96578885 ps
CPU time 4.45 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 214348 kb
Host smart-897f4609-fd17-4c4d-97ae-5470c64d496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635661928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2635661928
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2167466800
Short name T574
Test name
Test status
Simulation time 817726672 ps
CPU time 15.14 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:49:10 PM PDT 24
Peak memory 211032 kb
Host smart-46ae8b1f-e255-4ebd-b43b-066eb7362e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167466800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2167466800
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1956571577
Short name T544
Test name
Test status
Simulation time 56246800 ps
CPU time 0.79 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 205960 kb
Host smart-187a0598-f912-42a6-a304-c8e674a30c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956571577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1956571577
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1515469585
Short name T731
Test name
Test status
Simulation time 320982361 ps
CPU time 6.69 seconds
Started Jul 04 06:48:54 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 209776 kb
Host smart-01ba43ff-540d-4fc7-8c5a-cff7e8eefb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515469585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1515469585
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2029475847
Short name T690
Test name
Test status
Simulation time 47263798 ps
CPU time 2.42 seconds
Started Jul 04 06:49:01 PM PDT 24
Finished Jul 04 06:49:04 PM PDT 24
Peak memory 207696 kb
Host smart-86b6174d-9302-4393-b6a1-6330a8e48761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029475847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2029475847
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2057254211
Short name T295
Test name
Test status
Simulation time 398438921 ps
CPU time 3.48 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 214544 kb
Host smart-6821b449-f6f8-4b04-a503-f9d9e9c8f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057254211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2057254211
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1629855123
Short name T903
Test name
Test status
Simulation time 402555048 ps
CPU time 4.34 seconds
Started Jul 04 06:48:54 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 206676 kb
Host smart-adbdc21a-5e70-49d8-9562-e82fc3782a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629855123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1629855123
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1546761079
Short name T197
Test name
Test status
Simulation time 137740120 ps
CPU time 3.93 seconds
Started Jul 04 06:48:55 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 214320 kb
Host smart-0170843f-213e-493f-b018-ed8d4d28f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546761079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1546761079
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1430572169
Short name T456
Test name
Test status
Simulation time 440149519 ps
CPU time 4.64 seconds
Started Jul 04 06:48:58 PM PDT 24
Finished Jul 04 06:49:03 PM PDT 24
Peak memory 214376 kb
Host smart-b909153f-ccd8-4f70-bb10-2a5ccaf46c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430572169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1430572169
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.146957577
Short name T858
Test name
Test status
Simulation time 356912240 ps
CPU time 3.49 seconds
Started Jul 04 06:49:01 PM PDT 24
Finished Jul 04 06:49:05 PM PDT 24
Peak memory 208628 kb
Host smart-26e5f82f-54fe-4287-837e-57644f852a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146957577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.146957577
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.662354777
Short name T719
Test name
Test status
Simulation time 1833058333 ps
CPU time 12.09 seconds
Started Jul 04 06:48:59 PM PDT 24
Finished Jul 04 06:49:11 PM PDT 24
Peak memory 208120 kb
Host smart-bfb9ca7c-a045-4607-ae29-0b62491e37e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662354777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.662354777
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.119726451
Short name T81
Test name
Test status
Simulation time 110877431 ps
CPU time 3.98 seconds
Started Jul 04 06:49:01 PM PDT 24
Finished Jul 04 06:49:05 PM PDT 24
Peak memory 206784 kb
Host smart-0bbd7343-ecd3-4091-bb23-4f67a810ad44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119726451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.119726451
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.697968760
Short name T505
Test name
Test status
Simulation time 4725701559 ps
CPU time 30.05 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:27 PM PDT 24
Peak memory 208048 kb
Host smart-2cc39652-9c6d-4688-a5c6-8178486377a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697968760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.697968760
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3412315205
Short name T682
Test name
Test status
Simulation time 134966287 ps
CPU time 2.22 seconds
Started Jul 04 06:49:00 PM PDT 24
Finished Jul 04 06:49:02 PM PDT 24
Peak memory 215920 kb
Host smart-bb5d8388-9782-4797-991f-7e90e4ff61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412315205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3412315205
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2722843762
Short name T497
Test name
Test status
Simulation time 103873932 ps
CPU time 3.42 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:01 PM PDT 24
Peak memory 206708 kb
Host smart-6268c92a-332f-4b08-9aae-cb338671ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722843762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2722843762
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2240662335
Short name T49
Test name
Test status
Simulation time 801596811 ps
CPU time 28.15 seconds
Started Jul 04 06:48:57 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 222544 kb
Host smart-1cf234e9-eea0-499e-b955-fb725113f93e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240662335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2240662335
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.603150920
Short name T1
Test name
Test status
Simulation time 342382162 ps
CPU time 11.01 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 222624 kb
Host smart-a82bdf3e-71bf-4848-99b8-2cbda1fb3ad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603150920 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.603150920
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4111332972
Short name T424
Test name
Test status
Simulation time 857552961 ps
CPU time 5.97 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:49:02 PM PDT 24
Peak memory 208256 kb
Host smart-51f2a51e-b7da-4c68-a163-1008852d9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111332972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4111332972
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2450933058
Short name T148
Test name
Test status
Simulation time 98021395 ps
CPU time 3.06 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:48:59 PM PDT 24
Peak memory 210264 kb
Host smart-c4309e68-2347-466b-a179-81bb8e6d3430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450933058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2450933058
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2268261871
Short name T853
Test name
Test status
Simulation time 19224004 ps
CPU time 0.74 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 206020 kb
Host smart-47f103b4-98f2-4e47-8611-c90bce8644f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268261871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2268261871
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1942362997
Short name T403
Test name
Test status
Simulation time 227203745 ps
CPU time 3.83 seconds
Started Jul 04 06:49:05 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 214312 kb
Host smart-2a92e413-3864-492f-ad54-59794b83fc27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942362997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1942362997
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1897484287
Short name T207
Test name
Test status
Simulation time 62513362 ps
CPU time 2.48 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:06 PM PDT 24
Peak memory 210196 kb
Host smart-a4aa6a87-384a-4559-a704-81abbd03cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897484287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1897484287
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3760062837
Short name T696
Test name
Test status
Simulation time 963727719 ps
CPU time 3.32 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:49:08 PM PDT 24
Peak memory 209756 kb
Host smart-53ec5fa8-d828-4289-8b94-4fd1f6aefbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760062837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3760062837
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1050723116
Short name T91
Test name
Test status
Simulation time 179905874 ps
CPU time 6.92 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 220900 kb
Host smart-47423e5a-032b-4cbd-8e95-53643e478dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050723116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1050723116
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2002752389
Short name T315
Test name
Test status
Simulation time 309628000 ps
CPU time 4.39 seconds
Started Jul 04 06:49:05 PM PDT 24
Finished Jul 04 06:49:10 PM PDT 24
Peak memory 220784 kb
Host smart-45163f39-8aaa-4904-9b4c-05f7ca4f6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002752389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2002752389
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3287912810
Short name T325
Test name
Test status
Simulation time 107705787 ps
CPU time 5.45 seconds
Started Jul 04 06:49:05 PM PDT 24
Finished Jul 04 06:49:10 PM PDT 24
Peak memory 219080 kb
Host smart-5b2c1bfc-4088-4305-8cf0-496504501b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287912810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3287912810
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.168964642
Short name T217
Test name
Test status
Simulation time 38185339 ps
CPU time 2.58 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 209136 kb
Host smart-2ff041c9-2a93-49a5-840b-0dbb9076dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168964642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.168964642
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4293739549
Short name T845
Test name
Test status
Simulation time 2667752062 ps
CPU time 27.38 seconds
Started Jul 04 06:48:58 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 208092 kb
Host smart-9f64b617-a279-443c-9fde-3da119c44e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293739549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4293739549
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1957736898
Short name T816
Test name
Test status
Simulation time 221769574 ps
CPU time 3.08 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 206984 kb
Host smart-15a26642-138e-43bf-9224-dcdd2cfd9031
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957736898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1957736898
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1485717798
Short name T266
Test name
Test status
Simulation time 232397610 ps
CPU time 6.16 seconds
Started Jul 04 06:49:05 PM PDT 24
Finished Jul 04 06:49:11 PM PDT 24
Peak memory 208980 kb
Host smart-05d5ac29-14e4-40c2-a48b-a9350d2ae6cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485717798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1485717798
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.871196662
Short name T487
Test name
Test status
Simulation time 616878277 ps
CPU time 5.85 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:49:10 PM PDT 24
Peak memory 208176 kb
Host smart-1135c7f3-6be3-4348-a0f6-a94469135cf9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871196662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.871196662
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4025998077
Short name T869
Test name
Test status
Simulation time 400742381 ps
CPU time 3.91 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:07 PM PDT 24
Peak memory 209240 kb
Host smart-274e56e9-469d-4c6a-b8ad-cfc1fd9430f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025998077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4025998077
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3160358959
Short name T443
Test name
Test status
Simulation time 99461078 ps
CPU time 2.25 seconds
Started Jul 04 06:48:56 PM PDT 24
Finished Jul 04 06:48:58 PM PDT 24
Peak memory 206892 kb
Host smart-fa65ea80-8a10-47bf-a5e5-f9c567c58e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160358959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3160358959
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.257941412
Short name T762
Test name
Test status
Simulation time 688182386 ps
CPU time 7.88 seconds
Started Jul 04 06:49:05 PM PDT 24
Finished Jul 04 06:49:13 PM PDT 24
Peak memory 216064 kb
Host smart-d5bfaf03-4e99-454a-9ab3-b8790c06a0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257941412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.257941412
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1232258556
Short name T50
Test name
Test status
Simulation time 292776625 ps
CPU time 6.32 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:13 PM PDT 24
Peak memory 218832 kb
Host smart-c45ba3d3-0fc3-4a91-8a58-fbe1bad9909b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232258556 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1232258556
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3114909627
Short name T79
Test name
Test status
Simulation time 242967306 ps
CPU time 4.89 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:08 PM PDT 24
Peak memory 218356 kb
Host smart-1274a367-bba3-4fad-9a99-ce195ef138cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114909627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3114909627
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2978251068
Short name T536
Test name
Test status
Simulation time 134820782 ps
CPU time 2.84 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:06 PM PDT 24
Peak memory 210020 kb
Host smart-f9a1d1f6-26e3-4acb-b773-0684dced7b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978251068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2978251068
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1977426307
Short name T552
Test name
Test status
Simulation time 47145681 ps
CPU time 0.79 seconds
Started Jul 04 06:49:11 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 206032 kb
Host smart-76c0235d-1525-4a37-af30-3860f6d27191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977426307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1977426307
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3326758148
Short name T223
Test name
Test status
Simulation time 4784884743 ps
CPU time 58.97 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:50:04 PM PDT 24
Peak memory 214736 kb
Host smart-973bc625-a406-4700-bc09-d6ea05bc87a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326758148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3326758148
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.126357649
Short name T512
Test name
Test status
Simulation time 153743519 ps
CPU time 1.88 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 214708 kb
Host smart-b467e5c4-3288-4540-bd97-376a0958bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126357649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.126357649
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3113040236
Short name T572
Test name
Test status
Simulation time 2996023024 ps
CPU time 24.65 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:28 PM PDT 24
Peak memory 208584 kb
Host smart-6f81e097-bb77-48ae-b01f-079943d2dfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113040236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3113040236
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.336378953
Short name T717
Test name
Test status
Simulation time 242342648 ps
CPU time 9.05 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:19 PM PDT 24
Peak memory 209804 kb
Host smart-d6669fe0-cb39-4bb6-b463-672cb82b8c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336378953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.336378953
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1392937076
Short name T24
Test name
Test status
Simulation time 73138654 ps
CPU time 2.05 seconds
Started Jul 04 06:49:11 PM PDT 24
Finished Jul 04 06:49:13 PM PDT 24
Peak memory 219936 kb
Host smart-625674dd-3a9f-429f-9aaa-15f2ca2548f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392937076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1392937076
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.773042834
Short name T645
Test name
Test status
Simulation time 40792917 ps
CPU time 3.33 seconds
Started Jul 04 06:49:09 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 220988 kb
Host smart-4472ecef-7b62-42d9-97cc-16e89749e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773042834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.773042834
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.500717450
Short name T468
Test name
Test status
Simulation time 110421671 ps
CPU time 4.73 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 206984 kb
Host smart-337ecd88-7800-40a6-bdc8-1867cc3bd859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500717450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.500717450
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.858920802
Short name T271
Test name
Test status
Simulation time 3533205958 ps
CPU time 64.28 seconds
Started Jul 04 06:49:04 PM PDT 24
Finished Jul 04 06:50:08 PM PDT 24
Peak memory 209072 kb
Host smart-b2a0c353-71a9-4526-9b4b-27ef4117c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858920802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.858920802
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3937012411
Short name T624
Test name
Test status
Simulation time 158185559 ps
CPU time 2.94 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:09 PM PDT 24
Peak memory 207000 kb
Host smart-31992634-e423-4649-9fde-a384979bdfd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937012411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3937012411
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2709395004
Short name T387
Test name
Test status
Simulation time 459977790 ps
CPU time 4.16 seconds
Started Jul 04 06:49:06 PM PDT 24
Finished Jul 04 06:49:11 PM PDT 24
Peak memory 207056 kb
Host smart-4747ba0a-7d66-47ce-af2c-4505d22ba9d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709395004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2709395004
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1443668688
Short name T702
Test name
Test status
Simulation time 52771815 ps
CPU time 2.98 seconds
Started Jul 04 06:49:03 PM PDT 24
Finished Jul 04 06:49:06 PM PDT 24
Peak memory 208672 kb
Host smart-001b31ce-01e6-4075-b290-4175676323a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443668688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1443668688
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.889824518
Short name T229
Test name
Test status
Simulation time 336958033 ps
CPU time 2.97 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:13 PM PDT 24
Peak memory 214356 kb
Host smart-c623ff4d-14a8-4bd8-a2c5-e53a8fbcd521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889824518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.889824518
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1098932025
Short name T900
Test name
Test status
Simulation time 128063821 ps
CPU time 3.1 seconds
Started Jul 04 06:49:08 PM PDT 24
Finished Jul 04 06:49:11 PM PDT 24
Peak memory 206636 kb
Host smart-571cefe3-5849-4ce3-b6c8-64d394464532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098932025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1098932025
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.998543951
Short name T259
Test name
Test status
Simulation time 507100093 ps
CPU time 11.57 seconds
Started Jul 04 06:49:09 PM PDT 24
Finished Jul 04 06:49:21 PM PDT 24
Peak memory 220424 kb
Host smart-15e3e314-0e46-40c0-a881-6fd22641bfd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998543951 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.998543951
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2097683493
Short name T855
Test name
Test status
Simulation time 59790489 ps
CPU time 3.65 seconds
Started Jul 04 06:49:14 PM PDT 24
Finished Jul 04 06:49:17 PM PDT 24
Peak memory 209620 kb
Host smart-10e42758-b2f1-4fd4-aec4-8090c46824eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097683493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2097683493
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2071585737
Short name T176
Test name
Test status
Simulation time 377425907 ps
CPU time 2.58 seconds
Started Jul 04 06:49:12 PM PDT 24
Finished Jul 04 06:49:15 PM PDT 24
Peak memory 210476 kb
Host smart-7b550b6d-283c-41db-86bb-baf89fe39167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071585737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2071585737
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.243193902
Short name T559
Test name
Test status
Simulation time 15896338 ps
CPU time 0.77 seconds
Started Jul 04 06:49:22 PM PDT 24
Finished Jul 04 06:49:23 PM PDT 24
Peak memory 206004 kb
Host smart-6f17adfd-d62d-4c61-a14b-3f80a62bd5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243193902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.243193902
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1068997576
Short name T122
Test name
Test status
Simulation time 307043778 ps
CPU time 5.11 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:15 PM PDT 24
Peak memory 214328 kb
Host smart-56b940f1-b6c7-4fa4-86ef-cbbf4b62671e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068997576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1068997576
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3619149681
Short name T7
Test name
Test status
Simulation time 539351511 ps
CPU time 5.27 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:27 PM PDT 24
Peak memory 209428 kb
Host smart-4fce9bae-7ef7-48ed-b4c0-a075765a039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619149681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3619149681
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1209878498
Short name T615
Test name
Test status
Simulation time 180603534 ps
CPU time 4.12 seconds
Started Jul 04 06:49:14 PM PDT 24
Finished Jul 04 06:49:18 PM PDT 24
Peak memory 209552 kb
Host smart-664c5d26-dcb9-44c0-924f-c49eeb19de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209878498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1209878498
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1738970714
Short name T550
Test name
Test status
Simulation time 19899257072 ps
CPU time 46.48 seconds
Started Jul 04 06:49:22 PM PDT 24
Finished Jul 04 06:50:09 PM PDT 24
Peak memory 214496 kb
Host smart-f7fadded-91ce-4460-b900-21115144a3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738970714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1738970714
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3221835974
Short name T209
Test name
Test status
Simulation time 202956102 ps
CPU time 4.65 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:15 PM PDT 24
Peak memory 220032 kb
Host smart-687711f5-3978-4643-839c-5a1b27afc051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221835974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3221835974
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2528457623
Short name T788
Test name
Test status
Simulation time 1279190150 ps
CPU time 9.34 seconds
Started Jul 04 06:49:14 PM PDT 24
Finished Jul 04 06:49:24 PM PDT 24
Peak memory 218184 kb
Host smart-b8507c68-8741-4a6a-9a10-ee0410e9a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528457623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2528457623
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.190250748
Short name T416
Test name
Test status
Simulation time 481929542 ps
CPU time 3.99 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:14 PM PDT 24
Peak memory 206852 kb
Host smart-738bc5a0-abf9-4a57-bacf-8c78b6dd68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190250748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.190250748
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3986357135
Short name T608
Test name
Test status
Simulation time 1470652817 ps
CPU time 20.79 seconds
Started Jul 04 06:49:12 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 208676 kb
Host smart-5135df08-0e4f-4b67-8d32-16c003afacfc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986357135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3986357135
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.696241504
Short name T728
Test name
Test status
Simulation time 127957077 ps
CPU time 3.08 seconds
Started Jul 04 06:49:12 PM PDT 24
Finished Jul 04 06:49:15 PM PDT 24
Peak memory 208644 kb
Host smart-e39ebfb7-e3d5-44a6-8c0b-aafc1a6763c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696241504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.696241504
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3059961182
Short name T182
Test name
Test status
Simulation time 66654331 ps
CPU time 3.33 seconds
Started Jul 04 06:49:12 PM PDT 24
Finished Jul 04 06:49:16 PM PDT 24
Peak memory 208772 kb
Host smart-1310ccbf-9c10-4202-b1c2-898bbe67e65f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059961182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3059961182
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4200335828
Short name T868
Test name
Test status
Simulation time 309227712 ps
CPU time 3.33 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:24 PM PDT 24
Peak memory 214404 kb
Host smart-7ff1913d-28f7-450e-8bf2-58bed6662e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200335828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4200335828
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.527855235
Short name T80
Test name
Test status
Simulation time 147863108 ps
CPU time 2.28 seconds
Started Jul 04 06:49:10 PM PDT 24
Finished Jul 04 06:49:12 PM PDT 24
Peak memory 206884 kb
Host smart-d5a838a7-98d0-492e-8850-1e9e416eb0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527855235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.527855235
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.753831439
Short name T592
Test name
Test status
Simulation time 1408681354 ps
CPU time 25.17 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:47 PM PDT 24
Peak memory 215204 kb
Host smart-5880c27c-4558-49c6-b052-c62b39205a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753831439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.753831439
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3967001993
Short name T685
Test name
Test status
Simulation time 142192606 ps
CPU time 3.99 seconds
Started Jul 04 06:49:11 PM PDT 24
Finished Jul 04 06:49:16 PM PDT 24
Peak memory 207908 kb
Host smart-61cfe1a1-b863-48ae-aa58-44aaa60e335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967001993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3967001993
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1931531744
Short name T366
Test name
Test status
Simulation time 48287977 ps
CPU time 2.29 seconds
Started Jul 04 06:49:20 PM PDT 24
Finished Jul 04 06:49:22 PM PDT 24
Peak memory 209772 kb
Host smart-b17f1588-fc7e-4fce-b09c-5fc08ae99416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931531744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1931531744
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.92064445
Short name T579
Test name
Test status
Simulation time 44250880 ps
CPU time 0.72 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:22 PM PDT 24
Peak memory 205972 kb
Host smart-8d1966f3-49b9-485a-b25b-91b509e70068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92064445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.92064445
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1218798935
Short name T33
Test name
Test status
Simulation time 229574073 ps
CPU time 4.13 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:26 PM PDT 24
Peak memory 221936 kb
Host smart-2f727e41-9938-4288-a409-3ad8e35b54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218798935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1218798935
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2631378068
Short name T377
Test name
Test status
Simulation time 149372424 ps
CPU time 6.16 seconds
Started Jul 04 06:49:19 PM PDT 24
Finished Jul 04 06:49:26 PM PDT 24
Peak memory 209596 kb
Host smart-a5139de6-7050-4a29-8e26-ce7a3a893666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631378068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2631378068
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1081304717
Short name T917
Test name
Test status
Simulation time 561158209 ps
CPU time 13.66 seconds
Started Jul 04 06:49:20 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 214392 kb
Host smart-66eb7e5a-23fc-43e2-8e32-4d9c00c4d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081304717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1081304717
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1166853271
Short name T60
Test name
Test status
Simulation time 194289900 ps
CPU time 2.44 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:24 PM PDT 24
Peak memory 220312 kb
Host smart-fff4b834-e57b-4ec4-8d75-c24769f352d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166853271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1166853271
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2749827927
Short name T894
Test name
Test status
Simulation time 411581789 ps
CPU time 4.58 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:26 PM PDT 24
Peak memory 209960 kb
Host smart-ff8357f3-7bcf-414a-94c0-b30ec73fedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749827927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2749827927
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2839914057
Short name T895
Test name
Test status
Simulation time 445788904 ps
CPU time 4.18 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 214400 kb
Host smart-0d938fad-c52f-4e2b-acf9-711354514e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839914057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2839914057
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1179892068
Short name T772
Test name
Test status
Simulation time 56153330 ps
CPU time 2.85 seconds
Started Jul 04 06:49:20 PM PDT 24
Finished Jul 04 06:49:23 PM PDT 24
Peak memory 208568 kb
Host smart-6000204e-bd58-4593-987c-b2df097388d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179892068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1179892068
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2737586649
Short name T787
Test name
Test status
Simulation time 75086049 ps
CPU time 1.89 seconds
Started Jul 04 06:49:23 PM PDT 24
Finished Jul 04 06:49:25 PM PDT 24
Peak memory 206968 kb
Host smart-b673b604-a82d-47d6-914b-36dc9546f398
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737586649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2737586649
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1023859649
Short name T289
Test name
Test status
Simulation time 143979167 ps
CPU time 3.53 seconds
Started Jul 04 06:49:23 PM PDT 24
Finished Jul 04 06:49:26 PM PDT 24
Peak memory 208548 kb
Host smart-bcef9df9-c095-4281-8dee-7ebc21f8ca78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023859649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1023859649
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3295383750
Short name T561
Test name
Test status
Simulation time 257473280 ps
CPU time 6.53 seconds
Started Jul 04 06:49:23 PM PDT 24
Finished Jul 04 06:49:29 PM PDT 24
Peak memory 208196 kb
Host smart-2a8bfaf5-45ab-4a24-ada6-274b44ed19d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295383750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3295383750
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2900370475
Short name T484
Test name
Test status
Simulation time 192048582 ps
CPU time 4.44 seconds
Started Jul 04 06:49:19 PM PDT 24
Finished Jul 04 06:49:24 PM PDT 24
Peak memory 214364 kb
Host smart-31aed82c-1e77-43bc-9359-b6bb529f4ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900370475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2900370475
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1065135454
Short name T597
Test name
Test status
Simulation time 110442791 ps
CPU time 3.86 seconds
Started Jul 04 06:49:22 PM PDT 24
Finished Jul 04 06:49:26 PM PDT 24
Peak memory 208256 kb
Host smart-6a3ccafc-7c59-4578-8520-4f8c1f62b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065135454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1065135454
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.950341349
Short name T710
Test name
Test status
Simulation time 3094846356 ps
CPU time 59.33 seconds
Started Jul 04 06:49:20 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 219792 kb
Host smart-2b15f01c-b6db-4da4-867e-ff47ecb6219a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950341349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.950341349
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1673716080
Short name T861
Test name
Test status
Simulation time 1059796146 ps
CPU time 12.18 seconds
Started Jul 04 06:49:21 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 214304 kb
Host smart-e9240e70-194e-4290-a216-86be525bd583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673716080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1673716080
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2596757188
Short name T459
Test name
Test status
Simulation time 44491674 ps
CPU time 1.72 seconds
Started Jul 04 06:49:19 PM PDT 24
Finished Jul 04 06:49:21 PM PDT 24
Peak memory 209676 kb
Host smart-dbe63d1f-0a6c-4d04-bad1-5cfbe78e4d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596757188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2596757188
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3247441503
Short name T819
Test name
Test status
Simulation time 12729280 ps
CPU time 0.89 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:30 PM PDT 24
Peak memory 205968 kb
Host smart-05882db4-3001-493b-b457-fa2fe357ced6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247441503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3247441503
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.562104418
Short name T121
Test name
Test status
Simulation time 222113263 ps
CPU time 4.81 seconds
Started Jul 04 06:49:28 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 215400 kb
Host smart-b1234a49-e0a7-4509-a4df-e6ce080c5ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562104418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.562104418
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2414733506
Short name T679
Test name
Test status
Simulation time 49177585 ps
CPU time 1.93 seconds
Started Jul 04 06:49:33 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 214428 kb
Host smart-567aa1c4-739f-4d33-b10a-0ee3806666cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414733506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2414733506
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1262048763
Short name T382
Test name
Test status
Simulation time 569871400 ps
CPU time 4.29 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 214436 kb
Host smart-f1818774-d909-4fdf-ab5a-e49e71d97ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262048763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1262048763
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3374018338
Short name T566
Test name
Test status
Simulation time 43513809 ps
CPU time 2.01 seconds
Started Jul 04 06:49:28 PM PDT 24
Finished Jul 04 06:49:30 PM PDT 24
Peak memory 214328 kb
Host smart-f4d8f8c5-74ff-4eb3-9a60-4c5e879d4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374018338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3374018338
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2614824878
Short name T226
Test name
Test status
Simulation time 358444428 ps
CPU time 3.23 seconds
Started Jul 04 06:49:27 PM PDT 24
Finished Jul 04 06:49:31 PM PDT 24
Peak memory 214276 kb
Host smart-87dd29df-eb7d-4b43-9dea-a40eeb10cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614824878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2614824878
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2101352533
Short name T779
Test name
Test status
Simulation time 235377270 ps
CPU time 3.45 seconds
Started Jul 04 06:49:28 PM PDT 24
Finished Jul 04 06:49:31 PM PDT 24
Peak memory 208764 kb
Host smart-d0c382c0-0831-4162-8878-ad89c6000d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101352533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2101352533
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1255915680
Short name T752
Test name
Test status
Simulation time 260637661 ps
CPU time 6.91 seconds
Started Jul 04 06:49:28 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 214340 kb
Host smart-33b9359f-7b09-4cc8-a3aa-448980518531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255915680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1255915680
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.472148259
Short name T76
Test name
Test status
Simulation time 605798060 ps
CPU time 5.9 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 208504 kb
Host smart-f7d3914e-0da2-4802-ad5c-cc85c380c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472148259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.472148259
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3669088066
Short name T464
Test name
Test status
Simulation time 118835058 ps
CPU time 3.52 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 208556 kb
Host smart-d13d885f-4d97-4578-b4ce-0ad1163db7b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669088066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3669088066
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3073085198
Short name T727
Test name
Test status
Simulation time 114080353 ps
CPU time 2.04 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:32 PM PDT 24
Peak memory 208624 kb
Host smart-5defdf8c-cd7c-425c-b418-d1f7401203c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073085198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3073085198
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.224463934
Short name T480
Test name
Test status
Simulation time 94551067 ps
CPU time 2.13 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 208616 kb
Host smart-a34bc59c-8d7a-4921-8962-51064eb46007
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224463934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.224463934
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4147782510
Short name T269
Test name
Test status
Simulation time 312934443 ps
CPU time 8.21 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:37 PM PDT 24
Peak memory 214352 kb
Host smart-4d52255c-24a5-4072-bc3c-0f97c2ea5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147782510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4147782510
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1047128034
Short name T419
Test name
Test status
Simulation time 697655258 ps
CPU time 10.52 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:42 PM PDT 24
Peak memory 206932 kb
Host smart-ab909923-e555-4662-988d-ec3b5e0302ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047128034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1047128034
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1317875876
Short name T54
Test name
Test status
Simulation time 3856851701 ps
CPU time 27.13 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 217544 kb
Host smart-3e3a799c-8eea-4c29-875c-8b4a9225d48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317875876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1317875876
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2589374519
Short name T830
Test name
Test status
Simulation time 70716171 ps
CPU time 4.02 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 207844 kb
Host smart-9ef28721-4ff4-4080-965d-c26147af5891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589374519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2589374519
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3550879993
Short name T924
Test name
Test status
Simulation time 310766557 ps
CPU time 3.09 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 209924 kb
Host smart-02d61d3a-917a-4372-810f-a03854e2bb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550879993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3550879993
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1421403722
Short name T478
Test name
Test status
Simulation time 10370438 ps
CPU time 0.7 seconds
Started Jul 04 06:49:33 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 206032 kb
Host smart-f3954dc0-8f9d-44e9-a11c-d49dc9d73c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421403722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1421403722
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.230459358
Short name T704
Test name
Test status
Simulation time 41949678 ps
CPU time 3.07 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:36 PM PDT 24
Peak memory 214348 kb
Host smart-c6a7dd6d-7e96-40ce-ac25-3627a58f68ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230459358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.230459358
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1723649824
Short name T27
Test name
Test status
Simulation time 2117568282 ps
CPU time 7.32 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 214764 kb
Host smart-7513f9f3-9a9b-4193-8567-cdbe5b0c5fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723649824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1723649824
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.967314586
Short name T278
Test name
Test status
Simulation time 375795597 ps
CPU time 2.74 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 209896 kb
Host smart-a0bc3b7c-e091-4c68-8853-98a75057336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967314586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.967314586
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.290791728
Short name T736
Test name
Test status
Simulation time 304578032 ps
CPU time 4.04 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 222464 kb
Host smart-82840210-966d-41a9-8a4c-72a6af4d17eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290791728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.290791728
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1118823809
Short name T311
Test name
Test status
Simulation time 78927419 ps
CPU time 4.27 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 211864 kb
Host smart-4d8ceb23-f4e1-4fd1-9d44-10c745bcecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118823809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1118823809
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3988742008
Short name T395
Test name
Test status
Simulation time 263515988 ps
CPU time 7.05 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:40 PM PDT 24
Peak memory 219884 kb
Host smart-3d0899d0-e015-4fc8-85e5-c8d8fe6ca8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988742008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3988742008
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.202882730
Short name T307
Test name
Test status
Simulation time 547776889 ps
CPU time 4.84 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 208136 kb
Host smart-63d11fad-6f7f-4060-b210-ec19ab2407ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202882730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.202882730
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1354008215
Short name T378
Test name
Test status
Simulation time 39262437 ps
CPU time 1.82 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:32 PM PDT 24
Peak memory 206852 kb
Host smart-1a1e1841-b054-48b1-9682-ae3b2bca2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354008215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1354008215
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1806662603
Short name T885
Test name
Test status
Simulation time 237427103 ps
CPU time 6.39 seconds
Started Jul 04 06:49:33 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 209068 kb
Host smart-f50b8162-4ef2-4578-8338-fd32403000ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806662603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1806662603
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1617861722
Short name T540
Test name
Test status
Simulation time 77938631 ps
CPU time 2.82 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 208812 kb
Host smart-7e7c50c2-0d14-4baa-9186-541fa3fbca70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617861722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1617861722
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1123052375
Short name T775
Test name
Test status
Simulation time 53491279 ps
CPU time 2.81 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 207060 kb
Host smart-4d6dcbcb-5f6f-4f29-9409-b6c9cbc653a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123052375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1123052375
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.724659383
Short name T517
Test name
Test status
Simulation time 4803568064 ps
CPU time 30.02 seconds
Started Jul 04 06:49:28 PM PDT 24
Finished Jul 04 06:49:58 PM PDT 24
Peak memory 214388 kb
Host smart-79efe12e-8705-447a-ad7a-09426cf4961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724659383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.724659383
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2120948728
Short name T535
Test name
Test status
Simulation time 572551131 ps
CPU time 5.61 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 208004 kb
Host smart-bcfbb264-4698-4040-89da-edeb8c9ff944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120948728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2120948728
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1153018832
Short name T668
Test name
Test status
Simulation time 574243795 ps
CPU time 24.06 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:53 PM PDT 24
Peak memory 214892 kb
Host smart-11d6448b-b261-4350-9c3a-a802f29f581e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153018832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1153018832
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2524646361
Short name T723
Test name
Test status
Simulation time 303155555 ps
CPU time 6.04 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:37 PM PDT 24
Peak memory 218464 kb
Host smart-dc74ac67-769c-40e3-9213-a27a7c215b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524646361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2524646361
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.956191965
Short name T388
Test name
Test status
Simulation time 142404391 ps
CPU time 3.12 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 210016 kb
Host smart-39de50b9-4a49-4446-9f74-921582cc117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956191965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.956191965
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2093601076
Short name T432
Test name
Test status
Simulation time 63812875 ps
CPU time 0.81 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 206032 kb
Host smart-1bfd96ad-7424-48be-9213-1bbd821b15d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093601076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2093601076
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.786338327
Short name T407
Test name
Test status
Simulation time 52416141 ps
CPU time 3.55 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 214316 kb
Host smart-4aac1908-f90f-4f38-ad18-4becfbf82864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786338327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.786338327
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.959295235
Short name T874
Test name
Test status
Simulation time 47798541 ps
CPU time 1.89 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 209828 kb
Host smart-de9770da-33ef-43d4-a995-d77539d33ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959295235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.959295235
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2971106638
Short name T856
Test name
Test status
Simulation time 299699329 ps
CPU time 4.3 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:36 PM PDT 24
Peak memory 214316 kb
Host smart-558fda96-8899-4172-955e-868673902110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971106638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2971106638
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1480025361
Short name T859
Test name
Test status
Simulation time 31158524 ps
CPU time 2.49 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 219352 kb
Host smart-6dacbbf4-be79-477c-9566-dc87f1dd312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480025361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1480025361
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2610844362
Short name T203
Test name
Test status
Simulation time 356085776 ps
CPU time 3.66 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 220352 kb
Host smart-40dcf353-79d7-46e3-9124-5f28d611c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610844362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2610844362
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1491323424
Short name T421
Test name
Test status
Simulation time 182470287 ps
CPU time 4.78 seconds
Started Jul 04 06:49:30 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 218416 kb
Host smart-d77d75b1-5534-4659-bb5e-3aacdba34fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491323424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1491323424
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.763815733
Short name T692
Test name
Test status
Simulation time 1534214489 ps
CPU time 3.31 seconds
Started Jul 04 06:49:27 PM PDT 24
Finished Jul 04 06:49:31 PM PDT 24
Peak memory 206916 kb
Host smart-737beece-eeb0-49c1-864e-64410b834265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763815733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.763815733
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3304178254
Short name T672
Test name
Test status
Simulation time 143944616 ps
CPU time 2.52 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 207520 kb
Host smart-49953be3-cfa8-4caa-8615-501eea630b8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304178254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3304178254
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3649828041
Short name T495
Test name
Test status
Simulation time 112620513 ps
CPU time 2.43 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:31 PM PDT 24
Peak memory 206912 kb
Host smart-3f4cb57d-87fd-452b-9fb4-c4173d126281
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649828041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3649828041
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1632241527
Short name T434
Test name
Test status
Simulation time 346361419 ps
CPU time 2.82 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 206944 kb
Host smart-9325105c-0442-4fef-87ae-f9dc6786eb3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632241527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1632241527
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.705907055
Short name T784
Test name
Test status
Simulation time 139195498 ps
CPU time 2.27 seconds
Started Jul 04 06:49:31 PM PDT 24
Finished Jul 04 06:49:33 PM PDT 24
Peak memory 209736 kb
Host smart-f2e5fb0b-a487-4d58-8c72-a04ab870e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705907055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.705907055
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.865517719
Short name T613
Test name
Test status
Simulation time 193350150 ps
CPU time 2.68 seconds
Started Jul 04 06:49:32 PM PDT 24
Finished Jul 04 06:49:35 PM PDT 24
Peak memory 208664 kb
Host smart-d5d27684-a222-476d-a297-a8f9ae332389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865517719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.865517719
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3295109822
Short name T328
Test name
Test status
Simulation time 1082327765 ps
CPU time 10.3 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 222552 kb
Host smart-01de0ea8-fe0d-4265-9e95-bb0ff43d8fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295109822 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3295109822
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1081230686
Short name T509
Test name
Test status
Simulation time 345657948 ps
CPU time 4.46 seconds
Started Jul 04 06:49:29 PM PDT 24
Finished Jul 04 06:49:34 PM PDT 24
Peak memory 208076 kb
Host smart-9a029027-23d9-4398-b71b-0464cf04ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081230686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1081230686
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1063311237
Short name T658
Test name
Test status
Simulation time 47200743 ps
CPU time 1 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 205984 kb
Host smart-a6474b52-46ca-4be2-ac91-3f1a9d78dbce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063311237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1063311237
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3389339104
Short name T228
Test name
Test status
Simulation time 112464024 ps
CPU time 6.73 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:43 PM PDT 24
Peak memory 214932 kb
Host smart-1b37d78b-c47f-4c46-8a21-8bf9fdaafcdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389339104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3389339104
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2019046213
Short name T751
Test name
Test status
Simulation time 407555545 ps
CPU time 3.08 seconds
Started Jul 04 06:49:39 PM PDT 24
Finished Jul 04 06:49:42 PM PDT 24
Peak memory 214356 kb
Host smart-843799cb-4fab-47dd-8b28-fd944038bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019046213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2019046213
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1145929682
Short name T260
Test name
Test status
Simulation time 659113041 ps
CPU time 8.74 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:50 PM PDT 24
Peak memory 220708 kb
Host smart-20117a6d-3029-4002-9d9a-ff3df38fa691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145929682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1145929682
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2682209343
Short name T275
Test name
Test status
Simulation time 32545376 ps
CPU time 2.34 seconds
Started Jul 04 06:49:40 PM PDT 24
Finished Jul 04 06:49:43 PM PDT 24
Peak memory 214216 kb
Host smart-e27ed74f-0b28-4129-bfb4-8accd0f5782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682209343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2682209343
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3067727504
Short name T614
Test name
Test status
Simulation time 204968937 ps
CPU time 4.32 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 209992 kb
Host smart-550c5ace-2fad-42a8-8989-83871ec1c761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067727504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3067727504
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1935211103
Short name T753
Test name
Test status
Simulation time 222610109 ps
CPU time 5.02 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 210116 kb
Host smart-c01ef599-0f3c-4d9f-9cf7-097445e47147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935211103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1935211103
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.284169833
Short name T102
Test name
Test status
Simulation time 397432713 ps
CPU time 4.92 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:41 PM PDT 24
Peak memory 208384 kb
Host smart-d7438bcf-61be-4f96-b02c-8923121e255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284169833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.284169833
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1636805334
Short name T488
Test name
Test status
Simulation time 449437352 ps
CPU time 3.51 seconds
Started Jul 04 06:49:34 PM PDT 24
Finished Jul 04 06:49:38 PM PDT 24
Peak memory 208856 kb
Host smart-a04a6662-231f-48e3-b404-dfa9862d1916
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636805334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1636805334
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2055748032
Short name T494
Test name
Test status
Simulation time 356153682 ps
CPU time 5.9 seconds
Started Jul 04 06:49:35 PM PDT 24
Finished Jul 04 06:49:41 PM PDT 24
Peak memory 208048 kb
Host smart-d13ac946-129e-4744-8fb1-3f2738c3fb79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055748032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2055748032
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3600690400
Short name T322
Test name
Test status
Simulation time 94788673 ps
CPU time 3.47 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:40 PM PDT 24
Peak memory 208632 kb
Host smart-030491e5-e31b-4661-a10c-fc0bd950afd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600690400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3600690400
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.419127270
Short name T537
Test name
Test status
Simulation time 115453146 ps
CPU time 2.73 seconds
Started Jul 04 06:49:40 PM PDT 24
Finished Jul 04 06:49:44 PM PDT 24
Peak memory 208000 kb
Host smart-7c794dac-25c5-406a-8674-513815191650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419127270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.419127270
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.959576318
Short name T701
Test name
Test status
Simulation time 647938744 ps
CPU time 4.92 seconds
Started Jul 04 06:49:34 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 206700 kb
Host smart-f85f3356-5103-4642-8704-8ce2819a5ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959576318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.959576318
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.4171632704
Short name T117
Test name
Test status
Simulation time 502509002 ps
CPU time 17.58 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 222564 kb
Host smart-a7b52c19-2a72-402a-abab-82eaa1f4577e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171632704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.4171632704
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.476633019
Short name T656
Test name
Test status
Simulation time 61028863 ps
CPU time 3.84 seconds
Started Jul 04 06:49:37 PM PDT 24
Finished Jul 04 06:49:41 PM PDT 24
Peak memory 208516 kb
Host smart-af380d8f-d5ef-40de-a126-af3806c7f12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476633019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.476633019
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2887779951
Short name T369
Test name
Test status
Simulation time 323411024 ps
CPU time 3.48 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:40 PM PDT 24
Peak memory 210192 kb
Host smart-cd338571-e5ed-4ba7-9a9c-7f14f21c267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887779951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2887779951
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2456665347
Short name T801
Test name
Test status
Simulation time 26944959 ps
CPU time 1.13 seconds
Started Jul 04 06:46:32 PM PDT 24
Finished Jul 04 06:46:33 PM PDT 24
Peak memory 206128 kb
Host smart-62720e68-3b26-4a46-89f6-b09be52b5159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456665347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2456665347
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2559405330
Short name T691
Test name
Test status
Simulation time 66762647 ps
CPU time 3.3 seconds
Started Jul 04 06:46:31 PM PDT 24
Finished Jul 04 06:46:34 PM PDT 24
Peak memory 208660 kb
Host smart-064154bf-2d57-4e5c-a162-07b30a1e0660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559405330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2559405330
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1856203448
Short name T489
Test name
Test status
Simulation time 164079325 ps
CPU time 2.16 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:32 PM PDT 24
Peak memory 208024 kb
Host smart-bdcf38c6-7c74-4ac7-bc94-41f57fb32444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856203448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1856203448
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4237523091
Short name T308
Test name
Test status
Simulation time 862130112 ps
CPU time 9.81 seconds
Started Jul 04 06:46:33 PM PDT 24
Finished Jul 04 06:46:43 PM PDT 24
Peak memory 214336 kb
Host smart-43c777d8-22b3-43f7-b935-7ed98f7d1a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237523091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4237523091
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1008156924
Short name T654
Test name
Test status
Simulation time 195535802 ps
CPU time 3.93 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 214336 kb
Host smart-86674a6d-4fcc-4594-af25-c64c4d8e34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008156924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1008156924
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3257886476
Short name T905
Test name
Test status
Simulation time 76877684 ps
CPU time 2.91 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:33 PM PDT 24
Peak memory 214324 kb
Host smart-af29426c-c839-4a17-897b-a91baba9d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257886476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3257886476
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1516556105
Short name T652
Test name
Test status
Simulation time 107815854 ps
CPU time 4.88 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 219668 kb
Host smart-51084649-74bf-4000-be10-da54401d4617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516556105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1516556105
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2523567242
Short name T11
Test name
Test status
Simulation time 1505674247 ps
CPU time 7.91 seconds
Started Jul 04 06:46:33 PM PDT 24
Finished Jul 04 06:46:42 PM PDT 24
Peak memory 237476 kb
Host smart-0ebaaca9-a8e8-488a-a6ca-8f4920caff4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523567242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2523567242
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1485788165
Short name T655
Test name
Test status
Simulation time 307784751 ps
CPU time 3.76 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:34 PM PDT 24
Peak memory 208620 kb
Host smart-04649c90-6974-4825-9bbf-f2b3e2018eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485788165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1485788165
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3622496062
Short name T527
Test name
Test status
Simulation time 1268127604 ps
CPU time 26.12 seconds
Started Jul 04 06:46:31 PM PDT 24
Finished Jul 04 06:46:57 PM PDT 24
Peak memory 208196 kb
Host smart-eef73a7b-e8df-4edb-a120-c553be44577f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622496062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3622496062
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2846026655
Short name T700
Test name
Test status
Simulation time 671618969 ps
CPU time 23.4 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 209148 kb
Host smart-39332b00-7b5e-48ff-87e5-1122aed274c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846026655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2846026655
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3982947493
Short name T483
Test name
Test status
Simulation time 422811479 ps
CPU time 3.57 seconds
Started Jul 04 06:46:32 PM PDT 24
Finished Jul 04 06:46:36 PM PDT 24
Peak memory 206996 kb
Host smart-ba7d7022-8df7-4c1d-9388-a1be2ff48802
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982947493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3982947493
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2768129914
Short name T305
Test name
Test status
Simulation time 69728511 ps
CPU time 1.48 seconds
Started Jul 04 06:46:29 PM PDT 24
Finished Jul 04 06:46:31 PM PDT 24
Peak memory 206848 kb
Host smart-65cc12f6-2221-4b73-9ab9-27562b71417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768129914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2768129914
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1667957456
Short name T922
Test name
Test status
Simulation time 1785223770 ps
CPU time 3.4 seconds
Started Jul 04 06:46:31 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 208648 kb
Host smart-db0a7140-07a6-4910-99ae-29b1577f8975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667957456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1667957456
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.626484763
Short name T115
Test name
Test status
Simulation time 1647212842 ps
CPU time 16.97 seconds
Started Jul 04 06:46:29 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 221028 kb
Host smart-9b92b50d-99cb-4b19-912d-73adddb340ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626484763 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.626484763
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4166108063
Short name T567
Test name
Test status
Simulation time 158087159 ps
CPU time 5.07 seconds
Started Jul 04 06:46:30 PM PDT 24
Finished Jul 04 06:46:35 PM PDT 24
Peak memory 208252 kb
Host smart-d8fbc1f6-3f14-41d7-9b91-0fc9da754659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166108063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4166108063
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2211763457
Short name T818
Test name
Test status
Simulation time 313987136 ps
CPU time 2.51 seconds
Started Jul 04 06:46:29 PM PDT 24
Finished Jul 04 06:46:32 PM PDT 24
Peak memory 211084 kb
Host smart-06b6b41e-5826-46dc-905c-bf25e1e76622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211763457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2211763457
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.664838812
Short name T454
Test name
Test status
Simulation time 28581727 ps
CPU time 0.73 seconds
Started Jul 04 06:49:46 PM PDT 24
Finished Jul 04 06:49:47 PM PDT 24
Peak memory 206016 kb
Host smart-1d823443-7d48-4110-9dd4-4ea0c3fcca5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664838812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.664838812
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1515328943
Short name T469
Test name
Test status
Simulation time 438732050 ps
CPU time 3.21 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:40 PM PDT 24
Peak memory 218256 kb
Host smart-87577078-b63d-4b17-a02c-011d637a69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515328943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1515328943
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1295042687
Short name T618
Test name
Test status
Simulation time 121720302 ps
CPU time 4.74 seconds
Started Jul 04 06:49:40 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 213988 kb
Host smart-282a4b89-e107-4fde-8bf7-cad2648a2848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295042687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1295042687
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2551282625
Short name T264
Test name
Test status
Simulation time 597702687 ps
CPU time 7.21 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:45 PM PDT 24
Peak memory 222476 kb
Host smart-aa36992f-f2e0-4025-bdeb-c4dc28d64be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551282625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2551282625
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1578964122
Short name T659
Test name
Test status
Simulation time 125987004 ps
CPU time 6.12 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:44 PM PDT 24
Peak memory 220484 kb
Host smart-4c68450e-7fef-41ff-84bb-eb22ce72d82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578964122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1578964122
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1975922939
Short name T541
Test name
Test status
Simulation time 95765429 ps
CPU time 3.13 seconds
Started Jul 04 06:49:34 PM PDT 24
Finished Jul 04 06:49:38 PM PDT 24
Peak memory 207664 kb
Host smart-746d94fd-194d-4743-bbb7-e41564412c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975922939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1975922939
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1778784439
Short name T766
Test name
Test status
Simulation time 250299424 ps
CPU time 3.06 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 208128 kb
Host smart-e72b87cf-e091-40c2-981e-a6bffe40ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778784439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1778784439
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.254617634
Short name T735
Test name
Test status
Simulation time 78273684 ps
CPU time 2.29 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:44 PM PDT 24
Peak memory 207044 kb
Host smart-c33be7d1-c3cc-4eb2-96cf-2a35142a06ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254617634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.254617634
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1705503842
Short name T829
Test name
Test status
Simulation time 1757047112 ps
CPU time 18.48 seconds
Started Jul 04 06:49:37 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 208860 kb
Host smart-59f976f0-1eb8-402d-8e58-46e7f40464b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705503842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1705503842
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.142169699
Short name T236
Test name
Test status
Simulation time 69809163 ps
CPU time 1.71 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:43 PM PDT 24
Peak memory 206852 kb
Host smart-4bb8f1fa-cb71-42dd-a67f-0b25dbec0f13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142169699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.142169699
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2722392256
Short name T222
Test name
Test status
Simulation time 56938757 ps
CPU time 1.69 seconds
Started Jul 04 06:49:37 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 207528 kb
Host smart-e4441981-5083-4913-8580-ef8fdf593f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722392256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2722392256
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.957417042
Short name T823
Test name
Test status
Simulation time 340567925 ps
CPU time 3.08 seconds
Started Jul 04 06:49:38 PM PDT 24
Finished Jul 04 06:49:41 PM PDT 24
Peak memory 206880 kb
Host smart-b6696664-a076-481d-bbd9-8ce6bc39dfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957417042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.957417042
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3092230306
Short name T906
Test name
Test status
Simulation time 1224300944 ps
CPU time 12.12 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:49 PM PDT 24
Peak memory 219296 kb
Host smart-24f706d6-eefb-460a-849f-98cf9f1398e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092230306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3092230306
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3110441072
Short name T545
Test name
Test status
Simulation time 196561162 ps
CPU time 11.66 seconds
Started Jul 04 06:49:45 PM PDT 24
Finished Jul 04 06:49:57 PM PDT 24
Peak memory 222660 kb
Host smart-f8389a84-41ff-4868-bdcb-b3db89898c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110441072 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3110441072
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1738732732
Short name T518
Test name
Test status
Simulation time 221995676 ps
CPU time 3.65 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:45 PM PDT 24
Peak memory 218336 kb
Host smart-49abb3f3-d518-458e-8f06-5d14ad378abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738732732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1738732732
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2485478675
Short name T715
Test name
Test status
Simulation time 323686146 ps
CPU time 2.22 seconds
Started Jul 04 06:49:36 PM PDT 24
Finished Jul 04 06:49:39 PM PDT 24
Peak memory 210064 kb
Host smart-722bc8f6-bb8c-42d1-b4a5-5b7c48a32b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485478675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2485478675
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4165719071
Short name T841
Test name
Test status
Simulation time 25837537 ps
CPU time 0.73 seconds
Started Jul 04 06:49:47 PM PDT 24
Finished Jul 04 06:49:48 PM PDT 24
Peak memory 206020 kb
Host smart-53f40c06-9489-44b5-a9fe-2f2d60403bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165719071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4165719071
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1604880774
Short name T638
Test name
Test status
Simulation time 52569960 ps
CPU time 2.72 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 219784 kb
Host smart-b008c00e-3ef3-4965-94e3-d8c52069008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604880774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1604880774
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1601657542
Short name T243
Test name
Test status
Simulation time 64611121 ps
CPU time 3.15 seconds
Started Jul 04 06:49:45 PM PDT 24
Finished Jul 04 06:49:48 PM PDT 24
Peak memory 207516 kb
Host smart-7919cabe-e608-4fab-be3a-ca318b7c24dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601657542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1601657542
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3358335208
Short name T332
Test name
Test status
Simulation time 74063531 ps
CPU time 3.68 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:45 PM PDT 24
Peak memory 214412 kb
Host smart-5578b007-475c-4700-830e-b6f472bde977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358335208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3358335208
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1674681837
Short name T300
Test name
Test status
Simulation time 298098900 ps
CPU time 2.64 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 206076 kb
Host smart-37d850fa-44c8-470e-a254-44296aaab8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674681837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1674681837
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1956199824
Short name T919
Test name
Test status
Simulation time 97621575 ps
CPU time 4.56 seconds
Started Jul 04 06:49:47 PM PDT 24
Finished Jul 04 06:49:52 PM PDT 24
Peak memory 209752 kb
Host smart-834e3600-61a2-486a-8f79-476a715d7cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956199824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1956199824
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3531141551
Short name T821
Test name
Test status
Simulation time 418992303 ps
CPU time 6.54 seconds
Started Jul 04 06:49:42 PM PDT 24
Finished Jul 04 06:49:49 PM PDT 24
Peak memory 209920 kb
Host smart-887f035d-0fdb-4f6f-985f-1bd9e40d779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531141551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3531141551
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.637345784
Short name T720
Test name
Test status
Simulation time 96264197 ps
CPU time 3.76 seconds
Started Jul 04 06:49:42 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 208784 kb
Host smart-cb84e7fc-695a-4d4f-8757-9d570c6752a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637345784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.637345784
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.241140509
Short name T621
Test name
Test status
Simulation time 1676209617 ps
CPU time 13.81 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:57 PM PDT 24
Peak memory 209128 kb
Host smart-3054b11f-259c-47b4-ad9d-6355d5780adc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241140509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.241140509
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4128411545
Short name T667
Test name
Test status
Simulation time 796603164 ps
CPU time 6.87 seconds
Started Jul 04 06:49:42 PM PDT 24
Finished Jul 04 06:49:49 PM PDT 24
Peak memory 208952 kb
Host smart-56a65e07-8067-4c77-bc46-d8eb5a214b0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128411545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4128411545
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1248053383
Short name T75
Test name
Test status
Simulation time 61594507 ps
CPU time 3.04 seconds
Started Jul 04 06:49:47 PM PDT 24
Finished Jul 04 06:49:50 PM PDT 24
Peak memory 207028 kb
Host smart-6d5c5397-28a3-4b46-95b1-4b24f04ef6c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248053383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1248053383
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2730587332
Short name T496
Test name
Test status
Simulation time 128576001 ps
CPU time 3.17 seconds
Started Jul 04 06:49:47 PM PDT 24
Finished Jul 04 06:49:51 PM PDT 24
Peak memory 209304 kb
Host smart-198de4ee-09bd-4ccf-aa06-01918ea86575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730587332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2730587332
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3187056267
Short name T833
Test name
Test status
Simulation time 3939061218 ps
CPU time 15.37 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:59 PM PDT 24
Peak memory 208304 kb
Host smart-13847c21-81b3-48c4-a207-e59126d0c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187056267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3187056267
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1496357117
Short name T804
Test name
Test status
Simulation time 1444949440 ps
CPU time 46.44 seconds
Started Jul 04 06:49:46 PM PDT 24
Finished Jul 04 06:50:33 PM PDT 24
Peak memory 222784 kb
Host smart-4d02a2f9-1748-44ef-b747-a87a40c990a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496357117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1496357117
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.672016267
Short name T472
Test name
Test status
Simulation time 565018526 ps
CPU time 5.44 seconds
Started Jul 04 06:49:44 PM PDT 24
Finished Jul 04 06:49:50 PM PDT 24
Peak memory 214308 kb
Host smart-abe15bd9-54b7-49de-bd97-7f604705b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672016267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.672016267
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1776365817
Short name T724
Test name
Test status
Simulation time 261199300 ps
CPU time 2.72 seconds
Started Jul 04 06:49:41 PM PDT 24
Finished Jul 04 06:49:44 PM PDT 24
Peak memory 210524 kb
Host smart-a76c72de-393a-47d5-98e0-2f76d61287fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776365817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1776365817
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3864186993
Short name T510
Test name
Test status
Simulation time 26536940 ps
CPU time 0.81 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:51 PM PDT 24
Peak memory 206012 kb
Host smart-328ecd76-9912-4a0c-a22c-2183b9ec8a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864186993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3864186993
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1087306139
Short name T323
Test name
Test status
Simulation time 248603654 ps
CPU time 14.03 seconds
Started Jul 04 06:49:53 PM PDT 24
Finished Jul 04 06:50:07 PM PDT 24
Peak memory 215716 kb
Host smart-902d05cc-edb6-48d9-8a74-23828aab9205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087306139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1087306139
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2793974483
Short name T814
Test name
Test status
Simulation time 105928829 ps
CPU time 4.14 seconds
Started Jul 04 06:49:52 PM PDT 24
Finished Jul 04 06:49:57 PM PDT 24
Peak memory 220664 kb
Host smart-256dd0d8-a533-4743-abd1-ae26313aea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793974483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2793974483
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.478095432
Short name T62
Test name
Test status
Simulation time 59652032 ps
CPU time 3.16 seconds
Started Jul 04 06:49:49 PM PDT 24
Finished Jul 04 06:49:53 PM PDT 24
Peak memory 219624 kb
Host smart-a3c3c3f1-a14e-4fd2-bf1a-8c0958161b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478095432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.478095432
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4063077968
Short name T227
Test name
Test status
Simulation time 97087287 ps
CPU time 3.1 seconds
Started Jul 04 06:49:52 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 214408 kb
Host smart-8e6eac48-5690-41a0-8df7-13db8b5a3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063077968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4063077968
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2594481431
Short name T418
Test name
Test status
Simulation time 141539009 ps
CPU time 3.72 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 208504 kb
Host smart-da9cf479-326f-4a5d-b4d4-2aa48929ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594481431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2594481431
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1911234765
Short name T350
Test name
Test status
Simulation time 901298213 ps
CPU time 5.93 seconds
Started Jul 04 06:49:42 PM PDT 24
Finished Jul 04 06:49:48 PM PDT 24
Peak memory 208568 kb
Host smart-ca0b97ad-97a2-4d58-9367-d6c1ab4583d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911234765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1911234765
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3545707507
Short name T748
Test name
Test status
Simulation time 69202840 ps
CPU time 2.98 seconds
Started Jul 04 06:49:44 PM PDT 24
Finished Jul 04 06:49:47 PM PDT 24
Peak memory 206992 kb
Host smart-c6e27b27-26a6-4063-8daa-e6adecb1f6f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545707507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3545707507
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.576679409
Short name T538
Test name
Test status
Simulation time 175958478 ps
CPU time 5.84 seconds
Started Jul 04 06:49:47 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 208692 kb
Host smart-b0276fb8-2d32-46a6-97b7-433d8526de6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576679409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.576679409
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.469814065
Short name T231
Test name
Test status
Simulation time 23023947 ps
CPU time 2.01 seconds
Started Jul 04 06:49:44 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 208444 kb
Host smart-1e6089e2-9e31-4f23-98be-e88ec0f804ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469814065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.469814065
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4091564512
Short name T601
Test name
Test status
Simulation time 507111012 ps
CPU time 2.8 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 215860 kb
Host smart-cd447452-ea72-491f-93ae-f4b0e2e6ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091564512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4091564512
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2075849
Short name T836
Test name
Test status
Simulation time 199957727 ps
CPU time 2.53 seconds
Started Jul 04 06:49:43 PM PDT 24
Finished Jul 04 06:49:45 PM PDT 24
Peak memory 207940 kb
Host smart-126ddd16-d4c8-4f0a-8c02-039ead2130b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2075849
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1077363621
Short name T202
Test name
Test status
Simulation time 1890181091 ps
CPU time 36.24 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:50:28 PM PDT 24
Peak memory 216464 kb
Host smart-deaea9b6-e18b-4f25-b52f-1c08ba1d05e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077363621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1077363621
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2544879008
Short name T674
Test name
Test status
Simulation time 487472850 ps
CPU time 7.21 seconds
Started Jul 04 06:49:53 PM PDT 24
Finished Jul 04 06:50:01 PM PDT 24
Peak memory 209700 kb
Host smart-c57d031a-f8f0-4db0-be26-5e40d751336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544879008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2544879008
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2551098910
Short name T901
Test name
Test status
Simulation time 81797506 ps
CPU time 2.12 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:52 PM PDT 24
Peak memory 210432 kb
Host smart-79617645-bf40-4caa-b349-c3d055a2f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551098910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2551098910
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.243394658
Short name T846
Test name
Test status
Simulation time 9688713 ps
CPU time 0.87 seconds
Started Jul 04 06:49:57 PM PDT 24
Finished Jul 04 06:49:58 PM PDT 24
Peak memory 206012 kb
Host smart-937939f9-0b66-4a62-8124-769887555cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243394658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.243394658
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2601336935
Short name T214
Test name
Test status
Simulation time 195622466 ps
CPU time 3.09 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 214312 kb
Host smart-2778a938-70d1-4137-84c8-7aec7124a561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601336935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2601336935
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3601756870
Short name T283
Test name
Test status
Simulation time 316552177 ps
CPU time 4.21 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 209044 kb
Host smart-92866d21-6545-4c9c-9706-39b3c76f7927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601756870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3601756870
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.345504084
Short name T486
Test name
Test status
Simulation time 48245427 ps
CPU time 1.99 seconds
Started Jul 04 06:49:52 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 207444 kb
Host smart-438b9f53-5ebe-4292-a564-d1ee525320c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345504084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.345504084
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2335217159
Short name T34
Test name
Test status
Simulation time 117942102 ps
CPU time 2.27 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:53 PM PDT 24
Peak memory 214316 kb
Host smart-0750ab3d-293c-4904-b50d-c3f98414ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335217159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2335217159
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2096055951
Short name T396
Test name
Test status
Simulation time 85680610 ps
CPU time 1.82 seconds
Started Jul 04 06:49:52 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 214280 kb
Host smart-dfcf13c2-e3f7-47f5-bfd3-2afbc72e1336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096055951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2096055951
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.659141049
Short name T68
Test name
Test status
Simulation time 280655789 ps
CPU time 4.25 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 209696 kb
Host smart-c2041632-5edd-4f55-a1cb-3c68ca12d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659141049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.659141049
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1604631283
Short name T232
Test name
Test status
Simulation time 474541174 ps
CPU time 5.43 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 219592 kb
Host smart-e2b13203-2164-4235-871c-512c1591098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604631283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1604631283
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2388737408
Short name T697
Test name
Test status
Simulation time 124363090 ps
CPU time 3.15 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:54 PM PDT 24
Peak memory 206900 kb
Host smart-2b0c207d-1f22-4a8b-9aac-f5925d681d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388737408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2388737408
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1908103827
Short name T77
Test name
Test status
Simulation time 44445948 ps
CPU time 1.91 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:49:53 PM PDT 24
Peak memory 208532 kb
Host smart-e83bf004-a91d-4d62-806f-c2bf39db7b79
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908103827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1908103827
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2807740260
Short name T760
Test name
Test status
Simulation time 97764620 ps
CPU time 2.82 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:53 PM PDT 24
Peak memory 209124 kb
Host smart-6da3bc29-eef2-4f26-a1db-a9b91d40c720
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807740260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2807740260
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1940381826
Short name T603
Test name
Test status
Simulation time 333332090 ps
CPU time 5.53 seconds
Started Jul 04 06:49:50 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 206844 kb
Host smart-60b31550-7052-4e79-9235-e0223fc72ad5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940381826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1940381826
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2790220099
Short name T337
Test name
Test status
Simulation time 118254532 ps
CPU time 4.64 seconds
Started Jul 04 06:49:52 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 218348 kb
Host smart-7dead48c-17d1-4901-80d7-706bd3a43b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790220099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2790220099
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.27854994
Short name T686
Test name
Test status
Simulation time 79509515 ps
CPU time 2.43 seconds
Started Jul 04 06:49:54 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 207000 kb
Host smart-b578ac2f-4450-4eae-bb7e-6ed6395a52ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27854994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.27854994
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2561891312
Short name T195
Test name
Test status
Simulation time 8724622157 ps
CPU time 50.22 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:50:41 PM PDT 24
Peak memory 215464 kb
Host smart-5b8327e4-9042-4f5a-a30a-5f128ddc43e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561891312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2561891312
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4262171855
Short name T620
Test name
Test status
Simulation time 307807292 ps
CPU time 8.71 seconds
Started Jul 04 06:49:51 PM PDT 24
Finished Jul 04 06:50:00 PM PDT 24
Peak memory 218244 kb
Host smart-4d930d8a-c76f-4002-b4b2-8d8372cb16d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262171855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4262171855
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1958388569
Short name T530
Test name
Test status
Simulation time 163053624 ps
CPU time 3.06 seconds
Started Jul 04 06:49:53 PM PDT 24
Finished Jul 04 06:49:56 PM PDT 24
Peak memory 209852 kb
Host smart-df831b9f-d5ac-468c-90c7-91b5fb89b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958388569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1958388569
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4195399608
Short name T911
Test name
Test status
Simulation time 12120923 ps
CPU time 0.75 seconds
Started Jul 04 06:50:06 PM PDT 24
Finished Jul 04 06:50:07 PM PDT 24
Peak memory 205996 kb
Host smart-a3d32ef2-1567-4e26-a81e-8d9df8fa509d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195399608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4195399608
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.117607089
Short name T408
Test name
Test status
Simulation time 35138594 ps
CPU time 2.87 seconds
Started Jul 04 06:49:59 PM PDT 24
Finished Jul 04 06:50:02 PM PDT 24
Peak memory 214584 kb
Host smart-280d8910-8ab9-4969-bb46-7231a17dc6c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117607089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.117607089
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3044953345
Short name T193
Test name
Test status
Simulation time 372711826 ps
CPU time 2.98 seconds
Started Jul 04 06:50:03 PM PDT 24
Finished Jul 04 06:50:06 PM PDT 24
Peak memory 217668 kb
Host smart-9154c663-01a0-4e3e-809a-9f7302dbf51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044953345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3044953345
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4138741008
Short name T422
Test name
Test status
Simulation time 54399965 ps
CPU time 1.72 seconds
Started Jul 04 06:50:03 PM PDT 24
Finished Jul 04 06:50:05 PM PDT 24
Peak memory 208976 kb
Host smart-ba1740b7-0668-4986-87d8-d5b00e2ee15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138741008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4138741008
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3993473789
Short name T93
Test name
Test status
Simulation time 116260361 ps
CPU time 3.48 seconds
Started Jul 04 06:50:00 PM PDT 24
Finished Jul 04 06:50:04 PM PDT 24
Peak memory 209200 kb
Host smart-1a057f3a-3443-413c-9c67-c8947bc2abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993473789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3993473789
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2559021382
Short name T358
Test name
Test status
Simulation time 87849841 ps
CPU time 2.09 seconds
Started Jul 04 06:49:56 PM PDT 24
Finished Jul 04 06:49:58 PM PDT 24
Peak memory 214292 kb
Host smart-c205e16f-a74c-4e16-b9ce-099178843beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559021382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2559021382
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.70928769
Short name T883
Test name
Test status
Simulation time 116499547 ps
CPU time 3.47 seconds
Started Jul 04 06:49:58 PM PDT 24
Finished Jul 04 06:50:02 PM PDT 24
Peak memory 214408 kb
Host smart-7585061a-51c1-4484-b626-f2fcb42c6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70928769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.70928769
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.640987340
Short name T272
Test name
Test status
Simulation time 61047864 ps
CPU time 3.2 seconds
Started Jul 04 06:49:56 PM PDT 24
Finished Jul 04 06:49:59 PM PDT 24
Peak memory 209508 kb
Host smart-bb53865b-de95-439b-beef-eaf140be6459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640987340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.640987340
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2565848187
Short name T298
Test name
Test status
Simulation time 23924519 ps
CPU time 2.08 seconds
Started Jul 04 06:50:03 PM PDT 24
Finished Jul 04 06:50:05 PM PDT 24
Peak memory 208688 kb
Host smart-d402be62-2198-4e89-81f9-266ddc6c81f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565848187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2565848187
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3582632611
Short name T812
Test name
Test status
Simulation time 101574535 ps
CPU time 3.44 seconds
Started Jul 04 06:49:59 PM PDT 24
Finished Jul 04 06:50:02 PM PDT 24
Peak memory 208888 kb
Host smart-21e9365d-6ed0-494a-a4d7-96f5ee601071
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582632611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3582632611
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3471225545
Short name T893
Test name
Test status
Simulation time 31942464 ps
CPU time 2.36 seconds
Started Jul 04 06:49:58 PM PDT 24
Finished Jul 04 06:50:01 PM PDT 24
Peak memory 206960 kb
Host smart-7e87697f-9136-48d0-9811-53eaf02486d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471225545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3471225545
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.31559981
Short name T725
Test name
Test status
Simulation time 123043329 ps
CPU time 3.25 seconds
Started Jul 04 06:49:57 PM PDT 24
Finished Jul 04 06:50:01 PM PDT 24
Peak memory 206912 kb
Host smart-57cf78b6-f4ae-4a70-b43e-1d07aeab9a08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31559981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.31559981
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.109855631
Short name T448
Test name
Test status
Simulation time 122034830 ps
CPU time 2.52 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:07 PM PDT 24
Peak memory 209416 kb
Host smart-10791082-0880-4d68-af0e-1ffeced41107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109855631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.109855631
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2089527713
Short name T589
Test name
Test status
Simulation time 117522566 ps
CPU time 2.81 seconds
Started Jul 04 06:50:01 PM PDT 24
Finished Jul 04 06:50:04 PM PDT 24
Peak memory 206824 kb
Host smart-536a52b4-d9af-4b32-ae44-075e927383bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089527713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2089527713
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3292314782
Short name T604
Test name
Test status
Simulation time 192001463 ps
CPU time 5.2 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:10 PM PDT 24
Peak memory 214360 kb
Host smart-100a47ec-7b0f-4ff9-a159-ad7094b315c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292314782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3292314782
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4100994429
Short name T470
Test name
Test status
Simulation time 959898316 ps
CPU time 9.03 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 217820 kb
Host smart-c877a22b-70e7-4391-83a4-d9d12f6e6ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100994429 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4100994429
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2713184334
Short name T769
Test name
Test status
Simulation time 280883964 ps
CPU time 2.83 seconds
Started Jul 04 06:49:59 PM PDT 24
Finished Jul 04 06:50:02 PM PDT 24
Peak memory 207692 kb
Host smart-8e34108a-87e7-4401-bcf3-f46878648181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713184334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2713184334
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3736110902
Short name T771
Test name
Test status
Simulation time 60464278 ps
CPU time 1.25 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:05 PM PDT 24
Peak memory 209636 kb
Host smart-05339721-55d2-4e97-bc71-990ddb01cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736110902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3736110902
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3703066485
Short name T479
Test name
Test status
Simulation time 22365251 ps
CPU time 0.78 seconds
Started Jul 04 06:50:06 PM PDT 24
Finished Jul 04 06:50:07 PM PDT 24
Peak memory 206008 kb
Host smart-8d7b65d3-2efd-486e-9e12-a805f484d30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703066485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3703066485
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.297766723
Short name T280
Test name
Test status
Simulation time 64199322 ps
CPU time 2.78 seconds
Started Jul 04 06:50:07 PM PDT 24
Finished Jul 04 06:50:10 PM PDT 24
Peak memory 215392 kb
Host smart-e81fb4e2-35d7-4314-93f6-6c7f43beb3fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297766723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.297766723
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2274320901
Short name T22
Test name
Test status
Simulation time 161045099 ps
CPU time 2.19 seconds
Started Jul 04 06:50:03 PM PDT 24
Finished Jul 04 06:50:06 PM PDT 24
Peak memory 221104 kb
Host smart-14dfb7c2-bc1d-4567-8f06-f652993e8f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274320901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2274320901
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.737039398
Short name T585
Test name
Test status
Simulation time 142985591 ps
CPU time 4.34 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:10 PM PDT 24
Peak memory 218488 kb
Host smart-711dac19-9be0-4adb-a400-41e739609c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737039398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.737039398
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2304470903
Short name T319
Test name
Test status
Simulation time 144429310 ps
CPU time 3.98 seconds
Started Jul 04 06:50:06 PM PDT 24
Finished Jul 04 06:50:11 PM PDT 24
Peak memory 214328 kb
Host smart-f402f905-970a-4038-890c-72f9750e9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304470903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2304470903
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2275540248
Short name T47
Test name
Test status
Simulation time 32776396 ps
CPU time 1.89 seconds
Started Jul 04 06:50:07 PM PDT 24
Finished Jul 04 06:50:09 PM PDT 24
Peak memory 214384 kb
Host smart-b2532110-a1ca-403f-aec2-d887ef7a1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275540248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2275540248
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1175382728
Short name T135
Test name
Test status
Simulation time 97190924 ps
CPU time 1.64 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:06 PM PDT 24
Peak memory 206208 kb
Host smart-9cf0aea8-6515-487b-afcd-1798956cb953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175382728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1175382728
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1888022325
Short name T756
Test name
Test status
Simulation time 502404084 ps
CPU time 18.22 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 214408 kb
Host smart-d6cf443b-c6b0-4537-a84f-7801cbc93b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888022325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1888022325
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.900147526
Short name T381
Test name
Test status
Simulation time 59990952 ps
CPU time 2.38 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:08 PM PDT 24
Peak memory 206848 kb
Host smart-eab550a8-aa40-4ab6-b4a5-cf8ff5b6715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900147526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.900147526
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1099081077
Short name T916
Test name
Test status
Simulation time 5822069102 ps
CPU time 48.06 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:52 PM PDT 24
Peak memory 208664 kb
Host smart-a24dac21-f2ec-4740-825f-e9d688c5d6e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099081077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1099081077
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1075611685
Short name T709
Test name
Test status
Simulation time 404683189 ps
CPU time 15 seconds
Started Jul 04 06:50:07 PM PDT 24
Finished Jul 04 06:50:22 PM PDT 24
Peak memory 208980 kb
Host smart-f2969791-667e-4bf9-89d9-e5b46a396531
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075611685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1075611685
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.907513781
Short name T605
Test name
Test status
Simulation time 100956855 ps
CPU time 1.82 seconds
Started Jul 04 06:50:07 PM PDT 24
Finished Jul 04 06:50:09 PM PDT 24
Peak memory 207036 kb
Host smart-cbe03b09-fb73-4483-b39c-17ed46fad650
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907513781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.907513781
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3731125598
Short name T255
Test name
Test status
Simulation time 500555996 ps
CPU time 2.34 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:08 PM PDT 24
Peak memory 214300 kb
Host smart-f14100ce-9c56-4981-98b7-ed39f41fb231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731125598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3731125598
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.846911801
Short name T429
Test name
Test status
Simulation time 909935949 ps
CPU time 4.23 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:08 PM PDT 24
Peak memory 208504 kb
Host smart-c89f2e51-aae6-4185-ad13-d7ca7cd7afa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846911801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.846911801
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3953060115
Short name T267
Test name
Test status
Simulation time 7018167214 ps
CPU time 93.77 seconds
Started Jul 04 06:50:08 PM PDT 24
Finished Jul 04 06:51:42 PM PDT 24
Peak memory 222548 kb
Host smart-ecd73c07-b388-47b4-86c1-f26cc12ff4ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953060115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3953060115
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.254575494
Short name T907
Test name
Test status
Simulation time 516888966 ps
CPU time 17.08 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 221044 kb
Host smart-caf7826d-e829-40eb-a7d2-1ce16b41104a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254575494 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.254575494
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2223736085
Short name T862
Test name
Test status
Simulation time 67814929 ps
CPU time 4.17 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:09 PM PDT 24
Peak memory 214428 kb
Host smart-8056259e-8c63-4086-85b7-321be7e720ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223736085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2223736085
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.997010381
Short name T55
Test name
Test status
Simulation time 39908042 ps
CPU time 2.04 seconds
Started Jul 04 06:50:04 PM PDT 24
Finished Jul 04 06:50:06 PM PDT 24
Peak memory 209848 kb
Host smart-9d11ff09-88c9-4c56-b7c5-2d14173fb388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997010381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.997010381
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1181244009
Short name T570
Test name
Test status
Simulation time 44447195 ps
CPU time 0.83 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:13 PM PDT 24
Peak memory 206032 kb
Host smart-0905bae6-99bb-4eaf-a6a6-38636857e37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181244009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1181244009
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.276971831
Short name T476
Test name
Test status
Simulation time 539476377 ps
CPU time 2.78 seconds
Started Jul 04 06:50:20 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 214332 kb
Host smart-a140a14d-da1d-43ee-8499-96f23463cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276971831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.276971831
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3351147421
Short name T759
Test name
Test status
Simulation time 123601016 ps
CPU time 3.94 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 214288 kb
Host smart-c4ade67a-7f48-40ca-98de-91d2e7d69287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351147421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3351147421
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3796452965
Short name T212
Test name
Test status
Simulation time 38766151 ps
CPU time 2.92 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:16 PM PDT 24
Peak memory 207952 kb
Host smart-bdc07478-968c-47c4-8981-ae68058ba4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796452965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3796452965
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1585091971
Short name T354
Test name
Test status
Simulation time 784064209 ps
CPU time 19.04 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:33 PM PDT 24
Peak memory 219256 kb
Host smart-a4892e8d-1bb4-4a47-bacf-a4bc7e1fbaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585091971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1585091971
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1203689465
Short name T553
Test name
Test status
Simulation time 260389193 ps
CPU time 7.55 seconds
Started Jul 04 06:50:11 PM PDT 24
Finished Jul 04 06:50:18 PM PDT 24
Peak memory 207976 kb
Host smart-baee8103-53b2-4542-9234-fae21c3cb0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203689465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1203689465
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3367214159
Short name T380
Test name
Test status
Simulation time 64770643 ps
CPU time 2.46 seconds
Started Jul 04 06:50:11 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 207020 kb
Host smart-60530161-8a9e-4104-b0b3-4ba922f8b171
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367214159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3367214159
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4071891202
Short name T628
Test name
Test status
Simulation time 42320181 ps
CPU time 2.47 seconds
Started Jul 04 06:50:19 PM PDT 24
Finished Jul 04 06:50:22 PM PDT 24
Peak memory 206980 kb
Host smart-abc7c139-8b20-438e-a1f2-f630d7b63c62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071891202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4071891202
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2561481567
Short name T626
Test name
Test status
Simulation time 388635289 ps
CPU time 6.61 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:20 PM PDT 24
Peak memory 218204 kb
Host smart-44403c99-d099-42ac-9ea7-16f8f6b4a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561481567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2561481567
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3172294756
Short name T602
Test name
Test status
Simulation time 56190311 ps
CPU time 2.72 seconds
Started Jul 04 06:50:05 PM PDT 24
Finished Jul 04 06:50:08 PM PDT 24
Peak memory 208172 kb
Host smart-03cd1d57-9cc1-4112-a729-025a151504b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172294756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3172294756
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.614513355
Short name T268
Test name
Test status
Simulation time 3052931602 ps
CPU time 39.6 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:52 PM PDT 24
Peak memory 222624 kb
Host smart-9edc4985-8eb1-4ec8-a4af-52d80befadf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614513355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.614513355
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3012591941
Short name T173
Test name
Test status
Simulation time 1175074593 ps
CPU time 9.85 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:24 PM PDT 24
Peak memory 222664 kb
Host smart-4a6fecb4-1018-4402-bdaf-b256e6296238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012591941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3012591941
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4227180009
Short name T317
Test name
Test status
Simulation time 3048709411 ps
CPU time 8.83 seconds
Started Jul 04 06:50:16 PM PDT 24
Finished Jul 04 06:50:25 PM PDT 24
Peak memory 218592 kb
Host smart-46f9ab21-e9a8-49cf-aff4-8318e934a252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227180009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4227180009
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1444425239
Short name T13
Test name
Test status
Simulation time 279614558 ps
CPU time 3.8 seconds
Started Jul 04 06:50:11 PM PDT 24
Finished Jul 04 06:50:15 PM PDT 24
Peak memory 209948 kb
Host smart-89f4adb1-a000-4f7a-96e3-b1dc25f41163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444425239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1444425239
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.525364888
Short name T413
Test name
Test status
Simulation time 14341230 ps
CPU time 0.79 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 206028 kb
Host smart-793c9d17-6fa6-4ef1-bb20-3bf0cafc60b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525364888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.525364888
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2658520339
Short name T913
Test name
Test status
Simulation time 32555930 ps
CPU time 2.73 seconds
Started Jul 04 06:50:11 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 214364 kb
Host smart-965e24ea-b923-4de1-a6cf-31b820901114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658520339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2658520339
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3013988265
Short name T811
Test name
Test status
Simulation time 138590060 ps
CPU time 3.07 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:15 PM PDT 24
Peak memory 214696 kb
Host smart-62f4dac2-edd4-435e-b465-f29cf68313ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013988265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3013988265
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3321398697
Short name T687
Test name
Test status
Simulation time 69593512 ps
CPU time 2.47 seconds
Started Jul 04 06:50:16 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 215320 kb
Host smart-57933cf8-4972-4baf-8893-d6b29593838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321398697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3321398697
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3772775616
Short name T246
Test name
Test status
Simulation time 254307431 ps
CPU time 4.78 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 222332 kb
Host smart-9556bda6-f12b-4def-9224-11ada7ff940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772775616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3772775616
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1511212878
Short name T57
Test name
Test status
Simulation time 93284485 ps
CPU time 3.78 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 209536 kb
Host smart-b56b2e45-bbab-4c08-8014-e2c491271c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511212878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1511212878
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.788501395
Short name T799
Test name
Test status
Simulation time 962025045 ps
CPU time 5.52 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 222580 kb
Host smart-0da5f087-9c20-403a-95f6-8684599ceec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788501395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.788501395
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1036897599
Short name T375
Test name
Test status
Simulation time 126959829 ps
CPU time 4.29 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:17 PM PDT 24
Peak memory 208652 kb
Host smart-cb12b884-5d1a-40a4-bc9a-b654dfb70748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036897599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1036897599
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3689673730
Short name T291
Test name
Test status
Simulation time 3202754489 ps
CPU time 31.93 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:46 PM PDT 24
Peak memory 208048 kb
Host smart-433fb7d6-c091-4c3c-b609-0cfef2f841c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689673730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3689673730
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1572025687
Short name T870
Test name
Test status
Simulation time 157990257 ps
CPU time 2.29 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:16 PM PDT 24
Peak memory 206812 kb
Host smart-d87b3e6f-5b1d-40bc-88ab-168cbac8abd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572025687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1572025687
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1665255748
Short name T285
Test name
Test status
Simulation time 194344612 ps
CPU time 7.4 seconds
Started Jul 04 06:50:30 PM PDT 24
Finished Jul 04 06:50:37 PM PDT 24
Peak memory 206916 kb
Host smart-9f1928fd-027b-473c-b7a2-e5695591a1a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665255748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1665255748
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4276202891
Short name T888
Test name
Test status
Simulation time 2161447576 ps
CPU time 12.35 seconds
Started Jul 04 06:50:16 PM PDT 24
Finished Jul 04 06:50:29 PM PDT 24
Peak memory 218560 kb
Host smart-40bd8c70-9360-4013-994b-151b1cb5cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276202891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4276202891
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3901109960
Short name T840
Test name
Test status
Simulation time 848044996 ps
CPU time 2.75 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:16 PM PDT 24
Peak memory 208432 kb
Host smart-d2874155-47b8-4615-b21f-c14b0a68fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901109960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3901109960
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4236174302
Short name T201
Test name
Test status
Simulation time 2817824084 ps
CPU time 34.66 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:47 PM PDT 24
Peak memory 215900 kb
Host smart-862f7c1c-acc1-462f-96ec-70b47e37e431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236174302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4236174302
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1314901759
Short name T586
Test name
Test status
Simulation time 9934677469 ps
CPU time 53.56 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:51:07 PM PDT 24
Peak memory 214404 kb
Host smart-8e0e8f38-9aea-464a-bee1-80644da2d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314901759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1314901759
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1527619973
Short name T914
Test name
Test status
Simulation time 26347828 ps
CPU time 1.53 seconds
Started Jul 04 06:50:19 PM PDT 24
Finished Jul 04 06:50:21 PM PDT 24
Peak memory 208676 kb
Host smart-2780c8d1-76a8-4ee4-88ab-a49daf41eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527619973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1527619973
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3995125288
Short name T447
Test name
Test status
Simulation time 40615397 ps
CPU time 0.97 seconds
Started Jul 04 06:50:18 PM PDT 24
Finished Jul 04 06:50:20 PM PDT 24
Peak memory 206132 kb
Host smart-23d17779-3f0b-43a5-8528-45124de557f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995125288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3995125288
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3063467389
Short name T326
Test name
Test status
Simulation time 76556193 ps
CPU time 2.99 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:15 PM PDT 24
Peak memory 214348 kb
Host smart-07b6c50c-5997-40e5-b7de-395402eaacaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063467389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3063467389
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.806293039
Short name T402
Test name
Test status
Simulation time 68768271 ps
CPU time 1.71 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:15 PM PDT 24
Peak memory 207812 kb
Host smart-1ad341fe-2362-4562-8363-dc0e12d61489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806293039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.806293039
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1448401276
Short name T699
Test name
Test status
Simulation time 222137871 ps
CPU time 4.01 seconds
Started Jul 04 06:50:15 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 209304 kb
Host smart-e96b8100-b419-4e6c-ba98-83a44d943d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448401276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1448401276
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2059380517
Short name T491
Test name
Test status
Simulation time 60973786 ps
CPU time 2.74 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:16 PM PDT 24
Peak memory 221124 kb
Host smart-6cc9a858-8137-48db-acf7-e1b49da2491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059380517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2059380517
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2106623972
Short name T482
Test name
Test status
Simulation time 380102801 ps
CPU time 3.91 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:16 PM PDT 24
Peak memory 222548 kb
Host smart-c5d01d8f-37fd-4e8c-a9fc-129ae7f6f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106623972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2106623972
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.785010099
Short name T353
Test name
Test status
Simulation time 106129992 ps
CPU time 3.71 seconds
Started Jul 04 06:50:17 PM PDT 24
Finished Jul 04 06:50:20 PM PDT 24
Peak memory 214920 kb
Host smart-03eff056-ee92-439a-b467-1705f176095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785010099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.785010099
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3253867532
Short name T467
Test name
Test status
Simulation time 34767753 ps
CPU time 2.2 seconds
Started Jul 04 06:50:19 PM PDT 24
Finished Jul 04 06:50:21 PM PDT 24
Peak memory 206988 kb
Host smart-8ea952fd-fee8-41e8-93ab-869458a51817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253867532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3253867532
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3578097102
Short name T343
Test name
Test status
Simulation time 467360456 ps
CPU time 6.64 seconds
Started Jul 04 06:50:12 PM PDT 24
Finished Jul 04 06:50:19 PM PDT 24
Peak memory 208724 kb
Host smart-b5cae091-b20b-44af-92f4-b18f3596f237
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578097102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3578097102
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2491646928
Short name T730
Test name
Test status
Simulation time 112408118 ps
CPU time 3.17 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:18 PM PDT 24
Peak memory 206956 kb
Host smart-6b1eef38-7e82-4dc4-b40e-202fc7603f8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491646928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2491646928
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3020888675
Short name T625
Test name
Test status
Simulation time 4059270412 ps
CPU time 23.12 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:37 PM PDT 24
Peak memory 208040 kb
Host smart-a54f98ad-ca3e-4f07-b70c-159695d1abb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020888675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3020888675
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2926301055
Short name T666
Test name
Test status
Simulation time 123559787 ps
CPU time 3.3 seconds
Started Jul 04 06:50:14 PM PDT 24
Finished Jul 04 06:50:18 PM PDT 24
Peak memory 209576 kb
Host smart-b9721f40-3c48-4bc4-87f0-b6bf728b564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926301055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2926301055
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1432107166
Short name T714
Test name
Test status
Simulation time 353640674 ps
CPU time 10.84 seconds
Started Jul 04 06:50:16 PM PDT 24
Finished Jul 04 06:50:27 PM PDT 24
Peak memory 207892 kb
Host smart-ff88a035-515e-47f9-9037-ced97088caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432107166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1432107166
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1182787339
Short name T253
Test name
Test status
Simulation time 3520700857 ps
CPU time 52.57 seconds
Started Jul 04 06:50:18 PM PDT 24
Finished Jul 04 06:51:11 PM PDT 24
Peak memory 222648 kb
Host smart-7f77d3e6-463e-4135-af2f-72a1f396f7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182787339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1182787339
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2650922871
Short name T349
Test name
Test status
Simulation time 702250097 ps
CPU time 14.25 seconds
Started Jul 04 06:50:22 PM PDT 24
Finished Jul 04 06:50:37 PM PDT 24
Peak memory 222580 kb
Host smart-5c10ecf8-fae7-40e2-83d8-9f8b38df14fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650922871 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2650922871
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3353116509
Short name T100
Test name
Test status
Simulation time 3116489970 ps
CPU time 32.77 seconds
Started Jul 04 06:50:13 PM PDT 24
Finished Jul 04 06:50:46 PM PDT 24
Peak memory 209116 kb
Host smart-4aac6616-1132-494a-81d8-fd0da560bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353116509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3353116509
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1837619786
Short name T594
Test name
Test status
Simulation time 100331183 ps
CPU time 2 seconds
Started Jul 04 06:50:19 PM PDT 24
Finished Jul 04 06:50:22 PM PDT 24
Peak memory 210252 kb
Host smart-e0166dbe-22b0-4d10-b07c-46303160c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837619786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1837619786
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3554451508
Short name T435
Test name
Test status
Simulation time 15534846 ps
CPU time 0.79 seconds
Started Jul 04 06:50:20 PM PDT 24
Finished Jul 04 06:50:21 PM PDT 24
Peak memory 205996 kb
Host smart-c2b4bb90-adaf-4361-8795-e8bd3943a95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554451508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3554451508
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3496507311
Short name T391
Test name
Test status
Simulation time 126642615 ps
CPU time 7.71 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:28 PM PDT 24
Peak memory 215044 kb
Host smart-ec429732-94af-4f42-a2f4-a63feb2676f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496507311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3496507311
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1629715408
Short name T773
Test name
Test status
Simulation time 62198782 ps
CPU time 4.11 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:26 PM PDT 24
Peak memory 209004 kb
Host smart-d769d524-3c42-454e-a9fb-1807052cbe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629715408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1629715408
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2798400829
Short name T588
Test name
Test status
Simulation time 106802883 ps
CPU time 2.06 seconds
Started Jul 04 06:50:18 PM PDT 24
Finished Jul 04 06:50:21 PM PDT 24
Peak memory 208012 kb
Host smart-6a700514-ce6f-4837-a1a7-04de4320763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798400829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2798400829
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2675221539
Short name T334
Test name
Test status
Simulation time 81578063 ps
CPU time 2.92 seconds
Started Jul 04 06:50:20 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 214340 kb
Host smart-a6b4b83b-40af-4fe1-ac30-d3b7551b6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675221539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2675221539
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2632134703
Short name T225
Test name
Test status
Simulation time 611926916 ps
CPU time 2.79 seconds
Started Jul 04 06:50:23 PM PDT 24
Finished Jul 04 06:50:26 PM PDT 24
Peak memory 214308 kb
Host smart-719f03bd-6100-486a-837d-62593edaf167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632134703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2632134703
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2822435442
Short name T191
Test name
Test status
Simulation time 115830164 ps
CPU time 3.03 seconds
Started Jul 04 06:50:20 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 222556 kb
Host smart-f8fbeb4d-3765-4c5e-bf0a-870f57d95dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822435442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2822435442
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1926546637
Short name T547
Test name
Test status
Simulation time 657045341 ps
CPU time 7.14 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:28 PM PDT 24
Peak memory 214304 kb
Host smart-550df522-eb2d-45a0-8947-badbaa39f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926546637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1926546637
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3460503141
Short name T737
Test name
Test status
Simulation time 77675146 ps
CPU time 2.63 seconds
Started Jul 04 06:50:22 PM PDT 24
Finished Jul 04 06:50:25 PM PDT 24
Peak memory 206152 kb
Host smart-8d8734c2-d0a0-440a-939a-c58e22f6f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460503141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3460503141
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1550680852
Short name T631
Test name
Test status
Simulation time 158003224 ps
CPU time 3.63 seconds
Started Jul 04 06:50:28 PM PDT 24
Finished Jul 04 06:50:32 PM PDT 24
Peak memory 207280 kb
Host smart-eb73c524-d7c5-4b2a-a0d4-daf10e561e3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550680852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1550680852
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.236761409
Short name T713
Test name
Test status
Simulation time 48706615 ps
CPU time 2.81 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:24 PM PDT 24
Peak memory 207092 kb
Host smart-85da856f-d39b-4ac6-949f-236af151362e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236761409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.236761409
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.765187772
Short name T385
Test name
Test status
Simulation time 244066493 ps
CPU time 3.14 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:24 PM PDT 24
Peak memory 206988 kb
Host smart-0120f494-70a3-42da-938b-973df9859460
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765187772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.765187772
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2409041331
Short name T884
Test name
Test status
Simulation time 207794612 ps
CPU time 2.57 seconds
Started Jul 04 06:50:20 PM PDT 24
Finished Jul 04 06:50:23 PM PDT 24
Peak memory 218208 kb
Host smart-80ef027f-1708-4526-b15d-2e8565967fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409041331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2409041331
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.459806962
Short name T741
Test name
Test status
Simulation time 419711147 ps
CPU time 5.5 seconds
Started Jul 04 06:50:22 PM PDT 24
Finished Jul 04 06:50:27 PM PDT 24
Peak memory 206952 kb
Host smart-397c48b2-0eaf-409c-b101-aa93577c17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459806962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.459806962
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3606775362
Short name T263
Test name
Test status
Simulation time 3178034999 ps
CPU time 14.37 seconds
Started Jul 04 06:50:21 PM PDT 24
Finished Jul 04 06:50:35 PM PDT 24
Peak memory 216672 kb
Host smart-cb300dbf-16c7-46bc-8637-ca9a42d953ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606775362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3606775362
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3607001390
Short name T69
Test name
Test status
Simulation time 105349887 ps
CPU time 6.18 seconds
Started Jul 04 06:50:22 PM PDT 24
Finished Jul 04 06:50:28 PM PDT 24
Peak memory 220580 kb
Host smart-388739a4-75eb-4b8d-ae2e-dab0978daed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607001390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3607001390
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.926015664
Short name T822
Test name
Test status
Simulation time 2526573896 ps
CPU time 19.87 seconds
Started Jul 04 06:50:23 PM PDT 24
Finished Jul 04 06:50:43 PM PDT 24
Peak memory 214608 kb
Host smart-ea6aef92-08cf-4ec6-a8fe-04e2bfce4d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926015664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.926015664
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3079598544
Short name T571
Test name
Test status
Simulation time 120704657 ps
CPU time 1.97 seconds
Started Jul 04 06:50:18 PM PDT 24
Finished Jul 04 06:50:20 PM PDT 24
Peak memory 210056 kb
Host smart-3550de45-6d2b-4cc6-befb-5f47f9ef6165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079598544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3079598544
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.579741066
Short name T431
Test name
Test status
Simulation time 176156447 ps
CPU time 1.07 seconds
Started Jul 04 06:46:46 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 206120 kb
Host smart-abefb87d-6378-4ca9-9edd-ec25fc34f1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579741066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.579741066
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2078898369
Short name T671
Test name
Test status
Simulation time 1251623863 ps
CPU time 31.99 seconds
Started Jul 04 06:46:39 PM PDT 24
Finished Jul 04 06:47:11 PM PDT 24
Peak memory 218440 kb
Host smart-4852e009-f960-4d18-af27-c056f7f33265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078898369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2078898369
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3975182150
Short name T299
Test name
Test status
Simulation time 179144633 ps
CPU time 4.15 seconds
Started Jul 04 06:46:39 PM PDT 24
Finished Jul 04 06:46:43 PM PDT 24
Peak memory 214360 kb
Host smart-f062c352-956c-4bbd-b6e4-2a9a09969d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975182150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3975182150
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3657669493
Short name T90
Test name
Test status
Simulation time 394425360 ps
CPU time 5.85 seconds
Started Jul 04 06:46:38 PM PDT 24
Finished Jul 04 06:46:44 PM PDT 24
Peak memory 209144 kb
Host smart-f0e590c9-6f3a-4684-a4e5-bb60ce3ba17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657669493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3657669493
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1051744018
Short name T882
Test name
Test status
Simulation time 116657463 ps
CPU time 2.78 seconds
Started Jul 04 06:46:37 PM PDT 24
Finished Jul 04 06:46:40 PM PDT 24
Peak memory 222412 kb
Host smart-09112407-d869-414e-b9e4-f1f48776649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051744018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1051744018
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1690207302
Short name T186
Test name
Test status
Simulation time 745974807 ps
CPU time 3.36 seconds
Started Jul 04 06:46:38 PM PDT 24
Finished Jul 04 06:46:41 PM PDT 24
Peak memory 214328 kb
Host smart-d17bd474-d42a-4e2a-96b6-ddb2bbe8c756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690207302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1690207302
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3889971164
Short name T475
Test name
Test status
Simulation time 65221562 ps
CPU time 4.2 seconds
Started Jul 04 06:46:37 PM PDT 24
Finished Jul 04 06:46:41 PM PDT 24
Peak memory 218412 kb
Host smart-b60df38a-6eb7-4d2b-a276-632c696621d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889971164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3889971164
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4090834918
Short name T591
Test name
Test status
Simulation time 142124789 ps
CPU time 3.53 seconds
Started Jul 04 06:46:29 PM PDT 24
Finished Jul 04 06:46:33 PM PDT 24
Peak memory 206984 kb
Host smart-91f68fc5-4f83-4f6b-bb56-08efb9edfcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090834918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4090834918
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4116758603
Short name T619
Test name
Test status
Simulation time 826164935 ps
CPU time 7.97 seconds
Started Jul 04 06:46:37 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 208092 kb
Host smart-73cde8de-7ba8-4563-98d7-0f3f32d39218
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116758603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4116758603
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1095715910
Short name T261
Test name
Test status
Simulation time 8866285964 ps
CPU time 22.37 seconds
Started Jul 04 06:46:38 PM PDT 24
Finished Jul 04 06:47:01 PM PDT 24
Peak memory 208560 kb
Host smart-3a39c6d7-4a6e-4e7d-9298-5f2494f36a46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095715910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1095715910
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2325361879
Short name T746
Test name
Test status
Simulation time 352135522 ps
CPU time 9.56 seconds
Started Jul 04 06:46:36 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 208196 kb
Host smart-4172d358-04ed-4702-b75d-0867912ce2e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325361879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2325361879
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.568735182
Short name T568
Test name
Test status
Simulation time 48404376 ps
CPU time 2.03 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 208144 kb
Host smart-33fee275-84a0-49a6-81dd-6e4d0f8d6d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568735182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.568735182
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1650136846
Short name T465
Test name
Test status
Simulation time 182312267 ps
CPU time 2.58 seconds
Started Jul 04 06:46:33 PM PDT 24
Finished Jul 04 06:46:36 PM PDT 24
Peak memory 208516 kb
Host smart-0a19b2e2-9994-4980-8e6d-619f3a92690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650136846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1650136846
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4277346758
Short name T344
Test name
Test status
Simulation time 2137179468 ps
CPU time 23.41 seconds
Started Jul 04 06:46:43 PM PDT 24
Finished Jul 04 06:47:07 PM PDT 24
Peak memory 217412 kb
Host smart-62f781c4-27da-488f-86eb-00f7350b1688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277346758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4277346758
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4116322125
Short name T669
Test name
Test status
Simulation time 1050291939 ps
CPU time 11.91 seconds
Started Jul 04 06:46:38 PM PDT 24
Finished Jul 04 06:46:50 PM PDT 24
Peak memory 210064 kb
Host smart-8e8634eb-b297-43d8-a80f-9dc0571a1912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116322125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4116322125
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2822426147
Short name T368
Test name
Test status
Simulation time 341497599 ps
CPU time 3.32 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 210720 kb
Host smart-e04f1d9a-bc5a-4181-b873-80ad3540e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822426147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2822426147
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3736682898
Short name T909
Test name
Test status
Simulation time 12443583 ps
CPU time 0.73 seconds
Started Jul 04 06:46:46 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 206020 kb
Host smart-a1393b7b-1cce-4067-8feb-d8c5ae9d7bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736682898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3736682898
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.513011776
Short name T763
Test name
Test status
Simulation time 2446690194 ps
CPU time 51.51 seconds
Started Jul 04 06:46:46 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 215036 kb
Host smart-1ff9e421-ac47-449c-a00c-49a7113af4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513011776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.513011776
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.93720069
Short name T28
Test name
Test status
Simulation time 582983044 ps
CPU time 4.4 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 216284 kb
Host smart-68a653ac-a97f-43da-9afa-b9090aa5216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93720069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.93720069
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3759771660
Short name T683
Test name
Test status
Simulation time 57569408 ps
CPU time 2.76 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 207472 kb
Host smart-8c91bd7c-a0ab-48ea-a7b5-063aa0e6858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759771660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3759771660
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3445461290
Short name T673
Test name
Test status
Simulation time 37618585 ps
CPU time 2.43 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 222496 kb
Host smart-2c0553e6-285f-4ef8-98a5-dc3574102585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445461290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3445461290
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3144052261
Short name T274
Test name
Test status
Simulation time 42419554 ps
CPU time 2.91 seconds
Started Jul 04 06:46:43 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 222440 kb
Host smart-7f1f3c8e-5c36-42ce-bbce-232841470b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144052261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3144052261
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2624094722
Short name T455
Test name
Test status
Simulation time 47720656 ps
CPU time 3 seconds
Started Jul 04 06:46:43 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 219816 kb
Host smart-af55b80f-0c08-4507-bb5b-7afce87bd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624094722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2624094722
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1976646259
Short name T466
Test name
Test status
Simulation time 89152812 ps
CPU time 4.58 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:49 PM PDT 24
Peak memory 208220 kb
Host smart-06f7b7d3-9465-401a-a0b3-5fd5720fb1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976646259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1976646259
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2523931836
Short name T526
Test name
Test status
Simulation time 39296501 ps
CPU time 2.73 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:46:48 PM PDT 24
Peak memory 208788 kb
Host smart-ac1aa4c3-f693-45c9-89ba-cd79bf25076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523931836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2523931836
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2787817795
Short name T778
Test name
Test status
Simulation time 463362578 ps
CPU time 4.06 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:49 PM PDT 24
Peak memory 208888 kb
Host smart-bb897639-7c2c-4114-84c7-db942cb1b9d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787817795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2787817795
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3613552196
Short name T825
Test name
Test status
Simulation time 350979496 ps
CPU time 2.27 seconds
Started Jul 04 06:46:48 PM PDT 24
Finished Jul 04 06:46:51 PM PDT 24
Peak memory 206976 kb
Host smart-c0bf524e-f3af-4d13-949c-2e294358e588
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613552196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3613552196
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1983293333
Short name T498
Test name
Test status
Simulation time 724841036 ps
CPU time 19.43 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:47:04 PM PDT 24
Peak memory 208844 kb
Host smart-33fc1bbb-c857-4011-a99c-e12584795a75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983293333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1983293333
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1310568283
Short name T854
Test name
Test status
Simulation time 80608015 ps
CPU time 2.6 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:46:48 PM PDT 24
Peak memory 209868 kb
Host smart-79d957a5-894f-4ecb-934d-9e22e30d36e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310568283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1310568283
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2599876007
Short name T670
Test name
Test status
Simulation time 184016825 ps
CPU time 5.3 seconds
Started Jul 04 06:46:47 PM PDT 24
Finished Jul 04 06:46:52 PM PDT 24
Peak memory 208124 kb
Host smart-fde84376-6742-41dc-9ecb-e6dfdd66c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599876007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2599876007
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1679873234
Short name T523
Test name
Test status
Simulation time 17239299502 ps
CPU time 113.51 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:48:44 PM PDT 24
Peak memory 216500 kb
Host smart-4627f6fe-1960-4e15-9658-43b5c504c9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679873234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1679873234
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1031571815
Short name T578
Test name
Test status
Simulation time 1511009807 ps
CPU time 7.24 seconds
Started Jul 04 06:46:46 PM PDT 24
Finished Jul 04 06:46:53 PM PDT 24
Peak memory 222548 kb
Host smart-e2223369-c160-40c9-9e72-cce077acc140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031571815 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1031571815
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.896437534
Short name T790
Test name
Test status
Simulation time 1917136694 ps
CPU time 35.78 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:47:21 PM PDT 24
Peak memory 214336 kb
Host smart-91814b88-4fa5-4304-a903-aa96ec640621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896437534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.896437534
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2068024844
Short name T141
Test name
Test status
Simulation time 59217206 ps
CPU time 2.39 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:47 PM PDT 24
Peak memory 210124 kb
Host smart-a4158dc2-3758-4365-a8b3-90e77c9ec016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068024844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2068024844
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.982912611
Short name T786
Test name
Test status
Simulation time 33722134 ps
CPU time 0.82 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:52 PM PDT 24
Peak memory 205992 kb
Host smart-6d849e17-eb78-4ea4-a09b-ffc16559f348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982912611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.982912611
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.849339688
Short name T14
Test name
Test status
Simulation time 69804444 ps
CPU time 2.48 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:53 PM PDT 24
Peak memory 207624 kb
Host smart-80d8da4f-44f0-44e9-a647-c4f5b54913d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849339688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.849339688
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2108226957
Short name T73
Test name
Test status
Simulation time 138822399 ps
CPU time 5.19 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:49 PM PDT 24
Peak memory 219988 kb
Host smart-2f9141fd-8171-4a3b-ac68-d498b94aa50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108226957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2108226957
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1565965118
Short name T85
Test name
Test status
Simulation time 453573820 ps
CPU time 4.81 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:56 PM PDT 24
Peak memory 222352 kb
Host smart-e62019d1-69b9-41d7-b91f-01b72b8f4b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565965118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1565965118
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2229469902
Short name T297
Test name
Test status
Simulation time 132235102 ps
CPU time 2.6 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:53 PM PDT 24
Peak memory 214312 kb
Host smart-8f1bb4f0-2a6b-4fcf-a7e3-bf51420dca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229469902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2229469902
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2281761846
Short name T531
Test name
Test status
Simulation time 487852273 ps
CPU time 2.22 seconds
Started Jul 04 06:46:52 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 220248 kb
Host smart-b9852631-f95f-4a80-8c77-120f39b7271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281761846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2281761846
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3088465106
Short name T555
Test name
Test status
Simulation time 196708854 ps
CPU time 3.43 seconds
Started Jul 04 06:46:44 PM PDT 24
Finished Jul 04 06:46:48 PM PDT 24
Peak memory 209900 kb
Host smart-a40be852-b7ad-4db2-9ac7-f0ffe9678223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088465106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3088465106
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1678603476
Short name T665
Test name
Test status
Simulation time 104011396 ps
CPU time 3.68 seconds
Started Jul 04 06:46:48 PM PDT 24
Finished Jul 04 06:46:52 PM PDT 24
Peak memory 208652 kb
Host smart-da1b273f-f5a0-4260-b22e-6d223b613586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678603476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1678603476
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3144977892
Short name T338
Test name
Test status
Simulation time 279528117 ps
CPU time 3.3 seconds
Started Jul 04 06:46:42 PM PDT 24
Finished Jul 04 06:46:46 PM PDT 24
Peak memory 208792 kb
Host smart-e583b02a-5036-4ef8-bade-19ecadbffa2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144977892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3144977892
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4269271928
Short name T630
Test name
Test status
Simulation time 881944054 ps
CPU time 7.96 seconds
Started Jul 04 06:46:45 PM PDT 24
Finished Jul 04 06:46:53 PM PDT 24
Peak memory 208724 kb
Host smart-f558dd44-6cf5-48f5-ab9e-076876c38b9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269271928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4269271928
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1059470607
Short name T321
Test name
Test status
Simulation time 2129815267 ps
CPU time 18.42 seconds
Started Jul 04 06:46:48 PM PDT 24
Finished Jul 04 06:47:07 PM PDT 24
Peak memory 208972 kb
Host smart-01d35c42-5f6d-4f05-ad3b-9a2520ee270f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059470607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1059470607
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3855378407
Short name T220
Test name
Test status
Simulation time 143860053 ps
CPU time 2.99 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 209312 kb
Host smart-627a17ea-fdfc-453a-8e75-ae32a391dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855378407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3855378407
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3201394953
Short name T532
Test name
Test status
Simulation time 68659805 ps
CPU time 2.31 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:52 PM PDT 24
Peak memory 206728 kb
Host smart-63467ef1-b310-4564-bcdc-075d37ca76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201394953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3201394953
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2689684503
Short name T636
Test name
Test status
Simulation time 262880008 ps
CPU time 5.28 seconds
Started Jul 04 06:46:52 PM PDT 24
Finished Jul 04 06:46:57 PM PDT 24
Peak memory 222600 kb
Host smart-20c93421-7688-4e51-b244-03fed5f55cd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689684503 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2689684503
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1512947090
Short name T303
Test name
Test status
Simulation time 218050483 ps
CPU time 3.16 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:55 PM PDT 24
Peak memory 218540 kb
Host smart-e8c4a224-fbc2-472c-884c-d22d81ac6224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512947090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1512947090
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1921162357
Short name T363
Test name
Test status
Simulation time 123246307 ps
CPU time 4.27 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:55 PM PDT 24
Peak memory 210512 kb
Host smart-57f2a883-72ce-4657-bddf-52cb520f8123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921162357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1921162357
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1252394773
Short name T609
Test name
Test status
Simulation time 39183106 ps
CPU time 0.83 seconds
Started Jul 04 06:46:57 PM PDT 24
Finished Jul 04 06:46:58 PM PDT 24
Peak memory 206036 kb
Host smart-755ededa-80e9-42db-95c3-f080fa2306a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252394773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1252394773
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3983804110
Short name T390
Test name
Test status
Simulation time 116153313 ps
CPU time 3.25 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 214340 kb
Host smart-2b5a7a93-e6cf-43c9-b71f-4474e7c382f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983804110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3983804110
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3649522716
Short name T29
Test name
Test status
Simulation time 150784841 ps
CPU time 2.88 seconds
Started Jul 04 06:46:58 PM PDT 24
Finished Jul 04 06:47:01 PM PDT 24
Peak memory 214352 kb
Host smart-08d6df7e-f130-429b-a26f-b84fb542d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649522716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3649522716
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.112172294
Short name T867
Test name
Test status
Simulation time 67910869 ps
CPU time 2.75 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:46:59 PM PDT 24
Peak memory 208144 kb
Host smart-71f189ce-f821-44ec-b85b-dc9e71d18de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112172294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.112172294
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4068556048
Short name T94
Test name
Test status
Simulation time 4479854014 ps
CPU time 33.25 seconds
Started Jul 04 06:46:49 PM PDT 24
Finished Jul 04 06:47:23 PM PDT 24
Peak memory 214356 kb
Host smart-53e0c2a3-377c-43c6-b386-a1507f20978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068556048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4068556048
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2682982101
Short name T695
Test name
Test status
Simulation time 161140518 ps
CPU time 3.84 seconds
Started Jul 04 06:46:59 PM PDT 24
Finished Jul 04 06:47:03 PM PDT 24
Peak memory 214212 kb
Host smart-ba6c12de-4f77-468a-8145-8224ae7af80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682982101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2682982101
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3360873998
Short name T622
Test name
Test status
Simulation time 169690158 ps
CPU time 7.65 seconds
Started Jul 04 06:46:52 PM PDT 24
Finished Jul 04 06:47:00 PM PDT 24
Peak memory 222412 kb
Host smart-613cf668-65dd-4a79-9c0a-1ed598372744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360873998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3360873998
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2487119890
Short name T520
Test name
Test status
Simulation time 52543584 ps
CPU time 2.9 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 206860 kb
Host smart-8bcbefbc-2b9b-40ae-9a4d-df330954ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487119890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2487119890
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1151505409
Short name T355
Test name
Test status
Simulation time 319856147 ps
CPU time 8.54 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:46:58 PM PDT 24
Peak memory 208656 kb
Host smart-1339b6aa-a326-4dc0-b5b9-46507fafab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151505409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1151505409
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1021203543
Short name T767
Test name
Test status
Simulation time 110560573 ps
CPU time 2.3 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:46:58 PM PDT 24
Peak memory 206976 kb
Host smart-362f48fa-539a-4d0c-98f4-0c24e521d852
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021203543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1021203543
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4026793680
Short name T848
Test name
Test status
Simulation time 208552887 ps
CPU time 3.85 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:55 PM PDT 24
Peak memory 207120 kb
Host smart-db442867-7e09-406c-b690-24ebfa4d7448
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026793680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4026793680
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.556919869
Short name T15
Test name
Test status
Simulation time 13953371953 ps
CPU time 71.11 seconds
Started Jul 04 06:46:50 PM PDT 24
Finished Jul 04 06:48:02 PM PDT 24
Peak memory 208524 kb
Host smart-39b61236-2911-4777-8e9f-1666cfd403ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556919869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.556919869
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1892576150
Short name T678
Test name
Test status
Simulation time 351091514 ps
CPU time 3.99 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:47:00 PM PDT 24
Peak memory 216028 kb
Host smart-c2ef9146-a0aa-49aa-8d5a-0a69c8e76974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892576150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1892576150
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1165353202
Short name T412
Test name
Test status
Simulation time 5691788954 ps
CPU time 32.92 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:47:24 PM PDT 24
Peak memory 208084 kb
Host smart-763be088-c554-4913-9df4-056c07d5cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165353202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1165353202
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3422394503
Short name T58
Test name
Test status
Simulation time 411760309 ps
CPU time 15.72 seconds
Started Jul 04 06:47:00 PM PDT 24
Finished Jul 04 06:47:15 PM PDT 24
Peak memory 220940 kb
Host smart-18c16893-3ebd-4b5a-96ca-7afa9bfe7e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422394503 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3422394503
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3242322449
Short name T216
Test name
Test status
Simulation time 141251844 ps
CPU time 4.69 seconds
Started Jul 04 06:46:51 PM PDT 24
Finished Jul 04 06:46:56 PM PDT 24
Peak memory 214344 kb
Host smart-166c44f0-3728-45e3-9cf0-e37e688ceb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242322449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3242322449
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3515131334
Short name T158
Test name
Test status
Simulation time 65997117 ps
CPU time 1.41 seconds
Started Jul 04 06:47:00 PM PDT 24
Finished Jul 04 06:47:02 PM PDT 24
Peak memory 210208 kb
Host smart-e903d4e2-c358-4f64-b741-19fcfec087ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515131334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3515131334
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1278888481
Short name T716
Test name
Test status
Simulation time 36272324 ps
CPU time 0.75 seconds
Started Jul 04 06:47:02 PM PDT 24
Finished Jul 04 06:47:02 PM PDT 24
Peak memory 206032 kb
Host smart-1863ec5f-f838-4d7d-a6b7-7c1c8dc9d237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278888481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1278888481
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1301825836
Short name T276
Test name
Test status
Simulation time 3324951910 ps
CPU time 9.73 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:47:06 PM PDT 24
Peak memory 215864 kb
Host smart-dc5a6a59-cb58-4a21-a758-a3f42ecd0ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301825836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1301825836
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1154774701
Short name T635
Test name
Test status
Simulation time 4860637057 ps
CPU time 33.62 seconds
Started Jul 04 06:47:04 PM PDT 24
Finished Jul 04 06:47:38 PM PDT 24
Peak memory 222972 kb
Host smart-98b83a53-9b3a-43dc-b91f-5746dd17fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154774701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1154774701
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.17807086
Short name T440
Test name
Test status
Simulation time 251300070 ps
CPU time 3.13 seconds
Started Jul 04 06:46:58 PM PDT 24
Finished Jul 04 06:47:01 PM PDT 24
Peak memory 209412 kb
Host smart-870a2960-f983-4155-a47d-51481029ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17807086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.17807086
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1793655154
Short name T248
Test name
Test status
Simulation time 281666683 ps
CPU time 3.84 seconds
Started Jul 04 06:47:02 PM PDT 24
Finished Jul 04 06:47:06 PM PDT 24
Peak memory 222340 kb
Host smart-c0631e32-c216-4fab-ab24-e6026604f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793655154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1793655154
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3400621096
Short name T67
Test name
Test status
Simulation time 149176355 ps
CPU time 7.25 seconds
Started Jul 04 06:47:04 PM PDT 24
Finished Jul 04 06:47:12 PM PDT 24
Peak memory 220416 kb
Host smart-ada095d4-f901-4f41-8d2a-a2367957587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400621096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3400621096
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2236001566
Short name T583
Test name
Test status
Simulation time 201218692 ps
CPU time 5.08 seconds
Started Jul 04 06:46:56 PM PDT 24
Finished Jul 04 06:47:02 PM PDT 24
Peak memory 209224 kb
Host smart-f118a364-1da9-45fd-abd6-fb0ef48a4926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236001566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2236001566
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.458595502
Short name T519
Test name
Test status
Simulation time 83062036 ps
CPU time 3.23 seconds
Started Jul 04 06:47:00 PM PDT 24
Finished Jul 04 06:47:03 PM PDT 24
Peak memory 206928 kb
Host smart-4de06c49-eed0-4f64-bc2f-dc1e013d4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458595502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.458595502
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2068948283
Short name T556
Test name
Test status
Simulation time 109956308 ps
CPU time 2.29 seconds
Started Jul 04 06:46:58 PM PDT 24
Finished Jul 04 06:47:00 PM PDT 24
Peak memory 208692 kb
Host smart-3bb27a83-db66-457c-9efc-3bf75a7adea2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068948283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2068948283
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2883235744
Short name T789
Test name
Test status
Simulation time 507636705 ps
CPU time 5.9 seconds
Started Jul 04 06:46:57 PM PDT 24
Finished Jul 04 06:47:03 PM PDT 24
Peak memory 207904 kb
Host smart-4de1faf9-b365-413b-b5cb-4b177dff873b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883235744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2883235744
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2516052916
Short name T181
Test name
Test status
Simulation time 894184620 ps
CPU time 6.3 seconds
Started Jul 04 06:46:59 PM PDT 24
Finished Jul 04 06:47:06 PM PDT 24
Peak memory 208620 kb
Host smart-9ad54e3c-fc1d-49fc-b256-1ef2418ccfc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516052916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2516052916
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2822143428
Short name T502
Test name
Test status
Simulation time 1835065415 ps
CPU time 4.79 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:08 PM PDT 24
Peak memory 208892 kb
Host smart-af754e00-4b06-42dd-a78f-29c81f5ac03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822143428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2822143428
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2828123794
Short name T794
Test name
Test status
Simulation time 566321353 ps
CPU time 5.73 seconds
Started Jul 04 06:46:57 PM PDT 24
Finished Jul 04 06:47:03 PM PDT 24
Peak memory 208796 kb
Host smart-74e1944b-0deb-45b9-9728-8e9c1e57bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828123794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2828123794
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2365934584
Short name T194
Test name
Test status
Simulation time 1763803812 ps
CPU time 45.19 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:49 PM PDT 24
Peak memory 216108 kb
Host smart-4c0e3045-8630-4904-aca9-8542d268b51d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365934584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2365934584
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2053291174
Short name T168
Test name
Test status
Simulation time 1385677851 ps
CPU time 13.63 seconds
Started Jul 04 06:47:06 PM PDT 24
Finished Jul 04 06:47:20 PM PDT 24
Peak memory 222608 kb
Host smart-8b6c8682-e786-4ad7-b891-1a4abeb9d198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053291174 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2053291174
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1469321113
Short name T886
Test name
Test status
Simulation time 6329937394 ps
CPU time 61.48 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:48:05 PM PDT 24
Peak memory 208928 kb
Host smart-60cf5d1d-2c15-43ef-b3a5-ff287276c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469321113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1469321113
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2233974177
Short name T511
Test name
Test status
Simulation time 115189739 ps
CPU time 4.12 seconds
Started Jul 04 06:47:03 PM PDT 24
Finished Jul 04 06:47:07 PM PDT 24
Peak memory 210452 kb
Host smart-a9650122-3f86-471b-beff-4b80e6c817cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233974177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2233974177
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%