Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	46	1			T28	1		T48	1		T49	3
auto[OpGenId]	15	1			T8	1		T49	1		T29	1
auto[OpGenSwOut]	24	1			T46	1		T64	1		T137	2
auto[OpGenHwOut]	25	1			T5	1		T6	1		T7	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1679	1			T5	1		T46	1		T104	1
auto[StInit]	87	1			T28	1		T5	2		T6	1
auto[StCreatorRootKey]	64	1			T5	1		T46	1		T8	1
auto[StOwnerIntKey]	65	1			T46	1		T63	1		T64	1
auto[StOwnerKey]	29	1			T37	1		T46	1		T65	1
auto[StDisabled]	523	1			T5	6		T46	1		T65	7
auto[StInvalid]	50	1			T1	1		T39	1		T42	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3468

1

T1

2

T2

1

T3

1

auto[1]

110

1

T28

1

T5

1

T46

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1676	1			T5	1		T46	1		T104	1
auto[StReset]	auto[1]	3	1			T56	1		T57	1		T58	1
auto[StInit]	auto[0]	37	1			T5	1		T38	1		T104	2
auto[StInit]	auto[1]	50	1			T28	1		T5	1		T6	1
auto[StCreatorRootKey]	auto[0]	45	1			T5	1		T46	1		T62	1
auto[StCreatorRootKey]	auto[1]	19	1			T8	1		T48	1		T29	1
auto[StOwnerIntKey]	auto[0]	48	1			T63	1		T104	1		T20	1
auto[StOwnerIntKey]	auto[1]	17	1			T46	1		T64	1		T70	1
auto[StOwnerKey]	auto[0]	23	1			T37	1		T46	1		T65	1
auto[StOwnerKey]	auto[1]	6	1			T66	1		T177	1		T231	1
auto[StDisabled]	auto[0]	508	1			T5	6		T46	1		T65	7
auto[StDisabled]	auto[1]	15	1			T49	1		T70	2		T136	1
auto[StInvalid]	auto[0]	50	1			T1	1		T39	1		T42	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T56	1		T57	1		T58	1
auto[StInit]	auto[OpAdvance]	16	1			T28	1		T49	3		T70	1
auto[StInit]	auto[OpGenId]	8	1			T72	1		T232	1		T32	1
auto[StInit]	auto[OpGenSwOut]	11	1			T193	1		T138	1		T233	1
auto[StInit]	auto[OpGenHwOut]	15	1			T5	1		T6	1		T7	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T48	1		T50	1		T234	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T8	1		T29	1		T235	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T137	1		T236	1		T237	2
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T7	1		T200	1		T238	1
auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T70	1		T137	1		T139	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T46	1		T64	1		T239	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T232	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T177	1		T240	1		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T231	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T241	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T66	1		T242	1		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T70	1		T136	1		T137	1
auto[StDisabled]	auto[OpGenId]	2	1			T49	1		T243	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T137	1		T244	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	4	1			T70	1		T245	1		T246	1