Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

12016

1

T1

21

T2

10

T3

10

auto[Attestation]

8243

1

T1

1

T2

8

T3

10

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2953	1			T1	3		T2	5		T3	2
auto[Aes]	3511	1			T1	3		T3	6		T4	9
auto[Kmac]	3641	1			T1	3		T2	6		T3	3
auto[Otbn]	3570	1			T1	4		T2	2		T3	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8191	1			T1	1		T2	8		T3	8
auto[OpGenId]	6584	1			T1	9		T2	5		T3	4
auto[OpGenSwOut]	6388	1			T1	8		T2	8		T3	12
auto[OpGenHwOut]	7287	1			T1	5		T2	5		T3	4
auto[OpDisable]	139	1			T18	1		T51	1		T52	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11372

1

T1

1

T2

7

T3

9

auto[OpDoneFail]

17217

1

T1

22

T2

19

T3

19

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	7101	1			T1	19		T2	3		T3	3
auto[StInit]	4120	1			T1	4		T2	3		T3	4
auto[StCreatorRootKey]	3412	1			T2	3		T3	3		T4	1
auto[StOwnerIntKey]	3014	1			T2	3		T3	2		T4	4
auto[StOwnerKey]	2611	1			T2	2		T3	3		T4	6
auto[StDisabled]	8331	1			T2	12		T3	13		T4	6

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	383	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	126	1			T4	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T5	2		T22	1		T69	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T3	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T65	1		T131	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T2	1		T17	2		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	345	1			T1	1		T4	3		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	102	1			T1	1		T17	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	72	1			T37	1		T46	1		T65	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T19	1		T65	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	68	1			T3	1		T65	2		T213	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	233	1			T4	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	385	1			T1	2		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	130	1			T84	2		T39	1		T104	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T3	1		T15	1		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T4	1		T19	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	70	1			T4	1		T65	1		T49	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	210	1			T2	1		T18	1		T65	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	395	1			T1	2		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T19	1		T37	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T46	1		T52	2		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T84	1		T65	2		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T5	1		T215	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	226	1			T4	1		T5	1		T65	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	85	1			T5	2		T65	2		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	123	1			T19	1		T5	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T46	1		T22	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	86	1			T5	2		T25	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	68	1			T17	1		T5	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	232	1			T2	1		T4	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	85	1			T5	2		T65	2		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T46	1		T63	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	83	1			T25	1		T216	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	87	1			T4	1		T5	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T5	1		T104	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	228	1			T3	4		T16	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	83	1			T5	2		T46	2		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T3	1		T17	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T2	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T2	2		T85	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	78	1			T5	1		T47	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	240	1			T2	1		T52	1		T65	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	80	1			T5	5		T65	2		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T3	1		T17	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T51	1		T22	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T104	1		T49	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T3	1		T15	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	219	1			T5	2		T65	2		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	301	1			T4	2		T51	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T1	1		T5	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T5	1		T49	3		T217	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	75	1			T4	1		T37	1		T132	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T2	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T3	1		T17	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	471	1			T1	1		T4	2		T51	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	128	1			T4	1		T6	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	135	1			T45	1		T46	2		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	92	1			T84	2		T25	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T45	1		T65	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	277	1			T15	1		T45	2		T65	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	492	1			T1	1		T4	2		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T4	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T17	1		T130	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T84	2		T65	1		T9	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T46	1		T214	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	269	1			T17	1		T5	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	467	1			T1	1		T4	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	147	1			T1	1		T46	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T2	1		T84	1		T65	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T52	1		T132	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	100	1			T4	1		T19	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	292	1			T2	1		T3	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T5	3		T65	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T216	1		T87	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T46	3		T65	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T9	1		T69	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T4	1		T65	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	178	1			T2	1		T19	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T5	2		T104	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	142	1			T15	1		T45	1		T65	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	104	1			T47	1		T25	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	85	1			T19	1		T45	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	94	1			T4	1		T104	1		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	283	1			T3	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	82	1			T5	2		T46	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T2	1		T17	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T225	1		T226	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T84	2		T65	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T37	1		T130	1		T225	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	306	1			T65	4		T130	3		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T5	4		T65	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T25	1		T222	1		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T83	1		T65	1		T129	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T51	1		T5	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T229	1		T214	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	295	1			T5	1		T83	2		T65	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	188	1			T3	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	746	1			T1	2		T2	2		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T19	1		T37	1		T65	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	694	1			T1	2		T3	1		T4	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T3	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	748	1			T1	2		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T5	1		T84	1		T52	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	765	1			T1	2		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	227	1			T17	1		T5	3		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	455	1			T2	1		T4	1		T19	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	203	1			T4	1		T5	2		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	438	1			T3	4		T16	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	240	1			T2	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	437	1			T2	3		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T3	1		T15	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	427	1			T3	1		T17	1		T5	8
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	206	1			T2	1		T4	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	604	1			T1	1		T3	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	294	1			T45	2		T46	1		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	903	1			T1	1		T4	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T17	1		T46	1		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	906	1			T1	1		T4	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T4	1		T19	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	931	1			T1	2		T2	2		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T4	1		T46	3		T65	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	348	1			T2	1		T19	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	268	1			T19	1		T45	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	510	1			T3	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T37	1		T84	2		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	539	1			T2	1		T17	1		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T51	1		T5	1		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T5	5		T83	2		T65	2