Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1739

1

T1

1

T2

2

T3

1

auto[1]

1929

1

T1

5

T2

4

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T5	1		T46	1		T65	1
auto[134217728:268435455]	93	1			T52	1		T25	1		T64	1
auto[268435456:402653183]	104	1			T46	1		T52	1		T128	1
auto[402653184:536870911]	121	1			T2	1		T4	1		T19	1
auto[536870912:671088639]	119	1			T84	1		T65	1		T128	1
auto[671088640:805306367]	105	1			T22	1		T65	4		T38	1
auto[805306368:939524095]	104	1			T5	1		T6	1		T48	1
auto[939524096:1073741823]	130	1			T1	2		T65	1		T39	2
auto[1073741824:1207959551]	124	1			T1	1		T2	1		T3	1
auto[1207959552:1342177279]	116	1			T1	2		T3	1		T46	1
auto[1342177280:1476395007]	98	1			T1	1		T19	1		T65	1
auto[1476395008:1610612735]	116	1			T4	1		T5	2		T65	1
auto[1610612736:1744830463]	115	1			T2	1		T17	1		T28	1
auto[1744830464:1879048191]	117	1			T46	1		T6	1		T47	1
auto[1879048192:2013265919]	119	1			T19	1		T5	1		T65	3
auto[2013265920:2147483647]	121	1			T4	1		T51	1		T5	1
auto[2147483648:2281701375]	95	1			T4	1		T19	1		T5	1
auto[2281701376:2415919103]	114	1			T46	1		T84	1		T87	1
auto[2415919104:2550136831]	132	1			T5	1		T46	1		T6	1
auto[2550136832:2684354559]	100	1			T19	1		T51	1		T5	3
auto[2684354560:2818572287]	105	1			T17	1		T52	1		T213	1
auto[2818572288:2952790015]	123	1			T46	1		T84	1		T47	1
auto[2952790016:3087007743]	112	1			T46	1		T128	1		T60	1
auto[3087007744:3221225471]	130	1			T4	1		T5	1		T46	1
auto[3221225472:3355443199]	108	1			T3	1		T65	1		T53	2
auto[3355443200:3489660927]	134	1			T46	1		T6	1		T48	1
auto[3489660928:3623878655]	119	1			T2	1		T4	1		T65	1
auto[3623878656:3758096383]	91	1			T2	1		T3	1		T4	1
auto[3758096384:3892314111]	129	1			T3	1		T18	1		T65	1
auto[3892314112:4026531839]	104	1			T2	1		T51	1		T5	1
auto[4026531840:4160749567]	145	1			T5	2		T132	1		T25	1
auto[4160749568:4294967295]	106	1			T46	1		T65	1		T42	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T5	1		T74	1		T49	2
auto[0:134217727]	auto[1]	63	1			T46	1		T65	1		T69	1
auto[134217728:268435455]	auto[0]	46	1			T52	1		T25	1		T64	1
auto[134217728:268435455]	auto[1]	47	1			T69	1		T49	2		T40	1
auto[268435456:402653183]	auto[0]	51	1			T128	1		T60	1		T307	1
auto[268435456:402653183]	auto[1]	53	1			T46	1		T52	1		T63	1
auto[402653184:536870911]	auto[0]	65	1			T2	1		T4	1		T46	1
auto[402653184:536870911]	auto[1]	56	1			T19	1		T46	1		T261	1
auto[536870912:671088639]	auto[0]	58	1			T48	1		T104	1		T69	1
auto[536870912:671088639]	auto[1]	61	1			T84	1		T65	1		T128	1
auto[671088640:805306367]	auto[0]	48	1			T22	1		T65	2		T74	1
auto[671088640:805306367]	auto[1]	57	1			T65	2		T38	1		T60	1
auto[805306368:939524095]	auto[0]	52	1			T5	1		T6	1		T48	1
auto[805306368:939524095]	auto[1]	52	1			T42	1		T49	1		T7	1
auto[939524096:1073741823]	auto[0]	55	1			T65	1		T39	2		T256	1
auto[939524096:1073741823]	auto[1]	75	1			T1	2		T418	1		T49	1
auto[1073741824:1207959551]	auto[0]	63	1			T3	1		T65	1		T39	2
auto[1073741824:1207959551]	auto[1]	61	1			T1	1		T2	1		T69	1
auto[1207959552:1342177279]	auto[0]	54	1			T6	2		T65	3		T39	1
auto[1207959552:1342177279]	auto[1]	62	1			T1	2		T3	1		T46	1
auto[1342177280:1476395007]	auto[0]	39	1			T1	1		T59	1		T88	1
auto[1342177280:1476395007]	auto[1]	59	1			T19	1		T65	1		T74	1
auto[1476395008:1610612735]	auto[0]	56	1			T5	2		T49	1		T66	2
auto[1476395008:1610612735]	auto[1]	60	1			T4	1		T65	1		T53	1
auto[1610612736:1744830463]	auto[0]	55	1			T46	1		T22	1		T42	1
auto[1610612736:1744830463]	auto[1]	60	1			T2	1		T17	1		T28	1
auto[1744830464:1879048191]	auto[0]	50	1			T6	1		T47	1		T65	1
auto[1744830464:1879048191]	auto[1]	67	1			T46	1		T49	2		T307	1
auto[1879048192:2013265919]	auto[0]	51	1			T5	1		T65	3		T63	1
auto[1879048192:2013265919]	auto[1]	68	1			T19	1		T49	1		T148	1
auto[2013265920:2147483647]	auto[0]	64	1			T51	1		T46	1		T84	1
auto[2013265920:2147483647]	auto[1]	57	1			T4	1		T5	1		T25	1
auto[2147483648:2281701375]	auto[0]	39	1			T4	1		T5	1		T213	1
auto[2147483648:2281701375]	auto[1]	56	1			T19	1		T22	1		T49	5
auto[2281701376:2415919103]	auto[0]	51	1			T84	1		T49	2		T258	1
auto[2281701376:2415919103]	auto[1]	63	1			T46	1		T87	1		T104	1
auto[2415919104:2550136831]	auto[0]	75	1			T5	1		T6	1		T65	1
auto[2415919104:2550136831]	auto[1]	57	1			T46	1		T47	1		T65	1
auto[2550136832:2684354559]	auto[0]	44	1			T51	1		T5	3		T47	1
auto[2550136832:2684354559]	auto[1]	56	1			T19	1		T39	1		T256	1
auto[2684354560:2818572287]	auto[0]	49	1			T52	1		T214	1		T49	2
auto[2684354560:2818572287]	auto[1]	56	1			T17	1		T213	1		T218	1
auto[2818572288:2952790015]	auto[0]	60	1			T84	1		T59	1		T375	1
auto[2818572288:2952790015]	auto[1]	63	1			T46	1		T47	1		T65	2
auto[2952790016:3087007743]	auto[0]	57	1			T46	1		T128	1		T60	1
auto[2952790016:3087007743]	auto[1]	55	1			T59	1		T218	1		T87	2
auto[3087007744:3221225471]	auto[0]	57	1			T4	1		T5	1		T47	1
auto[3087007744:3221225471]	auto[1]	73	1			T46	1		T65	1		T69	1
auto[3221225472:3355443199]	auto[0]	48	1			T53	1		T87	1		T49	2
auto[3221225472:3355443199]	auto[1]	60	1			T3	1		T65	1		T53	1
auto[3355443200:3489660927]	auto[0]	60	1			T6	1		T48	1		T213	1
auto[3355443200:3489660927]	auto[1]	74	1			T46	1		T49	1		T108	1
auto[3489660928:3623878655]	auto[0]	61	1			T8	1		T39	1		T7	1
auto[3489660928:3623878655]	auto[1]	58	1			T2	1		T4	1		T65	1
auto[3623878656:3758096383]	auto[0]	50	1			T4	1		T60	1		T218	1
auto[3623878656:3758096383]	auto[1]	41	1			T2	1		T3	1		T218	1
auto[3758096384:3892314111]	auto[0]	61	1			T65	1		T213	1		T104	1
auto[3758096384:3892314111]	auto[1]	68	1			T3	1		T18	1		T64	1
auto[3892314112:4026531839]	auto[0]	48	1			T2	1		T51	1		T5	1
auto[3892314112:4026531839]	auto[1]	56	1			T46	1		T213	1		T104	1
auto[4026531840:4160749567]	auto[0]	72	1			T5	1		T213	1		T73	1
auto[4026531840:4160749567]	auto[1]	73	1			T5	1		T132	1		T25	1
auto[4160749568:4294967295]	auto[0]	44	1			T261	1		T69	1		T49	1
auto[4160749568:4294967295]	auto[1]	62	1			T46	1		T65	1		T42	2