Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5162

1

T1

10

T2

12

T3

4

auto[1]

2173

1

T1

2

T3

6

T17

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	238	1			T4	2		T5	2		T52	4
auto[134217728:268435455]	224	1			T51	2		T5	2		T65	6
auto[268435456:402653183]	268	1			T5	2		T65	6		T25	2
auto[402653184:536870911]	212	1			T65	2		T128	2		T49	4
auto[536870912:671088639]	270	1			T2	2		T3	2		T46	2
auto[671088640:805306367]	252	1			T1	2		T47	2		T65	2
auto[805306368:939524095]	232	1			T3	2		T5	4		T46	2
auto[939524096:1073741823]	178	1			T4	2		T52	2		T65	4
auto[1073741824:1207959551]	222	1			T1	2		T4	2		T65	2
auto[1207959552:1342177279]	234	1			T5	2		T46	6		T48	2
auto[1342177280:1476395007]	192	1			T2	2		T46	2		T65	2
auto[1476395008:1610612735]	206	1			T3	2		T5	2		T25	2
auto[1610612736:1744830463]	224	1			T19	2		T5	2		T22	2
auto[1744830464:1879048191]	242	1			T52	2		T65	2		T64	2
auto[1879048192:2013265919]	208	1			T17	2		T46	2		T213	2
auto[2013265920:2147483647]	246	1			T28	2		T5	4		T46	2
auto[2147483648:2281701375]	212	1			T46	4		T25	2		T87	2
auto[2281701376:2415919103]	212	1			T17	2		T6	2		T60	2
auto[2415919104:2550136831]	226	1			T2	4		T46	2		T69	2
auto[2550136832:2684354559]	236	1			T19	2		T51	2		T46	2
auto[2684354560:2818572287]	236	1			T2	2		T4	2		T84	2
auto[2818572288:2952790015]	238	1			T3	2		T4	2		T5	2
auto[2952790016:3087007743]	220	1			T47	2		T65	6		T9	2
auto[3087007744:3221225471]	246	1			T3	2		T18	2		T46	4
auto[3221225472:3355443199]	244	1			T2	2		T39	2		T49	6
auto[3355443200:3489660927]	259	1			T1	2		T4	2		T19	2
auto[3489660928:3623878655]	244	1			T1	2		T51	2		T22	2
auto[3623878656:3758096383]	204	1			T1	2		T4	2		T5	2
auto[3758096384:3892314111]	222	1			T5	4		T46	2		T84	2
auto[3892314112:4026531839]	208	1			T19	2		T5	2		T84	2
auto[4026531840:4160749567]	250	1			T19	2		T46	2		T65	2
auto[4160749568:4294967295]	230	1			T1	2		T47	2		T65	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	180	1			T4	2		T5	2		T52	4
auto[0:134217727]	auto[1]	58	1			T65	4		T42	2		T64	2
auto[134217728:268435455]	auto[0]	160	1			T5	2		T65	2		T213	2
auto[134217728:268435455]	auto[1]	64	1			T51	2		T65	4		T128	2
auto[268435456:402653183]	auto[0]	174	1			T5	2		T65	4		T25	2
auto[268435456:402653183]	auto[1]	94	1			T65	2		T53	4		T218	2
auto[402653184:536870911]	auto[0]	154	1			T65	2		T49	4		T75	2
auto[402653184:536870911]	auto[1]	58	1			T128	2		T217	2		T73	2
auto[536870912:671088639]	auto[0]	188	1			T2	2		T46	2		T22	2
auto[536870912:671088639]	auto[1]	82	1			T3	2		T39	2		T9	2
auto[671088640:805306367]	auto[0]	160	1			T1	2		T213	2		T39	2
auto[671088640:805306367]	auto[1]	92	1			T47	2		T65	2		T63	2
auto[805306368:939524095]	auto[0]	168	1			T5	2		T46	2		T6	2
auto[805306368:939524095]	auto[1]	64	1			T3	2		T5	2		T417	2
auto[939524096:1073741823]	auto[0]	132	1			T4	2		T52	2		T65	4
auto[939524096:1073741823]	auto[1]	46	1			T74	2		T66	2		T364	2
auto[1073741824:1207959551]	auto[0]	160	1			T1	2		T4	2		T8	2
auto[1073741824:1207959551]	auto[1]	62	1			T65	2		T128	2		T214	2
auto[1207959552:1342177279]	auto[0]	158	1			T5	2		T46	2		T48	2
auto[1207959552:1342177279]	auto[1]	76	1			T46	4		T66	2		T70	2
auto[1342177280:1476395007]	auto[0]	144	1			T2	2		T46	2		T65	2
auto[1342177280:1476395007]	auto[1]	48	1			T49	2		T217	2		T137	2
auto[1476395008:1610612735]	auto[0]	142	1			T5	2		T25	2		T213	2
auto[1476395008:1610612735]	auto[1]	64	1			T3	2		T104	2		T49	2
auto[1610612736:1744830463]	auto[0]	152	1			T5	2		T22	2		T48	2
auto[1610612736:1744830463]	auto[1]	72	1			T19	2		T65	2		T38	2
auto[1744830464:1879048191]	auto[0]	174	1			T52	2		T65	2		T64	2
auto[1744830464:1879048191]	auto[1]	68	1			T87	2		T69	2		T49	2
auto[1879048192:2013265919]	auto[0]	172	1			T46	2		T213	2		T87	2
auto[1879048192:2013265919]	auto[1]	36	1			T17	2		T69	2		T111	2
auto[2013265920:2147483647]	auto[0]	162	1			T5	2		T46	2		T65	2
auto[2013265920:2147483647]	auto[1]	84	1			T28	2		T5	2		T65	2
auto[2147483648:2281701375]	auto[0]	146	1			T46	2		T25	2		T418	2
auto[2147483648:2281701375]	auto[1]	66	1			T46	2		T87	2		T49	4
auto[2281701376:2415919103]	auto[0]	152	1			T17	2		T60	2		T49	8
auto[2281701376:2415919103]	auto[1]	60	1			T6	2		T104	2		T49	2
auto[2415919104:2550136831]	auto[0]	154	1			T2	4		T46	2		T49	2
auto[2415919104:2550136831]	auto[1]	72	1			T69	2		T256	2		T283	2
auto[2550136832:2684354559]	auto[0]	180	1			T19	2		T51	2		T48	2
auto[2550136832:2684354559]	auto[1]	56	1			T46	2		T65	4		T104	2
auto[2684354560:2818572287]	auto[0]	164	1			T2	2		T4	2		T6	2
auto[2684354560:2818572287]	auto[1]	72	1			T84	2		T135	2		T332	2
auto[2818572288:2952790015]	auto[0]	178	1			T3	2		T4	2		T5	2
auto[2818572288:2952790015]	auto[1]	60	1			T6	2		T53	2		T135	2
auto[2952790016:3087007743]	auto[0]	158	1			T47	2		T65	6		T69	2
auto[2952790016:3087007743]	auto[1]	62	1			T9	2		T66	2		T70	2
auto[3087007744:3221225471]	auto[0]	180	1			T3	2		T46	4		T65	2
auto[3087007744:3221225471]	auto[1]	66	1			T18	2		T65	2		T424	2
auto[3221225472:3355443199]	auto[0]	168	1			T2	2		T39	2		T49	4
auto[3221225472:3355443199]	auto[1]	76	1			T49	2		T304	2		T70	2
auto[3355443200:3489660927]	auto[0]	186	1			T4	2		T25	2		T60	2
auto[3355443200:3489660927]	auto[1]	73	1			T1	2		T19	2		T84	2
auto[3489660928:3623878655]	auto[0]	178	1			T1	2		T51	2		T65	2
auto[3489660928:3623878655]	auto[1]	66	1			T22	2		T112	2		T20	2
auto[3623878656:3758096383]	auto[0]	138	1			T1	2		T4	2		T5	2
auto[3623878656:3758096383]	auto[1]	66	1			T52	2		T6	2		T104	2
auto[3758096384:3892314111]	auto[0]	154	1			T5	4		T48	2		T213	2
auto[3758096384:3892314111]	auto[1]	68	1			T46	2		T84	2		T47	2
auto[3892314112:4026531839]	auto[0]	124	1			T5	2		T60	2		T256	2
auto[3892314112:4026531839]	auto[1]	84	1			T19	2		T84	2		T47	2
auto[4026531840:4160749567]	auto[0]	180	1			T19	2		T65	2		T218	2
auto[4026531840:4160749567]	auto[1]	70	1			T46	2		T69	2		T66	2
auto[4160749568:4294967295]	auto[0]	142	1			T1	2		T69	2		T256	2
auto[4160749568:4294967295]	auto[1]	88	1			T47	2		T65	2		T63	2