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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.15 98.37 100.00 99.02 98.41 91.17


Total test records in report: 1081
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T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.856900741 Jul 05 04:28:18 PM PDT 24 Jul 05 04:28:32 PM PDT 24 62542776 ps
T1011 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3417414669 Jul 05 04:28:46 PM PDT 24 Jul 05 04:28:58 PM PDT 24 70341087 ps
T1012 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.242961939 Jul 05 04:28:23 PM PDT 24 Jul 05 04:28:37 PM PDT 24 9872015 ps
T1013 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2578114021 Jul 05 04:28:27 PM PDT 24 Jul 05 04:28:45 PM PDT 24 123240840 ps
T1014 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2009439024 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:03 PM PDT 24 36760634 ps
T1015 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1187762332 Jul 05 04:28:22 PM PDT 24 Jul 05 04:28:38 PM PDT 24 127657912 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2679358750 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:45 PM PDT 24 55452476 ps
T151 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.123863004 Jul 05 04:28:36 PM PDT 24 Jul 05 04:29:01 PM PDT 24 485337894 ps
T1017 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2240965344 Jul 05 04:28:27 PM PDT 24 Jul 05 04:28:42 PM PDT 24 31025760 ps
T1018 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3582453647 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:52 PM PDT 24 50372086 ps
T1019 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1349442696 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:01 PM PDT 24 36447414 ps
T1020 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3172892984 Jul 05 04:28:15 PM PDT 24 Jul 05 04:28:30 PM PDT 24 106372554 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2788550931 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:34 PM PDT 24 299581248 ps
T1022 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2486201965 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:44 PM PDT 24 64026964 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4181924733 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:45 PM PDT 24 13170172 ps
T1024 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3756586579 Jul 05 04:28:47 PM PDT 24 Jul 05 04:28:58 PM PDT 24 44910090 ps
T157 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3851088472 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:06 PM PDT 24 159234803 ps
T1025 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2111788889 Jul 05 04:29:23 PM PDT 24 Jul 05 04:29:33 PM PDT 24 40810277 ps
T1026 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2443175640 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:46 PM PDT 24 657258056 ps
T1027 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.153854684 Jul 05 04:28:48 PM PDT 24 Jul 05 04:28:59 PM PDT 24 84323546 ps
T1028 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.225895492 Jul 05 04:28:13 PM PDT 24 Jul 05 04:28:27 PM PDT 24 16336474 ps
T1029 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2672029996 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:34 PM PDT 24 117861605 ps
T1030 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3183760566 Jul 05 04:28:30 PM PDT 24 Jul 05 04:28:44 PM PDT 24 37060130 ps
T1031 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1927786481 Jul 05 04:28:30 PM PDT 24 Jul 05 04:28:46 PM PDT 24 110126657 ps
T1032 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.444931547 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:06 PM PDT 24 182970812 ps
T1033 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1536130861 Jul 05 04:28:41 PM PDT 24 Jul 05 04:28:54 PM PDT 24 60888807 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2683368517 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:53 PM PDT 24 524117062 ps
T1035 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1415965698 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:03 PM PDT 24 23044940 ps
T1036 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4011058175 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:02 PM PDT 24 43384254 ps
T1037 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1558811449 Jul 05 04:28:23 PM PDT 24 Jul 05 04:28:37 PM PDT 24 60827217 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1183357979 Jul 05 04:28:22 PM PDT 24 Jul 05 04:28:41 PM PDT 24 693254179 ps
T166 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.475015275 Jul 05 04:28:17 PM PDT 24 Jul 05 04:28:41 PM PDT 24 1612271436 ps
T1039 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3483634025 Jul 05 04:28:43 PM PDT 24 Jul 05 04:29:04 PM PDT 24 560805061 ps
T1040 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4021393469 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:24 PM PDT 24 83602856 ps
T1041 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2572422860 Jul 05 04:28:13 PM PDT 24 Jul 05 04:28:27 PM PDT 24 17596353 ps
T152 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3486059386 Jul 05 04:28:20 PM PDT 24 Jul 05 04:28:37 PM PDT 24 100617537 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2259976215 Jul 05 04:28:47 PM PDT 24 Jul 05 04:29:13 PM PDT 24 5842581580 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.642996559 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:55 PM PDT 24 3939907270 ps
T1044 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1037854576 Jul 05 04:28:47 PM PDT 24 Jul 05 04:28:58 PM PDT 24 21063513 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3275475870 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:20 PM PDT 24 12849472 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4266067026 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:46 PM PDT 24 138208584 ps
T1047 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1409296563 Jul 05 04:28:35 PM PDT 24 Jul 05 04:29:04 PM PDT 24 2670405311 ps
T1048 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3456612986 Jul 05 04:28:33 PM PDT 24 Jul 05 04:28:48 PM PDT 24 88681342 ps
T1049 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2778445461 Jul 05 04:28:26 PM PDT 24 Jul 05 04:28:42 PM PDT 24 297451998 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.582679050 Jul 05 04:28:46 PM PDT 24 Jul 05 04:28:57 PM PDT 24 28467123 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3954195616 Jul 05 04:28:23 PM PDT 24 Jul 05 04:28:38 PM PDT 24 16809080 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.476800172 Jul 05 04:28:35 PM PDT 24 Jul 05 04:28:49 PM PDT 24 196596714 ps
T1053 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4185564514 Jul 05 04:28:42 PM PDT 24 Jul 05 04:28:55 PM PDT 24 120837836 ps
T1054 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.770572569 Jul 05 04:28:23 PM PDT 24 Jul 05 04:28:39 PM PDT 24 91724716 ps
T1055 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1841796951 Jul 05 04:28:39 PM PDT 24 Jul 05 04:28:52 PM PDT 24 9130111 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2414026847 Jul 05 04:28:33 PM PDT 24 Jul 05 04:28:58 PM PDT 24 612239522 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.240230261 Jul 05 04:28:18 PM PDT 24 Jul 05 04:28:33 PM PDT 24 74527274 ps
T174 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3086039590 Jul 05 04:28:08 PM PDT 24 Jul 05 04:28:20 PM PDT 24 55804603 ps
T1058 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2635337318 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:43 PM PDT 24 100177000 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2564553201 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:55 PM PDT 24 732295476 ps
T1060 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2384586035 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:06 PM PDT 24 27683037 ps
T1061 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3627603888 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:35 PM PDT 24 778337882 ps
T1062 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2695533959 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:47 PM PDT 24 28090789 ps
T164 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3927864868 Jul 05 04:28:47 PM PDT 24 Jul 05 04:29:05 PM PDT 24 1897950822 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2451570668 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:48 PM PDT 24 47707258 ps
T165 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1466282871 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:47 PM PDT 24 103070143 ps
T1064 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3657073871 Jul 05 04:28:21 PM PDT 24 Jul 05 04:28:36 PM PDT 24 67277253 ps
T1065 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.369677304 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:43 PM PDT 24 9755010 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.213610117 Jul 05 04:28:14 PM PDT 24 Jul 05 04:28:31 PM PDT 24 282384584 ps
T1067 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2643385747 Jul 05 04:29:26 PM PDT 24 Jul 05 04:29:36 PM PDT 24 27406058 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3042711582 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:17 PM PDT 24 36566880 ps
T161 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2423008451 Jul 05 04:28:38 PM PDT 24 Jul 05 04:28:53 PM PDT 24 111032823 ps
T1069 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3658299136 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:42 PM PDT 24 197450514 ps
T1070 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.41853294 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:52 PM PDT 24 23012079 ps
T1071 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.745840398 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:36 PM PDT 24 1152097321 ps
T1072 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.887348930 Jul 05 04:28:43 PM PDT 24 Jul 05 04:28:57 PM PDT 24 149957987 ps
T1073 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4103070335 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:43 PM PDT 24 235201086 ps
T1074 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2747544847 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:43 PM PDT 24 42042624 ps
T1075 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2779804302 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:49 PM PDT 24 425803786 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4113563663 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:42 PM PDT 24 45426562 ps
T1077 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3783190723 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:45 PM PDT 24 419431114 ps
T1078 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2581155317 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:53 PM PDT 24 22794344 ps
T1079 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2424449009 Jul 05 04:28:17 PM PDT 24 Jul 05 04:28:35 PM PDT 24 270119063 ps
T1080 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.787990103 Jul 05 04:28:18 PM PDT 24 Jul 05 04:28:36 PM PDT 24 166694955 ps
T1081 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4140569941 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:49 PM PDT 24 285265239 ps
T158 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.486219755 Jul 05 04:28:14 PM PDT 24 Jul 05 04:28:35 PM PDT 24 473558198 ps

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.404825366
Short name T19
Test name
Test status
Simulation time 7362141719 ps
CPU time 103.63 seconds
Started Jul 05 05:13:05 PM PDT 24
Finished Jul 05 05:14:51 PM PDT 24
Peak memory 217968 kb
Host smart-1be38316-b5f8-47cc-b6ee-b9ff76ae6904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404825366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.404825366
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2765688525
Short name T49
Test name
Test status
Simulation time 26237408525 ps
CPU time 113.8 seconds
Started Jul 05 05:13:16 PM PDT 24
Finished Jul 05 05:15:11 PM PDT 24
Peak memory 216196 kb
Host smart-953d69b3-a4f2-4a4e-865f-0fee9d781ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765688525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2765688525
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1603835640
Short name T46
Test name
Test status
Simulation time 262529528 ps
CPU time 13.26 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 222968 kb
Host smart-a95d41ad-6c9c-47b3-9ce7-ad88a00bc1d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603835640 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1603835640
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.828344084
Short name T66
Test name
Test status
Simulation time 2931141322 ps
CPU time 46.34 seconds
Started Jul 05 05:11:52 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 222164 kb
Host smart-17ff9be7-0823-40f7-ba82-c3c93d69008b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828344084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.828344084
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1331970403
Short name T11
Test name
Test status
Simulation time 1590647566 ps
CPU time 12.15 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:46 PM PDT 24
Peak memory 230764 kb
Host smart-f24d62b1-411b-48e3-abd2-8e2ef08f0115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331970403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1331970403
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1394711087
Short name T188
Test name
Test status
Simulation time 92991521 ps
CPU time 1.92 seconds
Started Jul 05 04:29:18 PM PDT 24
Finished Jul 05 04:29:29 PM PDT 24
Peak memory 213640 kb
Host smart-41f68c94-c7eb-4043-8128-fe4538826d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394711087 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1394711087
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.949150737
Short name T72
Test name
Test status
Simulation time 6177810365 ps
CPU time 51.37 seconds
Started Jul 05 05:11:31 PM PDT 24
Finished Jul 05 05:12:23 PM PDT 24
Peak memory 215488 kb
Host smart-973644e0-80e4-47d7-a271-1669b143041f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949150737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.949150737
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3053342835
Short name T8
Test name
Test status
Simulation time 231252262 ps
CPU time 5.35 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 210064 kb
Host smart-88502286-54b1-4ade-ad4c-599213ff5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053342835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3053342835
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1439800177
Short name T65
Test name
Test status
Simulation time 3124554589 ps
CPU time 30.17 seconds
Started Jul 05 05:13:33 PM PDT 24
Finished Jul 05 05:14:05 PM PDT 24
Peak memory 222480 kb
Host smart-82325079-5fe1-4330-9771-99bfb36fcfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439800177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1439800177
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.792688395
Short name T53
Test name
Test status
Simulation time 76892691 ps
CPU time 3.06 seconds
Started Jul 05 05:13:03 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 214272 kb
Host smart-7c0305e1-7665-4152-a88a-6ad75a0eada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792688395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.792688395
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3042242471
Short name T115
Test name
Test status
Simulation time 317418706 ps
CPU time 6.56 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:28:51 PM PDT 24
Peak memory 213716 kb
Host smart-f23c0302-eb52-4643-8942-82075a360d22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042242471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3042242471
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1469896032
Short name T112
Test name
Test status
Simulation time 587099672 ps
CPU time 14.24 seconds
Started Jul 05 05:12:17 PM PDT 24
Finished Jul 05 05:12:32 PM PDT 24
Peak memory 222404 kb
Host smart-4edc01cb-eadd-4dc0-a9cb-6cffe213f59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469896032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1469896032
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.136927804
Short name T26
Test name
Test status
Simulation time 58074480 ps
CPU time 3.4 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 208840 kb
Host smart-add8e3da-36e7-461a-8193-e0c39095cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136927804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.136927804
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.88185141
Short name T376
Test name
Test status
Simulation time 1816981924 ps
CPU time 88.34 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:15:13 PM PDT 24
Peak memory 214488 kb
Host smart-0aa7ddaf-35aa-4b91-a137-b804eeeafae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88185141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.88185141
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2285450469
Short name T137
Test name
Test status
Simulation time 584088974 ps
CPU time 24.88 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 215184 kb
Host smart-9981c61c-aedd-444d-b2c5-a82e0fe21f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285450469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2285450469
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3491189917
Short name T37
Test name
Test status
Simulation time 513852118 ps
CPU time 2.28 seconds
Started Jul 05 05:11:36 PM PDT 24
Finished Jul 05 05:11:39 PM PDT 24
Peak memory 209804 kb
Host smart-012cd748-206c-4e53-af66-51dee1ac736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491189917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3491189917
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2395146611
Short name T253
Test name
Test status
Simulation time 196963043 ps
CPU time 11.17 seconds
Started Jul 05 05:11:41 PM PDT 24
Finished Jul 05 05:11:52 PM PDT 24
Peak memory 215540 kb
Host smart-c2ce3085-fa25-4fb2-9cc5-fd9363e62694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395146611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2395146611
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2484214571
Short name T69
Test name
Test status
Simulation time 792189680 ps
CPU time 22.36 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:40 PM PDT 24
Peak memory 223248 kb
Host smart-94c5171f-19a8-482c-813f-84da4df9ef9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484214571 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2484214571
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2436158076
Short name T22
Test name
Test status
Simulation time 126009320 ps
CPU time 3.17 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:39 PM PDT 24
Peak memory 209368 kb
Host smart-cb6b07a3-4245-4222-96ea-b8562c276311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436158076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2436158076
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.599433460
Short name T77
Test name
Test status
Simulation time 18959275678 ps
CPU time 116.77 seconds
Started Jul 05 05:12:37 PM PDT 24
Finished Jul 05 05:14:35 PM PDT 24
Peak memory 216964 kb
Host smart-a0f4a757-27ee-4eda-bdd4-1e2f95b7b5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599433460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.599433460
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2252575032
Short name T135
Test name
Test status
Simulation time 564459727 ps
CPU time 6.24 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:24 PM PDT 24
Peak memory 214332 kb
Host smart-d3039861-8000-4e64-bfb6-0ed6474e997d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252575032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2252575032
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1048249923
Short name T979
Test name
Test status
Simulation time 272915791 ps
CPU time 2.88 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 213916 kb
Host smart-f5fd9a90-faa6-46f9-8938-f408df19993e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048249923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1048249923
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3047535702
Short name T409
Test name
Test status
Simulation time 426030874 ps
CPU time 14.08 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:15 PM PDT 24
Peak memory 215564 kb
Host smart-5ae390ce-ed00-4e93-b104-75d553c05391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047535702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3047535702
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.679551555
Short name T41
Test name
Test status
Simulation time 44997421 ps
CPU time 2.26 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:10 PM PDT 24
Peak memory 208688 kb
Host smart-e5e74f13-4e56-4a0f-90c4-d8474f87a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679551555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.679551555
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3422806312
Short name T24
Test name
Test status
Simulation time 1104379436 ps
CPU time 4.88 seconds
Started Jul 05 05:12:12 PM PDT 24
Finished Jul 05 05:12:19 PM PDT 24
Peak memory 219532 kb
Host smart-647076ef-8e2b-440f-bca5-bd33b5427da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422806312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3422806312
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1240633257
Short name T176
Test name
Test status
Simulation time 141915503 ps
CPU time 2.9 seconds
Started Jul 05 05:11:50 PM PDT 24
Finished Jul 05 05:11:54 PM PDT 24
Peak memory 217816 kb
Host smart-35942fb4-b6a0-4d52-b671-27391ddfbcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240633257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1240633257
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3253130766
Short name T273
Test name
Test status
Simulation time 279474585 ps
CPU time 15.01 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 215380 kb
Host smart-dbdaf7aa-44fa-437e-b6af-a3a7796f044b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253130766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3253130766
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3793929734
Short name T685
Test name
Test status
Simulation time 126232873 ps
CPU time 2.5 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:19 PM PDT 24
Peak memory 208696 kb
Host smart-e25509b3-e8bd-40fd-a59e-5c0734b41070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793929734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3793929734
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3399630006
Short name T70
Test name
Test status
Simulation time 5359865784 ps
CPU time 26.04 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 222480 kb
Host smart-5e96d391-3f18-4fe6-a145-0236dba2a6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399630006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3399630006
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2645891114
Short name T312
Test name
Test status
Simulation time 192224954 ps
CPU time 4.41 seconds
Started Jul 05 05:13:48 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 215132 kb
Host smart-5e1bb30f-24df-443d-a904-cf023b011d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645891114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2645891114
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3649900193
Short name T266
Test name
Test status
Simulation time 835302494 ps
CPU time 41.86 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 215496 kb
Host smart-48bd6ecf-9d0b-4587-b022-4edd46b694a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649900193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3649900193
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1265001518
Short name T39
Test name
Test status
Simulation time 509698128 ps
CPU time 3.9 seconds
Started Jul 05 05:12:05 PM PDT 24
Finished Jul 05 05:12:10 PM PDT 24
Peak memory 214164 kb
Host smart-5743bfef-d8e5-474d-bc76-bc5f329681b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265001518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1265001518
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1042589071
Short name T429
Test name
Test status
Simulation time 31185009 ps
CPU time 0.89 seconds
Started Jul 05 05:11:46 PM PDT 24
Finished Jul 05 05:11:47 PM PDT 24
Peak memory 205880 kb
Host smart-b7edaefe-16b2-4e69-8c9d-c6373763f690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042589071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1042589071
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.653477522
Short name T244
Test name
Test status
Simulation time 10700192106 ps
CPU time 59.43 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 222644 kb
Host smart-0fb41b9b-9778-4646-b2ae-fad94032c3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653477522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.653477522
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3486059386
Short name T152
Test name
Test status
Simulation time 100617537 ps
CPU time 4.21 seconds
Started Jul 05 04:28:20 PM PDT 24
Finished Jul 05 04:28:37 PM PDT 24
Peak memory 205324 kb
Host smart-38810722-b5ff-4cb5-be30-b0bc49719d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486059386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3486059386
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1709785909
Short name T326
Test name
Test status
Simulation time 104224577 ps
CPU time 3.28 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:15 PM PDT 24
Peak memory 214200 kb
Host smart-8413d542-4ae2-46fa-bfd8-86ccf1f0c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709785909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1709785909
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.175818767
Short name T58
Test name
Test status
Simulation time 7074339986 ps
CPU time 46.66 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 216904 kb
Host smart-f42b6556-3d28-468d-8524-62bd88dd2179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175818767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.175818767
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2059117412
Short name T239
Test name
Test status
Simulation time 2309688609 ps
CPU time 65.32 seconds
Started Jul 05 05:13:02 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 221312 kb
Host smart-537eb4ac-bee8-458b-95d5-0ab1a910c89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059117412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2059117412
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2057190949
Short name T410
Test name
Test status
Simulation time 126823174 ps
CPU time 4.2 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 215100 kb
Host smart-9fe5995d-5618-41a9-b35b-eaf51fe39b1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057190949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2057190949
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3433405888
Short name T7
Test name
Test status
Simulation time 2235553886 ps
CPU time 24.45 seconds
Started Jul 05 05:10:38 PM PDT 24
Finished Jul 05 05:11:03 PM PDT 24
Peak memory 216984 kb
Host smart-ff044acb-191f-459d-bf64-e6af8b08196b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433405888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3433405888
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2423008451
Short name T161
Test name
Test status
Simulation time 111032823 ps
CPU time 3.01 seconds
Started Jul 05 04:28:38 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 213524 kb
Host smart-c32b7217-1d04-4d6d-bc67-cf375d362924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423008451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2423008451
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.517178057
Short name T71
Test name
Test status
Simulation time 161565483 ps
CPU time 2.19 seconds
Started Jul 05 05:10:31 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 220708 kb
Host smart-6ce63059-86b0-4153-b9cc-29467a2d5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517178057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.517178057
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.604202219
Short name T1
Test name
Test status
Simulation time 92799176 ps
CPU time 3.06 seconds
Started Jul 05 05:12:38 PM PDT 24
Finished Jul 05 05:12:43 PM PDT 24
Peak memory 221980 kb
Host smart-93f0751f-9652-42e5-88e3-6fa49e697c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604202219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.604202219
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3499908347
Short name T154
Test name
Test status
Simulation time 297731503 ps
CPU time 5.65 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:35 PM PDT 24
Peak memory 213556 kb
Host smart-512a4bd6-070a-4f58-9c75-9cf8cd98e592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499908347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3499908347
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.161905623
Short name T290
Test name
Test status
Simulation time 339565247 ps
CPU time 2.74 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 206092 kb
Host smart-c0de7afe-bc46-46a7-8c51-1b01e58d1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161905623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.161905623
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3725326928
Short name T76
Test name
Test status
Simulation time 8010071550 ps
CPU time 27.1 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:14:12 PM PDT 24
Peak memory 215664 kb
Host smart-ca858211-46cc-4eab-a5b3-01cae2d380d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725326928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3725326928
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.123863004
Short name T151
Test name
Test status
Simulation time 485337894 ps
CPU time 9.19 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 213596 kb
Host smart-747cc584-57b3-4e84-b3aa-8b15d94dcaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123863004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
123863004
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.307332154
Short name T309
Test name
Test status
Simulation time 28887646 ps
CPU time 1.88 seconds
Started Jul 05 05:13:28 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 214436 kb
Host smart-a7e75824-5c62-475b-8cc4-7fa3a9133fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307332154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.307332154
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.245504444
Short name T179
Test name
Test status
Simulation time 174765173 ps
CPU time 2.57 seconds
Started Jul 05 05:13:07 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 222636 kb
Host smart-f7fa936b-ef0b-43ca-b62d-aefa04b9b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245504444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.245504444
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1158137059
Short name T180
Test name
Test status
Simulation time 244057453 ps
CPU time 3.35 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:56 PM PDT 24
Peak memory 217220 kb
Host smart-107755bf-eccd-4c29-813a-442ce43a9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158137059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1158137059
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.648946288
Short name T226
Test name
Test status
Simulation time 38883998 ps
CPU time 2.5 seconds
Started Jul 05 05:10:31 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 208472 kb
Host smart-f0ebdad6-5b9a-41cb-9952-381e5bf6d133
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648946288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.648946288
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3572755814
Short name T302
Test name
Test status
Simulation time 57118151 ps
CPU time 3.56 seconds
Started Jul 05 05:11:33 PM PDT 24
Finished Jul 05 05:11:37 PM PDT 24
Peak memory 214732 kb
Host smart-ed46ddf2-c240-49d0-a798-02ab82de3449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572755814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3572755814
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.355613247
Short name T412
Test name
Test status
Simulation time 2482615048 ps
CPU time 11.83 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:53 PM PDT 24
Peak memory 214492 kb
Host smart-b1c26241-f970-493b-b90a-cfcd105c16ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355613247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.355613247
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3243308469
Short name T314
Test name
Test status
Simulation time 2358263180 ps
CPU time 30.32 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:29 PM PDT 24
Peak memory 222388 kb
Host smart-d81458d6-eb1a-49b7-b08c-7050ff14c4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243308469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3243308469
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1405087081
Short name T13
Test name
Test status
Simulation time 1118673519 ps
CPU time 18.98 seconds
Started Jul 05 05:10:45 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 233288 kb
Host smart-1a92a5ac-7c90-4863-a278-d07672b1602d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405087081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1405087081
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.244039812
Short name T25
Test name
Test status
Simulation time 116965701 ps
CPU time 3.56 seconds
Started Jul 05 05:13:11 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 208992 kb
Host smart-262d681f-b575-4301-a99d-8ef1c5ea9c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244039812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.244039812
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2537151217
Short name T171
Test name
Test status
Simulation time 98557078 ps
CPU time 2.18 seconds
Started Jul 05 05:13:15 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 210236 kb
Host smart-6ca73742-34e1-4a8f-aa25-7d6be997c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537151217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2537151217
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.475015275
Short name T166
Test name
Test status
Simulation time 1612271436 ps
CPU time 11.17 seconds
Started Jul 05 04:28:17 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 216008 kb
Host smart-6df03c54-bfc3-48e8-9f6e-1ed202af2add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475015275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
475015275
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3623347961
Short name T175
Test name
Test status
Simulation time 92648028 ps
CPU time 2.86 seconds
Started Jul 05 04:36:10 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 213672 kb
Host smart-da3d4bc2-04cd-4710-a2f7-2da8f4cd3443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623347961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3623347961
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1102379630
Short name T359
Test name
Test status
Simulation time 101543324 ps
CPU time 4.57 seconds
Started Jul 05 05:10:32 PM PDT 24
Finished Jul 05 05:10:37 PM PDT 24
Peak memory 207016 kb
Host smart-8d38834f-4305-496f-917c-a93b935de64c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102379630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1102379630
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.557846847
Short name T102
Test name
Test status
Simulation time 75923853 ps
CPU time 2.89 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:30 PM PDT 24
Peak memory 222364 kb
Host smart-0c9e154d-4707-4016-b31a-5569b9f5cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557846847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.557846847
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1721223999
Short name T124
Test name
Test status
Simulation time 581339792 ps
CPU time 19.56 seconds
Started Jul 05 05:11:37 PM PDT 24
Finished Jul 05 05:11:57 PM PDT 24
Peak memory 222340 kb
Host smart-48d37f59-64d1-4b63-8c09-2a3b7e0b4eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721223999 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1721223999
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2838807058
Short name T427
Test name
Test status
Simulation time 91914361 ps
CPU time 4.98 seconds
Started Jul 05 05:10:42 PM PDT 24
Finished Jul 05 05:10:47 PM PDT 24
Peak memory 215600 kb
Host smart-b380846b-c9fa-45ee-8152-dd6b6731affb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838807058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2838807058
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3845369379
Short name T134
Test name
Test status
Simulation time 242489969 ps
CPU time 3.24 seconds
Started Jul 05 05:13:13 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 214340 kb
Host smart-b4afa770-9933-4bba-88a0-a21b7973b38c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845369379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3845369379
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3551205825
Short name T367
Test name
Test status
Simulation time 509250276 ps
CPU time 5.93 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 222300 kb
Host smart-e6a3ab88-cdab-4e2d-a474-2d370b980d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551205825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3551205825
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2031749039
Short name T265
Test name
Test status
Simulation time 48337056 ps
CPU time 2.21 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 214260 kb
Host smart-4a63128e-3f5a-4dac-8db7-e5fff56a543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031749039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2031749039
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2949967875
Short name T130
Test name
Test status
Simulation time 81033391 ps
CPU time 1.9 seconds
Started Jul 05 05:12:29 PM PDT 24
Finished Jul 05 05:12:32 PM PDT 24
Peak memory 207552 kb
Host smart-06438182-2e1f-4c50-8c98-b6f0291142f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949967875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2949967875
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1391982106
Short name T181
Test name
Test status
Simulation time 101426133 ps
CPU time 3.27 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:20 PM PDT 24
Peak memory 222628 kb
Host smart-dae84cbc-6ffb-45bd-b3b0-7e059b486996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391982106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1391982106
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3144587526
Short name T182
Test name
Test status
Simulation time 977745283 ps
CPU time 29.76 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 218460 kb
Host smart-8793c047-3d22-4430-83cc-04596ee1f4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144587526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3144587526
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2056601424
Short name T89
Test name
Test status
Simulation time 585978850 ps
CPU time 9.38 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:35 PM PDT 24
Peak memory 214316 kb
Host smart-4c0f12d6-b82e-4ee3-9b9a-6a6a50df1d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056601424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2056601424
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1937786908
Short name T357
Test name
Test status
Simulation time 1579283528 ps
CPU time 8.01 seconds
Started Jul 05 05:11:30 PM PDT 24
Finished Jul 05 05:11:39 PM PDT 24
Peak memory 214360 kb
Host smart-5c0c03c2-f49a-471c-8fe1-4029002ef821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937786908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1937786908
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1890775431
Short name T170
Test name
Test status
Simulation time 4271461070 ps
CPU time 20.87 seconds
Started Jul 05 05:11:55 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 211596 kb
Host smart-26c476e7-2086-4ba0-9755-d712e49980d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890775431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1890775431
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3429999957
Short name T422
Test name
Test status
Simulation time 227052345 ps
CPU time 11.61 seconds
Started Jul 05 05:12:06 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 215392 kb
Host smart-ac842356-391a-471a-aa47-1f9796e14846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429999957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3429999957
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1525341642
Short name T383
Test name
Test status
Simulation time 4037885030 ps
CPU time 100.9 seconds
Started Jul 05 05:12:39 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 217264 kb
Host smart-770c65e2-b0e0-48b5-81c2-d898f46e4d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525341642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1525341642
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1824147099
Short name T3
Test name
Test status
Simulation time 800341159 ps
CPU time 7.16 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:44 PM PDT 24
Peak memory 208608 kb
Host smart-79a142d6-624f-434b-89a8-2dc5b910541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824147099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1824147099
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2952528316
Short name T289
Test name
Test status
Simulation time 72958598 ps
CPU time 3.4 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 214284 kb
Host smart-c0ec5955-1707-4fc0-9cde-e79ce2ce873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952528316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2952528316
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.762553675
Short name T153
Test name
Test status
Simulation time 533300084 ps
CPU time 9.26 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:54 PM PDT 24
Peak memory 213776 kb
Host smart-408d871c-c9fe-4d0e-b50e-8945a97a6b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762553675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
762553675
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3851088472
Short name T157
Test name
Test status
Simulation time 159234803 ps
CPU time 4.2 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 213560 kb
Host smart-1d61342b-3701-490b-9bb6-9fa7ce0abace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851088472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3851088472
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3927864868
Short name T164
Test name
Test status
Simulation time 1897950822 ps
CPU time 8.32 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 213496 kb
Host smart-6976e43b-912f-45b0-9484-f873e6fd2fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927864868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3927864868
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.486219755
Short name T158
Test name
Test status
Simulation time 473558198 ps
CPU time 7.69 seconds
Started Jul 05 04:28:14 PM PDT 24
Finished Jul 05 04:28:35 PM PDT 24
Peak memory 213584 kb
Host smart-bb1e9640-d40b-4d83-baa9-2f6499fd4e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486219755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
486219755
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.196844027
Short name T177
Test name
Test status
Simulation time 78290282 ps
CPU time 2.18 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:11:54 PM PDT 24
Peak memory 222700 kb
Host smart-5cd71aec-fb7f-4f0a-b675-2f3846495d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196844027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.196844027
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3686333672
Short name T873
Test name
Test status
Simulation time 177349052 ps
CPU time 3.44 seconds
Started Jul 05 05:10:28 PM PDT 24
Finished Jul 05 05:10:32 PM PDT 24
Peak memory 214304 kb
Host smart-3631e7d2-b78d-42ab-b879-5c184571e593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686333672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3686333672
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3628085035
Short name T368
Test name
Test status
Simulation time 41162132 ps
CPU time 2.37 seconds
Started Jul 05 05:10:29 PM PDT 24
Finished Jul 05 05:10:32 PM PDT 24
Peak memory 221264 kb
Host smart-44fb63af-b989-4e79-8ca4-871b4e109aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628085035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3628085035
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2551290072
Short name T183
Test name
Test status
Simulation time 889673458 ps
CPU time 8.04 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:42 PM PDT 24
Peak memory 218912 kb
Host smart-2e5d3cb5-a5b7-48e2-8496-073c046ecbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551290072 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2551290072
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.860241548
Short name T340
Test name
Test status
Simulation time 56856751 ps
CPU time 2.47 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:37 PM PDT 24
Peak memory 214336 kb
Host smart-0265a82c-96ed-41af-9824-0d83e3489687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860241548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.860241548
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1213020627
Short name T237
Test name
Test status
Simulation time 6803086332 ps
CPU time 35.86 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 216216 kb
Host smart-4a1f1dd8-339c-4291-b4fc-13e2401c3b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213020627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1213020627
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4083345941
Short name T291
Test name
Test status
Simulation time 147378336 ps
CPU time 3.05 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 214352 kb
Host smart-c918d7f8-9486-494c-9be0-68259537c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083345941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4083345941
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2400741670
Short name T232
Test name
Test status
Simulation time 1964408574 ps
CPU time 58.76 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 215648 kb
Host smart-fe32921a-789a-43aa-bcdd-ff7f88baf46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400741670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2400741670
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.223587262
Short name T74
Test name
Test status
Simulation time 632086214 ps
CPU time 2.93 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 214320 kb
Host smart-29d6973f-c753-4023-80c0-3590450c7f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223587262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.223587262
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_random.846657687
Short name T321
Test name
Test status
Simulation time 47137693 ps
CPU time 2.82 seconds
Started Jul 05 05:11:30 PM PDT 24
Finished Jul 05 05:11:33 PM PDT 24
Peak memory 207272 kb
Host smart-d51f9ab1-0e8d-4360-a998-5a194d5455c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846657687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.846657687
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.20142401
Short name T483
Test name
Test status
Simulation time 53150430 ps
CPU time 2.59 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:30 PM PDT 24
Peak memory 207068 kb
Host smart-181dcf13-1a78-4fc2-9793-763d83bdeebe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.20142401
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3236975847
Short name T250
Test name
Test status
Simulation time 935872548 ps
CPU time 10.68 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 214060 kb
Host smart-6606c95c-dae3-4e98-99b4-17e96685bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236975847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3236975847
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.716509544
Short name T139
Test name
Test status
Simulation time 10173466674 ps
CPU time 208.08 seconds
Started Jul 05 05:12:13 PM PDT 24
Finished Jul 05 05:15:43 PM PDT 24
Peak memory 222528 kb
Host smart-71305f09-af73-4f3f-b933-23a0a804ac56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716509544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.716509544
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1882614577
Short name T426
Test name
Test status
Simulation time 1646649300 ps
CPU time 29.39 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:13:17 PM PDT 24
Peak memory 214508 kb
Host smart-d8312937-d2a4-41cf-84a8-e74e4621b907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882614577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1882614577
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3998564378
Short name T345
Test name
Test status
Simulation time 469382604 ps
CPU time 3.61 seconds
Started Jul 05 05:12:42 PM PDT 24
Finished Jul 05 05:12:47 PM PDT 24
Peak memory 221388 kb
Host smart-0a7fc265-7d16-4370-a11d-fb682dce196c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998564378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3998564378
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1666911994
Short name T372
Test name
Test status
Simulation time 1503823141 ps
CPU time 18.28 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:13:03 PM PDT 24
Peak memory 218864 kb
Host smart-2b1d7511-1243-439f-8894-a77aad703516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666911994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1666911994
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2654949602
Short name T298
Test name
Test status
Simulation time 602913685 ps
CPU time 5.27 seconds
Started Jul 05 05:13:24 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 215344 kb
Host smart-b168a48c-d3d4-4fed-b400-135ccfefcf39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654949602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2654949602
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3993248056
Short name T241
Test name
Test status
Simulation time 198505839 ps
CPU time 5.25 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:52 PM PDT 24
Peak memory 209380 kb
Host smart-8455d672-e5c9-4fb6-8995-10be1e723764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993248056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3993248056
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3417778940
Short name T231
Test name
Test status
Simulation time 242461284 ps
CPU time 7.23 seconds
Started Jul 05 05:11:03 PM PDT 24
Finished Jul 05 05:11:10 PM PDT 24
Peak memory 214720 kb
Host smart-20f1df04-37e7-4a43-bf89-bf6c5c100844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417778940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3417778940
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3587648685
Short name T178
Test name
Test status
Simulation time 53592083 ps
CPU time 3.54 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 222640 kb
Host smart-1c51b6b9-1f48-4ea8-9773-d4fabfa24e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587648685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3587648685
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.200371248
Short name T1003
Test name
Test status
Simulation time 1714027642 ps
CPU time 8.57 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:24 PM PDT 24
Peak memory 205480 kb
Host smart-17966612-f81c-49da-a21a-4b32c616244b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200371248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.200371248
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1409296563
Short name T1047
Test name
Test status
Simulation time 2670405311 ps
CPU time 16.48 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 205452 kb
Host smart-225a2418-0fa7-410b-992e-2857815caeb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409296563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
409296563
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3253369060
Short name T975
Test name
Test status
Simulation time 19944062 ps
CPU time 1.14 seconds
Started Jul 05 04:28:25 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 205420 kb
Host smart-b0cfe933-5804-4ab4-bbf1-5b995ed01537
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253369060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
253369060
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2711566047
Short name T190
Test name
Test status
Simulation time 124589309 ps
CPU time 1.27 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:38 PM PDT 24
Peak memory 213728 kb
Host smart-2760c9e6-51f2-44e5-b8bc-0a09beb3f76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711566047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2711566047
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3853126123
Short name T144
Test name
Test status
Simulation time 262219442 ps
CPU time 1.24 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205380 kb
Host smart-20509809-9f39-4166-afa8-00337dd4b930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853126123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3853126123
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2328355387
Short name T994
Test name
Test status
Simulation time 14783619 ps
CPU time 0.89 seconds
Started Jul 05 04:28:16 PM PDT 24
Finished Jul 05 04:28:30 PM PDT 24
Peak memory 205648 kb
Host smart-8634b733-8a27-42d8-8ced-6d4b5bafe52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328355387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2328355387
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2860145523
Short name T143
Test name
Test status
Simulation time 94029802 ps
CPU time 2.17 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 205328 kb
Host smart-d7a4341a-8d4f-49a0-88d0-63ad659dcc0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860145523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2860145523
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.240230261
Short name T1057
Test name
Test status
Simulation time 74527274 ps
CPU time 2.75 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:33 PM PDT 24
Peak memory 213868 kb
Host smart-5774f2d1-677b-464c-b081-08358fca962d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240230261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.240230261
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3398693295
Short name T1001
Test name
Test status
Simulation time 1025575860 ps
CPU time 6.46 seconds
Started Jul 05 04:28:15 PM PDT 24
Finished Jul 05 04:28:34 PM PDT 24
Peak memory 219712 kb
Host smart-25ede11e-4b4e-4186-9828-0e40b7e1d644
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398693295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3398693295
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1481165090
Short name T972
Test name
Test status
Simulation time 100500240 ps
CPU time 2.39 seconds
Started Jul 05 04:29:35 PM PDT 24
Finished Jul 05 04:29:42 PM PDT 24
Peak memory 213548 kb
Host smart-53890c6e-7ee0-4535-936f-9acafae263c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481165090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1481165090
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2169908944
Short name T156
Test name
Test status
Simulation time 739735808 ps
CPU time 6.21 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:37 PM PDT 24
Peak memory 205232 kb
Host smart-65664536-88bf-4402-884e-a5617afdd219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169908944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
169908944
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.745840398
Short name T1071
Test name
Test status
Simulation time 1152097321 ps
CPU time 14.69 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 205408 kb
Host smart-5880771a-0c92-4127-87c3-36a1cff19913
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745840398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.745840398
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2111788889
Short name T1025
Test name
Test status
Simulation time 40810277 ps
CPU time 0.85 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 205308 kb
Host smart-45b44e9a-868a-4cb0-89cf-e85a5a671eab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111788889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
111788889
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3892974815
Short name T941
Test name
Test status
Simulation time 14070895 ps
CPU time 0.85 seconds
Started Jul 05 04:28:20 PM PDT 24
Finished Jul 05 04:28:34 PM PDT 24
Peak memory 205180 kb
Host smart-7da69234-aac4-4d4b-b69e-fc704400744e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892974815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3892974815
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3275475870
Short name T1045
Test name
Test status
Simulation time 12849472 ps
CPU time 0.72 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:20 PM PDT 24
Peak memory 205128 kb
Host smart-8b497db9-61a6-4520-825c-c46af4274f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275475870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3275475870
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.281461786
Short name T991
Test name
Test status
Simulation time 111620313 ps
CPU time 2.5 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:07 PM PDT 24
Peak memory 204696 kb
Host smart-4aa3b4ef-8e10-40fd-9808-4edaff6c59da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281461786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.281461786
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2582800242
Short name T120
Test name
Test status
Simulation time 959431421 ps
CPU time 2.13 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:33 PM PDT 24
Peak memory 213880 kb
Host smart-65497569-1f43-4401-bd07-02cae3d55222
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582800242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2582800242
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3627603888
Short name T1061
Test name
Test status
Simulation time 778337882 ps
CPU time 9.26 seconds
Started Jul 05 04:28:12 PM PDT 24
Finished Jul 05 04:28:35 PM PDT 24
Peak memory 213784 kb
Host smart-17e582e0-e263-45c3-b760-944a60b64296
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627603888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3627603888
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3172892984
Short name T1020
Test name
Test status
Simulation time 106372554 ps
CPU time 2.67 seconds
Started Jul 05 04:28:15 PM PDT 24
Finished Jul 05 04:28:30 PM PDT 24
Peak memory 215764 kb
Host smart-ea26d91c-8ed2-4a63-b1c9-1d1e0a70b5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172892984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3172892984
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2643385747
Short name T1067
Test name
Test status
Simulation time 27406058 ps
CPU time 1.7 seconds
Started Jul 05 04:29:26 PM PDT 24
Finished Jul 05 04:29:36 PM PDT 24
Peak memory 213692 kb
Host smart-865cd3d1-5a62-4604-9f19-5c2c652cff5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643385747 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2643385747
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1037854576
Short name T1044
Test name
Test status
Simulation time 21063513 ps
CPU time 0.95 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 205264 kb
Host smart-b5754114-0e55-47ff-9a43-f4eec984c93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037854576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1037854576
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3341533913
Short name T1009
Test name
Test status
Simulation time 41519239 ps
CPU time 0.82 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 205096 kb
Host smart-c039c315-cbb8-4892-9ee7-8d9fb28304e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341533913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3341533913
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1825931821
Short name T142
Test name
Test status
Simulation time 65354791 ps
CPU time 2.01 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205316 kb
Host smart-a3aceebe-b8f9-41d7-9413-32bc2262b78c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825931821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1825931821
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4140569941
Short name T1081
Test name
Test status
Simulation time 285265239 ps
CPU time 3.05 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 214288 kb
Host smart-5b539464-32de-40e8-be4c-be8d38ca7464
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140569941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4140569941
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.787990103
Short name T1080
Test name
Test status
Simulation time 166694955 ps
CPU time 3.97 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 213868 kb
Host smart-1118f6df-d714-49bd-9fee-5164563f58cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787990103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.787990103
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4122097394
Short name T920
Test name
Test status
Simulation time 136003072 ps
CPU time 4.49 seconds
Started Jul 05 04:28:12 PM PDT 24
Finished Jul 05 04:28:29 PM PDT 24
Peak memory 213524 kb
Host smart-78e20427-b6bb-4be1-b5c1-4a9066ca6588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122097394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4122097394
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3086039590
Short name T174
Test name
Test status
Simulation time 55804603 ps
CPU time 2.44 seconds
Started Jul 05 04:28:08 PM PDT 24
Finished Jul 05 04:28:20 PM PDT 24
Peak memory 214840 kb
Host smart-783be543-eb99-4730-aefc-19a0a07fbb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086039590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3086039590
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1704825445
Short name T189
Test name
Test status
Simulation time 232387305 ps
CPU time 1.6 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 205364 kb
Host smart-fcd44618-60ee-4073-a180-42f8ae3b56d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704825445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1704825445
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3026272908
Short name T973
Test name
Test status
Simulation time 23144839 ps
CPU time 1.43 seconds
Started Jul 05 04:28:15 PM PDT 24
Finished Jul 05 04:28:29 PM PDT 24
Peak memory 205244 kb
Host smart-f1042784-bef1-4081-aac3-48cd7a1704f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026272908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3026272908
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1707547488
Short name T924
Test name
Test status
Simulation time 8799887 ps
CPU time 0.77 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:31 PM PDT 24
Peak memory 205208 kb
Host smart-7f9f1728-0be6-41bc-a7e8-37e14ee1502a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707547488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1707547488
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3673889968
Short name T967
Test name
Test status
Simulation time 218915327 ps
CPU time 4.03 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:28:51 PM PDT 24
Peak memory 205404 kb
Host smart-0b44377a-bec7-4fef-821e-6aad7022508b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673889968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3673889968
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3765027203
Short name T116
Test name
Test status
Simulation time 171621108 ps
CPU time 2.2 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:36 PM PDT 24
Peak memory 213824 kb
Host smart-6ff271ad-6d61-46fb-8408-ba94d1aa5dbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765027203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3765027203
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.247158077
Short name T951
Test name
Test status
Simulation time 1348522934 ps
CPU time 6.44 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 213852 kb
Host smart-00f8f427-bae4-434d-85f7-1b33ad9c2eda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247158077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.247158077
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1472894780
Short name T1008
Test name
Test status
Simulation time 77020387 ps
CPU time 2.95 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 213552 kb
Host smart-c18c0f0d-0869-4f49-bb24-f51f64caecb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472894780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1472894780
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3381364001
Short name T149
Test name
Test status
Simulation time 170682619 ps
CPU time 2.75 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 213544 kb
Host smart-76dd1498-2a38-48f9-b871-6127370e33a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381364001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3381364001
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.768504116
Short name T974
Test name
Test status
Simulation time 26725979 ps
CPU time 1.09 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 205332 kb
Host smart-cf1e9b1d-1fda-45e6-9f6f-69c1e28d2a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768504116 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.768504116
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1710145375
Short name T147
Test name
Test status
Simulation time 47506003 ps
CPU time 1.23 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 205276 kb
Host smart-2ee50e99-4aef-474e-a01d-3c120f28b8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710145375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1710145375
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4188715284
Short name T1004
Test name
Test status
Simulation time 13447728 ps
CPU time 0.73 seconds
Started Jul 05 04:28:44 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 205208 kb
Host smart-9b636b12-95e4-4845-a87a-aef68faee488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188715284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4188715284
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1415965698
Short name T1035
Test name
Test status
Simulation time 23044940 ps
CPU time 1.74 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:03 PM PDT 24
Peak memory 205368 kb
Host smart-2d77f353-00f3-4256-8518-c22d8e302a46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415965698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1415965698
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2631271560
Short name T119
Test name
Test status
Simulation time 154453912 ps
CPU time 3.61 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 213940 kb
Host smart-a6a46b2b-50fb-4a1c-aef0-688316ac5d64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631271560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2631271560
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2564553201
Short name T1059
Test name
Test status
Simulation time 732295476 ps
CPU time 4.11 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 213676 kb
Host smart-1f9a0723-3e33-442c-8705-40647bc4a91a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564553201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2564553201
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4113563663
Short name T1076
Test name
Test status
Simulation time 45426562 ps
CPU time 1.34 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:42 PM PDT 24
Peak memory 213588 kb
Host smart-cdf19914-e34f-48c5-926b-751eda1f7738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113563663 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4113563663
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.41853294
Short name T1070
Test name
Test status
Simulation time 23012079 ps
CPU time 0.88 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 205228 kb
Host smart-76f37c3b-cfba-4d43-bb1f-ecf1bc514522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.41853294
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.16395827
Short name T970
Test name
Test status
Simulation time 100344624 ps
CPU time 0.72 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:03 PM PDT 24
Peak memory 205140 kb
Host smart-13830998-2e43-4ce1-827d-2f6ddcb707f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16395827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.16395827
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2578114021
Short name T1013
Test name
Test status
Simulation time 123240840 ps
CPU time 4.03 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205328 kb
Host smart-d36a06fa-be22-4130-b2e6-692f9d40cf2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578114021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2578114021
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3456612986
Short name T1048
Test name
Test status
Simulation time 88681342 ps
CPU time 2.01 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:48 PM PDT 24
Peak memory 213852 kb
Host smart-dbee3aee-f24a-44be-8a98-75d775fc78fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456612986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3456612986
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3910447581
Short name T953
Test name
Test status
Simulation time 257807832 ps
CPU time 6.01 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:07 PM PDT 24
Peak memory 213852 kb
Host smart-53aa4732-bbae-4e83-a0e6-d856d96f6cd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910447581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3910447581
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.92653623
Short name T928
Test name
Test status
Simulation time 118152360 ps
CPU time 2.94 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:51 PM PDT 24
Peak memory 213596 kb
Host smart-e02b3927-9282-4308-9fe4-2e1333a43cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92653623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.92653623
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2486201965
Short name T1022
Test name
Test status
Simulation time 64026964 ps
CPU time 2.15 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 213624 kb
Host smart-7960716f-49fb-4e89-aeeb-56321f9ce6b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486201965 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2486201965
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.444931547
Short name T1032
Test name
Test status
Simulation time 182970812 ps
CPU time 1.14 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 205420 kb
Host smart-82a31eb7-8849-4455-a36d-2adb798bf396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444931547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.444931547
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3914763097
Short name T931
Test name
Test status
Simulation time 36537955 ps
CPU time 0.8 seconds
Started Jul 05 04:28:24 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 205184 kb
Host smart-ad8c1df5-b577-4161-a794-884c2296adfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914763097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3914763097
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4103070335
Short name T1073
Test name
Test status
Simulation time 235201086 ps
CPU time 1.97 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 205308 kb
Host smart-3b1aebd2-dcf1-4d7b-849a-c7917834b667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103070335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4103070335
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3382653324
Short name T113
Test name
Test status
Simulation time 88992542 ps
CPU time 2.01 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 213904 kb
Host smart-75eacb2a-884d-43b9-8fe2-4ef175711fa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382653324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3382653324
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1974146885
Short name T987
Test name
Test status
Simulation time 270910205 ps
CPU time 8.7 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 213872 kb
Host smart-4a053aa5-98b4-4900-9013-ce30db1498e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974146885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1974146885
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3783190723
Short name T1077
Test name
Test status
Simulation time 419431114 ps
CPU time 2.57 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 213580 kb
Host smart-387366b4-dcdc-4987-a6e0-f690eb1caaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783190723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3783190723
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3132539028
Short name T150
Test name
Test status
Simulation time 196099588 ps
CPU time 3.04 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:51 PM PDT 24
Peak memory 213488 kb
Host smart-76419a2f-b1f4-4d59-ba3d-2c7ee2375f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132539028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3132539028
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2282710616
Short name T965
Test name
Test status
Simulation time 99982037 ps
CPU time 1.33 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 213636 kb
Host smart-9b243749-c6e9-477b-bdb5-281a365a60fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282710616 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2282710616
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2581155317
Short name T1078
Test name
Test status
Simulation time 22794344 ps
CPU time 1.34 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205308 kb
Host smart-59340223-4f0d-4a23-bd4f-3686b3de0540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581155317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2581155317
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3456714506
Short name T989
Test name
Test status
Simulation time 31286210 ps
CPU time 0.79 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 205208 kb
Host smart-deb99928-b1d6-4b80-8b1f-e5c6762290c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456714506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3456714506
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2767756696
Short name T946
Test name
Test status
Simulation time 506869834 ps
CPU time 2.5 seconds
Started Jul 05 04:28:25 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 205444 kb
Host smart-45161153-8c9b-46fa-b2b0-2ae756e4666b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767756696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2767756696
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2443175640
Short name T1026
Test name
Test status
Simulation time 657258056 ps
CPU time 2.04 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 213856 kb
Host smart-1b7f5983-2d29-479e-869a-5a4dab5a677b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443175640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2443175640
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4272644670
Short name T121
Test name
Test status
Simulation time 652120571 ps
CPU time 4.44 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 213892 kb
Host smart-fd253090-828a-4076-b1c0-52e434a969e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272644670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4272644670
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2614705338
Short name T929
Test name
Test status
Simulation time 270520244 ps
CPU time 1.87 seconds
Started Jul 05 04:28:12 PM PDT 24
Finished Jul 05 04:28:27 PM PDT 24
Peak memory 214536 kb
Host smart-469917a0-91e1-47b3-8985-4d465a7ae5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614705338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2614705338
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1558811449
Short name T1037
Test name
Test status
Simulation time 60827217 ps
CPU time 1.1 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:37 PM PDT 24
Peak memory 205372 kb
Host smart-b641ea8a-c514-4d23-9c33-959bf9642fe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558811449 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1558811449
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1124788797
Short name T930
Test name
Test status
Simulation time 30224714 ps
CPU time 0.89 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 205328 kb
Host smart-5f4fc71a-b82a-4791-bc1c-32185c741e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124788797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1124788797
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4011058175
Short name T1036
Test name
Test status
Simulation time 43384254 ps
CPU time 0.86 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:02 PM PDT 24
Peak memory 205212 kb
Host smart-7ebe61b9-56da-4227-ba47-25f4421ac442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011058175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4011058175
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1295134742
Short name T949
Test name
Test status
Simulation time 87753502 ps
CPU time 1.66 seconds
Started Jul 05 04:28:16 PM PDT 24
Finished Jul 05 04:28:31 PM PDT 24
Peak memory 205256 kb
Host smart-029ed5ea-ec8b-4381-add8-4af5b805122a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295134742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1295134742
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4185564514
Short name T1053
Test name
Test status
Simulation time 120837836 ps
CPU time 1.73 seconds
Started Jul 05 04:28:42 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 213876 kb
Host smart-3326aefa-c61d-4c1f-b0e9-0c44a51f3233
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185564514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4185564514
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2235713897
Short name T117
Test name
Test status
Simulation time 206419692 ps
CPU time 6.97 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 213760 kb
Host smart-af0d3e16-f30e-43b2-9344-435ba5985d6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235713897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2235713897
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2451570668
Short name T1063
Test name
Test status
Simulation time 47707258 ps
CPU time 2.45 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:48 PM PDT 24
Peak memory 215776 kb
Host smart-76b2bd99-05e4-48a4-b860-a13128c8a088
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451570668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2451570668
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2240965344
Short name T1017
Test name
Test status
Simulation time 31025760 ps
CPU time 1.39 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:42 PM PDT 24
Peak memory 213688 kb
Host smart-bb1e6c62-7d45-4347-9571-e8129eeb1ee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240965344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2240965344
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.207495164
Short name T934
Test name
Test status
Simulation time 16918155 ps
CPU time 0.92 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 205264 kb
Host smart-92ec4d16-b33b-4d20-9820-2f4ce023bd19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207495164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.207495164
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2009439024
Short name T1014
Test name
Test status
Simulation time 36760634 ps
CPU time 0.8 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:03 PM PDT 24
Peak memory 205144 kb
Host smart-1527f82b-3954-471a-927c-d2e392a1dcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009439024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2009439024
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3417414669
Short name T1011
Test name
Test status
Simulation time 70341087 ps
CPU time 2.3 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 205396 kb
Host smart-da0083d3-e620-45d6-87f0-a6bcb4f99fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417414669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3417414669
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.341847835
Short name T958
Test name
Test status
Simulation time 311330882 ps
CPU time 3.14 seconds
Started Jul 05 04:28:20 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 213876 kb
Host smart-b90e403b-6898-42ec-878b-c2918c122242
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341847835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.341847835
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2414026847
Short name T1056
Test name
Test status
Simulation time 612239522 ps
CPU time 7.72 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 213980 kb
Host smart-a05623e3-ce8f-43b9-aaf3-ae7a238f828d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414026847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2414026847
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.770572569
Short name T1054
Test name
Test status
Simulation time 91724716 ps
CPU time 2.14 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 215760 kb
Host smart-89c3ebdc-b633-427b-8d78-45898607c710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770572569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.770572569
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4199182176
Short name T173
Test name
Test status
Simulation time 79342938 ps
CPU time 2.41 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 213528 kb
Host smart-7f013280-713a-49d5-8e19-aedc206c1557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199182176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4199182176
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2194611757
Short name T945
Test name
Test status
Simulation time 223766634 ps
CPU time 1.72 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 213728 kb
Host smart-b1b9c329-c8fb-4141-9b84-2fa5f017cad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194611757 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2194611757
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2677362861
Short name T947
Test name
Test status
Simulation time 19647883 ps
CPU time 0.9 seconds
Started Jul 05 04:28:26 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 205332 kb
Host smart-3910faec-1c01-4551-a9d5-6aa2dc187aa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677362861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2677362861
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.654838709
Short name T926
Test name
Test status
Simulation time 9723200 ps
CPU time 0.8 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 205208 kb
Host smart-cb23902a-a755-4b07-9ec0-4289df545941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654838709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.654838709
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2683368517
Short name T1034
Test name
Test status
Simulation time 524117062 ps
CPU time 1.82 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205484 kb
Host smart-a0f32d6f-6f3b-4dc3-a858-91b3c91d082a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683368517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2683368517
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2004364149
Short name T984
Test name
Test status
Simulation time 90598036 ps
CPU time 2.29 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 213816 kb
Host smart-6b795e5d-d324-4431-9bac-93738b2615e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004364149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2004364149
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2219729665
Short name T983
Test name
Test status
Simulation time 2316388777 ps
CPU time 13.87 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 220792 kb
Host smart-2e31ca3a-dadd-47f4-9da6-3633592bf9c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219729665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2219729665
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2004843430
Short name T1000
Test name
Test status
Simulation time 51058501 ps
CPU time 3.72 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 216160 kb
Host smart-32ac2667-a5d5-4463-9be1-432ba4136196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004843430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2004843430
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1466282871
Short name T165
Test name
Test status
Simulation time 103070143 ps
CPU time 3.09 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 213536 kb
Host smart-31b0cc48-41b8-4090-bc39-cf08e2cb9715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466282871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1466282871
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3529059298
Short name T992
Test name
Test status
Simulation time 368625253 ps
CPU time 1.63 seconds
Started Jul 05 04:28:43 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 213696 kb
Host smart-e96a54d3-456d-4359-bcee-e29a10a67b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529059298 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3529059298
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3756586579
Short name T1024
Test name
Test status
Simulation time 44910090 ps
CPU time 1.09 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 205312 kb
Host smart-f7638152-7e8f-476c-ae0d-e5cc54b9b339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756586579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3756586579
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2020269738
Short name T961
Test name
Test status
Simulation time 24825874 ps
CPU time 0.91 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205092 kb
Host smart-94f7ccba-7d61-4a91-9826-3c464da4e638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020269738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2020269738
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.582679050
Short name T1050
Test name
Test status
Simulation time 28467123 ps
CPU time 1.37 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 205356 kb
Host smart-39212238-7c1b-4e6b-af70-5e3923c45e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582679050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.582679050
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.153854684
Short name T1027
Test name
Test status
Simulation time 84323546 ps
CPU time 1.9 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 213844 kb
Host smart-2f808866-b4ad-4241-8175-406e8b988308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153854684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.153854684
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2536114655
Short name T118
Test name
Test status
Simulation time 281134497 ps
CPU time 3.88 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 219884 kb
Host smart-0c3a5942-d390-490e-b8e8-ecfa6c1505ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536114655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2536114655
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3650716130
Short name T988
Test name
Test status
Simulation time 88697272 ps
CPU time 2.09 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 216632 kb
Host smart-d266435c-29c7-4e12-b19d-4b3514f1a022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650716130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3650716130
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.246089773
Short name T168
Test name
Test status
Simulation time 220550666 ps
CPU time 6.16 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 213564 kb
Host smart-0f13495b-3f54-4d34-b9ce-7dce41fe38b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246089773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.246089773
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2424449009
Short name T1079
Test name
Test status
Simulation time 270119063 ps
CPU time 4.86 seconds
Started Jul 05 04:28:17 PM PDT 24
Finished Jul 05 04:28:35 PM PDT 24
Peak memory 205456 kb
Host smart-046aee12-aa33-4fe8-b1ed-db7b4f0a1719
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424449009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
424449009
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3569367342
Short name T203
Test name
Test status
Simulation time 1339275715 ps
CPU time 17.47 seconds
Started Jul 05 04:29:22 PM PDT 24
Finished Jul 05 04:29:48 PM PDT 24
Peak memory 205388 kb
Host smart-7ebbf3b4-5fe9-4196-8b4b-1a35efc227fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569367342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
569367342
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2384586035
Short name T1060
Test name
Test status
Simulation time 27683037 ps
CPU time 0.93 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 204612 kb
Host smart-770324b1-25e6-44bc-b877-725feda1dddc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384586035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
384586035
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2918692857
Short name T938
Test name
Test status
Simulation time 79149365 ps
CPU time 1.8 seconds
Started Jul 05 04:28:16 PM PDT 24
Finished Jul 05 04:28:30 PM PDT 24
Peak memory 213760 kb
Host smart-d881e4f2-3c5f-4466-b58d-93e7fa496d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918692857 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2918692857
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3954195616
Short name T1051
Test name
Test status
Simulation time 16809080 ps
CPU time 1.2 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:38 PM PDT 24
Peak memory 205488 kb
Host smart-e76e7f1c-ce97-49f9-b9d3-8cbb6e56e92b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954195616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3954195616
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1768914255
Short name T933
Test name
Test status
Simulation time 43033605 ps
CPU time 0.71 seconds
Started Jul 05 04:28:14 PM PDT 24
Finished Jul 05 04:28:28 PM PDT 24
Peak memory 205128 kb
Host smart-e461ed81-17f2-4518-94ff-fe668ccddb7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768914255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1768914255
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3007169036
Short name T990
Test name
Test status
Simulation time 454675388 ps
CPU time 1.7 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:38 PM PDT 24
Peak memory 205284 kb
Host smart-f3b9381a-66d5-48df-b0bb-7019ac3922ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007169036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3007169036
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3679688976
Short name T999
Test name
Test status
Simulation time 633175514 ps
CPU time 3.01 seconds
Started Jul 05 04:28:13 PM PDT 24
Finished Jul 05 04:28:29 PM PDT 24
Peak memory 213828 kb
Host smart-03de3764-e67f-457e-812a-3519a0bf9a0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679688976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3679688976
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2243528323
Short name T943
Test name
Test status
Simulation time 193454194 ps
CPU time 4.64 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:26 PM PDT 24
Peak memory 214220 kb
Host smart-f84d6f85-76d3-431b-abd5-5bc93dc667de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243528323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2243528323
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.850704894
Short name T944
Test name
Test status
Simulation time 73861150 ps
CPU time 2.7 seconds
Started Jul 05 04:28:19 PM PDT 24
Finished Jul 05 04:28:35 PM PDT 24
Peak memory 213988 kb
Host smart-a33fee8a-2022-4261-a638-a02b63b0842b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850704894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.850704894
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.458585655
Short name T977
Test name
Test status
Simulation time 43468551 ps
CPU time 0.69 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205156 kb
Host smart-d187833e-c44e-422c-87f3-401e6a867043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458585655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.458585655
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1995611259
Short name T968
Test name
Test status
Simulation time 33147990 ps
CPU time 0.75 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205208 kb
Host smart-b6d2d485-dcc9-42c9-94b7-ec13fc944821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995611259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1995611259
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2695533959
Short name T1062
Test name
Test status
Simulation time 28090789 ps
CPU time 0.67 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 205208 kb
Host smart-25aaddcf-eab2-4574-9c1a-de768bcd5ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695533959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2695533959
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.369677304
Short name T1065
Test name
Test status
Simulation time 9755010 ps
CPU time 0.82 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 205140 kb
Host smart-d13a3eb1-d992-4fa9-9d99-1b5d86f17d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369677304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.369677304
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.587021830
Short name T940
Test name
Test status
Simulation time 12551172 ps
CPU time 0.73 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 205200 kb
Host smart-93e22581-adc2-4e46-b8cd-9f9757f0f6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587021830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.587021830
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2502474349
Short name T985
Test name
Test status
Simulation time 28100493 ps
CPU time 0.82 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 205216 kb
Host smart-59008f38-8b4b-4621-8c76-6292b8baca4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502474349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2502474349
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1289803858
Short name T966
Test name
Test status
Simulation time 35420656 ps
CPU time 0.7 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 205216 kb
Host smart-d024bade-649e-4ab8-b558-d16cef68b438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289803858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1289803858
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.939477334
Short name T919
Test name
Test status
Simulation time 10334374 ps
CPU time 0.74 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205128 kb
Host smart-b1fcb0f5-0b93-4deb-ba8b-7311cff7d884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939477334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.939477334
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.242961939
Short name T1012
Test name
Test status
Simulation time 9872015 ps
CPU time 0.69 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:37 PM PDT 24
Peak memory 205204 kb
Host smart-58dc4926-8645-42cf-84f6-b7152d25b3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242961939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.242961939
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2747544847
Short name T1074
Test name
Test status
Simulation time 42042624 ps
CPU time 0.71 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 205132 kb
Host smart-1defecf1-1310-45cb-9990-283964476565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747544847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2747544847
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3483634025
Short name T1039
Test name
Test status
Simulation time 560805061 ps
CPU time 9.71 seconds
Started Jul 05 04:28:43 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 205328 kb
Host smart-b2c4b513-fc8c-48f8-997c-8e59155bc565
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483634025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
483634025
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2259976215
Short name T1042
Test name
Test status
Simulation time 5842581580 ps
CPU time 16.63 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 205484 kb
Host smart-2d25894d-d710-44d8-b8c0-a7b606df773f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259976215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
259976215
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.856900741
Short name T1010
Test name
Test status
Simulation time 62542776 ps
CPU time 1.19 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:32 PM PDT 24
Peak memory 205328 kb
Host smart-66f2684b-f13d-4a0a-b6bc-4b254fa16d3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856900741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.856900741
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1536130861
Short name T1033
Test name
Test status
Simulation time 60888807 ps
CPU time 1.61 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:54 PM PDT 24
Peak memory 217700 kb
Host smart-0b1abeca-8c7c-420d-a347-f0b89c1f09cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536130861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1536130861
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1058596125
Short name T963
Test name
Test status
Simulation time 116438919 ps
CPU time 1.23 seconds
Started Jul 05 04:28:37 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 205312 kb
Host smart-04c96a47-ae2c-4154-873d-3056b1faa100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058596125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1058596125
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3042711582
Short name T1068
Test name
Test status
Simulation time 36566880 ps
CPU time 0.72 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:17 PM PDT 24
Peak memory 205160 kb
Host smart-d86ed10d-8873-42fe-9875-49adfcbeb44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042711582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3042711582
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1503423280
Short name T146
Test name
Test status
Simulation time 93543988 ps
CPU time 3.25 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205780 kb
Host smart-f4971137-eb98-475d-a9ee-7e5021792468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503423280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1503423280
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2055141488
Short name T981
Test name
Test status
Simulation time 88252428 ps
CPU time 1.77 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:32 PM PDT 24
Peak memory 213876 kb
Host smart-c53f54cb-0fde-4d4a-ba83-65256d42650f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055141488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2055141488
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2979675842
Short name T122
Test name
Test status
Simulation time 312681913 ps
CPU time 6.71 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:28 PM PDT 24
Peak memory 213892 kb
Host smart-cf0c0a4d-4524-4e19-9cb0-73a638ee13f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979675842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2979675842
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2266014141
Short name T935
Test name
Test status
Simulation time 281846779 ps
CPU time 2.14 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 213656 kb
Host smart-e1aa399b-1d2a-4d9b-831a-4d797752f720
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266014141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2266014141
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3574046688
Short name T923
Test name
Test status
Simulation time 81644784 ps
CPU time 3.38 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 213596 kb
Host smart-5e609f9f-1c07-4e45-a3ec-1369fa63476d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574046688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3574046688
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3751923321
Short name T922
Test name
Test status
Simulation time 48993643 ps
CPU time 0.74 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 205216 kb
Host smart-a0c2d5bd-502a-40fa-a6dc-78159cfe4ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751923321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3751923321
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2615831970
Short name T937
Test name
Test status
Simulation time 27825195 ps
CPU time 0.8 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 205216 kb
Host smart-871245d6-4320-4633-be33-10069a1a63b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615831970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2615831970
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2375143018
Short name T959
Test name
Test status
Simulation time 51015804 ps
CPU time 0.86 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 205216 kb
Host smart-65b70971-4a05-4ef4-a481-463b7a840a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375143018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2375143018
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3582453647
Short name T1018
Test name
Test status
Simulation time 50372086 ps
CPU time 0.69 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 205212 kb
Host smart-df8b8bf2-4f81-454b-89c6-ade24d6f7aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582453647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3582453647
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.933648818
Short name T950
Test name
Test status
Simulation time 35727013 ps
CPU time 0.81 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205176 kb
Host smart-83be68b4-dc07-447e-bceb-638db737eb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933648818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.933648818
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.525138977
Short name T955
Test name
Test status
Simulation time 21181565 ps
CPU time 0.71 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205136 kb
Host smart-441659cf-32f7-43af-a50e-0c499322d225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525138977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.525138977
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1242326313
Short name T995
Test name
Test status
Simulation time 8466033 ps
CPU time 0.71 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205248 kb
Host smart-fdbe38e5-3116-4a43-b45f-4eebdb6d1090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242326313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1242326313
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2142553004
Short name T978
Test name
Test status
Simulation time 59916174 ps
CPU time 0.75 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 205268 kb
Host smart-5f2c64f4-f3a9-416b-909a-f310dc13bdf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142553004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2142553004
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.940380223
Short name T939
Test name
Test status
Simulation time 17795803 ps
CPU time 0.72 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205208 kb
Host smart-1e20c0cb-d370-4bc9-8cc4-a0ad0f28d11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940380223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.940380223
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4216590165
Short name T921
Test name
Test status
Simulation time 74803800 ps
CPU time 0.77 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 205132 kb
Host smart-5b64bf7e-a63a-445c-957f-686117e85002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216590165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.4216590165
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4266067026
Short name T1046
Test name
Test status
Simulation time 138208584 ps
CPU time 4.18 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205380 kb
Host smart-84e8433f-c12c-4fab-b6c5-66a8985e7783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266067026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
266067026
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3499201222
Short name T982
Test name
Test status
Simulation time 1113058408 ps
CPU time 16.78 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 205412 kb
Host smart-12329714-f7c1-409b-8d24-5b794b5afc1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499201222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
499201222
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3095050037
Short name T212
Test name
Test status
Simulation time 38559592 ps
CPU time 1.48 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205324 kb
Host smart-fc100cce-7bc9-4a75-bd3f-1aa38d7fa4e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095050037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
095050037
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3658299136
Short name T1069
Test name
Test status
Simulation time 197450514 ps
CPU time 1.17 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:42 PM PDT 24
Peak memory 205476 kb
Host smart-f692eca1-b2b6-44de-bdc3-92e5525ec5d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658299136 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3658299136
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3762316461
Short name T145
Test name
Test status
Simulation time 14051209 ps
CPU time 1.08 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 205384 kb
Host smart-2f270dc4-f9b4-498a-b071-aa4cd9c6593d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762316461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3762316461
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2795564229
Short name T986
Test name
Test status
Simulation time 15625360 ps
CPU time 0.86 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205296 kb
Host smart-9ede1e6f-a34d-45c7-95b4-a61edb36886c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795564229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2795564229
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4014895368
Short name T141
Test name
Test status
Simulation time 150074873 ps
CPU time 2.43 seconds
Started Jul 05 04:28:25 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 213616 kb
Host smart-bed2a043-8ccc-4d1d-b1f5-2c6604b4c414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014895368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4014895368
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2788550931
Short name T1021
Test name
Test status
Simulation time 299581248 ps
CPU time 1.78 seconds
Started Jul 05 04:28:19 PM PDT 24
Finished Jul 05 04:28:34 PM PDT 24
Peak memory 213840 kb
Host smart-6e4d8a81-ec53-47ac-a966-f678e2e60ebb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788550931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2788550931
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.642996559
Short name T1043
Test name
Test status
Simulation time 3939907270 ps
CPU time 11.04 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 221048 kb
Host smart-e33c7f6d-848a-4184-aeec-7a4e77351f33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642996559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.642996559
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2778445461
Short name T1049
Test name
Test status
Simulation time 297451998 ps
CPU time 2.08 seconds
Started Jul 05 04:28:26 PM PDT 24
Finished Jul 05 04:28:42 PM PDT 24
Peak memory 213584 kb
Host smart-c0e72bec-ea42-4d98-98ad-2fb8e47c1cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778445461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2778445461
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1349442696
Short name T1019
Test name
Test status
Simulation time 36447414 ps
CPU time 0.78 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 205136 kb
Host smart-7f8901c9-8efa-4141-91f1-aa6db7e99d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349442696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1349442696
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3361747162
Short name T993
Test name
Test status
Simulation time 10815714 ps
CPU time 0.68 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:47 PM PDT 24
Peak memory 205068 kb
Host smart-d0225bd0-dc70-46df-a391-5421387ed959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361747162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3361747162
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1841796951
Short name T1055
Test name
Test status
Simulation time 9130111 ps
CPU time 0.83 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 205216 kb
Host smart-b19c4f5c-b233-4e1b-8706-b6d7a9e1c4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841796951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1841796951
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.240329481
Short name T936
Test name
Test status
Simulation time 21096596 ps
CPU time 0.71 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 205192 kb
Host smart-4c50fc12-807d-4be7-b629-63bd1276f838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240329481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.240329481
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3136921492
Short name T1005
Test name
Test status
Simulation time 18942715 ps
CPU time 0.82 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:54 PM PDT 24
Peak memory 205200 kb
Host smart-04405cf5-5f14-4632-8d58-fb3176385b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136921492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3136921492
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.544194419
Short name T952
Test name
Test status
Simulation time 41917617 ps
CPU time 0.74 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 205220 kb
Host smart-fed43fd9-58dc-4211-9a7d-afa66089dcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544194419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.544194419
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1191448102
Short name T942
Test name
Test status
Simulation time 42558178 ps
CPU time 0.85 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 205188 kb
Host smart-ab4687a0-c3e0-41c3-9748-604843d1223a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191448102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1191448102
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3183760566
Short name T1030
Test name
Test status
Simulation time 37060130 ps
CPU time 0.68 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 205136 kb
Host smart-c84236a9-7faf-4698-beb7-19e2ebb3b876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183760566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3183760566
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1463996437
Short name T956
Test name
Test status
Simulation time 39663890 ps
CPU time 0.72 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 205204 kb
Host smart-4123a5db-2bd6-4855-90af-c85ce650afd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463996437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1463996437
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.735908110
Short name T997
Test name
Test status
Simulation time 16443792 ps
CPU time 0.71 seconds
Started Jul 05 04:28:17 PM PDT 24
Finished Jul 05 04:28:31 PM PDT 24
Peak memory 205168 kb
Host smart-075d0040-88c2-4fa3-a461-f07f41d129fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735908110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.735908110
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.508200189
Short name T155
Test name
Test status
Simulation time 32871418 ps
CPU time 1.28 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 205332 kb
Host smart-b0b70431-b7e2-4578-b9a6-854e318b43e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508200189 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.508200189
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2679358750
Short name T1016
Test name
Test status
Simulation time 55452476 ps
CPU time 1.25 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205360 kb
Host smart-5b0eac2a-06a2-4141-874f-83c669c3ec18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679358750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2679358750
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2635337318
Short name T1058
Test name
Test status
Simulation time 100177000 ps
CPU time 0.7 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 205096 kb
Host smart-e8856092-c1ae-4243-8f51-eadea1db2ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635337318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2635337318
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.817994193
Short name T1007
Test name
Test status
Simulation time 91640108 ps
CPU time 2.13 seconds
Started Jul 05 04:28:10 PM PDT 24
Finished Jul 05 04:28:24 PM PDT 24
Peak memory 205376 kb
Host smart-63c309b7-430e-4061-9c03-603a2385cc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817994193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.817994193
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1927786481
Short name T1031
Test name
Test status
Simulation time 110126657 ps
CPU time 2.66 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:46 PM PDT 24
Peak memory 213768 kb
Host smart-908db53b-4570-49d2-95ae-733a03dce5f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927786481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1927786481
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.968234674
Short name T964
Test name
Test status
Simulation time 151058735 ps
CPU time 5.85 seconds
Started Jul 05 04:28:38 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 213904 kb
Host smart-5e16cd52-8dc7-4450-9cc5-5e3093fb9546
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968234674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.968234674
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.927325236
Short name T954
Test name
Test status
Simulation time 253362202 ps
CPU time 1.83 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 213580 kb
Host smart-6b29afd3-fb7b-40c0-b64d-9bbc0f29cde4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927325236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.927325236
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1327463109
Short name T160
Test name
Test status
Simulation time 191885426 ps
CPU time 3.05 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 213656 kb
Host smart-0e17030f-c581-4818-9500-1bd4c6b9b8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327463109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1327463109
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.476800172
Short name T1052
Test name
Test status
Simulation time 196596714 ps
CPU time 2.18 seconds
Started Jul 05 04:28:35 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 213676 kb
Host smart-48cbbf20-7dd1-41dd-902c-18d2859d18d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476800172 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.476800172
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1552256195
Short name T969
Test name
Test status
Simulation time 48417981 ps
CPU time 1.17 seconds
Started Jul 05 04:28:08 PM PDT 24
Finished Jul 05 04:28:20 PM PDT 24
Peak memory 205384 kb
Host smart-f0434a7c-4e2f-445f-aa2c-d3d69b7297b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552256195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1552256195
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4181924733
Short name T1023
Test name
Test status
Simulation time 13170172 ps
CPU time 0.67 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 205204 kb
Host smart-1b6af5ae-f2da-4947-b74f-d213189f48b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181924733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4181924733
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.887348930
Short name T1072
Test name
Test status
Simulation time 149957987 ps
CPU time 2.66 seconds
Started Jul 05 04:28:43 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 205352 kb
Host smart-515df019-f91a-4c37-8649-f2581864b25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887348930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.887348930
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.807248325
Short name T998
Test name
Test status
Simulation time 143231938 ps
CPU time 1.55 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 213896 kb
Host smart-213814be-fd59-4ec1-84d0-8095e413cf75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807248325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.807248325
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2779804302
Short name T1075
Test name
Test status
Simulation time 425803786 ps
CPU time 2.84 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:49 PM PDT 24
Peak memory 213624 kb
Host smart-8486bc4c-1284-4232-9072-11e8168e6f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779804302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2779804302
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4021393469
Short name T1040
Test name
Test status
Simulation time 83602856 ps
CPU time 1.52 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:24 PM PDT 24
Peak memory 213732 kb
Host smart-fec83453-88cf-4a3a-8c23-ac635348b44d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021393469 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4021393469
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2572422860
Short name T1041
Test name
Test status
Simulation time 17596353 ps
CPU time 1 seconds
Started Jul 05 04:28:13 PM PDT 24
Finished Jul 05 04:28:27 PM PDT 24
Peak memory 205388 kb
Host smart-b24943f1-9750-45a4-9639-dfc270cd0f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572422860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2572422860
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2525213100
Short name T957
Test name
Test status
Simulation time 11399623 ps
CPU time 0.73 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 205200 kb
Host smart-e6d4f90b-50fd-4eb5-9875-4747ee958aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525213100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2525213100
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3657073871
Short name T1064
Test name
Test status
Simulation time 67277253 ps
CPU time 2.27 seconds
Started Jul 05 04:28:21 PM PDT 24
Finished Jul 05 04:28:36 PM PDT 24
Peak memory 205404 kb
Host smart-641bbaa1-0c11-4280-9c87-bca7feeb0762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657073871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3657073871
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2189045641
Short name T948
Test name
Test status
Simulation time 160793667 ps
CPU time 1.47 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 213932 kb
Host smart-e1d59bff-37a2-4138-a9f4-7b9fc87b093a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189045641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2189045641
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1183357979
Short name T1038
Test name
Test status
Simulation time 693254179 ps
CPU time 6.65 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 219612 kb
Host smart-3068d9e6-801a-48bd-84b6-5f288fc1c20f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183357979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1183357979
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4043647957
Short name T927
Test name
Test status
Simulation time 24832415 ps
CPU time 1.67 seconds
Started Jul 05 04:28:24 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 221708 kb
Host smart-729a4eb6-ba4b-47ba-b17f-502782380d32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043647957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4043647957
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.600449332
Short name T932
Test name
Test status
Simulation time 97400813 ps
CPU time 2.92 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:28:38 PM PDT 24
Peak memory 213640 kb
Host smart-ad8c51bf-3a9d-42b2-a0dc-03c4884e7ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600449332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
600449332
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4294122332
Short name T971
Test name
Test status
Simulation time 24391591 ps
CPU time 1.14 seconds
Started Jul 05 04:28:25 PM PDT 24
Finished Jul 05 04:28:43 PM PDT 24
Peak memory 205376 kb
Host smart-f7b803b0-7ee4-4463-85ad-75d04d301eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294122332 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4294122332
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.225895492
Short name T1028
Test name
Test status
Simulation time 16336474 ps
CPU time 0.96 seconds
Started Jul 05 04:28:13 PM PDT 24
Finished Jul 05 04:28:27 PM PDT 24
Peak memory 205304 kb
Host smart-25ee8754-71fa-4fa4-8028-9fa4e089b7b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225895492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.225895492
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.52781642
Short name T960
Test name
Test status
Simulation time 8155769 ps
CPU time 0.68 seconds
Started Jul 05 04:28:10 PM PDT 24
Finished Jul 05 04:28:23 PM PDT 24
Peak memory 205192 kb
Host smart-19bf4a1f-bfaf-43b1-87d5-da7baace6343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52781642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.52781642
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1018152780
Short name T962
Test name
Test status
Simulation time 125813869 ps
CPU time 2.28 seconds
Started Jul 05 04:28:18 PM PDT 24
Finished Jul 05 04:28:33 PM PDT 24
Peak memory 205384 kb
Host smart-4bf1b12e-cb7e-4c38-be52-35d8864f7a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018152780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1018152780
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1187762332
Short name T1015
Test name
Test status
Simulation time 127657912 ps
CPU time 3.81 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:28:38 PM PDT 24
Peak memory 213940 kb
Host smart-4f9afcd7-9514-4ada-a9ec-700915446528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187762332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1187762332
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3681353653
Short name T114
Test name
Test status
Simulation time 88293844 ps
CPU time 3.62 seconds
Started Jul 05 04:28:12 PM PDT 24
Finished Jul 05 04:28:29 PM PDT 24
Peak memory 219884 kb
Host smart-00f101d8-228c-4686-89ff-c58cf059cdd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681353653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3681353653
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3653767293
Short name T925
Test name
Test status
Simulation time 104598151 ps
CPU time 1.94 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 213608 kb
Host smart-ea26335f-1ed4-4226-88ca-208b3b888ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653767293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3653767293
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1426178062
Short name T172
Test name
Test status
Simulation time 372979171 ps
CPU time 4.64 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:45 PM PDT 24
Peak memory 213652 kb
Host smart-46062802-8236-49b8-b7f2-9879d5648fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426178062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1426178062
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1651007226
Short name T996
Test name
Test status
Simulation time 122309512 ps
CPU time 1.22 seconds
Started Jul 05 04:28:14 PM PDT 24
Finished Jul 05 04:28:28 PM PDT 24
Peak memory 213592 kb
Host smart-23e393bb-47ed-4156-9dd7-65fd3da4bdd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651007226 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1651007226
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2672029996
Short name T1029
Test name
Test status
Simulation time 117861605 ps
CPU time 1.49 seconds
Started Jul 05 04:28:19 PM PDT 24
Finished Jul 05 04:28:34 PM PDT 24
Peak memory 205332 kb
Host smart-81433114-a309-4bbb-b8de-fefd447c94b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672029996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2672029996
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2678387227
Short name T976
Test name
Test status
Simulation time 24360613 ps
CPU time 0.84 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:08 PM PDT 24
Peak memory 205128 kb
Host smart-5d7c0ce1-3ae7-4b76-81a0-3e66cb9bc496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678387227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2678387227
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2343010324
Short name T1002
Test name
Test status
Simulation time 475442864 ps
CPU time 3.27 seconds
Started Jul 05 04:28:23 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 205800 kb
Host smart-64013caf-59e7-40e0-ad7c-6f431c656b8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343010324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2343010324
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1007758789
Short name T1006
Test name
Test status
Simulation time 87435004 ps
CPU time 2.83 seconds
Started Jul 05 04:28:27 PM PDT 24
Finished Jul 05 04:28:44 PM PDT 24
Peak memory 213872 kb
Host smart-aad974f7-7381-4434-b633-9b6e53dae056
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007758789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1007758789
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.416855303
Short name T980
Test name
Test status
Simulation time 337872540 ps
CPU time 4.43 seconds
Started Jul 05 04:28:21 PM PDT 24
Finished Jul 05 04:28:39 PM PDT 24
Peak memory 213880 kb
Host smart-af725460-5f65-4937-aada-b4bde6227216
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416855303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.416855303
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.213610117
Short name T1066
Test name
Test status
Simulation time 282384584 ps
CPU time 3.57 seconds
Started Jul 05 04:28:14 PM PDT 24
Finished Jul 05 04:28:31 PM PDT 24
Peak memory 216664 kb
Host smart-1d19d39a-0d14-4564-b19a-137b186a07c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213610117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.213610117
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.770225654
Short name T569
Test name
Test status
Simulation time 16391482 ps
CPU time 0.72 seconds
Started Jul 05 05:10:32 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 205948 kb
Host smart-c82dcd5d-e849-40fd-a9d3-36e8138a06b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770225654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.770225654
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3404409728
Short name T715
Test name
Test status
Simulation time 194224558 ps
CPU time 2.69 seconds
Started Jul 05 05:10:29 PM PDT 24
Finished Jul 05 05:10:32 PM PDT 24
Peak memory 208900 kb
Host smart-3d55e898-0bd7-4e64-b184-3c70f7e34fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404409728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3404409728
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1056117668
Short name T262
Test name
Test status
Simulation time 396683275 ps
CPU time 4.79 seconds
Started Jul 05 05:10:25 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 208160 kb
Host smart-37618616-441f-4408-87c0-368f94660870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056117668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1056117668
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2574630028
Short name T95
Test name
Test status
Simulation time 263071160 ps
CPU time 6.78 seconds
Started Jul 05 05:10:28 PM PDT 24
Finished Jul 05 05:10:36 PM PDT 24
Peak memory 214216 kb
Host smart-fdc0a009-3637-4721-97d4-ed498036fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574630028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2574630028
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.55395981
Short name T589
Test name
Test status
Simulation time 457787614 ps
CPU time 5.71 seconds
Started Jul 05 05:10:27 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 209772 kb
Host smart-1170f00a-632e-4d76-aa8f-fb2d70813860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55395981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.55395981
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1170835777
Short name T404
Test name
Test status
Simulation time 800484613 ps
CPU time 23.62 seconds
Started Jul 05 05:10:23 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 218504 kb
Host smart-19cba985-3277-415d-9999-9fd8c8bd7425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170835777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1170835777
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3297765507
Short name T208
Test name
Test status
Simulation time 36406216 ps
CPU time 2.13 seconds
Started Jul 05 05:10:22 PM PDT 24
Finished Jul 05 05:10:25 PM PDT 24
Peak memory 206912 kb
Host smart-05146863-99ba-461d-aa59-b50388845b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297765507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3297765507
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3712267330
Short name T518
Test name
Test status
Simulation time 3551576510 ps
CPU time 9.67 seconds
Started Jul 05 05:10:23 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 209080 kb
Host smart-dff5daf9-a344-4f49-9453-d50669c0d015
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712267330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3712267330
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3927115424
Short name T724
Test name
Test status
Simulation time 65676515 ps
CPU time 2.41 seconds
Started Jul 05 05:10:24 PM PDT 24
Finished Jul 05 05:10:27 PM PDT 24
Peak memory 207636 kb
Host smart-cd6f3d40-0420-48f7-983e-c5f2e86a5ac2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927115424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3927115424
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4249006713
Short name T855
Test name
Test status
Simulation time 149804534 ps
CPU time 2.76 seconds
Started Jul 05 05:10:23 PM PDT 24
Finished Jul 05 05:10:27 PM PDT 24
Peak memory 208496 kb
Host smart-85bd4aa5-5dfe-4c42-82c5-afe24c848739
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249006713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4249006713
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1044861259
Short name T596
Test name
Test status
Simulation time 198702636 ps
CPU time 2.6 seconds
Started Jul 05 05:10:27 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 209308 kb
Host smart-4ea42519-33c9-433a-ac7e-f2fa98487e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044861259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1044861259
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1788437479
Short name T432
Test name
Test status
Simulation time 219977472 ps
CPU time 3.07 seconds
Started Jul 05 05:10:19 PM PDT 24
Finished Jul 05 05:10:23 PM PDT 24
Peak memory 208348 kb
Host smart-0da92265-6557-45f2-9584-8950b5b6e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788437479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1788437479
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2861746317
Short name T240
Test name
Test status
Simulation time 623757056 ps
CPU time 23.03 seconds
Started Jul 05 05:10:28 PM PDT 24
Finished Jul 05 05:10:52 PM PDT 24
Peak memory 222476 kb
Host smart-62e068bc-51cf-4021-ae31-d63fd812eec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861746317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2861746317
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1300370281
Short name T378
Test name
Test status
Simulation time 345367663 ps
CPU time 4.49 seconds
Started Jul 05 05:10:28 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 210232 kb
Host smart-7f5ced69-db33-447e-81f6-5988ab85aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300370281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1300370281
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1804359631
Short name T529
Test name
Test status
Simulation time 105831826 ps
CPU time 2.75 seconds
Started Jul 05 05:10:29 PM PDT 24
Finished Jul 05 05:10:32 PM PDT 24
Peak memory 209728 kb
Host smart-5a4d73fb-374e-43d1-b6de-b016d3de565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804359631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1804359631
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3264467684
Short name T681
Test name
Test status
Simulation time 7844336 ps
CPU time 0.76 seconds
Started Jul 05 05:10:38 PM PDT 24
Finished Jul 05 05:10:40 PM PDT 24
Peak memory 206004 kb
Host smart-30f0e501-14d9-420d-9356-4325b7aaa6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264467684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3264467684
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1574958753
Short name T467
Test name
Test status
Simulation time 236987889 ps
CPU time 2.61 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:36 PM PDT 24
Peak memory 207156 kb
Host smart-731a68f0-7f03-4cfe-bfbc-8d84a6619c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574958753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1574958753
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1115250911
Short name T99
Test name
Test status
Simulation time 63632359 ps
CPU time 3.47 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:37 PM PDT 24
Peak memory 210188 kb
Host smart-940d5d23-a9b9-478e-8135-527df6f24c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115250911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1115250911
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1137637572
Short name T90
Test name
Test status
Simulation time 140549035 ps
CPU time 4.75 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 222368 kb
Host smart-4c4cb78f-c803-45d2-a589-a294f1d4cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137637572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1137637572
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4247785692
Short name T234
Test name
Test status
Simulation time 135999903 ps
CPU time 3.56 seconds
Started Jul 05 05:10:34 PM PDT 24
Finished Jul 05 05:10:38 PM PDT 24
Peak memory 208480 kb
Host smart-af4919c7-f5b8-4f3b-b6d2-ce99487bd502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247785692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4247785692
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4181439572
Short name T912
Test name
Test status
Simulation time 30228318 ps
CPU time 2.47 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:36 PM PDT 24
Peak memory 207692 kb
Host smart-26cb5529-c199-40b0-ab45-6fdaa09f5a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181439572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4181439572
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1006002416
Short name T12
Test name
Test status
Simulation time 642579893 ps
CPU time 13.3 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:54 PM PDT 24
Peak memory 232156 kb
Host smart-db61c02b-f47f-4871-9f84-67cd0532437f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006002416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1006002416
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.14886345
Short name T215
Test name
Test status
Simulation time 280125653 ps
CPU time 3.51 seconds
Started Jul 05 05:10:33 PM PDT 24
Finished Jul 05 05:10:38 PM PDT 24
Peak memory 208764 kb
Host smart-280f56c9-3997-46ba-ae53-d9ed03ce2d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14886345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.14886345
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4277015257
Short name T281
Test name
Test status
Simulation time 96376465 ps
CPU time 4.14 seconds
Started Jul 05 05:10:35 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 208844 kb
Host smart-ba49194d-8656-4f7a-b112-ee19e8503601
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277015257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4277015257
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1090885209
Short name T907
Test name
Test status
Simulation time 116657759 ps
CPU time 2.45 seconds
Started Jul 05 05:10:31 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 208816 kb
Host smart-848473ed-50a6-48d9-9e43-9fb2e9088293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090885209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1090885209
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1280679882
Short name T553
Test name
Test status
Simulation time 68514395 ps
CPU time 2.47 seconds
Started Jul 05 05:10:32 PM PDT 24
Finished Jul 05 05:10:36 PM PDT 24
Peak memory 208428 kb
Host smart-4aef49d0-447f-466b-87cb-78e76a0cd3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280679882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1280679882
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.782594274
Short name T747
Test name
Test status
Simulation time 917926566 ps
CPU time 18.33 seconds
Started Jul 05 05:10:41 PM PDT 24
Finished Jul 05 05:11:00 PM PDT 24
Peak memory 222564 kb
Host smart-415f686a-d261-4cce-babd-39ee105fd4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782594274 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.782594274
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3530099679
Short name T284
Test name
Test status
Simulation time 356655065 ps
CPU time 4.02 seconds
Started Jul 05 05:10:34 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 209680 kb
Host smart-e957d941-7694-4386-ac50-83d02e722eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530099679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3530099679
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2025123183
Short name T204
Test name
Test status
Simulation time 209225952 ps
CPU time 2.27 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:43 PM PDT 24
Peak memory 209952 kb
Host smart-643121a9-4932-4802-a2b8-805cf77e4b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025123183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2025123183
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1829760471
Short name T698
Test name
Test status
Simulation time 42470371 ps
CPU time 0.74 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 205952 kb
Host smart-8b22e859-6b78-4657-a9f9-15be447b7873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829760471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1829760471
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3632015512
Short name T911
Test name
Test status
Simulation time 81904800 ps
CPU time 2.22 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 218112 kb
Host smart-89f00746-4af9-48e0-88cd-8b040b08e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632015512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3632015512
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2976252028
Short name T537
Test name
Test status
Simulation time 128384206 ps
CPU time 2.8 seconds
Started Jul 05 05:11:22 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 214260 kb
Host smart-8393d4cf-f8da-43ee-af4c-8538ae91a8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976252028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2976252028
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2924602585
Short name T100
Test name
Test status
Simulation time 1625191359 ps
CPU time 44.88 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:12:11 PM PDT 24
Peak memory 214328 kb
Host smart-a2a0da91-499c-44c9-81d3-25e2c77cd2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924602585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2924602585
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3085278939
Short name T48
Test name
Test status
Simulation time 888040222 ps
CPU time 3.71 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 220340 kb
Host smart-09f152d6-9a67-477e-82d7-4e2079b30acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085278939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3085278939
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1745656633
Short name T478
Test name
Test status
Simulation time 29007194 ps
CPU time 2.13 seconds
Started Jul 05 05:11:21 PM PDT 24
Finished Jul 05 05:11:23 PM PDT 24
Peak memory 207536 kb
Host smart-10022b25-c043-4c79-a770-e7253c5cacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745656633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1745656633
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3134171828
Short name T219
Test name
Test status
Simulation time 708731582 ps
CPU time 23.02 seconds
Started Jul 05 05:11:19 PM PDT 24
Finished Jul 05 05:11:43 PM PDT 24
Peak memory 208768 kb
Host smart-7f0b6b60-df00-4004-aeba-513501d46469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134171828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3134171828
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1358113678
Short name T667
Test name
Test status
Simulation time 168788876 ps
CPU time 4.58 seconds
Started Jul 05 05:11:19 PM PDT 24
Finished Jul 05 05:11:24 PM PDT 24
Peak memory 208772 kb
Host smart-67cc9b5a-9c66-41e1-b489-2672a0d21347
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358113678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1358113678
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2144392448
Short name T827
Test name
Test status
Simulation time 120200590 ps
CPU time 2.45 seconds
Started Jul 05 05:11:22 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 206980 kb
Host smart-6d33620e-1a54-4210-8442-860720e239e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144392448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2144392448
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3876713109
Short name T501
Test name
Test status
Simulation time 126495019 ps
CPU time 3.14 seconds
Started Jul 05 05:11:19 PM PDT 24
Finished Jul 05 05:11:23 PM PDT 24
Peak memory 207028 kb
Host smart-84efcd28-cf0f-445f-a169-e43abdf7d5c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876713109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3876713109
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.498151634
Short name T546
Test name
Test status
Simulation time 141848665 ps
CPU time 2.27 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:30 PM PDT 24
Peak memory 215244 kb
Host smart-18474d49-4b54-4968-9562-1483f3d27a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498151634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.498151634
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1301450586
Short name T675
Test name
Test status
Simulation time 131614279 ps
CPU time 3.16 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 208400 kb
Host smart-6e8dc1ff-ff32-4801-971c-6c31c5ff0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301450586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1301450586
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.354610369
Short name T187
Test name
Test status
Simulation time 1210393063 ps
CPU time 11.02 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:37 PM PDT 24
Peak memory 218152 kb
Host smart-84f725a8-97bb-4132-97db-6549f62b65ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354610369 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.354610369
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3603382991
Short name T377
Test name
Test status
Simulation time 917661281 ps
CPU time 7.68 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:34 PM PDT 24
Peak memory 218500 kb
Host smart-3a7cbb40-4256-44cb-81c4-1283c1111f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603382991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3603382991
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2161246136
Short name T197
Test name
Test status
Simulation time 165721352 ps
CPU time 2.78 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 210068 kb
Host smart-15321d33-7510-4da2-9a5c-b15f0da4dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161246136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2161246136
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3648998856
Short name T449
Test name
Test status
Simulation time 36399894 ps
CPU time 0.7 seconds
Started Jul 05 05:11:36 PM PDT 24
Finished Jul 05 05:11:37 PM PDT 24
Peak memory 205920 kb
Host smart-f781bb12-f9ac-4515-b72c-4578d9d8cf84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648998856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3648998856
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1912169553
Short name T900
Test name
Test status
Simulation time 297425571 ps
CPU time 2.15 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 209744 kb
Host smart-b3fa0e21-16e9-4505-8fc7-d313fa1fc24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912169553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1912169553
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.499455206
Short name T540
Test name
Test status
Simulation time 61991027 ps
CPU time 3.67 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 219124 kb
Host smart-68335c34-f51f-487d-b2f2-696fceb5f1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499455206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.499455206
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1875499497
Short name T362
Test name
Test status
Simulation time 123520305 ps
CPU time 4.02 seconds
Started Jul 05 05:11:26 PM PDT 24
Finished Jul 05 05:11:32 PM PDT 24
Peak memory 208824 kb
Host smart-31d7b054-3836-40ec-ada6-4d9eb729ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875499497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1875499497
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.658268727
Short name T692
Test name
Test status
Simulation time 138843345 ps
CPU time 3.38 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 206916 kb
Host smart-58c13633-2ed7-4acd-aa2d-0983a01f4a1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658268727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.658268727
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4190241395
Short name T488
Test name
Test status
Simulation time 109574374 ps
CPU time 4 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 206932 kb
Host smart-04d8b37e-6b4a-413f-be61-2ca8d6e25e9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190241395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4190241395
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1578278389
Short name T318
Test name
Test status
Simulation time 24405585 ps
CPU time 2.1 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 209020 kb
Host smart-965ca33c-6911-4d4f-9931-3c89452d027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578278389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1578278389
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3474119374
Short name T879
Test name
Test status
Simulation time 70417040 ps
CPU time 3.01 seconds
Started Jul 05 05:11:27 PM PDT 24
Finished Jul 05 05:11:31 PM PDT 24
Peak memory 208160 kb
Host smart-247329bc-d388-4822-8dc4-34394cafce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474119374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3474119374
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1191156821
Short name T607
Test name
Test status
Simulation time 4750964788 ps
CPU time 96.11 seconds
Started Jul 05 05:11:33 PM PDT 24
Finished Jul 05 05:13:10 PM PDT 24
Peak memory 216380 kb
Host smart-dc32f08e-3d31-469f-88bd-cabe5ccf7bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191156821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1191156821
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2929362383
Short name T504
Test name
Test status
Simulation time 46662373 ps
CPU time 3.31 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 214284 kb
Host smart-8aa997ec-533a-4e18-9e09-ccd176e96a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929362383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2929362383
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3559775164
Short name T670
Test name
Test status
Simulation time 103685678 ps
CPU time 2.48 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 210312 kb
Host smart-dcd96daa-339d-497d-9afe-c02a7f1f0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559775164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3559775164
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3636252747
Short name T834
Test name
Test status
Simulation time 25569707 ps
CPU time 0.72 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:36 PM PDT 24
Peak memory 206016 kb
Host smart-c8bba912-9c89-4546-8b27-3dfeaaa2767c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636252747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3636252747
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1815123301
Short name T416
Test name
Test status
Simulation time 5136383722 ps
CPU time 79.88 seconds
Started Jul 05 05:11:31 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 215844 kb
Host smart-c04bb3aa-7f70-4c43-85ad-701addc503f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815123301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1815123301
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1787920170
Short name T32
Test name
Test status
Simulation time 125324582 ps
CPU time 2.98 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 222472 kb
Host smart-d8181a40-fa87-4967-9171-9aed596a82a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787920170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1787920170
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3360487246
Short name T597
Test name
Test status
Simulation time 24261257 ps
CPU time 1.53 seconds
Started Jul 05 05:11:36 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 206980 kb
Host smart-9c5d82c4-4713-4bcc-a219-cbe7a569c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360487246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3360487246
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2000995441
Short name T282
Test name
Test status
Simulation time 35479035 ps
CPU time 2.57 seconds
Started Jul 05 05:11:32 PM PDT 24
Finished Jul 05 05:11:35 PM PDT 24
Peak memory 221056 kb
Host smart-8b62765d-26de-4e68-926b-a0063caf9899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000995441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2000995441
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.445261736
Short name T353
Test name
Test status
Simulation time 199646255 ps
CPU time 3 seconds
Started Jul 05 05:11:32 PM PDT 24
Finished Jul 05 05:11:35 PM PDT 24
Peak memory 209088 kb
Host smart-d99270a6-5949-4a3f-8b76-8522249c9a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445261736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.445261736
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.4252628075
Short name T792
Test name
Test status
Simulation time 83285819 ps
CPU time 4.37 seconds
Started Jul 05 05:11:37 PM PDT 24
Finished Jul 05 05:11:42 PM PDT 24
Peak memory 207576 kb
Host smart-eecb3dc3-0d35-4abd-9c8a-c7c74ae52a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252628075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4252628075
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3297437177
Short name T679
Test name
Test status
Simulation time 558532217 ps
CPU time 4.58 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:40 PM PDT 24
Peak memory 208616 kb
Host smart-09c5b05c-edfd-4ab9-9f93-9a9779e55cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297437177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3297437177
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3654504656
Short name T885
Test name
Test status
Simulation time 145797660 ps
CPU time 4.31 seconds
Started Jul 05 05:11:32 PM PDT 24
Finished Jul 05 05:11:37 PM PDT 24
Peak memory 208792 kb
Host smart-419bb4aa-d4a6-4e70-9e02-5766e3069b78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654504656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3654504656
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2846333928
Short name T452
Test name
Test status
Simulation time 2685877745 ps
CPU time 23.75 seconds
Started Jul 05 05:11:37 PM PDT 24
Finished Jul 05 05:12:02 PM PDT 24
Peak memory 208076 kb
Host smart-3d237e49-8d73-4d78-9343-f54bbddabd25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846333928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2846333928
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.85317972
Short name T335
Test name
Test status
Simulation time 427006611 ps
CPU time 5.6 seconds
Started Jul 05 05:11:38 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 208136 kb
Host smart-679dc5a5-ba8f-4a2a-bfb9-c59527629065
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85317972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.85317972
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.592160575
Short name T84
Test name
Test status
Simulation time 63325363 ps
CPU time 3.36 seconds
Started Jul 05 05:11:37 PM PDT 24
Finished Jul 05 05:11:41 PM PDT 24
Peak memory 209616 kb
Host smart-a642ccfb-c203-48a7-a7fa-28eaed3b880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592160575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.592160575
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2123299727
Short name T903
Test name
Test status
Simulation time 215301241 ps
CPU time 4.39 seconds
Started Jul 05 05:11:31 PM PDT 24
Finished Jul 05 05:11:36 PM PDT 24
Peak memory 208064 kb
Host smart-1cf3a66c-528f-4dc7-a747-d2b3d9137630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123299727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2123299727
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2675887123
Short name T606
Test name
Test status
Simulation time 1466745429 ps
CPU time 13.27 seconds
Started Jul 05 05:11:34 PM PDT 24
Finished Jul 05 05:11:48 PM PDT 24
Peak memory 209492 kb
Host smart-77a84da9-2330-4cf4-b116-925265679166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675887123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2675887123
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1874917309
Short name T534
Test name
Test status
Simulation time 21513496 ps
CPU time 0.78 seconds
Started Jul 05 05:11:38 PM PDT 24
Finished Jul 05 05:11:39 PM PDT 24
Peak memory 206020 kb
Host smart-accf21d5-5cd0-4329-9545-9ef6b2a7269e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874917309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1874917309
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1062448200
Short name T10
Test name
Test status
Simulation time 308038304 ps
CPU time 2.3 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:42 PM PDT 24
Peak memory 222732 kb
Host smart-802f78cd-182b-477a-aee4-58eeec295fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062448200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1062448200
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3129158008
Short name T871
Test name
Test status
Simulation time 40175469 ps
CPU time 1.73 seconds
Started Jul 05 05:11:33 PM PDT 24
Finished Jul 05 05:11:35 PM PDT 24
Peak memory 208868 kb
Host smart-e38cc05e-0296-4837-85d3-36e4d9f556a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129158008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3129158008
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1044138239
Short name T94
Test name
Test status
Simulation time 534051446 ps
CPU time 9.47 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 209892 kb
Host smart-9f07306a-0d5e-47ac-b7b7-48c062146393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044138239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1044138239
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2154038677
Short name T785
Test name
Test status
Simulation time 605525264 ps
CPU time 6.31 seconds
Started Jul 05 05:11:43 PM PDT 24
Finished Jul 05 05:11:49 PM PDT 24
Peak memory 214160 kb
Host smart-f113c5fa-b5f9-4a80-81cd-a0512e400c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154038677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2154038677
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2750324284
Short name T402
Test name
Test status
Simulation time 300053100 ps
CPU time 3.91 seconds
Started Jul 05 05:11:33 PM PDT 24
Finished Jul 05 05:11:37 PM PDT 24
Peak memory 222508 kb
Host smart-ffd25391-3fbe-4e2a-9bc8-d2973eedc1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750324284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2750324284
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2546319645
Short name T585
Test name
Test status
Simulation time 136767728 ps
CPU time 5.62 seconds
Started Jul 05 05:11:34 PM PDT 24
Finished Jul 05 05:11:40 PM PDT 24
Peak memory 207436 kb
Host smart-7ebf1434-ee00-4e6e-b6af-d59b3bca8284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546319645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2546319645
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2715701791
Short name T494
Test name
Test status
Simulation time 107238056 ps
CPU time 3.59 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:39 PM PDT 24
Peak memory 206772 kb
Host smart-286d1fed-4bf8-4e82-bd6f-33d10ce4d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715701791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2715701791
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1505057404
Short name T297
Test name
Test status
Simulation time 354253844 ps
CPU time 8.44 seconds
Started Jul 05 05:11:35 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 209184 kb
Host smart-1b95e53c-fc47-44eb-81a6-974131d2fdd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505057404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1505057404
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1432503784
Short name T225
Test name
Test status
Simulation time 208677363 ps
CPU time 2.64 seconds
Started Jul 05 05:11:32 PM PDT 24
Finished Jul 05 05:11:35 PM PDT 24
Peak memory 206956 kb
Host smart-0e5ef526-1592-4766-88ba-33182aa856a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432503784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1432503784
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3153702600
Short name T229
Test name
Test status
Simulation time 270368150 ps
CPU time 3.29 seconds
Started Jul 05 05:11:36 PM PDT 24
Finished Jul 05 05:11:40 PM PDT 24
Peak memory 208564 kb
Host smart-face056b-97a0-4bfb-9e1d-96ab5f34cbe4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153702600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3153702600
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2654105265
Short name T721
Test name
Test status
Simulation time 83642562 ps
CPU time 3.53 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 214300 kb
Host smart-c13c0887-9a45-4297-8171-4a37b864b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654105265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2654105265
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1970505268
Short name T594
Test name
Test status
Simulation time 467258965 ps
CPU time 4.68 seconds
Started Jul 05 05:11:33 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 208708 kb
Host smart-87fb13b9-76cf-47d1-81f9-5dc1ed2b3c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970505268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1970505268
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3830758418
Short name T330
Test name
Test status
Simulation time 397152256 ps
CPU time 19.57 seconds
Started Jul 05 05:11:42 PM PDT 24
Finished Jul 05 05:12:02 PM PDT 24
Peak memory 222296 kb
Host smart-72e27dc5-2a5f-4f11-a5a3-7f7a84969d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830758418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3830758418
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3757932051
Short name T657
Test name
Test status
Simulation time 383676149 ps
CPU time 13.06 seconds
Started Jul 05 05:11:37 PM PDT 24
Finished Jul 05 05:11:51 PM PDT 24
Peak memory 218516 kb
Host smart-39a26d24-9d47-4637-b6db-b9a3de784071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757932051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3757932051
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1240815603
Short name T770
Test name
Test status
Simulation time 169048888 ps
CPU time 2.46 seconds
Started Jul 05 05:11:43 PM PDT 24
Finished Jul 05 05:11:46 PM PDT 24
Peak memory 210360 kb
Host smart-31df9014-f7d7-4777-b4d0-6a347ec3ee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240815603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1240815603
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3842374263
Short name T31
Test name
Test status
Simulation time 56378879 ps
CPU time 1.71 seconds
Started Jul 05 05:11:43 PM PDT 24
Finished Jul 05 05:11:46 PM PDT 24
Peak memory 214324 kb
Host smart-0df7e073-5ed0-424a-a7ef-cd93a693f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842374263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3842374263
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1814007961
Short name T551
Test name
Test status
Simulation time 621120438 ps
CPU time 5.98 seconds
Started Jul 05 05:11:38 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 209208 kb
Host smart-665f1cef-bda8-48aa-bc26-5d2c60011a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814007961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1814007961
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4277568335
Short name T344
Test name
Test status
Simulation time 24437166 ps
CPU time 1.67 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:42 PM PDT 24
Peak memory 214340 kb
Host smart-ef4a8b13-df6c-4788-9cae-04664e0f7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277568335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4277568335
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2419758806
Short name T703
Test name
Test status
Simulation time 127252961 ps
CPU time 2.02 seconds
Started Jul 05 05:11:42 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 220688 kb
Host smart-5747489e-46f3-4735-a74b-536590192776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419758806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2419758806
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3357930569
Short name T245
Test name
Test status
Simulation time 147782185 ps
CPU time 6.33 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:47 PM PDT 24
Peak memory 222472 kb
Host smart-f82a61dd-ea1f-4c41-a940-72507faf247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357930569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3357930569
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3775382829
Short name T710
Test name
Test status
Simulation time 319218396 ps
CPU time 8.79 seconds
Started Jul 05 05:11:38 PM PDT 24
Finished Jul 05 05:11:48 PM PDT 24
Peak memory 208996 kb
Host smart-4fb1efcf-ffb3-4747-9b98-3f672ada04d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775382829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3775382829
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2409402779
Short name T259
Test name
Test status
Simulation time 305720414 ps
CPU time 3.94 seconds
Started Jul 05 05:11:42 PM PDT 24
Finished Jul 05 05:11:47 PM PDT 24
Peak memory 207512 kb
Host smart-74f87e3a-c7a6-4104-b0c0-3282b252c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409402779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2409402779
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.215878641
Short name T735
Test name
Test status
Simulation time 555820936 ps
CPU time 7.67 seconds
Started Jul 05 05:11:38 PM PDT 24
Finished Jul 05 05:11:47 PM PDT 24
Peak memory 208516 kb
Host smart-64ae3f52-e8f5-4746-95e9-b2ab9a8c7c72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215878641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.215878641
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.393973761
Short name T910
Test name
Test status
Simulation time 96334614 ps
CPU time 3.21 seconds
Started Jul 05 05:11:41 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 206868 kb
Host smart-d391cf59-5660-4094-9c94-854088dad45a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393973761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.393973761
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4042051983
Short name T829
Test name
Test status
Simulation time 765992493 ps
CPU time 8.35 seconds
Started Jul 05 05:11:45 PM PDT 24
Finished Jul 05 05:11:54 PM PDT 24
Peak memory 208140 kb
Host smart-6eb0d072-9c82-4ef2-bc52-db0354e86911
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042051983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4042051983
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3063901103
Short name T515
Test name
Test status
Simulation time 34995653 ps
CPU time 2.62 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 210148 kb
Host smart-0c4dd42f-afcf-45d9-b85a-355ac34e5390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063901103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3063901103
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3067056857
Short name T531
Test name
Test status
Simulation time 241974585 ps
CPU time 4.51 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 208244 kb
Host smart-0ea1030a-cab0-435d-8d92-aeca1ddd561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067056857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3067056857
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1258761091
Short name T787
Test name
Test status
Simulation time 1256617468 ps
CPU time 17.44 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:58 PM PDT 24
Peak memory 216404 kb
Host smart-30737fa8-7e6b-49b9-aa84-e7b2779a826e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258761091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1258761091
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.125825726
Short name T764
Test name
Test status
Simulation time 1010348731 ps
CPU time 4.44 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 210080 kb
Host smart-2b106af5-916a-4e0c-b2a3-479be17caccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125825726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.125825726
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2675035830
Short name T626
Test name
Test status
Simulation time 46323145 ps
CPU time 2.35 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:42 PM PDT 24
Peak memory 210176 kb
Host smart-a092b577-576c-4e07-8058-b793d3d9667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675035830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2675035830
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2404906903
Short name T640
Test name
Test status
Simulation time 12793019 ps
CPU time 0.87 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:11:53 PM PDT 24
Peak memory 206004 kb
Host smart-ae29acf5-76ce-4b93-a469-83f2bc2ca51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404906903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2404906903
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3109994660
Short name T202
Test name
Test status
Simulation time 40505188 ps
CPU time 1.88 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:42 PM PDT 24
Peak memory 207816 kb
Host smart-dfd8a53f-1e06-49f6-85da-b41c4a2a8c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109994660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3109994660
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4288537826
Short name T676
Test name
Test status
Simulation time 755027897 ps
CPU time 8.11 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:12:04 PM PDT 24
Peak memory 214324 kb
Host smart-530ffb6e-c4e0-4576-84ec-1ab6c4b6c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288537826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4288537826
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.129896185
Short name T861
Test name
Test status
Simulation time 38374591 ps
CPU time 2.18 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:57 PM PDT 24
Peak memory 214300 kb
Host smart-ef54026f-b6f8-4c21-b36a-3c5d1c967eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129896185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.129896185
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.583442370
Short name T694
Test name
Test status
Simulation time 43196765 ps
CPU time 2.56 seconds
Started Jul 05 05:11:50 PM PDT 24
Finished Jul 05 05:11:54 PM PDT 24
Peak memory 220252 kb
Host smart-81020c9a-de75-4aec-bc04-0be2add6b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583442370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.583442370
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1290997634
Short name T825
Test name
Test status
Simulation time 419163645 ps
CPU time 4.48 seconds
Started Jul 05 05:11:43 PM PDT 24
Finished Jul 05 05:11:48 PM PDT 24
Peak memory 209972 kb
Host smart-6baa558a-8fc7-4810-b2f6-6fbf56f98da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290997634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1290997634
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.166423171
Short name T614
Test name
Test status
Simulation time 158171745 ps
CPU time 4.5 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 206680 kb
Host smart-fd40de4c-bd92-4d04-b65f-89a5dd2d94c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166423171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.166423171
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2729635356
Short name T470
Test name
Test status
Simulation time 123648005 ps
CPU time 3.22 seconds
Started Jul 05 05:11:41 PM PDT 24
Finished Jul 05 05:11:45 PM PDT 24
Peak memory 206848 kb
Host smart-486901a3-9235-4aea-8e5c-02b7e5fc2f67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729635356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2729635356
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1403667744
Short name T896
Test name
Test status
Simulation time 155192860 ps
CPU time 3 seconds
Started Jul 05 05:11:40 PM PDT 24
Finished Jul 05 05:11:44 PM PDT 24
Peak memory 208564 kb
Host smart-1869ab95-8740-4d0d-8b1d-a5f593f2fe0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403667744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1403667744
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2456240739
Short name T588
Test name
Test status
Simulation time 47582936 ps
CPU time 2.81 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:43 PM PDT 24
Peak memory 206972 kb
Host smart-e5f76aac-563f-440e-9aa5-790b4fc93a9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456240739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2456240739
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3232955001
Short name T216
Test name
Test status
Simulation time 59612738 ps
CPU time 1.93 seconds
Started Jul 05 05:11:50 PM PDT 24
Finished Jul 05 05:11:53 PM PDT 24
Peak memory 208396 kb
Host smart-1cc97021-2897-4c20-ad50-c0959a24bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232955001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3232955001
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4053284349
Short name T574
Test name
Test status
Simulation time 225925284 ps
CPU time 2.72 seconds
Started Jul 05 05:11:39 PM PDT 24
Finished Jul 05 05:11:43 PM PDT 24
Peak memory 207148 kb
Host smart-8484901f-aef0-4d51-a407-162616f3ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053284349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4053284349
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1649603690
Short name T610
Test name
Test status
Simulation time 1009472133 ps
CPU time 8.02 seconds
Started Jul 05 05:11:52 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 210048 kb
Host smart-11009468-fb7d-4a1b-a113-f46c9e31250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649603690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1649603690
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2146101345
Short name T162
Test name
Test status
Simulation time 76752275 ps
CPU time 1.99 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 209928 kb
Host smart-441dc417-8884-405f-8bc6-b8c066656f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146101345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2146101345
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.14288830
Short name T605
Test name
Test status
Simulation time 21301162 ps
CPU time 0.87 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 205988 kb
Host smart-00f61ac7-1371-478a-9851-399ef63cbb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.14288830
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3064062402
Short name T316
Test name
Test status
Simulation time 8267703590 ps
CPU time 37.13 seconds
Started Jul 05 05:11:48 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 214312 kb
Host smart-ac4cac5a-5212-480e-a13e-85e0fb250885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064062402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3064062402
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3020080901
Short name T366
Test name
Test status
Simulation time 176011117 ps
CPU time 2.18 seconds
Started Jul 05 05:11:52 PM PDT 24
Finished Jul 05 05:11:55 PM PDT 24
Peak memory 215512 kb
Host smart-8f4be835-705f-4601-b011-eb762bbed9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020080901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3020080901
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3950852354
Short name T844
Test name
Test status
Simulation time 430646779 ps
CPU time 3.37 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 214272 kb
Host smart-c579d45c-f2e1-43ed-9aab-33a3447904ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950852354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3950852354
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1712252843
Short name T709
Test name
Test status
Simulation time 152824789 ps
CPU time 2.89 seconds
Started Jul 05 05:11:52 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 208196 kb
Host smart-51c8cc72-7fa9-4d7a-83a6-757369fa7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712252843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1712252843
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.805706563
Short name T617
Test name
Test status
Simulation time 60720487 ps
CPU time 3.32 seconds
Started Jul 05 05:11:49 PM PDT 24
Finished Jul 05 05:11:52 PM PDT 24
Peak memory 209328 kb
Host smart-12993260-44a5-4f46-bfb6-16049741b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805706563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.805706563
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2202531201
Short name T348
Test name
Test status
Simulation time 105629701 ps
CPU time 2.17 seconds
Started Jul 05 05:11:50 PM PDT 24
Finished Jul 05 05:11:53 PM PDT 24
Peak memory 208912 kb
Host smart-073f76fd-3a81-44af-a4a1-c0fde74328af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202531201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2202531201
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.55040457
Short name T812
Test name
Test status
Simulation time 63798073 ps
CPU time 3.15 seconds
Started Jul 05 05:11:52 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 206876 kb
Host smart-e61731a0-b78f-4721-8c57-88b21edab5c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55040457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.55040457
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1373435212
Short name T500
Test name
Test status
Simulation time 217454152 ps
CPU time 2.44 seconds
Started Jul 05 05:11:49 PM PDT 24
Finished Jul 05 05:11:52 PM PDT 24
Peak memory 206976 kb
Host smart-a4241785-ca69-4b59-abf8-4b7d9d56435c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373435212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1373435212
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.175391194
Short name T818
Test name
Test status
Simulation time 472722501 ps
CPU time 3.92 seconds
Started Jul 05 05:11:50 PM PDT 24
Finished Jul 05 05:11:55 PM PDT 24
Peak memory 207020 kb
Host smart-07c8bb4f-1329-4d27-8baa-1b07e122fa69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175391194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.175391194
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.366599953
Short name T789
Test name
Test status
Simulation time 85359633 ps
CPU time 1.8 seconds
Started Jul 05 05:11:49 PM PDT 24
Finished Jul 05 05:11:51 PM PDT 24
Peak memory 208012 kb
Host smart-d9452d48-1957-4d40-b1ad-2e256e22bde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366599953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.366599953
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1508302157
Short name T756
Test name
Test status
Simulation time 169994721 ps
CPU time 4.12 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:11:57 PM PDT 24
Peak memory 208488 kb
Host smart-3767e090-c7a1-4a2e-9ca2-e2c369270ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508302157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1508302157
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3844027073
Short name T127
Test name
Test status
Simulation time 952734241 ps
CPU time 16.65 seconds
Started Jul 05 05:11:48 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 222620 kb
Host smart-b85759ce-56b6-4062-934d-e570d1f80028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844027073 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3844027073
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1556283907
Short name T218
Test name
Test status
Simulation time 257279432 ps
CPU time 8.66 seconds
Started Jul 05 05:11:49 PM PDT 24
Finished Jul 05 05:11:58 PM PDT 24
Peak memory 210532 kb
Host smart-82d47d1c-6ad6-4752-b544-c5f1e7e82cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556283907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1556283907
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2597732965
Short name T163
Test name
Test status
Simulation time 1223304223 ps
CPU time 2.19 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:57 PM PDT 24
Peak memory 210168 kb
Host smart-9b652564-1d39-4717-9d37-910ed933dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597732965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2597732965
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.313765895
Short name T474
Test name
Test status
Simulation time 54030830 ps
CPU time 0.72 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:11:55 PM PDT 24
Peak memory 206016 kb
Host smart-676aaba5-1438-4f40-a871-f5e49143f333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313765895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.313765895
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2401939913
Short name T836
Test name
Test status
Simulation time 25762437 ps
CPU time 1.65 seconds
Started Jul 05 05:20:59 PM PDT 24
Finished Jul 05 05:21:02 PM PDT 24
Peak memory 207424 kb
Host smart-15cdb14c-617c-45f8-ad2e-9da5ee799426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401939913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2401939913
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.177892559
Short name T252
Test name
Test status
Simulation time 76198840 ps
CPU time 3.59 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:59 PM PDT 24
Peak memory 210544 kb
Host smart-a52b5ffd-1486-4862-8aa2-267ae7fd3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177892559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.177892559
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.6715782
Short name T849
Test name
Test status
Simulation time 735022628 ps
CPU time 6.15 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 214896 kb
Host smart-7ff7fdd8-c908-406e-8a26-6182ddd099c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6715782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.6715782
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2784943187
Short name T243
Test name
Test status
Simulation time 506218032 ps
CPU time 3.97 seconds
Started Jul 05 05:11:57 PM PDT 24
Finished Jul 05 05:12:03 PM PDT 24
Peak memory 210156 kb
Host smart-01ff0353-79c7-46c4-9027-0bf57595a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784943187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2784943187
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3699816372
Short name T214
Test name
Test status
Simulation time 348616566 ps
CPU time 4.14 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:11:59 PM PDT 24
Peak memory 207444 kb
Host smart-b22a09e8-5c59-4769-94f7-3fc3ab49c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699816372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3699816372
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.923193767
Short name T322
Test name
Test status
Simulation time 809844748 ps
CPU time 6.54 seconds
Started Jul 05 05:11:56 PM PDT 24
Finished Jul 05 05:12:04 PM PDT 24
Peak memory 208740 kb
Host smart-6afce8db-c0a9-49d8-8df8-e259bd2dcbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923193767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.923193767
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3192968169
Short name T485
Test name
Test status
Simulation time 150714214 ps
CPU time 3.78 seconds
Started Jul 05 05:11:59 PM PDT 24
Finished Jul 05 05:12:04 PM PDT 24
Peak memory 206952 kb
Host smart-6c965129-c31c-445e-8721-f283cb64a372
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192968169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3192968169
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.477124023
Short name T441
Test name
Test status
Simulation time 505793616 ps
CPU time 6.23 seconds
Started Jul 05 05:11:58 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 207912 kb
Host smart-b2c217a1-6d0e-4a00-a690-3e7aa2ad66f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477124023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.477124023
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1500594900
Short name T192
Test name
Test status
Simulation time 1481851507 ps
CPU time 27.6 seconds
Started Jul 05 05:11:57 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 209120 kb
Host smart-1207c50d-c713-4e98-a43a-5de18da5e9c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500594900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1500594900
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3489744418
Short name T563
Test name
Test status
Simulation time 136098169 ps
CPU time 2.22 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:57 PM PDT 24
Peak memory 209580 kb
Host smart-7d273830-9c4f-477b-bbb7-029d934cd175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489744418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3489744418
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1820250847
Short name T457
Test name
Test status
Simulation time 642586143 ps
CPU time 6.1 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 208064 kb
Host smart-2a6e3167-5958-4de7-b478-413282c142b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820250847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1820250847
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3766365494
Short name T766
Test name
Test status
Simulation time 68847738 ps
CPU time 1.01 seconds
Started Jul 05 05:11:56 PM PDT 24
Finished Jul 05 05:11:58 PM PDT 24
Peak memory 206004 kb
Host smart-8aa2fea6-cb8b-4c75-9e3c-8feb2149418d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766365494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3766365494
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2609683154
Short name T736
Test name
Test status
Simulation time 149809584 ps
CPU time 5.55 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 214292 kb
Host smart-80b77ba4-1bc2-4284-ad5e-171fa0a7cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609683154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2609683154
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4222077105
Short name T746
Test name
Test status
Simulation time 9538682 ps
CPU time 0.72 seconds
Started Jul 05 05:12:04 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 205896 kb
Host smart-3d764dcd-d34a-428a-bfc9-6ff8d36e6974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222077105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4222077105
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.168461914
Short name T852
Test name
Test status
Simulation time 222384030 ps
CPU time 2.67 seconds
Started Jul 05 05:11:55 PM PDT 24
Finished Jul 05 05:11:59 PM PDT 24
Peak memory 214316 kb
Host smart-c35c48c6-dfc1-4bfb-9542-d3d2f61fc370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168461914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.168461914
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2202811084
Short name T35
Test name
Test status
Simulation time 108474522 ps
CPU time 3.24 seconds
Started Jul 05 05:12:01 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 222848 kb
Host smart-b9d76a16-0d4b-4156-ae65-ef1afddda5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202811084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2202811084
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3965375323
Short name T624
Test name
Test status
Simulation time 46873111 ps
CPU time 2.43 seconds
Started Jul 05 05:11:56 PM PDT 24
Finished Jul 05 05:12:00 PM PDT 24
Peak memory 209164 kb
Host smart-8888ed69-76e0-4140-bfba-6869323fbb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965375323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3965375323
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1838504423
Short name T274
Test name
Test status
Simulation time 105656920 ps
CPU time 2.8 seconds
Started Jul 05 05:12:01 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 214284 kb
Host smart-60d5c404-8e81-4bf8-8fd5-55d7ffa15789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838504423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1838504423
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4246623656
Short name T625
Test name
Test status
Simulation time 179105896 ps
CPU time 3.46 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:11:58 PM PDT 24
Peak memory 214208 kb
Host smart-b44d3f4f-f809-41d3-8a73-ed56be10791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246623656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4246623656
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3267378153
Short name T336
Test name
Test status
Simulation time 259448443 ps
CPU time 3.88 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 214120 kb
Host smart-0e475caa-52aa-4539-99f4-e8f78ad5173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267378153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3267378153
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1406998840
Short name T623
Test name
Test status
Simulation time 188994053 ps
CPU time 6.54 seconds
Started Jul 05 05:11:55 PM PDT 24
Finished Jul 05 05:12:03 PM PDT 24
Peak memory 207004 kb
Host smart-0fc91043-193f-4820-9462-7571b8895a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406998840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1406998840
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3659823766
Short name T754
Test name
Test status
Simulation time 239464651 ps
CPU time 3.13 seconds
Started Jul 05 05:11:51 PM PDT 24
Finished Jul 05 05:11:56 PM PDT 24
Peak memory 208364 kb
Host smart-9c306158-59c2-46f8-9123-f556a3ea6730
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659823766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3659823766
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.842637309
Short name T800
Test name
Test status
Simulation time 294227534 ps
CPU time 6.35 seconds
Started Jul 05 05:11:53 PM PDT 24
Finished Jul 05 05:12:00 PM PDT 24
Peak memory 208268 kb
Host smart-e1eac2b8-3e35-452f-9926-69cadc542e1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842637309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.842637309
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2236923597
Short name T918
Test name
Test status
Simulation time 33448332 ps
CPU time 2.34 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:04 PM PDT 24
Peak memory 206760 kb
Host smart-bd3462d5-d5e0-4c92-8e4f-175689bec2b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236923597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2236923597
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.607597596
Short name T744
Test name
Test status
Simulation time 399377975 ps
CPU time 10.15 seconds
Started Jul 05 05:12:01 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 209072 kb
Host smart-eee83e28-ca9c-4157-8395-34101cfd5de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607597596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.607597596
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3823394135
Short name T454
Test name
Test status
Simulation time 54329696 ps
CPU time 2.81 seconds
Started Jul 05 05:11:54 PM PDT 24
Finished Jul 05 05:11:59 PM PDT 24
Peak memory 206812 kb
Host smart-be6a1e78-e4e7-489e-9e8b-fcb431a98f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823394135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3823394135
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1228402592
Short name T138
Test name
Test status
Simulation time 9389724252 ps
CPU time 105.87 seconds
Started Jul 05 05:12:01 PM PDT 24
Finished Jul 05 05:13:48 PM PDT 24
Peak memory 222576 kb
Host smart-94a468b3-414c-4d0b-be08-684ac0f84429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228402592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1228402592
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1793051242
Short name T185
Test name
Test status
Simulation time 567574930 ps
CPU time 12.71 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:20 PM PDT 24
Peak memory 222612 kb
Host smart-33005da8-0c4e-4abe-9af9-e6f067e63e93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793051242 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1793051242
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3737385408
Short name T802
Test name
Test status
Simulation time 172919481 ps
CPU time 4.36 seconds
Started Jul 05 05:11:56 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 210144 kb
Host smart-2d80adb9-d462-4dce-b875-e0774f568975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737385408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3737385408
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.919128037
Short name T167
Test name
Test status
Simulation time 823261794 ps
CPU time 2.66 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:04 PM PDT 24
Peak memory 209712 kb
Host smart-cc70eacd-3d7b-4886-a198-ab8649870557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919128037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.919128037
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3566634795
Short name T762
Test name
Test status
Simulation time 14999889 ps
CPU time 0.79 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:02 PM PDT 24
Peak memory 205968 kb
Host smart-2548027a-c9dd-456f-bed0-63bc92f6f5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566634795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3566634795
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3796567192
Short name T894
Test name
Test status
Simulation time 327301736 ps
CPU time 4.69 seconds
Started Jul 05 05:12:00 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 214328 kb
Host smart-7c030cf1-ae98-492d-936a-9a73bcf8d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796567192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3796567192
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2483712604
Short name T52
Test name
Test status
Simulation time 192436531 ps
CPU time 3.88 seconds
Started Jul 05 05:12:05 PM PDT 24
Finished Jul 05 05:12:10 PM PDT 24
Peak memory 209852 kb
Host smart-d61cb332-58ed-411b-8933-90f4e55410af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483712604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2483712604
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.453521216
Short name T753
Test name
Test status
Simulation time 110029831 ps
CPU time 1.78 seconds
Started Jul 05 05:12:05 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 214224 kb
Host smart-2973711e-da9b-4f75-a5b6-40332f04471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453521216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.453521216
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3000248158
Short name T238
Test name
Test status
Simulation time 86856442 ps
CPU time 3.46 seconds
Started Jul 05 05:12:09 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 222464 kb
Host smart-307469bd-fea8-479b-bd5c-e5b842fb7fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000248158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3000248158
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2048135608
Short name T260
Test name
Test status
Simulation time 130392810 ps
CPU time 2.66 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 208608 kb
Host smart-cf487ed1-0e7c-4553-9791-8286a0351e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048135608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2048135608
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2338324362
Short name T491
Test name
Test status
Simulation time 58254657 ps
CPU time 3.15 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 208352 kb
Host smart-53d8334b-d356-40e4-86db-094d3929e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338324362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2338324362
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1195132049
Short name T783
Test name
Test status
Simulation time 131704804 ps
CPU time 2.68 seconds
Started Jul 05 05:12:03 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 207312 kb
Host smart-0192c876-8e21-45f1-9a82-d8d5923ebf23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195132049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1195132049
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1828838112
Short name T708
Test name
Test status
Simulation time 96058821 ps
CPU time 3.07 seconds
Started Jul 05 05:11:58 PM PDT 24
Finished Jul 05 05:12:02 PM PDT 24
Peak memory 208568 kb
Host smart-5278be62-a352-424a-9712-d065933871a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828838112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1828838112
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2359516472
Short name T810
Test name
Test status
Simulation time 97262162 ps
CPU time 3.98 seconds
Started Jul 05 05:15:02 PM PDT 24
Finished Jul 05 05:15:07 PM PDT 24
Peak memory 207208 kb
Host smart-ee3b0bb0-aa20-4498-bcf5-9e115ca7fa95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359516472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2359516472
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2096017350
Short name T745
Test name
Test status
Simulation time 45139277 ps
CPU time 2 seconds
Started Jul 05 05:12:02 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 215792 kb
Host smart-6212b5e8-e06a-4f23-aee9-a94b21d44773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096017350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2096017350
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4254272933
Short name T439
Test name
Test status
Simulation time 101189505 ps
CPU time 2.08 seconds
Started Jul 05 05:12:03 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 208588 kb
Host smart-09f91f84-8de8-49bc-bbfd-ae07498754a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254272933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4254272933
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2004296393
Short name T339
Test name
Test status
Simulation time 310744605 ps
CPU time 9.07 seconds
Started Jul 05 05:12:02 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 208488 kb
Host smart-8e95e785-e880-4a0a-b787-8efc063b33bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004296393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2004296393
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3321238090
Short name T888
Test name
Test status
Simulation time 41373706 ps
CPU time 1.78 seconds
Started Jul 05 05:12:02 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 209912 kb
Host smart-6a0b5aed-ae0f-45f5-aa84-245258eeed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321238090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3321238090
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3939726887
Short name T86
Test name
Test status
Simulation time 9140683 ps
CPU time 0.7 seconds
Started Jul 05 05:10:40 PM PDT 24
Finished Jul 05 05:10:42 PM PDT 24
Peak memory 206000 kb
Host smart-877bb02e-4002-476d-9097-9155561fb3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939726887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3939726887
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1939254164
Short name T363
Test name
Test status
Simulation time 354119273 ps
CPU time 9.55 seconds
Started Jul 05 05:10:38 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 215296 kb
Host smart-e99683e3-b1a0-4159-93e5-ef56d1d87d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939254164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1939254164
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1888096124
Short name T707
Test name
Test status
Simulation time 141161133 ps
CPU time 2.26 seconds
Started Jul 05 05:10:41 PM PDT 24
Finished Jul 05 05:10:44 PM PDT 24
Peak memory 222852 kb
Host smart-762eed05-abdf-4c0a-bc63-2e0b3cb5a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888096124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1888096124
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1091604200
Short name T803
Test name
Test status
Simulation time 299662970 ps
CPU time 3.45 seconds
Started Jul 05 05:10:38 PM PDT 24
Finished Jul 05 05:10:42 PM PDT 24
Peak memory 210220 kb
Host smart-4e553f13-e005-492a-82f0-1eb3a2ef4b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091604200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1091604200
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2379551542
Short name T874
Test name
Test status
Simulation time 563417391 ps
CPU time 4.41 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:45 PM PDT 24
Peak memory 214208 kb
Host smart-c29dd1b3-2390-4cc8-9734-e67a30ff921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379551542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2379551542
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3863134483
Short name T892
Test name
Test status
Simulation time 58044774 ps
CPU time 1.81 seconds
Started Jul 05 05:10:40 PM PDT 24
Finished Jul 05 05:10:43 PM PDT 24
Peak memory 214268 kb
Host smart-88c1e991-b555-49a5-9e8b-1816c4db31fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863134483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3863134483
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1590123891
Short name T791
Test name
Test status
Simulation time 48337199 ps
CPU time 1.64 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:10:45 PM PDT 24
Peak memory 219600 kb
Host smart-efc72147-6379-4de1-b481-c85a99000e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590123891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1590123891
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2162833107
Short name T797
Test name
Test status
Simulation time 768541033 ps
CPU time 4.61 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 208312 kb
Host smart-2207c745-da74-4354-ac73-e5febc8f2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162833107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2162833107
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3578622419
Short name T44
Test name
Test status
Simulation time 299868396 ps
CPU time 7.16 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:10:51 PM PDT 24
Peak memory 237096 kb
Host smart-c0b65e7c-4776-45bc-afd5-915bf2145b74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578622419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3578622419
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2776881238
Short name T713
Test name
Test status
Simulation time 223876825 ps
CPU time 3.06 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:43 PM PDT 24
Peak memory 208484 kb
Host smart-154513ed-18db-495d-b2bd-dbbd6fe5f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776881238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2776881238
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2418884300
Short name T317
Test name
Test status
Simulation time 302991849 ps
CPU time 6.1 seconds
Started Jul 05 05:10:37 PM PDT 24
Finished Jul 05 05:10:44 PM PDT 24
Peak memory 208636 kb
Host smart-b74b20d7-0035-49a7-8887-15c760f01c19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418884300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2418884300
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2713537044
Short name T848
Test name
Test status
Simulation time 146368685 ps
CPU time 2.44 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:10:46 PM PDT 24
Peak memory 206800 kb
Host smart-e82e9528-9076-4931-8ec5-1dd7696b3d12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713537044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2713537044
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.528902532
Short name T578
Test name
Test status
Simulation time 296012808 ps
CPU time 3.62 seconds
Started Jul 05 05:10:40 PM PDT 24
Finished Jul 05 05:10:45 PM PDT 24
Peak memory 208864 kb
Host smart-4e52f2f7-57e3-4858-a510-56ece032669b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528902532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.528902532
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2417957238
Short name T641
Test name
Test status
Simulation time 1256524512 ps
CPU time 3.68 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:44 PM PDT 24
Peak memory 215628 kb
Host smart-8459925e-3709-49b3-80ad-099573fc0255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417957238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2417957238
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1495427484
Short name T473
Test name
Test status
Simulation time 91753057 ps
CPU time 2.36 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:42 PM PDT 24
Peak memory 206972 kb
Host smart-3dbed68e-02f2-44c3-af80-3f17a6458bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495427484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1495427484
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3918813410
Short name T343
Test name
Test status
Simulation time 3182037242 ps
CPU time 17.97 seconds
Started Jul 05 05:10:42 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 222772 kb
Host smart-7663a1a7-535b-460a-beb4-1cabda83e151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918813410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3918813410
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2109684859
Short name T509
Test name
Test status
Simulation time 300878658 ps
CPU time 7.76 seconds
Started Jul 05 05:10:40 PM PDT 24
Finished Jul 05 05:10:49 PM PDT 24
Peak memory 222476 kb
Host smart-79e6abb6-eaa5-4d9d-b375-5d4d712e87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109684859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2109684859
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.782252452
Short name T458
Test name
Test status
Simulation time 92692575 ps
CPU time 3.66 seconds
Started Jul 05 05:10:38 PM PDT 24
Finished Jul 05 05:10:42 PM PDT 24
Peak memory 210668 kb
Host smart-b2d62af2-7958-4c13-9b21-23d818e56e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782252452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.782252452
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1544635651
Short name T712
Test name
Test status
Simulation time 10549637 ps
CPU time 0.85 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 206000 kb
Host smart-72459822-eca8-4a3e-8f3f-de4dc8f52a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544635651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1544635651
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1141380136
Short name T148
Test name
Test status
Simulation time 34302369 ps
CPU time 2.64 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:11 PM PDT 24
Peak memory 214304 kb
Host smart-b1329965-294a-4027-8181-0ed8ebe092a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141380136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1141380136
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1953559099
Short name T821
Test name
Test status
Simulation time 187001999 ps
CPU time 4.31 seconds
Started Jul 05 05:12:06 PM PDT 24
Finished Jul 05 05:12:11 PM PDT 24
Peak memory 218460 kb
Host smart-1c816ddf-ed92-4bc2-8426-df3afd35e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953559099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1953559099
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1919446481
Short name T286
Test name
Test status
Simulation time 199566165 ps
CPU time 2.21 seconds
Started Jul 05 05:12:05 PM PDT 24
Finished Jul 05 05:12:09 PM PDT 24
Peak memory 214220 kb
Host smart-fe52af66-e838-40c1-a045-4223ddf8c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919446481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1919446481
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3692637785
Short name T136
Test name
Test status
Simulation time 1125320678 ps
CPU time 4.32 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 209368 kb
Host smart-03609091-5770-4528-afb7-ad671aec9a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692637785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3692637785
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2333848490
Short name T495
Test name
Test status
Simulation time 392705884 ps
CPU time 8.86 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 208884 kb
Host smart-d0ba67b9-ca4b-4ce5-9f4c-711bd3d7cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333848490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2333848490
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1016152017
Short name T615
Test name
Test status
Simulation time 195460239 ps
CPU time 5.92 seconds
Started Jul 05 05:11:59 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 206976 kb
Host smart-73fdaf28-82d1-467c-96b0-5c7b1744291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016152017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1016152017
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2072462317
Short name T106
Test name
Test status
Simulation time 573949620 ps
CPU time 3.33 seconds
Started Jul 05 05:12:02 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 209084 kb
Host smart-d27bb963-bc32-4229-a96a-c6706245a06c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072462317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2072462317
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3627415714
Short name T194
Test name
Test status
Simulation time 938772044 ps
CPU time 5.36 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:16 PM PDT 24
Peak memory 208188 kb
Host smart-0fdaace6-1d8a-4e74-af49-1074e600a2eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627415714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3627415714
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.600912120
Short name T296
Test name
Test status
Simulation time 567983574 ps
CPU time 6.34 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:15 PM PDT 24
Peak memory 208728 kb
Host smart-2a468354-8df9-45b9-87bb-d17f3e9ea42e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600912120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.600912120
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1018831337
Short name T794
Test name
Test status
Simulation time 718816870 ps
CPU time 5.5 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 218344 kb
Host smart-b0ba4ee0-8342-48ce-acbe-ad8511f8c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018831337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1018831337
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.586519897
Short name T864
Test name
Test status
Simulation time 342055412 ps
CPU time 3.06 seconds
Started Jul 05 05:12:02 PM PDT 24
Finished Jul 05 05:12:06 PM PDT 24
Peak memory 208200 kb
Host smart-57a20ab0-d489-4178-a13e-6f5a134b6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586519897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.586519897
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.424711678
Short name T329
Test name
Test status
Simulation time 395012194 ps
CPU time 5.73 seconds
Started Jul 05 05:12:13 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 222396 kb
Host smart-77e00ecf-d340-402f-9151-87b43f1534d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424711678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.424711678
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3814208238
Short name T656
Test name
Test status
Simulation time 527908039 ps
CPU time 6.57 seconds
Started Jul 05 05:12:09 PM PDT 24
Finished Jul 05 05:12:16 PM PDT 24
Peak memory 218292 kb
Host smart-dee18b0f-c125-4ebb-a908-de5696a565ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814208238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3814208238
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.311298042
Short name T123
Test name
Test status
Simulation time 105732680 ps
CPU time 3.86 seconds
Started Jul 05 05:12:11 PM PDT 24
Finished Jul 05 05:12:16 PM PDT 24
Peak memory 210016 kb
Host smart-e6c67ec0-ff6c-4eb6-9f71-b11c8e58f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311298042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.311298042
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3855342604
Short name T880
Test name
Test status
Simulation time 10938442 ps
CPU time 0.83 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 205756 kb
Host smart-e9446f5f-87d9-4739-a584-1d8582073a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855342604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3855342604
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1180865978
Short name T211
Test name
Test status
Simulation time 82021253 ps
CPU time 2.66 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 209084 kb
Host smart-2b2f3ef7-a11c-490b-9833-4c751b898e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180865978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1180865978
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2928932738
Short name T686
Test name
Test status
Simulation time 56220670 ps
CPU time 3.52 seconds
Started Jul 05 05:12:13 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 214280 kb
Host smart-05141a0b-78e1-41a4-9de1-63339c05d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928932738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2928932738
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3728161719
Short name T863
Test name
Test status
Simulation time 160103105 ps
CPU time 3.91 seconds
Started Jul 05 05:12:12 PM PDT 24
Finished Jul 05 05:12:17 PM PDT 24
Peak memory 207172 kb
Host smart-1d0f6a58-b888-4b4c-801f-64ee8a984133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728161719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3728161719
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2794316386
Short name T64
Test name
Test status
Simulation time 717614959 ps
CPU time 3.52 seconds
Started Jul 05 05:12:11 PM PDT 24
Finished Jul 05 05:12:16 PM PDT 24
Peak memory 219736 kb
Host smart-5dc45df9-431b-454d-b568-dce6469b4828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794316386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2794316386
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1769833557
Short name T793
Test name
Test status
Simulation time 256568582 ps
CPU time 4.33 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 209856 kb
Host smart-6fb047bd-cddd-4346-894a-6e5245dbb18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769833557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1769833557
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2322872560
Short name T817
Test name
Test status
Simulation time 484581345 ps
CPU time 3.88 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 206780 kb
Host smart-0cac50d9-b912-4c30-bc9d-f3a7281a53ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322872560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2322872560
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3911725658
Short name T651
Test name
Test status
Simulation time 29849162 ps
CPU time 2.35 seconds
Started Jul 05 05:12:13 PM PDT 24
Finished Jul 05 05:12:17 PM PDT 24
Peak memory 206948 kb
Host smart-5d7fad9c-7ed5-4f81-b05c-2b8d097175e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911725658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3911725658
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2619119267
Short name T705
Test name
Test status
Simulation time 95752954 ps
CPU time 3.51 seconds
Started Jul 05 05:12:12 PM PDT 24
Finished Jul 05 05:12:17 PM PDT 24
Peak memory 208820 kb
Host smart-f8404cd1-4e03-4779-9042-2438ba55bf5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619119267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2619119267
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4197723841
Short name T776
Test name
Test status
Simulation time 221723876 ps
CPU time 2.89 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 207776 kb
Host smart-da49ed20-7c8a-4558-a803-7e9491ca785c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197723841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4197723841
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2013306302
Short name T299
Test name
Test status
Simulation time 91577087 ps
CPU time 4 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 210104 kb
Host smart-cc947f22-3154-4a71-b005-fef818affe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013306302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2013306302
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.980667562
Short name T435
Test name
Test status
Simulation time 3629399696 ps
CPU time 26.43 seconds
Started Jul 05 05:12:11 PM PDT 24
Finished Jul 05 05:12:38 PM PDT 24
Peak memory 208308 kb
Host smart-78f258d7-c110-4ed0-b81b-31258b25ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980667562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.980667562
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.497762448
Short name T846
Test name
Test status
Simulation time 184745991 ps
CPU time 5.81 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 209308 kb
Host smart-1866dbc3-fc56-4ecf-b709-d1ca189235b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497762448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.497762448
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2340516740
Short name T726
Test name
Test status
Simulation time 88011191 ps
CPU time 3.6 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:15 PM PDT 24
Peak memory 210372 kb
Host smart-21ceeafd-fa88-4f2c-b309-bcfa5b554c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340516740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2340516740
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3321937844
Short name T899
Test name
Test status
Simulation time 22141413 ps
CPU time 0.84 seconds
Started Jul 05 05:12:17 PM PDT 24
Finished Jul 05 05:12:19 PM PDT 24
Peak memory 206012 kb
Host smart-69d50cbc-4ab2-4074-936b-7208ba61ef73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321937844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3321937844
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1737677715
Short name T255
Test name
Test status
Simulation time 33474769 ps
CPU time 2.82 seconds
Started Jul 05 05:12:12 PM PDT 24
Finished Jul 05 05:12:16 PM PDT 24
Peak memory 214344 kb
Host smart-6ab61c51-e954-4f57-abff-9b46d8eb0ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737677715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1737677715
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3102911386
Short name T530
Test name
Test status
Simulation time 153650371 ps
CPU time 1.89 seconds
Started Jul 05 05:12:06 PM PDT 24
Finished Jul 05 05:12:09 PM PDT 24
Peak memory 218036 kb
Host smart-ca8dfcd9-cf9f-4586-87f1-790d6cfc0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102911386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3102911386
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3785139684
Short name T728
Test name
Test status
Simulation time 220938252 ps
CPU time 4.97 seconds
Started Jul 05 05:12:13 PM PDT 24
Finished Jul 05 05:12:20 PM PDT 24
Peak memory 222428 kb
Host smart-15022777-babc-44ed-905d-bac5fb2bd1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785139684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3785139684
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3251853959
Short name T714
Test name
Test status
Simulation time 801698746 ps
CPU time 9.12 seconds
Started Jul 05 05:12:16 PM PDT 24
Finished Jul 05 05:12:27 PM PDT 24
Peak memory 214724 kb
Host smart-0a5f1a1f-d3ef-4c97-9eb3-a4b203857aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251853959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3251853959
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1340469141
Short name T664
Test name
Test status
Simulation time 1409839996 ps
CPU time 9.65 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 222472 kb
Host smart-ca42a477-18a4-4484-b9c1-52a70bd4d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340469141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1340469141
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.860311712
Short name T795
Test name
Test status
Simulation time 280994632 ps
CPU time 4.09 seconds
Started Jul 05 05:12:08 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 208748 kb
Host smart-345f8a01-598b-4799-bc29-9c628700b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860311712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.860311712
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.4275019549
Short name T684
Test name
Test status
Simulation time 81490146 ps
CPU time 2.4 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 206912 kb
Host smart-e720a2ec-2423-4f9a-8187-e91eb8314f19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275019549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4275019549
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2065594254
Short name T875
Test name
Test status
Simulation time 245030875 ps
CPU time 2.38 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 206952 kb
Host smart-7297f0d0-bd42-4fbc-b740-24f91fa31012
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065594254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2065594254
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.186306398
Short name T524
Test name
Test status
Simulation time 112765337 ps
CPU time 3.07 seconds
Started Jul 05 05:12:07 PM PDT 24
Finished Jul 05 05:12:10 PM PDT 24
Peak memory 208784 kb
Host smart-f88bfade-225f-4661-b6c9-7112014a3ffc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186306398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.186306398
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1898344089
Short name T878
Test name
Test status
Simulation time 89976016 ps
CPU time 4.22 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 209776 kb
Host smart-6e678c62-607c-4083-9011-a96a5bb16792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898344089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1898344089
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3239786446
Short name T586
Test name
Test status
Simulation time 108418244 ps
CPU time 3.43 seconds
Started Jul 05 05:12:10 PM PDT 24
Finished Jul 05 05:12:15 PM PDT 24
Peak memory 208000 kb
Host smart-78ec0d0b-8869-4a2b-a661-e5a99941733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239786446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3239786446
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4216664935
Short name T104
Test name
Test status
Simulation time 421161599 ps
CPU time 19.75 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:37 PM PDT 24
Peak memory 222532 kb
Host smart-8ee380a2-7da7-4cd6-9a7f-450bca173d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216664935 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4216664935
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.374246624
Short name T729
Test name
Test status
Simulation time 397939354 ps
CPU time 4.62 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 207476 kb
Host smart-cbac7234-0ea8-4979-ae88-57895ab65845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374246624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.374246624
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3434750303
Short name T159
Test name
Test status
Simulation time 172015125 ps
CPU time 2.52 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:18 PM PDT 24
Peak memory 210264 kb
Host smart-df9ce6be-7770-42c7-83a6-99bf41a2814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434750303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3434750303
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2943796307
Short name T440
Test name
Test status
Simulation time 18394671 ps
CPU time 0.71 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 205948 kb
Host smart-49e06520-b3a5-4222-843d-9d5b7e840098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943796307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2943796307
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1507715601
Short name T788
Test name
Test status
Simulation time 60891276 ps
CPU time 2.65 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:19 PM PDT 24
Peak memory 214260 kb
Host smart-c7e37b3c-5d1f-4795-bcb6-946901c347c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507715601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1507715601
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3054577724
Short name T248
Test name
Test status
Simulation time 812352023 ps
CPU time 5.72 seconds
Started Jul 05 05:12:17 PM PDT 24
Finished Jul 05 05:12:24 PM PDT 24
Peak memory 221624 kb
Host smart-b44e6107-124f-4cea-b261-92d10d85d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054577724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3054577724
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3789764286
Short name T55
Test name
Test status
Simulation time 110995330 ps
CPU time 2.94 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:19 PM PDT 24
Peak memory 214264 kb
Host smart-fce50d34-29e3-4bbb-b274-fed8fa91512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789764286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3789764286
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3379091257
Short name T56
Test name
Test status
Simulation time 97577265 ps
CPU time 1.55 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 214288 kb
Host smart-2b7a9721-a8ce-4edb-ab81-be2bd7679c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379091257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3379091257
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3574398955
Short name T796
Test name
Test status
Simulation time 124521688 ps
CPU time 4.31 seconds
Started Jul 05 05:12:15 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 207244 kb
Host smart-74ccd496-50a1-4ce7-8763-9efaf8c75e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574398955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3574398955
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1600742872
Short name T616
Test name
Test status
Simulation time 132323656 ps
CPU time 2.76 seconds
Started Jul 05 05:12:17 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 207284 kb
Host smart-8c1552f2-c550-4112-9c25-2a5405d1a154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600742872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1600742872
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3810507301
Short name T807
Test name
Test status
Simulation time 137016437 ps
CPU time 3.87 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:12:32 PM PDT 24
Peak memory 206996 kb
Host smart-ce2fdb79-0b2a-4af7-bfd1-7dd8528f86a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810507301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3810507301
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3049109163
Short name T334
Test name
Test status
Simulation time 1731136624 ps
CPU time 5.49 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:22 PM PDT 24
Peak memory 208048 kb
Host smart-ad66a687-16f8-4ff1-b068-289679c83121
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049109163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3049109163
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2333652125
Short name T341
Test name
Test status
Simulation time 149119095 ps
CPU time 5.41 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 207940 kb
Host smart-682be561-89e2-4b3f-8b0d-da2c362be898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333652125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2333652125
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2093391400
Short name T562
Test name
Test status
Simulation time 1143413607 ps
CPU time 9.52 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:12:37 PM PDT 24
Peak memory 209004 kb
Host smart-0329db0e-b2b8-44c8-87b4-df7d1d688471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093391400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2093391400
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.466983707
Short name T702
Test name
Test status
Simulation time 21570667 ps
CPU time 1.67 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 206800 kb
Host smart-4051a82f-43e4-421b-9915-3a247c5a7d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466983707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.466983707
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1266558829
Short name T236
Test name
Test status
Simulation time 889080383 ps
CPU time 41.16 seconds
Started Jul 05 05:12:14 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 217288 kb
Host smart-c87bc963-ab65-4e9f-9830-559288b15e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266558829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1266558829
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3772812202
Short name T648
Test name
Test status
Simulation time 334019562 ps
CPU time 5.91 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 222724 kb
Host smart-f31d6446-6ffa-4718-b57b-c95157b041ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772812202 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3772812202
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3957507533
Short name T696
Test name
Test status
Simulation time 8612205193 ps
CPU time 51.2 seconds
Started Jul 05 05:12:27 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 208084 kb
Host smart-83617af6-20a7-41cb-86f9-7457edffe486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957507533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3957507533
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4207871703
Short name T711
Test name
Test status
Simulation time 531591003 ps
CPU time 3.63 seconds
Started Jul 05 05:12:16 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 219172 kb
Host smart-20b01c45-5afb-436a-9021-1fe8e22381e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207871703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4207871703
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3103244664
Short name T512
Test name
Test status
Simulation time 19551340 ps
CPU time 0.81 seconds
Started Jul 05 05:12:28 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 205980 kb
Host smart-c922457a-bb0d-4432-9c58-0a5bca4daa67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103244664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3103244664
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.798477856
Short name T394
Test name
Test status
Simulation time 45127194 ps
CPU time 3.15 seconds
Started Jul 05 05:12:19 PM PDT 24
Finished Jul 05 05:12:23 PM PDT 24
Peak memory 215480 kb
Host smart-5ed82f07-7f1a-4d25-a5f2-3978cecc3a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798477856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.798477856
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.101105241
Short name T29
Test name
Test status
Simulation time 305031676 ps
CPU time 3.45 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 208856 kb
Host smart-ed30b3f9-403c-4ad0-bcc5-02ddc4447d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101105241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.101105241
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.281287614
Short name T691
Test name
Test status
Simulation time 105693955 ps
CPU time 2.53 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:28 PM PDT 24
Peak memory 218212 kb
Host smart-334b841f-ec39-4375-aa4d-14d301b286ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281287614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.281287614
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.172345033
Short name T816
Test name
Test status
Simulation time 50519968 ps
CPU time 3.27 seconds
Started Jul 05 05:12:23 PM PDT 24
Finished Jul 05 05:12:27 PM PDT 24
Peak memory 221844 kb
Host smart-a037b43a-f1ab-47ed-b5af-e6e6a69ddb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172345033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.172345033
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2365162168
Short name T54
Test name
Test status
Simulation time 93169050 ps
CPU time 2.17 seconds
Started Jul 05 05:12:38 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 214252 kb
Host smart-d7b9467c-c388-49f3-9ec6-98a2048f0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365162168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2365162168
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1034428222
Short name T293
Test name
Test status
Simulation time 241264207 ps
CPU time 3.81 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:29 PM PDT 24
Peak memory 220168 kb
Host smart-d0caeb99-4315-4090-975f-8e7876ab1e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034428222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1034428222
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4230630266
Short name T283
Test name
Test status
Simulation time 436570822 ps
CPU time 7.62 seconds
Started Jul 05 05:12:25 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 214336 kb
Host smart-25aa8840-7243-4e1a-bd12-eda8fe656072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230630266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4230630266
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4156705271
Short name T653
Test name
Test status
Simulation time 879393981 ps
CPU time 3.46 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 208748 kb
Host smart-a4fd1059-354e-4c2d-be2a-ded3f0a49f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156705271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4156705271
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1062123442
Short name T688
Test name
Test status
Simulation time 71865337 ps
CPU time 3.56 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:28 PM PDT 24
Peak memory 209000 kb
Host smart-758459a4-c018-489e-a53c-94c1f0036531
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062123442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1062123442
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2334781478
Short name T786
Test name
Test status
Simulation time 820675294 ps
CPU time 5.62 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:28 PM PDT 24
Peak memory 208016 kb
Host smart-1708a7c7-5b37-4d09-a368-39f4fc6e4585
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334781478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2334781478
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.144399095
Short name T450
Test name
Test status
Simulation time 295241443 ps
CPU time 3.5 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:27 PM PDT 24
Peak memory 208868 kb
Host smart-6ec2dc7a-50ea-4561-8121-8674c63f21e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144399095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.144399095
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1713913797
Short name T475
Test name
Test status
Simulation time 279411859 ps
CPU time 2.57 seconds
Started Jul 05 05:12:20 PM PDT 24
Finished Jul 05 05:12:23 PM PDT 24
Peak memory 215776 kb
Host smart-44811c1b-d3a7-42fe-b279-c19f4eed27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713913797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1713913797
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3305616288
Short name T477
Test name
Test status
Simulation time 163396784 ps
CPU time 2.84 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 206804 kb
Host smart-c8d474ee-6460-474a-ae57-aa59334875e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305616288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3305616288
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2784412482
Short name T845
Test name
Test status
Simulation time 4336901651 ps
CPU time 54.51 seconds
Started Jul 05 05:12:20 PM PDT 24
Finished Jul 05 05:13:15 PM PDT 24
Peak memory 217244 kb
Host smart-4cda0fbe-ce83-4626-b39d-9a46a52a550e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784412482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2784412482
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1516961889
Short name T2
Test name
Test status
Simulation time 79723725 ps
CPU time 3.82 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 209076 kb
Host smart-12c39cf9-6fa3-4b29-adb0-24e6ad2afd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516961889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1516961889
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1915654654
Short name T693
Test name
Test status
Simulation time 2348353466 ps
CPU time 12.99 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:38 PM PDT 24
Peak memory 211052 kb
Host smart-a421a6c3-51ea-438e-8836-e2334a436ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915654654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1915654654
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.181313967
Short name T642
Test name
Test status
Simulation time 57957574 ps
CPU time 0.81 seconds
Started Jul 05 05:12:32 PM PDT 24
Finished Jul 05 05:12:33 PM PDT 24
Peak memory 206020 kb
Host smart-72ce4bdd-b69a-4c95-951a-44e555eef05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181313967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.181313967
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4169878259
Short name T128
Test name
Test status
Simulation time 2683226431 ps
CPU time 35.14 seconds
Started Jul 05 05:12:20 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 215192 kb
Host smart-6f21a152-956a-443f-8ecb-3c71d2fea31f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169878259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4169878259
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1449736288
Short name T36
Test name
Test status
Simulation time 177040176 ps
CPU time 2.95 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 214700 kb
Host smart-7b8d4b02-f58b-47cf-b4d3-e59c61c5230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449736288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1449736288
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3861335601
Short name T860
Test name
Test status
Simulation time 51243568 ps
CPU time 2.25 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 209364 kb
Host smart-2eca40f0-4fb7-4832-9155-2fd48b23a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861335601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3861335601
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3479282846
Short name T748
Test name
Test status
Simulation time 264395767 ps
CPU time 6.98 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:31 PM PDT 24
Peak memory 222476 kb
Host smart-2a7ee5f4-b3cb-4d86-aaca-17c986c59b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479282846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3479282846
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1969003325
Short name T809
Test name
Test status
Simulation time 148981585 ps
CPU time 2.73 seconds
Started Jul 05 05:12:22 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 214260 kb
Host smart-6c4514e8-0cf2-4a37-b6a6-db3cf3e81d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969003325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1969003325
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3322410673
Short name T695
Test name
Test status
Simulation time 80100309 ps
CPU time 3.67 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 209152 kb
Host smart-e4a82a8e-370d-49a9-a8cb-707398f71b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322410673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3322410673
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3262400651
Short name T881
Test name
Test status
Simulation time 956303878 ps
CPU time 4.21 seconds
Started Jul 05 05:12:20 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 208232 kb
Host smart-a6ca2479-7c20-413a-b1da-06a91c5e1eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262400651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3262400651
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1417235213
Short name T565
Test name
Test status
Simulation time 72087115 ps
CPU time 2.89 seconds
Started Jul 05 05:12:24 PM PDT 24
Finished Jul 05 05:12:28 PM PDT 24
Peak memory 207940 kb
Host smart-a523016e-f927-4bfe-a2a4-922ae9d5eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417235213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1417235213
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3778322453
Short name T847
Test name
Test status
Simulation time 510227221 ps
CPU time 4.35 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:26 PM PDT 24
Peak memory 208872 kb
Host smart-32e1d89d-933a-4d22-b9aa-0ff8ad16e6fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778322453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3778322453
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1277845314
Short name T221
Test name
Test status
Simulation time 236241702 ps
CPU time 6.84 seconds
Started Jul 05 05:12:25 PM PDT 24
Finished Jul 05 05:12:33 PM PDT 24
Peak memory 208328 kb
Host smart-9379e67c-c461-4457-9777-a471b53f5941
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277845314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1277845314
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.506864724
Short name T300
Test name
Test status
Simulation time 31115739867 ps
CPU time 80.88 seconds
Started Jul 05 05:12:23 PM PDT 24
Finished Jul 05 05:13:44 PM PDT 24
Peak memory 208544 kb
Host smart-2ca256bf-fd7f-4f1f-beca-60f7615efc03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506864724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.506864724
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2975124841
Short name T566
Test name
Test status
Simulation time 470105993 ps
CPU time 4.67 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:36 PM PDT 24
Peak memory 218288 kb
Host smart-091fa33f-a610-46bc-9346-fc88b9595f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975124841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2975124841
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.926496832
Short name T742
Test name
Test status
Simulation time 704782296 ps
CPU time 13.47 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:36 PM PDT 24
Peak memory 208492 kb
Host smart-5582a96a-4bf3-4fac-9e46-5edc811ce155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926496832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.926496832
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1880861929
Short name T701
Test name
Test status
Simulation time 404813725 ps
CPU time 10.33 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 222680 kb
Host smart-75c53812-35f4-478a-a5f9-3b8aa9a50c9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880861929 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1880861929
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.851166437
Short name T217
Test name
Test status
Simulation time 464308557 ps
CPU time 4.75 seconds
Started Jul 05 05:12:21 PM PDT 24
Finished Jul 05 05:12:27 PM PDT 24
Peak memory 210368 kb
Host smart-ca6e60c5-2f8d-4e2e-9178-b3b289320fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851166437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.851166437
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4208954970
Short name T388
Test name
Test status
Simulation time 65323808 ps
CPU time 3.07 seconds
Started Jul 05 05:12:31 PM PDT 24
Finished Jul 05 05:12:35 PM PDT 24
Peak memory 210052 kb
Host smart-1518495d-70c3-49f0-a5a4-84932e49de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208954970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4208954970
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1390819265
Short name T583
Test name
Test status
Simulation time 28347514 ps
CPU time 0.72 seconds
Started Jul 05 05:12:39 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 205912 kb
Host smart-0439313b-0f3e-4f47-9d33-0b7807c1dd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390819265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1390819265
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4189996921
Short name T628
Test name
Test status
Simulation time 36802450 ps
CPU time 2.97 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 214448 kb
Host smart-7c93a55c-ba2f-49c3-96ca-e2c1a8e40647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189996921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4189996921
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2393133453
Short name T9
Test name
Test status
Simulation time 66341748 ps
CPU time 3.41 seconds
Started Jul 05 05:12:32 PM PDT 24
Finished Jul 05 05:12:36 PM PDT 24
Peak memory 208764 kb
Host smart-e63d88c5-5e2e-400f-9168-e1b6402dba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393133453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2393133453
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1939834980
Short name T382
Test name
Test status
Simulation time 391327477 ps
CPU time 5.18 seconds
Started Jul 05 05:12:29 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 209784 kb
Host smart-087a0f2e-9357-4cda-807e-b664b6480717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939834980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1939834980
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.664638575
Short name T91
Test name
Test status
Simulation time 603442861 ps
CPU time 2.85 seconds
Started Jul 05 05:12:33 PM PDT 24
Finished Jul 05 05:12:37 PM PDT 24
Peak memory 214228 kb
Host smart-c3f78ec9-867a-44e4-b0dc-05a921dfb1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664638575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.664638575
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.4000188198
Short name T308
Test name
Test status
Simulation time 78336063 ps
CPU time 3.65 seconds
Started Jul 05 05:12:34 PM PDT 24
Finished Jul 05 05:12:38 PM PDT 24
Peak memory 214240 kb
Host smart-ff154022-5f83-49dc-adcc-89654df9c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000188198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.4000188198
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1881677098
Short name T196
Test name
Test status
Simulation time 265680988 ps
CPU time 4.24 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:35 PM PDT 24
Peak memory 210176 kb
Host smart-3f4644be-be8e-41f1-b8ac-10f8d37f2b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881677098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1881677098
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2249922005
Short name T331
Test name
Test status
Simulation time 595515613 ps
CPU time 7.94 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:39 PM PDT 24
Peak memory 208128 kb
Host smart-7601c31a-ebc6-4ce9-a5f5-56dfe3f97e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249922005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2249922005
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2546569528
Short name T914
Test name
Test status
Simulation time 218088921 ps
CPU time 2.66 seconds
Started Jul 05 05:12:32 PM PDT 24
Finished Jul 05 05:12:35 PM PDT 24
Peak memory 206796 kb
Host smart-23dcad19-6941-4835-8311-711332c39067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546569528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2546569528
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3690954419
Short name T224
Test name
Test status
Simulation time 84357612 ps
CPU time 2.54 seconds
Started Jul 05 05:12:30 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 207036 kb
Host smart-c3734fa8-ea7d-4996-9f81-a76dfc55d0ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690954419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3690954419
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1957123990
Short name T837
Test name
Test status
Simulation time 406349584 ps
CPU time 5.91 seconds
Started Jul 05 05:12:29 PM PDT 24
Finished Jul 05 05:12:36 PM PDT 24
Peak memory 207960 kb
Host smart-eff0d261-609b-4787-8e22-a05a512d11f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957123990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1957123990
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.568552190
Short name T780
Test name
Test status
Simulation time 140625323 ps
CPU time 3.97 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 209052 kb
Host smart-e9a252ff-307f-4098-8b7e-dec730e8448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568552190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.568552190
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2341104220
Short name T434
Test name
Test status
Simulation time 54712101 ps
CPU time 2.47 seconds
Started Jul 05 05:12:31 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 208416 kb
Host smart-e5050753-602e-4e71-9b27-b3b1210b1b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341104220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2341104220
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.4251332714
Short name T186
Test name
Test status
Simulation time 375863655 ps
CPU time 8.96 seconds
Started Jul 05 05:12:35 PM PDT 24
Finished Jul 05 05:12:45 PM PDT 24
Peak memory 222556 kb
Host smart-d1f1a4c4-2d4c-47d9-ac5c-1c24635a2ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251332714 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.4251332714
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4134875634
Short name T111
Test name
Test status
Simulation time 3530529485 ps
CPU time 22 seconds
Started Jul 05 05:12:29 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 208560 kb
Host smart-51b1174f-0685-4db8-9dab-eeb2a2d94bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134875634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4134875634
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3906137755
Short name T392
Test name
Test status
Simulation time 52235332 ps
CPU time 1.93 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:46 PM PDT 24
Peak memory 209708 kb
Host smart-2769492a-c0d3-49d9-9bda-9605a2e66624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906137755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3906137755
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.32844704
Short name T815
Test name
Test status
Simulation time 9033216 ps
CPU time 0.69 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:44 PM PDT 24
Peak memory 205952 kb
Host smart-8e5f9363-7325-46a6-95c1-839d7a59c03d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.32844704
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4192108524
Short name T602
Test name
Test status
Simulation time 67595989 ps
CPU time 3.06 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 210676 kb
Host smart-ead36b9a-0f0a-4b6b-94bd-590b1b5be4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192108524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4192108524
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3659689320
Short name T683
Test name
Test status
Simulation time 365193277 ps
CPU time 2.69 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 207692 kb
Host smart-bf006894-42e7-4c5a-a90a-d3d033bd79a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659689320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3659689320
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3959390214
Short name T752
Test name
Test status
Simulation time 44796872 ps
CPU time 2.6 seconds
Started Jul 05 05:12:35 PM PDT 24
Finished Jul 05 05:12:39 PM PDT 24
Peak memory 222312 kb
Host smart-94b6ad4d-c521-44e7-931e-19a0527bc91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959390214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3959390214
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.251419694
Short name T618
Test name
Test status
Simulation time 1102377758 ps
CPU time 6.76 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:55 PM PDT 24
Peak memory 218336 kb
Host smart-816daf0c-62d4-4e02-b463-beedb26744d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251419694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.251419694
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2780015186
Short name T257
Test name
Test status
Simulation time 184876716 ps
CPU time 7.03 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 208156 kb
Host smart-2c462761-74c4-41d0-bdc4-0e8045f3d00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780015186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2780015186
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3094670625
Short name T45
Test name
Test status
Simulation time 617384491 ps
CPU time 7.36 seconds
Started Jul 05 05:12:38 PM PDT 24
Finished Jul 05 05:12:47 PM PDT 24
Peak memory 208788 kb
Host smart-26606977-cc44-4b81-8c26-0577d9ffaef5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094670625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3094670625
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3202201457
Short name T227
Test name
Test status
Simulation time 311214639 ps
CPU time 2.6 seconds
Started Jul 05 05:12:40 PM PDT 24
Finished Jul 05 05:12:44 PM PDT 24
Peak memory 206860 kb
Host smart-899b84ac-0e61-4b34-98d5-7e73d62b6f1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202201457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3202201457
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2638554065
Short name T521
Test name
Test status
Simulation time 446186179 ps
CPU time 2.7 seconds
Started Jul 05 05:12:37 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 208952 kb
Host smart-0b9766ad-435a-4f34-a2ce-fb45deb7d0e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638554065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2638554065
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2251728103
Short name T228
Test name
Test status
Simulation time 1623702479 ps
CPU time 4.42 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 208240 kb
Host smart-9913a14f-8f4f-4479-8a3d-77f842711228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251728103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2251728103
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.38015867
Short name T401
Test name
Test status
Simulation time 124612891 ps
CPU time 3.65 seconds
Started Jul 05 05:12:38 PM PDT 24
Finished Jul 05 05:12:43 PM PDT 24
Peak memory 206848 kb
Host smart-25735552-46e8-47a2-8815-ba38428965f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38015867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.38015867
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.957994574
Short name T337
Test name
Test status
Simulation time 955950235 ps
CPU time 8.4 seconds
Started Jul 05 05:12:40 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 215924 kb
Host smart-5f9ab56c-6534-413b-aed0-047271aa1f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957994574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.957994574
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.99823941
Short name T460
Test name
Test status
Simulation time 62667021 ps
CPU time 3.32 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:41 PM PDT 24
Peak memory 214420 kb
Host smart-07620d49-e38e-4c97-80e5-e4aae4a4179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99823941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.99823941
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.59014286
Short name T591
Test name
Test status
Simulation time 302652392 ps
CPU time 1.97 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 209936 kb
Host smart-6df14b00-401c-4b60-a740-2b1f519fc965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59014286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.59014286
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2142221320
Short name T887
Test name
Test status
Simulation time 40478504 ps
CPU time 0.73 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:38 PM PDT 24
Peak memory 205948 kb
Host smart-778419f6-9b5e-49e0-9520-396437c39aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142221320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2142221320
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2681064530
Short name T428
Test name
Test status
Simulation time 238534369 ps
CPU time 4.9 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 215356 kb
Host smart-417837d9-2f1f-4c07-a569-2846fcfe435b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681064530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2681064530
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1882970412
Short name T21
Test name
Test status
Simulation time 137720138 ps
CPU time 3.87 seconds
Started Jul 05 05:12:39 PM PDT 24
Finished Jul 05 05:12:45 PM PDT 24
Peak memory 221764 kb
Host smart-e39fc239-056e-485a-8467-4a3c10f86f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882970412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1882970412
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.324853221
Short name T75
Test name
Test status
Simulation time 101317062 ps
CPU time 3.91 seconds
Started Jul 05 05:12:37 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 208052 kb
Host smart-1349b3ad-1f7c-43fb-8823-20999cb6973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324853221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.324853221
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1614874243
Short name T327
Test name
Test status
Simulation time 107140193 ps
CPU time 2.29 seconds
Started Jul 05 05:12:38 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 214304 kb
Host smart-da95a528-ac4d-475b-93d5-201c6760def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614874243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1614874243
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.371950971
Short name T385
Test name
Test status
Simulation time 326710562 ps
CPU time 2.85 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 214240 kb
Host smart-4e3cf6c9-30a4-44d8-a415-318736b7c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371950971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.371950971
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2352777650
Short name T584
Test name
Test status
Simulation time 143412692 ps
CPU time 5.52 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 222388 kb
Host smart-e261abfe-255e-4afc-a1d9-79eb2b9372ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352777650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2352777650
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4181107342
Short name T269
Test name
Test status
Simulation time 84203922 ps
CPU time 3.31 seconds
Started Jul 05 05:12:37 PM PDT 24
Finished Jul 05 05:12:41 PM PDT 24
Peak memory 218600 kb
Host smart-55abd7b1-3e22-470a-8d75-eea40d81bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181107342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4181107342
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.264672106
Short name T603
Test name
Test status
Simulation time 1393413900 ps
CPU time 4.98 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:42 PM PDT 24
Peak memory 207868 kb
Host smart-a9db3515-6f92-4534-b53d-fd0fc0b99c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264672106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.264672106
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.833510842
Short name T882
Test name
Test status
Simulation time 108137934 ps
CPU time 3.32 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 208784 kb
Host smart-45e4a738-9135-4b47-b966-5a2577776024
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833510842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.833510842
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3442813018
Short name T665
Test name
Test status
Simulation time 138920641 ps
CPU time 3.45 seconds
Started Jul 05 05:20:02 PM PDT 24
Finished Jul 05 05:20:06 PM PDT 24
Peak memory 208696 kb
Host smart-4b495b2e-0b69-4e0e-ab26-f8c01645d4a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442813018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3442813018
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2658616265
Short name T270
Test name
Test status
Simulation time 410518627 ps
CPU time 3.32 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 207956 kb
Host smart-a595c3b5-8882-43c4-98d8-4db33cd4f398
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658616265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2658616265
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2892576167
Short name T535
Test name
Test status
Simulation time 62319276 ps
CPU time 2.52 seconds
Started Jul 05 05:12:36 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 207676 kb
Host smart-3b2a9417-e12f-4cd5-bd99-9dffebc3b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892576167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2892576167
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2136040762
Short name T727
Test name
Test status
Simulation time 402151622 ps
CPU time 2.7 seconds
Started Jul 05 05:12:40 PM PDT 24
Finished Jul 05 05:12:44 PM PDT 24
Peak memory 208384 kb
Host smart-659d4220-8abf-4fe4-8a1a-551941e8fac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136040762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2136040762
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.269420359
Short name T819
Test name
Test status
Simulation time 304517962 ps
CPU time 12.67 seconds
Started Jul 05 05:12:40 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 222636 kb
Host smart-48793780-5269-43fe-86ea-49cf899a6e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269420359 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.269420359
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1342484642
Short name T62
Test name
Test status
Simulation time 1270064032 ps
CPU time 2.92 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:47 PM PDT 24
Peak memory 210516 kb
Host smart-4fb493ce-138d-4eab-950f-a4d8a97c82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342484642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1342484642
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1363599687
Short name T898
Test name
Test status
Simulation time 21373408 ps
CPU time 0.78 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 206004 kb
Host smart-0a329237-c01d-41a4-935a-20cd828b4770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363599687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1363599687
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.227183742
Short name T750
Test name
Test status
Simulation time 70912542 ps
CPU time 3.1 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 214316 kb
Host smart-e974661e-ed9d-492b-b62c-696f83076471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227183742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.227183742
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2555019114
Short name T338
Test name
Test status
Simulation time 186186801 ps
CPU time 2.14 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 207300 kb
Host smart-bdc871ab-b788-4e48-81c1-d274cac9fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555019114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2555019114
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1862996097
Short name T98
Test name
Test status
Simulation time 180923436 ps
CPU time 4.65 seconds
Started Jul 05 05:12:46 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 209140 kb
Host smart-e6cceaf0-fd27-4126-bfeb-bf3a0f0b23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862996097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1862996097
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4102770396
Short name T774
Test name
Test status
Simulation time 231340758 ps
CPU time 3.63 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 214276 kb
Host smart-c86df9df-5d52-4b20-a301-d448f2898be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102770396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4102770396
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.775903969
Short name T544
Test name
Test status
Simulation time 87251935 ps
CPU time 4.16 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 214332 kb
Host smart-bb51c463-d749-4aac-8d6b-18750586613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775903969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.775903969
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.851224901
Short name T805
Test name
Test status
Simulation time 915481143 ps
CPU time 5.75 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 214244 kb
Host smart-288b5c34-898e-45d9-aa43-d7b0ba617241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851224901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.851224901
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.599137798
Short name T311
Test name
Test status
Simulation time 130192559 ps
CPU time 3.12 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 208580 kb
Host smart-f1a5763f-c23b-4f4e-b115-4b6c0b03fc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599137798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.599137798
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3240991456
Short name T717
Test name
Test status
Simulation time 217224388 ps
CPU time 7.85 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 208052 kb
Host smart-6e548334-e27b-49f4-887f-2cb871b9701d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240991456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3240991456
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3121012208
Short name T737
Test name
Test status
Simulation time 418243306 ps
CPU time 6.04 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 207956 kb
Host smart-d051558c-8d90-42c5-b6b9-390c18c9e5a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121012208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3121012208
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1791734192
Short name T635
Test name
Test status
Simulation time 39317894 ps
CPU time 2.02 seconds
Started Jul 05 05:12:46 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 208916 kb
Host smart-488f5d61-4e5e-43df-82df-3837774c1f19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791734192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1791734192
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2503965714
Short name T612
Test name
Test status
Simulation time 71825121 ps
CPU time 2.1 seconds
Started Jul 05 05:12:46 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 208092 kb
Host smart-88f2d7f8-7326-475f-9284-56c6b11c3dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503965714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2503965714
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.368402438
Short name T814
Test name
Test status
Simulation time 69132338 ps
CPU time 2.3 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 206824 kb
Host smart-7585a07f-c02b-4328-9234-13513983ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368402438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.368402438
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3823952838
Short name T351
Test name
Test status
Simulation time 1570684477 ps
CPU time 28.35 seconds
Started Jul 05 05:12:42 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 215076 kb
Host smart-ff9be8aa-9021-406f-9a96-c56370cb88b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823952838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3823952838
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3430966622
Short name T125
Test name
Test status
Simulation time 956804867 ps
CPU time 8.25 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 220596 kb
Host smart-235b19c9-1ce4-4b55-8a92-4d59f9a121f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430966622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3430966622
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1244012113
Short name T379
Test name
Test status
Simulation time 93339028 ps
CPU time 4.23 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 214388 kb
Host smart-f4688031-5031-408a-92e5-7639c1b4f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244012113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1244012113
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3395758302
Short name T391
Test name
Test status
Simulation time 258501958 ps
CPU time 2.9 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 209700 kb
Host smart-815783a8-715c-41aa-9533-3ef90dcb95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395758302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3395758302
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.436146844
Short name T107
Test name
Test status
Simulation time 64920348 ps
CPU time 0.83 seconds
Started Jul 05 05:10:54 PM PDT 24
Finished Jul 05 05:10:56 PM PDT 24
Peak memory 205940 kb
Host smart-872c5121-4807-4305-a587-2568ad838ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436146844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.436146844
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1819275301
Short name T575
Test name
Test status
Simulation time 49156045 ps
CPU time 1.95 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 218316 kb
Host smart-e4d44281-a250-422b-ba11-a7d6b731553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819275301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1819275301
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1532633836
Short name T47
Test name
Test status
Simulation time 60741395 ps
CPU time 2.9 seconds
Started Jul 05 05:10:45 PM PDT 24
Finished Jul 05 05:10:49 PM PDT 24
Peak memory 214392 kb
Host smart-4e8b8766-35e2-4ea2-96fa-ba8c5db5a0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532633836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1532633836
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4251957663
Short name T93
Test name
Test status
Simulation time 1655268337 ps
CPU time 43.21 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 214312 kb
Host smart-fc9ebeb9-8761-4177-94d7-65a4e34c893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251957663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4251957663
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1033338306
Short name T347
Test name
Test status
Simulation time 55338275 ps
CPU time 3.4 seconds
Started Jul 05 05:10:44 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 214264 kb
Host smart-b3d019d6-1bd9-42c3-93d5-010b6ffb72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033338306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1033338306
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1826873727
Short name T897
Test name
Test status
Simulation time 38712694 ps
CPU time 2.33 seconds
Started Jul 05 05:10:46 PM PDT 24
Finished Jul 05 05:10:49 PM PDT 24
Peak memory 209560 kb
Host smart-76ea4d27-d0b1-4d50-94ba-65ade251998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826873727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1826873727
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.28048055
Short name T499
Test name
Test status
Simulation time 267993531 ps
CPU time 6.54 seconds
Started Jul 05 05:10:43 PM PDT 24
Finished Jul 05 05:10:50 PM PDT 24
Peak memory 209812 kb
Host smart-9cd52f4c-e07d-45bd-bd2d-d4a68f4dc61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28048055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.28048055
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3496673250
Short name T320
Test name
Test status
Simulation time 26895748 ps
CPU time 1.86 seconds
Started Jul 05 05:10:37 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 208476 kb
Host smart-7c6f1131-d6ff-4e3d-bd1e-5955a1ac9af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496673250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3496673250
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3538370042
Short name T730
Test name
Test status
Simulation time 394274596 ps
CPU time 7.33 seconds
Started Jul 05 05:10:37 PM PDT 24
Finished Jul 05 05:10:46 PM PDT 24
Peak memory 207072 kb
Host smart-a14f12cb-f44c-4205-850b-8951bb96ca5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538370042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3538370042
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3117982397
Short name T465
Test name
Test status
Simulation time 93564380 ps
CPU time 1.96 seconds
Started Jul 05 05:10:39 PM PDT 24
Finished Jul 05 05:10:43 PM PDT 24
Peak memory 208608 kb
Host smart-36a23b24-90a1-4b4b-bbc5-d1170e70f69e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117982397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3117982397
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1146393293
Short name T496
Test name
Test status
Simulation time 22364544560 ps
CPU time 85.18 seconds
Started Jul 05 05:10:42 PM PDT 24
Finished Jul 05 05:12:07 PM PDT 24
Peak memory 209308 kb
Host smart-7edd386b-e3b4-4524-9e55-b4ad6d8892fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146393293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1146393293
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2567921007
Short name T403
Test name
Test status
Simulation time 251306902 ps
CPU time 2.34 seconds
Started Jul 05 05:10:44 PM PDT 24
Finished Jul 05 05:10:47 PM PDT 24
Peak memory 208796 kb
Host smart-fb81d80f-c233-4e87-900a-82ad5acb2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567921007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2567921007
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2041464160
Short name T646
Test name
Test status
Simulation time 502985004 ps
CPU time 5.6 seconds
Started Jul 05 05:10:46 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 208384 kb
Host smart-2142b339-a0a1-4fa9-a458-09666a71dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041464160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2041464160
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3104508388
Short name T126
Test name
Test status
Simulation time 547142215 ps
CPU time 18.08 seconds
Started Jul 05 05:11:20 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 222496 kb
Host smart-5651d6fd-3e17-4e91-9a99-38b210e35405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104508388 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3104508388
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1280456420
Short name T374
Test name
Test status
Simulation time 128857904 ps
CPU time 5.91 seconds
Started Jul 05 05:10:54 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 210204 kb
Host smart-acc2642e-c926-439d-9883-8cb240953ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280456420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1280456420
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.845157852
Short name T621
Test name
Test status
Simulation time 343300515 ps
CPU time 7.41 seconds
Started Jul 05 05:10:45 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 210548 kb
Host smart-fcfafc22-eb1c-42bb-a200-c209eea8bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845157852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.845157852
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3122332254
Short name T14
Test name
Test status
Simulation time 15302602 ps
CPU time 0.94 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 206028 kb
Host smart-be39af4f-0c97-4ac8-ba52-0ce0e8155034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122332254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3122332254
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3607267826
Short name T395
Test name
Test status
Simulation time 183469451 ps
CPU time 2.67 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 215360 kb
Host smart-9a0eba70-0463-46dc-923a-7a2d796e3612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607267826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3607267826
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1919209897
Short name T858
Test name
Test status
Simulation time 232198891 ps
CPU time 2.32 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:48 PM PDT 24
Peak memory 209820 kb
Host smart-cf688686-150a-487c-bbc7-bf04c871fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919209897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1919209897
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.315236598
Short name T687
Test name
Test status
Simulation time 221780774 ps
CPU time 2.26 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 207532 kb
Host smart-711d3a01-605c-4abe-89e8-03e80e816cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315236598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.315236598
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2728201882
Short name T276
Test name
Test status
Simulation time 112954506 ps
CPU time 3.37 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 214236 kb
Host smart-6224fcd8-38d5-416b-ad7f-cde281a1f054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728201882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2728201882
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1864363920
Short name T6
Test name
Test status
Simulation time 82327860 ps
CPU time 3.56 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 222384 kb
Host smart-a7ce0dbb-aff1-437a-bb1d-0b35ee4d53ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864363920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1864363920
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4136185447
Short name T256
Test name
Test status
Simulation time 73049636 ps
CPU time 3.57 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 209848 kb
Host smart-c2cc7141-5362-4bcf-b26a-cacbb6ebadb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136185447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4136185447
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3640872356
Short name T634
Test name
Test status
Simulation time 103945810 ps
CPU time 2.8 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 208248 kb
Host smart-8297c5f2-417f-4b1f-a81f-fa8645d0f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640872356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3640872356
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3362119513
Short name T484
Test name
Test status
Simulation time 223436075 ps
CPU time 3.14 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 208816 kb
Host smart-b607e224-25cc-4000-b5e3-c77f63f2e15d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362119513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3362119513
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.866124073
Short name T552
Test name
Test status
Simulation time 52727871 ps
CPU time 2.78 seconds
Started Jul 05 05:12:44 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 207016 kb
Host smart-8b88750b-4f50-4f9d-99c7-55a27c40c105
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866124073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.866124073
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1427937628
Short name T507
Test name
Test status
Simulation time 56959501 ps
CPU time 2.87 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:53 PM PDT 24
Peak memory 207052 kb
Host smart-f3dc71b5-74a1-4b6e-9279-0e7ad590581d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427937628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1427937628
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3875356495
Short name T723
Test name
Test status
Simulation time 267387621 ps
CPU time 2.98 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 209288 kb
Host smart-bc4c7307-3d82-435e-960d-be4e71baa0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875356495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3875356495
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3985456357
Short name T629
Test name
Test status
Simulation time 153860367 ps
CPU time 2.54 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:12:55 PM PDT 24
Peak memory 206776 kb
Host smart-c630666d-bc6d-4a08-a0a5-abe2069af0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985456357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3985456357
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3549316555
Short name T280
Test name
Test status
Simulation time 1257547601 ps
CPU time 5.25 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 218100 kb
Host smart-bea4f2b5-a818-46d0-8864-acde185e340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549316555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3549316555
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.849317607
Short name T503
Test name
Test status
Simulation time 2233918326 ps
CPU time 25.13 seconds
Started Jul 05 05:12:46 PM PDT 24
Finished Jul 05 05:13:13 PM PDT 24
Peak memory 210892 kb
Host smart-c0c34fe0-a261-4331-813d-45c34d368b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849317607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.849317607
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2673528435
Short name T103
Test name
Test status
Simulation time 58879642 ps
CPU time 0.74 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:12:59 PM PDT 24
Peak memory 206016 kb
Host smart-2bd062d9-e1f3-49fb-bdf4-aaf368df3211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673528435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2673528435
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1362805282
Short name T877
Test name
Test status
Simulation time 118576545 ps
CPU time 2.58 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 214212 kb
Host smart-7ead399d-f4b2-476c-80f7-3539c2860d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362805282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1362805282
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3732094946
Short name T40
Test name
Test status
Simulation time 68222950 ps
CPU time 1.88 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 209248 kb
Host smart-f127bb1d-bdf0-4398-b0a2-4ecafa042a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732094946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3732094946
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.653496638
Short name T738
Test name
Test status
Simulation time 185319183 ps
CPU time 2.42 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 218552 kb
Host smart-212a9767-017f-4ebd-a417-813145abaaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653496638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.653496638
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2923072834
Short name T820
Test name
Test status
Simulation time 126375039 ps
CPU time 5.33 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 214380 kb
Host smart-aed8f0a1-0234-4425-af3f-a299a42f8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923072834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2923072834
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1189023357
Short name T277
Test name
Test status
Simulation time 125140007 ps
CPU time 4.36 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 220984 kb
Host smart-66c1023d-edb9-4aa3-b3ea-80e43d5a8284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189023357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1189023357
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1567807932
Short name T549
Test name
Test status
Simulation time 79209168 ps
CPU time 3.68 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 209628 kb
Host smart-4eb5d2ab-0f63-45bc-b223-7916ca05bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567807932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1567807932
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3630502069
Short name T481
Test name
Test status
Simulation time 1116891252 ps
CPU time 6.4 seconds
Started Jul 05 05:12:43 PM PDT 24
Finished Jul 05 05:12:50 PM PDT 24
Peak memory 214420 kb
Host smart-d18cd857-00dd-42d2-9553-117095300b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630502069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3630502069
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1939184671
Short name T526
Test name
Test status
Simulation time 203281804 ps
CPU time 5.97 seconds
Started Jul 05 05:12:47 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 207984 kb
Host smart-7912bea2-5f71-4315-bee7-632881b7e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939184671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1939184671
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1202035442
Short name T716
Test name
Test status
Simulation time 1697587904 ps
CPU time 4.62 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 208536 kb
Host smart-866aa664-9255-4abc-8c92-de2798d09f07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202035442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1202035442
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1461239191
Short name T548
Test name
Test status
Simulation time 89694408 ps
CPU time 2.14 seconds
Started Jul 05 05:12:45 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 208664 kb
Host smart-824856d4-2548-4119-8504-825208a5b230
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461239191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1461239191
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2180150775
Short name T613
Test name
Test status
Simulation time 37154717 ps
CPU time 2.74 seconds
Started Jul 05 05:12:46 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 208652 kb
Host smart-703c0d0f-bf15-44b5-a25c-82d81d172356
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180150775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2180150775
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1650226795
Short name T771
Test name
Test status
Simulation time 756956093 ps
CPU time 14.46 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:14 PM PDT 24
Peak memory 214340 kb
Host smart-28623efc-5846-447a-9314-c4a30378f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650226795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1650226795
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1313631145
Short name T445
Test name
Test status
Simulation time 98181052 ps
CPU time 2.55 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 206880 kb
Host smart-bcd97b0d-4fe2-473d-97ce-41327cf586d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313631145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1313631145
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3490213800
Short name T57
Test name
Test status
Simulation time 1114623365 ps
CPU time 40.74 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:13:36 PM PDT 24
Peak memory 216840 kb
Host smart-9a4156f4-206c-4211-9bd0-c5c544d1fcad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490213800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3490213800
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3087844184
Short name T68
Test name
Test status
Simulation time 297974965 ps
CPU time 12.3 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:13:05 PM PDT 24
Peak memory 221364 kb
Host smart-a7a829a4-e3e4-4f5d-932e-5a5cf0ace49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087844184 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3087844184
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3107628650
Short name T482
Test name
Test status
Simulation time 40370376 ps
CPU time 2.53 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 214420 kb
Host smart-90497db8-4237-4550-ac34-2bc2d97950d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107628650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3107628650
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1713105907
Short name T765
Test name
Test status
Simulation time 263276392 ps
CPU time 1.54 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 210488 kb
Host smart-e848eabc-241c-47a8-a071-d0f5c2d5adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713105907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1713105907
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4011518752
Short name T840
Test name
Test status
Simulation time 10562071 ps
CPU time 0.84 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 205952 kb
Host smart-6e5824e3-a834-4b9b-bf37-e273448fec6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011518752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4011518752
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.351867956
Short name T420
Test name
Test status
Simulation time 411712990 ps
CPU time 3.16 seconds
Started Jul 05 05:12:53 PM PDT 24
Finished Jul 05 05:12:59 PM PDT 24
Peak memory 214352 kb
Host smart-eecadc33-c9ab-4637-923a-6b22a78a004b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351867956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.351867956
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.490617755
Short name T30
Test name
Test status
Simulation time 122561606 ps
CPU time 1.73 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 209108 kb
Host smart-d00c8bef-c885-49b0-ad04-448d2ac36531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490617755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.490617755
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1145259663
Short name T73
Test name
Test status
Simulation time 74506854 ps
CPU time 2.15 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 214328 kb
Host smart-b9d798a0-f70a-4d7f-b7c4-dd3183574bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145259663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1145259663
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.135672277
Short name T370
Test name
Test status
Simulation time 168893784 ps
CPU time 2.33 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:56 PM PDT 24
Peak memory 214336 kb
Host smart-ece7821d-c3fd-4f65-b241-4f9d43f8caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135672277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.135672277
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.339412332
Short name T292
Test name
Test status
Simulation time 215594342 ps
CPU time 3.3 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 214260 kb
Host smart-2f6ae53c-39c2-4dd2-8028-c0d6e501f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339412332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.339412332
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1946561760
Short name T242
Test name
Test status
Simulation time 213383106 ps
CPU time 5.08 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 210476 kb
Host smart-7a2da95c-495a-444b-8569-b7f92751416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946561760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1946561760
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.42648084
Short name T513
Test name
Test status
Simulation time 147090644 ps
CPU time 2.62 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 218192 kb
Host smart-b0e406cf-8902-48a9-9e91-f16f4735c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42648084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.42648084
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1526493996
Short name T668
Test name
Test status
Simulation time 316493725 ps
CPU time 8.4 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 208764 kb
Host smart-7739f1f7-47c4-46fb-887c-31fefc89edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526493996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1526493996
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2764256273
Short name T678
Test name
Test status
Simulation time 292097975 ps
CPU time 2.11 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 206968 kb
Host smart-7a89c7ae-df95-4b78-8eb5-38c650bc9d48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764256273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2764256273
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3065150002
Short name T487
Test name
Test status
Simulation time 2607528810 ps
CPU time 20.83 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 207080 kb
Host smart-e7511802-6233-44dd-b08a-23ebf749f0a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065150002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3065150002
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1526589233
Short name T908
Test name
Test status
Simulation time 250194273 ps
CPU time 3.35 seconds
Started Jul 05 05:12:50 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 208644 kb
Host smart-6e6b8367-bda0-412e-892c-cbde850078e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526589233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1526589233
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3226843256
Short name T129
Test name
Test status
Simulation time 175062219 ps
CPU time 2.45 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 207032 kb
Host smart-6ad16583-c74f-4a5b-b299-3529f0bbd0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226843256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3226843256
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2024760871
Short name T442
Test name
Test status
Simulation time 1839427496 ps
CPU time 15.88 seconds
Started Jul 05 05:12:53 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 207972 kb
Host smart-825d9d45-f23a-4cca-aa8d-8bc0d7ac62a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024760871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2024760871
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.348591353
Short name T406
Test name
Test status
Simulation time 363009820 ps
CPU time 16.34 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 222712 kb
Host smart-4e120a7e-6857-4a6e-8d55-cfb087b4b441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348591353 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.348591353
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3163965710
Short name T619
Test name
Test status
Simulation time 1998254528 ps
CPU time 7.55 seconds
Started Jul 05 05:12:48 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 207392 kb
Host smart-b6b1e069-d642-400a-9732-732c58757cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163965710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3163965710
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4195284457
Short name T666
Test name
Test status
Simulation time 292189192 ps
CPU time 2.78 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 210552 kb
Host smart-ebaf6c5b-4a7a-47fb-9ef9-5ac0f611d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195284457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4195284457
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1469639835
Short name T510
Test name
Test status
Simulation time 52562678 ps
CPU time 0.91 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:04 PM PDT 24
Peak memory 206124 kb
Host smart-7107eac6-da51-4dcd-9ac7-ef19462a719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469639835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1469639835
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.822175953
Short name T254
Test name
Test status
Simulation time 765250957 ps
CPU time 11.61 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:15 PM PDT 24
Peak memory 214308 kb
Host smart-d3cda574-45a3-4fe9-99ae-6e9d9878a624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822175953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.822175953
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3468875537
Short name T757
Test name
Test status
Simulation time 79092814 ps
CPU time 2.78 seconds
Started Jul 05 05:12:59 PM PDT 24
Finished Jul 05 05:13:04 PM PDT 24
Peak memory 215892 kb
Host smart-da63ed5d-921c-469f-832e-bdbd387c906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468875537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3468875537
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3425841093
Short name T906
Test name
Test status
Simulation time 505040656 ps
CPU time 3.52 seconds
Started Jul 05 05:12:59 PM PDT 24
Finished Jul 05 05:13:05 PM PDT 24
Peak memory 216260 kb
Host smart-eb47b7a0-8857-438d-bdf7-4e3aee0c02b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425841093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3425841093
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3119277918
Short name T92
Test name
Test status
Simulation time 139081049 ps
CPU time 6.16 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 214316 kb
Host smart-14733552-d903-4d0b-b0da-5372ec6a3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119277918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3119277918
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3562769389
Short name T782
Test name
Test status
Simulation time 130377058 ps
CPU time 3.73 seconds
Started Jul 05 05:13:03 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 214268 kb
Host smart-9fefff0d-54ee-4739-a37f-4295e376961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562769389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3562769389
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4293968654
Short name T672
Test name
Test status
Simulation time 194486939 ps
CPU time 4.36 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:07 PM PDT 24
Peak memory 222500 kb
Host smart-2fa65dd1-af57-450f-adc9-7e3903997209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293968654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4293968654
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1653291302
Short name T758
Test name
Test status
Simulation time 122502910 ps
CPU time 2.45 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 207300 kb
Host smart-653608f7-baff-4cde-af68-9162e4644bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653291302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1653291302
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3261400366
Short name T777
Test name
Test status
Simulation time 34100238 ps
CPU time 2.26 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 206964 kb
Host smart-544a96ac-e18f-4a1d-8f19-56cdeadbbf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261400366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3261400366
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1254383416
Short name T579
Test name
Test status
Simulation time 80498005 ps
CPU time 1.77 seconds
Started Jul 05 05:12:49 PM PDT 24
Finished Jul 05 05:12:54 PM PDT 24
Peak memory 206720 kb
Host smart-cacef0dd-b2f5-470c-aa8a-ee0bfb981e37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254383416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1254383416
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1416167715
Short name T220
Test name
Test status
Simulation time 131093618 ps
CPU time 3.14 seconds
Started Jul 05 05:12:52 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 206800 kb
Host smart-16989595-c38e-4809-bf29-70f69523c168
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416167715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1416167715
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3737037467
Short name T798
Test name
Test status
Simulation time 318195385 ps
CPU time 3.97 seconds
Started Jul 05 05:12:55 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 208616 kb
Host smart-ec4493f9-318d-4fe0-ac66-ca5f488ccb1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737037467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3737037467
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1954178827
Short name T295
Test name
Test status
Simulation time 1996186348 ps
CPU time 10.16 seconds
Started Jul 05 05:13:02 PM PDT 24
Finished Jul 05 05:13:14 PM PDT 24
Peak memory 217988 kb
Host smart-eb57d32b-16a7-4408-973c-1f3d19c0d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954178827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1954178827
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.415808735
Short name T866
Test name
Test status
Simulation time 53702567 ps
CPU time 2.35 seconds
Started Jul 05 05:12:51 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 206876 kb
Host smart-dfd33b0e-c9f1-4710-a67a-f67da3dbe678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415808735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.415808735
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.929487769
Short name T649
Test name
Test status
Simulation time 107746108 ps
CPU time 3.51 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 207784 kb
Host smart-90a9fc03-3aa1-433e-a424-ece3f7d102e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929487769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.929487769
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3038957915
Short name T67
Test name
Test status
Simulation time 73675785 ps
CPU time 2.43 seconds
Started Jul 05 05:13:02 PM PDT 24
Finished Jul 05 05:13:07 PM PDT 24
Peak memory 209976 kb
Host smart-a1b9bcbf-c727-46bc-975a-73299a12e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038957915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3038957915
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3910010129
Short name T851
Test name
Test status
Simulation time 16898467 ps
CPU time 0.8 seconds
Started Jul 05 05:12:57 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 205908 kb
Host smart-d13cb3a6-72b7-4ddb-8b9d-ad9b6db160b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910010129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3910010129
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.632908723
Short name T271
Test name
Test status
Simulation time 167528840 ps
CPU time 2.95 seconds
Started Jul 05 05:12:59 PM PDT 24
Finished Jul 05 05:13:05 PM PDT 24
Peak memory 214336 kb
Host smart-76a300f3-3bea-426e-b93b-55a76934b218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632908723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.632908723
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.660024900
Short name T28
Test name
Test status
Simulation time 6579864131 ps
CPU time 25.15 seconds
Started Jul 05 05:12:57 PM PDT 24
Finished Jul 05 05:13:25 PM PDT 24
Peak memory 222884 kb
Host smart-d94ea7c5-04ff-4f90-8e63-3692ddb7ac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660024900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.660024900
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.506735956
Short name T307
Test name
Test status
Simulation time 2570051354 ps
CPU time 17.22 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 209908 kb
Host smart-9d0c9312-75a8-42ac-9165-425251646c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506735956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.506735956
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3333556125
Short name T386
Test name
Test status
Simulation time 717724521 ps
CPU time 3.77 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:07 PM PDT 24
Peak memory 214428 kb
Host smart-82b2a758-edd3-45ce-a85d-57efcdc493b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333556125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3333556125
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2035812138
Short name T760
Test name
Test status
Simulation time 163321528 ps
CPU time 3.4 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 214308 kb
Host smart-778b4e12-1d31-48bc-8ab6-5df851dafe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035812138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2035812138
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.472635931
Short name T637
Test name
Test status
Simulation time 170878282 ps
CPU time 3.08 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 220328 kb
Host smart-22ea4fe4-eb03-4f32-b14c-319eeabfd287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472635931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.472635931
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.108121832
Short name T872
Test name
Test status
Simulation time 231944093 ps
CPU time 3.61 seconds
Started Jul 05 05:13:03 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 218420 kb
Host smart-17298ae8-a20a-4c52-8034-b119878f1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108121832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.108121832
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.393836010
Short name T560
Test name
Test status
Simulation time 285873828 ps
CPU time 3.55 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:07 PM PDT 24
Peak memory 208876 kb
Host smart-75ba2686-27aa-4039-a2b0-a6a18e803c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393836010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.393836010
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.836835483
Short name T556
Test name
Test status
Simulation time 548039546 ps
CPU time 3.12 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:03 PM PDT 24
Peak memory 207036 kb
Host smart-279f7da4-6c0d-4af3-925f-69352aa3baf7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836835483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.836835483
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.200369741
Short name T493
Test name
Test status
Simulation time 154785219 ps
CPU time 2.3 seconds
Started Jul 05 05:12:57 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 206904 kb
Host smart-f3d3d136-b4ee-4806-8810-39f6efcc423d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200369741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.200369741
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2170763635
Short name T706
Test name
Test status
Simulation time 564923116 ps
CPU time 4.79 seconds
Started Jul 05 05:12:59 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 207036 kb
Host smart-09d05c12-6e6e-4362-abc9-2ead25f1f350
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170763635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2170763635
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2262951118
Short name T301
Test name
Test status
Simulation time 47401482 ps
CPU time 2.91 seconds
Started Jul 05 05:13:03 PM PDT 24
Finished Jul 05 05:13:08 PM PDT 24
Peak memory 209640 kb
Host smart-cd768ba2-50f5-458f-bb5b-890fc0d0a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262951118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2262951118
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2537718157
Short name T865
Test name
Test status
Simulation time 36155837 ps
CPU time 2.15 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 206864 kb
Host smart-8069a300-ec4b-4f7f-bced-2360c3203dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537718157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2537718157
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3188226912
Short name T417
Test name
Test status
Simulation time 53498702 ps
CPU time 3.47 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 209712 kb
Host smart-7f9af31c-1e03-48ab-b944-fd14f5846a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188226912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3188226912
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2231185493
Short name T567
Test name
Test status
Simulation time 175795038 ps
CPU time 2.31 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:05 PM PDT 24
Peak memory 210108 kb
Host smart-a6a9c49f-f8e1-4b39-9a0c-f04aab2f8cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231185493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2231185493
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.447722522
Short name T905
Test name
Test status
Simulation time 22538942 ps
CPU time 0.77 seconds
Started Jul 05 05:13:13 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 206008 kb
Host smart-470b6372-bdba-4ff3-b029-f6b5686a8b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447722522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.447722522
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2420312512
Short name T333
Test name
Test status
Simulation time 3185005665 ps
CPU time 28.16 seconds
Started Jul 05 05:12:57 PM PDT 24
Finished Jul 05 05:13:28 PM PDT 24
Peak memory 215880 kb
Host smart-762f726b-9ad7-475a-8565-88d33c17a19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420312512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2420312512
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4098931855
Short name T511
Test name
Test status
Simulation time 55592947 ps
CPU time 1.78 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 209276 kb
Host smart-111c0a90-0554-4383-b888-c18f8d5aaf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098931855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4098931855
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1943707091
Short name T909
Test name
Test status
Simulation time 618640189 ps
CPU time 5.1 seconds
Started Jul 05 05:13:11 PM PDT 24
Finished Jul 05 05:13:17 PM PDT 24
Peak memory 220464 kb
Host smart-98c926b2-b964-4826-a9de-b93e52e5a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943707091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1943707091
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1191255736
Short name T841
Test name
Test status
Simulation time 125749860 ps
CPU time 2.91 seconds
Started Jul 05 05:12:57 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 220004 kb
Host smart-9b541f66-59e6-406b-b168-94e90a96ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191255736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1191255736
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.664520138
Short name T108
Test name
Test status
Simulation time 913983568 ps
CPU time 21.42 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:22 PM PDT 24
Peak memory 208372 kb
Host smart-32ac3aee-de41-4db7-bc3e-a9ea5ff3869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664520138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.664520138
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.936748887
Short name T522
Test name
Test status
Simulation time 175840506 ps
CPU time 2.55 seconds
Started Jul 05 05:13:01 PM PDT 24
Finished Jul 05 05:13:06 PM PDT 24
Peak memory 206880 kb
Host smart-445ef88b-feb5-465d-a5ea-f239e085a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936748887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.936748887
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.78214184
Short name T223
Test name
Test status
Simulation time 484107225 ps
CPU time 4.35 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 206776 kb
Host smart-a437b383-7809-4c9c-98aa-43ab3a0a1914
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78214184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.78214184
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1595453654
Short name T476
Test name
Test status
Simulation time 134752953 ps
CPU time 3.56 seconds
Started Jul 05 05:12:58 PM PDT 24
Finished Jul 05 05:13:03 PM PDT 24
Peak memory 208572 kb
Host smart-f5734fee-355b-43ec-aee7-de7eebf123a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595453654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1595453654
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1126405532
Short name T630
Test name
Test status
Simulation time 365446557 ps
CPU time 4.36 seconds
Started Jul 05 05:13:00 PM PDT 24
Finished Jul 05 05:13:07 PM PDT 24
Peak memory 206892 kb
Host smart-f6530828-303b-43ef-8ecc-d123bf1d3a52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126405532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1126405532
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1935417109
Short name T644
Test name
Test status
Simulation time 102524650 ps
CPU time 1.94 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:10 PM PDT 24
Peak memory 215732 kb
Host smart-86e69f3c-7b3f-490a-a67c-ab8b30f3d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935417109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1935417109
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2905893727
Short name T554
Test name
Test status
Simulation time 125435684 ps
CPU time 2.8 seconds
Started Jul 05 05:12:56 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 208572 kb
Host smart-8bfc4007-934a-41b6-9bc9-a00327fbc1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905893727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2905893727
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3957232897
Short name T342
Test name
Test status
Simulation time 2419844389 ps
CPU time 71.59 seconds
Started Jul 05 05:13:07 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 215512 kb
Host smart-d9cf3ebf-5223-4b78-b1be-f902fe68aa5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957232897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3957232897
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2457470643
Short name T506
Test name
Test status
Simulation time 147631144 ps
CPU time 9.29 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 220448 kb
Host smart-220bcd9d-5956-4376-be24-438f61355ffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457470643 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2457470643
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1443805375
Short name T466
Test name
Test status
Simulation time 718060369 ps
CPU time 8.15 seconds
Started Jul 05 05:13:05 PM PDT 24
Finished Jul 05 05:13:15 PM PDT 24
Peak memory 218464 kb
Host smart-6d9a1aec-ee8f-4a01-9358-266296d4aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443805375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1443805375
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2172669328
Short name T110
Test name
Test status
Simulation time 62619467 ps
CPU time 2.47 seconds
Started Jul 05 05:13:08 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 209956 kb
Host smart-a33259e7-9272-42eb-9a20-76e9e36998a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172669328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2172669328
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4269740489
Short name T652
Test name
Test status
Simulation time 20289564 ps
CPU time 0.8 seconds
Started Jul 05 05:13:07 PM PDT 24
Finished Jul 05 05:13:10 PM PDT 24
Peak memory 206004 kb
Host smart-a18936b4-238c-4ef7-b00c-fbf60246d833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269740489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4269740489
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2924907597
Short name T18
Test name
Test status
Simulation time 24129590 ps
CPU time 1.55 seconds
Started Jul 05 05:13:08 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 207504 kb
Host smart-abf7e822-6abc-4651-b57b-2b8f62807eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924907597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2924907597
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2777567752
Short name T287
Test name
Test status
Simulation time 270384952 ps
CPU time 5.32 seconds
Started Jul 05 05:13:05 PM PDT 24
Finished Jul 05 05:13:13 PM PDT 24
Peak memory 207296 kb
Host smart-6b5b4774-c1de-48a6-a42a-762e16895a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777567752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2777567752
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1395356070
Short name T423
Test name
Test status
Simulation time 659654963 ps
CPU time 2.84 seconds
Started Jul 05 05:13:07 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 219100 kb
Host smart-3112d6e0-52ab-4f17-8c71-a6d102bb05c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395356070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1395356070
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1687412169
Short name T755
Test name
Test status
Simulation time 826683404 ps
CPU time 5.57 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 209540 kb
Host smart-aed862e3-e6d5-4c26-8428-e356066cceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687412169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1687412169
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.151260302
Short name T131
Test name
Test status
Simulation time 63097682 ps
CPU time 2.36 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 208576 kb
Host smart-7a174b32-63f2-40d5-b003-aa0153528ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151260302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.151260302
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1344596652
Short name T743
Test name
Test status
Simulation time 704146216 ps
CPU time 6.75 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:14 PM PDT 24
Peak memory 208580 kb
Host smart-26c383f6-3ec3-446e-a4ed-31fa0c59434e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344596652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1344596652
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2771110299
Short name T620
Test name
Test status
Simulation time 119698580 ps
CPU time 4.59 seconds
Started Jul 05 05:13:05 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 208744 kb
Host smart-eb566003-e872-4936-a70e-c62828f14aed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771110299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2771110299
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4243988257
Short name T570
Test name
Test status
Simulation time 541407294 ps
CPU time 4.23 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 206748 kb
Host smart-ab55e7d4-37d5-4882-897f-ae1ec80e223c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243988257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4243988257
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3951996039
Short name T633
Test name
Test status
Simulation time 5132182164 ps
CPU time 9.4 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:17 PM PDT 24
Peak memory 218352 kb
Host smart-56aa17ec-87fe-43ce-90a6-9d326edf1011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951996039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3951996039
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1054379997
Short name T469
Test name
Test status
Simulation time 84750756 ps
CPU time 3.14 seconds
Started Jul 05 05:13:11 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 208608 kb
Host smart-76f1c4d9-2620-4847-9df3-03fc3da35283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054379997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1054379997
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3242725711
Short name T199
Test name
Test status
Simulation time 29196820192 ps
CPU time 159.27 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:15:46 PM PDT 24
Peak memory 222564 kb
Host smart-3ea1b844-2640-4e19-9beb-76fe07de2e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242725711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3242725711
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.547112789
Short name T279
Test name
Test status
Simulation time 76477775 ps
CPU time 4.01 seconds
Started Jul 05 05:13:13 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 209804 kb
Host smart-5edd0dd2-6391-4197-ba33-da2c03c24194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547112789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.547112789
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1191792700
Short name T389
Test name
Test status
Simulation time 278664233 ps
CPU time 2.02 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:10 PM PDT 24
Peak memory 209816 kb
Host smart-977a77d2-b7a0-45f9-8ce8-94c1836c30b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191792700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1191792700
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4227165881
Short name T663
Test name
Test status
Simulation time 66238035 ps
CPU time 0.96 seconds
Started Jul 05 05:13:18 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 205940 kb
Host smart-0bcc2209-431f-4850-a524-792263aaeba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227165881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4227165881
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1664170358
Short name T890
Test name
Test status
Simulation time 47772186 ps
CPU time 3.4 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 215124 kb
Host smart-3cf21f86-ce79-459a-992b-add39acea15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664170358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1664170358
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1192576960
Short name T519
Test name
Test status
Simulation time 321998838 ps
CPU time 2.42 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 221692 kb
Host smart-4e616c46-3c81-4796-948c-5b8d46934615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192576960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1192576960
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4139408897
Short name T79
Test name
Test status
Simulation time 86534060 ps
CPU time 1.59 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 207604 kb
Host smart-2e5c8360-d28b-412a-b713-c4df3c8b9662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139408897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4139408897
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3054254085
Short name T720
Test name
Test status
Simulation time 9859450532 ps
CPU time 86.65 seconds
Started Jul 05 05:13:06 PM PDT 24
Finished Jul 05 05:14:34 PM PDT 24
Peak memory 214376 kb
Host smart-a11c5262-adf7-4148-8ea5-22ab32c68a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054254085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3054254085
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2173484095
Short name T369
Test name
Test status
Simulation time 76857040 ps
CPU time 2.95 seconds
Started Jul 05 05:13:08 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 214268 kb
Host smart-4dda7e67-2850-4573-91c0-940729fc8606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173484095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2173484095
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.649150266
Short name T901
Test name
Test status
Simulation time 253377374 ps
CPU time 3.55 seconds
Started Jul 05 05:13:13 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 215348 kb
Host smart-3bafe1f2-eba0-4483-9a19-bb8d956713a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649150266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.649150266
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3909560694
Short name T206
Test name
Test status
Simulation time 407508582 ps
CPU time 3.56 seconds
Started Jul 05 05:13:11 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 207924 kb
Host smart-b08bfa52-1d7d-4d4c-a43b-0f9ecb04aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909560694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3909560694
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3202729095
Short name T15
Test name
Test status
Simulation time 1436129683 ps
CPU time 4.83 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 206868 kb
Host smart-b4d30289-8853-4d39-b43b-97d108806223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202729095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3202729095
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3560019378
Short name T559
Test name
Test status
Simulation time 222684630 ps
CPU time 4 seconds
Started Jul 05 05:13:08 PM PDT 24
Finished Jul 05 05:13:13 PM PDT 24
Peak memory 207008 kb
Host smart-f1150d97-a26a-43cc-9bde-c502736c993d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560019378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3560019378
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1286960789
Short name T455
Test name
Test status
Simulation time 111467327 ps
CPU time 2.67 seconds
Started Jul 05 05:13:27 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 206968 kb
Host smart-0e92e15a-dde8-485b-a61e-9042cc307260
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286960789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1286960789
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2081538426
Short name T558
Test name
Test status
Simulation time 141401424 ps
CPU time 3.18 seconds
Started Jul 05 05:13:03 PM PDT 24
Finished Jul 05 05:13:09 PM PDT 24
Peak memory 206956 kb
Host smart-901650c8-a5c3-4d88-bb31-dcad98ec1835
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081538426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2081538426
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3580152849
Short name T732
Test name
Test status
Simulation time 134155809 ps
CPU time 2.69 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 214332 kb
Host smart-37a5977a-9614-4a11-abc9-f3e6af160b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580152849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3580152849
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2782918692
Short name T448
Test name
Test status
Simulation time 311250272 ps
CPU time 6.78 seconds
Started Jul 05 05:13:04 PM PDT 24
Finished Jul 05 05:13:13 PM PDT 24
Peak memory 207856 kb
Host smart-3eb8fe5f-78b2-41a2-9e9e-9f29a6d2dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782918692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2782918692
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2361004956
Short name T81
Test name
Test status
Simulation time 785093553 ps
CPU time 27.32 seconds
Started Jul 05 05:13:11 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 215308 kb
Host smart-480074fe-6d91-4904-adaf-5449f18476ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361004956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2361004956
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3964791202
Short name T823
Test name
Test status
Simulation time 1496788240 ps
CPU time 20.16 seconds
Started Jul 05 05:13:09 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 221336 kb
Host smart-05114e4f-a4f1-49e3-96c8-69093fefeec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964791202 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3964791202
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3158287105
Short name T505
Test name
Test status
Simulation time 171686830 ps
CPU time 4.57 seconds
Started Jul 05 05:13:07 PM PDT 24
Finished Jul 05 05:13:13 PM PDT 24
Peak memory 207764 kb
Host smart-1b05e5f7-60f7-4e63-92d0-e988e505398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158287105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3158287105
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1208161730
Short name T661
Test name
Test status
Simulation time 372339130 ps
CPU time 10.57 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:26 PM PDT 24
Peak memory 210476 kb
Host smart-6c376d76-2118-446c-8478-019f9a494d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208161730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1208161730
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1491789951
Short name T734
Test name
Test status
Simulation time 56149061 ps
CPU time 0.78 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 205896 kb
Host smart-d0fcb925-4406-476f-aa77-38bbad653858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491789951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1491789951
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.16577835
Short name T397
Test name
Test status
Simulation time 249763594 ps
CPU time 2.58 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 214316 kb
Host smart-71aae125-1d82-4926-b598-2362cb9f8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16577835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.16577835
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3559904147
Short name T527
Test name
Test status
Simulation time 365389372 ps
CPU time 2.72 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 207392 kb
Host smart-43d14140-b228-4d16-b9b0-03916f8456f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559904147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3559904147
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4261913724
Short name T278
Test name
Test status
Simulation time 40062632 ps
CPU time 2.52 seconds
Started Jul 05 05:13:16 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 214228 kb
Host smart-239600c1-475c-43ec-ad83-aeaade647867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261913724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4261913724
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1518203973
Short name T471
Test name
Test status
Simulation time 441174655 ps
CPU time 2.9 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 220072 kb
Host smart-17832e06-ecae-493b-a2ca-6ff3ad5b2e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518203973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1518203973
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2129054149
Short name T520
Test name
Test status
Simulation time 244390438 ps
CPU time 3.53 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 215856 kb
Host smart-67cf174b-c223-4d35-b5d6-2e3505848b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129054149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2129054149
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.903463183
Short name T832
Test name
Test status
Simulation time 217527795 ps
CPU time 2.95 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 206768 kb
Host smart-3adc0ac5-17e6-485c-8d46-9fdf261ecf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903463183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.903463183
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2209510777
Short name T833
Test name
Test status
Simulation time 519792522 ps
CPU time 4.4 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 206784 kb
Host smart-e4e0ff4b-0061-477f-8c0e-29560aeffe01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209510777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2209510777
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2798433867
Short name T611
Test name
Test status
Simulation time 174823561 ps
CPU time 5.12 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 208548 kb
Host smart-469cc3de-d4a2-4b83-9f1b-fd1e8d719496
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798433867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2798433867
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.85457340
Short name T222
Test name
Test status
Simulation time 79409352 ps
CPU time 3.32 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:19 PM PDT 24
Peak memory 208208 kb
Host smart-1eba11c1-ca69-4fce-9dd1-6b464029f795
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85457340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.85457340
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1865612948
Short name T456
Test name
Test status
Simulation time 230438965 ps
CPU time 2.6 seconds
Started Jul 05 05:13:13 PM PDT 24
Finished Jul 05 05:13:17 PM PDT 24
Peak memory 208124 kb
Host smart-7375e27e-7741-4a57-9208-80a1f806891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865612948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1865612948
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3351786492
Short name T525
Test name
Test status
Simulation time 53483104 ps
CPU time 2.35 seconds
Started Jul 05 05:13:12 PM PDT 24
Finished Jul 05 05:13:16 PM PDT 24
Peak memory 206944 kb
Host smart-278d9a6c-6a3a-4bb8-8be6-44b7ed0336b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351786492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3351786492
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.266547820
Short name T699
Test name
Test status
Simulation time 1038426305 ps
CPU time 8.64 seconds
Started Jul 05 05:13:14 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 209216 kb
Host smart-3c7f5c2f-9011-4528-9da7-b3fa9f5ca9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266547820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.266547820
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1116671074
Short name T600
Test name
Test status
Simulation time 215873994 ps
CPU time 0.84 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 205964 kb
Host smart-b78b073b-7a21-4fea-8e39-95f0bd45773b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116671074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1116671074
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3305351616
Short name T463
Test name
Test status
Simulation time 1431808405 ps
CPU time 17.19 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:38 PM PDT 24
Peak memory 222492 kb
Host smart-033cd88c-69bd-4b17-b577-cfba80874278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305351616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3305351616
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3046533629
Short name T604
Test name
Test status
Simulation time 1488812531 ps
CPU time 5.09 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:13:29 PM PDT 24
Peak memory 209328 kb
Host smart-681b0dc2-2843-4291-90d3-9f277b414b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046533629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3046533629
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3131294006
Short name T636
Test name
Test status
Simulation time 607248008 ps
CPU time 12.6 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 214336 kb
Host smart-c52291be-1168-4919-b733-664654eb3f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131294006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3131294006
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2136077690
Short name T893
Test name
Test status
Simulation time 92857438 ps
CPU time 1.7 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:38 PM PDT 24
Peak memory 214276 kb
Host smart-b025039e-aec7-4991-a018-73c14d9bf644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136077690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2136077690
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.24896512
Short name T246
Test name
Test status
Simulation time 376279155 ps
CPU time 4.36 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:27 PM PDT 24
Peak memory 222592 kb
Host smart-bac5071f-9cab-4095-b9ff-53fe8d7e782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24896512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.24896512
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.706395717
Short name T294
Test name
Test status
Simulation time 298067233 ps
CPU time 4.15 seconds
Started Jul 05 05:13:25 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 214272 kb
Host smart-0ff6d2d9-77d7-4cad-ad0a-cf2615277d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706395717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.706395717
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1623419841
Short name T638
Test name
Test status
Simulation time 40744049 ps
CPU time 1.76 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:22 PM PDT 24
Peak memory 206844 kb
Host smart-20836b68-ba13-4972-9c04-f62c51b6212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623419841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1623419841
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.854537637
Short name T749
Test name
Test status
Simulation time 93929795 ps
CPU time 4.04 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:13:27 PM PDT 24
Peak memory 208428 kb
Host smart-ae7c1dfc-0a1a-4967-b3fb-c5eb856945d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854537637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.854537637
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.616125142
Short name T380
Test name
Test status
Simulation time 83303198 ps
CPU time 2.51 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:48 PM PDT 24
Peak memory 208688 kb
Host smart-0e420429-3226-4084-9cc3-795eee4d6c72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616125142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.616125142
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3811099965
Short name T671
Test name
Test status
Simulation time 146068261 ps
CPU time 3.13 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 208296 kb
Host smart-4076f2a9-e410-4c0d-8679-87a7e21b6f8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811099965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3811099965
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.665893430
Short name T453
Test name
Test status
Simulation time 1423680517 ps
CPU time 2.57 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 209376 kb
Host smart-0b303810-5cb4-4f2f-90f8-ddf782d68de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665893430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.665893430
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2334907996
Short name T689
Test name
Test status
Simulation time 40361337 ps
CPU time 2.57 seconds
Started Jul 05 05:13:19 PM PDT 24
Finished Jul 05 05:13:23 PM PDT 24
Peak memory 208644 kb
Host smart-8c135c23-8a4c-4ea4-a198-d8f36165329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334907996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2334907996
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4039607657
Short name T856
Test name
Test status
Simulation time 29580685440 ps
CPU time 77.34 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:14:41 PM PDT 24
Peak memory 221028 kb
Host smart-e9181d29-fa58-45ec-a021-d5657d1c3169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039607657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4039607657
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1864220847
Short name T659
Test name
Test status
Simulation time 72588201 ps
CPU time 3.62 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:26 PM PDT 24
Peak memory 208888 kb
Host smart-8ea31d05-1b65-4029-a3aa-33e92129d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864220847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1864220847
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2252095822
Short name T43
Test name
Test status
Simulation time 184085971 ps
CPU time 4.89 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:26 PM PDT 24
Peak memory 210860 kb
Host smart-65d5b0ee-927f-40f5-b51d-5d89f22aa457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252095822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2252095822
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1033806586
Short name T443
Test name
Test status
Simulation time 53610954 ps
CPU time 1.02 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 206144 kb
Host smart-0b5d2477-ec8c-45ae-aa3c-b9d109642041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033806586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1033806586
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3419246818
Short name T396
Test name
Test status
Simulation time 747084383 ps
CPU time 40.44 seconds
Started Jul 05 05:10:55 PM PDT 24
Finished Jul 05 05:11:36 PM PDT 24
Peak memory 222428 kb
Host smart-4f0f1b35-1199-465b-ac70-e0072481b5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419246818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3419246818
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1756045294
Short name T34
Test name
Test status
Simulation time 247518207 ps
CPU time 3.08 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:10:57 PM PDT 24
Peak memory 216372 kb
Host smart-9ae5f3c1-6c32-4707-a932-52ba50f3c209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756045294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1756045294
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2395037661
Short name T895
Test name
Test status
Simulation time 91937036 ps
CPU time 1.62 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 214340 kb
Host smart-80ed1b53-7bb1-4685-9ed3-1ce5cc0ed66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395037661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2395037661
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1586147261
Short name T324
Test name
Test status
Simulation time 727808167 ps
CPU time 19.6 seconds
Started Jul 05 05:10:57 PM PDT 24
Finished Jul 05 05:11:17 PM PDT 24
Peak memory 221740 kb
Host smart-7cda44ad-e572-4361-aaac-f839babc9378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586147261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1586147261
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1069156987
Short name T59
Test name
Test status
Simulation time 1059931954 ps
CPU time 3.48 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:55 PM PDT 24
Peak memory 222408 kb
Host smart-e9304b20-a3a2-401f-b4c2-62e58b2764f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069156987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1069156987
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2368242363
Short name T193
Test name
Test status
Simulation time 111775558 ps
CPU time 2.56 seconds
Started Jul 05 05:10:50 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 209664 kb
Host smart-9bd2a629-288c-41f0-8353-19b01ce85ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368242363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2368242363
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2727250808
Short name T305
Test name
Test status
Simulation time 423778913 ps
CPU time 4.73 seconds
Started Jul 05 05:10:46 PM PDT 24
Finished Jul 05 05:10:51 PM PDT 24
Peak memory 209116 kb
Host smart-d7206252-b5d6-46c1-9e22-c55b04bde75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727250808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2727250808
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3683052776
Short name T105
Test name
Test status
Simulation time 1169583665 ps
CPU time 7.34 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 229164 kb
Host smart-700e569b-1fd6-4fc5-b49a-18db6ae76ea7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683052776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3683052776
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.841926445
Short name T593
Test name
Test status
Simulation time 2877141026 ps
CPU time 17.71 seconds
Started Jul 05 05:10:44 PM PDT 24
Finished Jul 05 05:11:02 PM PDT 24
Peak memory 208292 kb
Host smart-7bb2a12f-da81-4cb0-966b-0aad6682f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841926445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.841926445
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.538878364
Short name T492
Test name
Test status
Simulation time 229235383 ps
CPU time 3.68 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:55 PM PDT 24
Peak memory 206876 kb
Host smart-2445ae41-69ed-409b-b2da-9f609189124d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538878364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.538878364
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1763136415
Short name T889
Test name
Test status
Simulation time 9347081032 ps
CPU time 26.46 seconds
Started Jul 05 05:10:55 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 208800 kb
Host smart-ee032dd0-0bee-42f1-8a30-59d4c655c0db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763136415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1763136415
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1590290333
Short name T502
Test name
Test status
Simulation time 847319077 ps
CPU time 21.37 seconds
Started Jul 05 05:10:46 PM PDT 24
Finished Jul 05 05:11:08 PM PDT 24
Peak memory 208032 kb
Host smart-c0bbec11-bac3-4e05-a03a-9e31d3c5b278
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590290333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1590290333
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2936309080
Short name T660
Test name
Test status
Simulation time 235975136 ps
CPU time 3.81 seconds
Started Jul 05 05:10:50 PM PDT 24
Finished Jul 05 05:10:54 PM PDT 24
Peak memory 218272 kb
Host smart-16ec1442-d37f-4546-add1-7b7abe447d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936309080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2936309080
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2777449493
Short name T632
Test name
Test status
Simulation time 88353369 ps
CPU time 1.96 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 208388 kb
Host smart-6f872e47-14df-4683-a677-14977868f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777449493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2777449493
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3980531666
Short name T200
Test name
Test status
Simulation time 4642110887 ps
CPU time 40.63 seconds
Started Jul 05 05:10:57 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 216696 kb
Host smart-d93f4de8-3253-4382-93be-1e298bdd5861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980531666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3980531666
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2893920626
Short name T859
Test name
Test status
Simulation time 449949141 ps
CPU time 4.08 seconds
Started Jul 05 05:10:56 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 218364 kb
Host smart-5f5754c1-d1bf-4465-b7ce-55d4b9902079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893920626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2893920626
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2795908867
Short name T109
Test name
Test status
Simulation time 116754935 ps
CPU time 2.5 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:10:56 PM PDT 24
Peak memory 209876 kb
Host smart-79392417-08de-4f3f-8cb7-a2dea1ccfc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795908867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2795908867
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2913196311
Short name T462
Test name
Test status
Simulation time 18290198 ps
CPU time 0.77 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 205952 kb
Host smart-bc479d5f-7b29-4d34-90bd-a610570e3209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913196311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2913196311
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4262687917
Short name T355
Test name
Test status
Simulation time 45855406 ps
CPU time 3.53 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 214436 kb
Host smart-b6329e61-d5c9-4eac-95f6-c610948f4a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262687917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4262687917
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2158318865
Short name T784
Test name
Test status
Simulation time 70967785 ps
CPU time 1.57 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 206132 kb
Host smart-c89df7c3-d1c8-4aa6-811a-15ecf0b4c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158318865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2158318865
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.739087681
Short name T201
Test name
Test status
Simulation time 770861140 ps
CPU time 5.27 seconds
Started Jul 05 05:13:19 PM PDT 24
Finished Jul 05 05:13:26 PM PDT 24
Peak memory 209076 kb
Host smart-cd5fafca-b8e8-4c39-a27d-95db8fcb0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739087681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.739087681
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3664098598
Short name T96
Test name
Test status
Simulation time 376780492 ps
CPU time 4.57 seconds
Started Jul 05 05:13:19 PM PDT 24
Finished Jul 05 05:13:25 PM PDT 24
Peak memory 208912 kb
Host smart-959f25d1-c4f4-41a2-ac3e-af2a1081b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664098598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3664098598
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2685937171
Short name T328
Test name
Test status
Simulation time 111735088 ps
CPU time 4.77 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:27 PM PDT 24
Peak memory 222388 kb
Host smart-3f29e62b-1d6c-4465-9d69-e53a3564d563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685937171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2685937171
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1295661931
Short name T700
Test name
Test status
Simulation time 145632722 ps
CPU time 2.94 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:24 PM PDT 24
Peak memory 209568 kb
Host smart-60d9636c-1f83-44b5-bc9c-cbd05fcb45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295661931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1295661931
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.144764094
Short name T306
Test name
Test status
Simulation time 678282613 ps
CPU time 8.61 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:30 PM PDT 24
Peak memory 214272 kb
Host smart-2cb944a1-d6aa-4dd3-b570-8e5d0c60a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144764094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.144764094
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4158267412
Short name T542
Test name
Test status
Simulation time 3185148411 ps
CPU time 36.28 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 209044 kb
Host smart-cccf62d7-55ba-4ddb-b239-83004799b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158267412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4158267412
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3034225478
Short name T590
Test name
Test status
Simulation time 724086682 ps
CPU time 5.71 seconds
Started Jul 05 05:13:22 PM PDT 24
Finished Jul 05 05:13:29 PM PDT 24
Peak memory 207856 kb
Host smart-ed8efad3-81c6-4426-8303-58f18b870e10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034225478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3034225478
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3974203848
Short name T517
Test name
Test status
Simulation time 246779698 ps
CPU time 6.17 seconds
Started Jul 05 05:13:20 PM PDT 24
Finished Jul 05 05:13:27 PM PDT 24
Peak memory 208860 kb
Host smart-b14b9905-2a5d-4616-a14a-e6426f9c4f15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974203848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3974203848
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.742442022
Short name T813
Test name
Test status
Simulation time 2454893146 ps
CPU time 43.35 seconds
Started Jul 05 05:13:21 PM PDT 24
Finished Jul 05 05:14:05 PM PDT 24
Peak memory 208948 kb
Host smart-7bb4fe27-26ea-453a-bac9-2f572ea7ed23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742442022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.742442022
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3629772663
Short name T645
Test name
Test status
Simulation time 223534758 ps
CPU time 2.05 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 214292 kb
Host smart-1be0e784-86e2-462c-b441-00f6b3ae57aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629772663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3629772663
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3905555142
Short name T464
Test name
Test status
Simulation time 95330829 ps
CPU time 3.28 seconds
Started Jul 05 05:13:24 PM PDT 24
Finished Jul 05 05:13:28 PM PDT 24
Peak memory 208576 kb
Host smart-58bd6939-b262-4cc6-9dc8-eacfa2f3ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905555142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3905555142
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3452802822
Short name T82
Test name
Test status
Simulation time 2548334017 ps
CPU time 28.14 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 216712 kb
Host smart-dff8852d-be14-4fb6-a4ed-0b882f5f1110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452802822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3452802822
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3219898477
Short name T261
Test name
Test status
Simulation time 631396016 ps
CPU time 8 seconds
Started Jul 05 05:13:23 PM PDT 24
Finished Jul 05 05:13:32 PM PDT 24
Peak memory 208004 kb
Host smart-af6ee2bc-0d7f-4d95-b409-080be0d768f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219898477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3219898477
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.423787794
Short name T198
Test name
Test status
Simulation time 109119091 ps
CPU time 2.58 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:34 PM PDT 24
Peak memory 210392 kb
Host smart-b07ed071-71e7-4286-962f-c346f9fa15d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423787794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.423787794
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.404270549
Short name T436
Test name
Test status
Simulation time 26596711 ps
CPU time 0.78 seconds
Started Jul 05 05:13:28 PM PDT 24
Finished Jul 05 05:13:29 PM PDT 24
Peak memory 205996 kb
Host smart-7f974685-2aa6-404f-b798-ccb96c55a791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404270549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.404270549
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3012147182
Short name T413
Test name
Test status
Simulation time 458140393 ps
CPU time 24.66 seconds
Started Jul 05 05:13:32 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 214692 kb
Host smart-be5ddf05-9776-48e1-b76d-34145961c7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012147182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3012147182
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2926925791
Short name T599
Test name
Test status
Simulation time 137922049 ps
CPU time 2.81 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:34 PM PDT 24
Peak memory 214228 kb
Host smart-974b08a5-65e3-4d4c-88e7-797dedd9c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926925791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2926925791
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2823735455
Short name T541
Test name
Test status
Simulation time 73474670 ps
CPU time 1.56 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:32 PM PDT 24
Peak memory 207160 kb
Host smart-c65cb3d7-05f3-4459-8e97-82b5d5a74cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823735455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2823735455
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3651361529
Short name T88
Test name
Test status
Simulation time 115379163 ps
CPU time 2.46 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 214296 kb
Host smart-d6ae1381-86bc-499a-8b8c-e566c32c4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651361529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3651361529
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2014855122
Short name T811
Test name
Test status
Simulation time 253043196 ps
CPU time 7.43 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 210508 kb
Host smart-a1cc6406-f6f4-402f-b584-c7859b9ef192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014855122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2014855122
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3980586411
Short name T839
Test name
Test status
Simulation time 427215997 ps
CPU time 4.84 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 210424 kb
Host smart-a018d62e-b7dd-46da-b8a7-11d646d4731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980586411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3980586411
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3213624543
Short name T580
Test name
Test status
Simulation time 5320426416 ps
CPU time 17.6 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 208092 kb
Host smart-dbbb6e6c-077c-41db-ab6e-b454f57a8bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213624543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3213624543
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3299155245
Short name T751
Test name
Test status
Simulation time 291651888 ps
CPU time 3.75 seconds
Started Jul 05 05:13:32 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 208680 kb
Host smart-df3b02a3-7eec-4a32-ae54-a515e07f5bde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299155245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3299155245
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.183431619
Short name T801
Test name
Test status
Simulation time 858382657 ps
CPU time 3.7 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 208932 kb
Host smart-30c06243-79fd-414c-8adb-a3f5da304b32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183431619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.183431619
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3084162613
Short name T673
Test name
Test status
Simulation time 222079530 ps
CPU time 2.47 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:32 PM PDT 24
Peak memory 206952 kb
Host smart-ba01edb6-c62f-40d4-add1-cef9f9e7d6ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084162613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3084162613
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1660577159
Short name T195
Test name
Test status
Simulation time 111343245 ps
CPU time 2.75 seconds
Started Jul 05 05:13:34 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 215900 kb
Host smart-a64c9b8c-5fb6-49c2-9555-0fd3069e5009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660577159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1660577159
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.922100830
Short name T778
Test name
Test status
Simulation time 158317483 ps
CPU time 2.5 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 206816 kb
Host smart-d7a2701c-8d16-42e4-8d0c-0e70e963dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922100830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.922100830
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2246545239
Short name T5
Test name
Test status
Simulation time 2287243935 ps
CPU time 27.46 seconds
Started Jul 05 05:13:28 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 222776 kb
Host smart-362d62ec-2544-42d8-ac52-31ee08ebff32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246545239 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2246545239
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.991805907
Short name T886
Test name
Test status
Simulation time 38694039 ps
CPU time 2.61 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:32 PM PDT 24
Peak memory 207712 kb
Host smart-dd94f555-0981-49d0-9fb0-5d0387069227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991805907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.991805907
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.595798920
Short name T390
Test name
Test status
Simulation time 158182834 ps
CPU time 1.97 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:34 PM PDT 24
Peak memory 210012 kb
Host smart-2709b57f-5ef7-49aa-89ee-77f734ef00ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595798920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.595798920
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.542151584
Short name T461
Test name
Test status
Simulation time 54711195 ps
CPU time 0.76 seconds
Started Jul 05 05:13:27 PM PDT 24
Finished Jul 05 05:13:29 PM PDT 24
Peak memory 205936 kb
Host smart-da3715e8-9a9a-4ae5-a7ca-c3e07da969e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542151584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.542151584
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2439226293
Short name T790
Test name
Test status
Simulation time 233003930 ps
CPU time 4.29 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 215720 kb
Host smart-20872a4e-c44f-4d57-af34-318ef5d77d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439226293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2439226293
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3453461968
Short name T33
Test name
Test status
Simulation time 210565110 ps
CPU time 3.3 seconds
Started Jul 05 05:13:28 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 215820 kb
Host smart-c9f402c5-3918-44f3-b648-13e5b525d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453461968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3453461968
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.598254056
Short name T830
Test name
Test status
Simulation time 160903361 ps
CPU time 2.17 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 207696 kb
Host smart-c0d72044-70a5-4556-a2cf-62795dac234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598254056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.598254056
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1421974920
Short name T310
Test name
Test status
Simulation time 670647956 ps
CPU time 3.22 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 214328 kb
Host smart-30024034-9290-4146-9e02-a71e3407ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421974920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1421974920
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1578307092
Short name T868
Test name
Test status
Simulation time 294957222 ps
CPU time 2.82 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:43 PM PDT 24
Peak memory 220404 kb
Host smart-bda229fb-acb4-4011-96e7-b2ddd0efbd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578307092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1578307092
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3606563501
Short name T381
Test name
Test status
Simulation time 7199274969 ps
CPU time 77.06 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:14:50 PM PDT 24
Peak memory 221288 kb
Host smart-5b787d40-b5fa-4d00-a316-9acbee502331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606563501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3606563501
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1286185240
Short name T191
Test name
Test status
Simulation time 736811837 ps
CPU time 3.9 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 208720 kb
Host smart-dc359b63-20fc-4c51-9733-7699b349275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286185240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1286185240
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4025486641
Short name T769
Test name
Test status
Simulation time 859655746 ps
CPU time 19.63 seconds
Started Jul 05 05:13:28 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 208212 kb
Host smart-8b57cd46-1ece-49e3-abc1-34b56738aa06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025486641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4025486641
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4229115009
Short name T768
Test name
Test status
Simulation time 114910395 ps
CPU time 3.84 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:36 PM PDT 24
Peak memory 206864 kb
Host smart-88ac7b27-1a77-4e5c-b86f-74200c8cafcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229115009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4229115009
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1379198799
Short name T850
Test name
Test status
Simulation time 403533888 ps
CPU time 13.55 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:44 PM PDT 24
Peak memory 208260 kb
Host smart-f9b5369d-ee3e-41c8-b2dc-6cce3f0c8270
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379198799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1379198799
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2199735592
Short name T669
Test name
Test status
Simulation time 543560601 ps
CPU time 3.78 seconds
Started Jul 05 05:13:33 PM PDT 24
Finished Jul 05 05:13:38 PM PDT 24
Peak memory 208688 kb
Host smart-84dd4959-47ad-4580-ad2f-43849494f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199735592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2199735592
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3545263262
Short name T571
Test name
Test status
Simulation time 46407365 ps
CPU time 1.75 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:32 PM PDT 24
Peak memory 207356 kb
Host smart-63682a6a-da93-40aa-93ac-a8364a62e993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545263262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3545263262
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1522425574
Short name T207
Test name
Test status
Simulation time 355854093 ps
CPU time 4.22 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 208156 kb
Host smart-0d983976-c5dd-471a-9522-93cbc42c1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522425574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1522425574
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1294478424
Short name T916
Test name
Test status
Simulation time 1514880784 ps
CPU time 6.02 seconds
Started Jul 05 05:13:30 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 210348 kb
Host smart-9f175bf8-94fb-466c-95ff-f9b3a6708af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294478424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1294478424
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.366848834
Short name T573
Test name
Test status
Simulation time 26127743 ps
CPU time 0.86 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 206012 kb
Host smart-71f872a6-7778-4075-acfe-9d4212afb815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366848834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.366848834
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1979895490
Short name T831
Test name
Test status
Simulation time 75114076 ps
CPU time 3.21 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:13:44 PM PDT 24
Peak memory 221388 kb
Host smart-49ac1ffe-fe6b-4a98-845e-3d178b79d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979895490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1979895490
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3551640545
Short name T60
Test name
Test status
Simulation time 131697950 ps
CPU time 2.53 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 214296 kb
Host smart-8c95c1a4-6257-4b0f-a23f-8ddff920b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551640545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3551640545
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.347895334
Short name T719
Test name
Test status
Simulation time 70344088 ps
CPU time 2.69 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 214296 kb
Host smart-bf121454-613a-4383-93cc-50d4f7c84d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347895334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.347895334
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2266263646
Short name T576
Test name
Test status
Simulation time 180395468 ps
CPU time 3.14 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 218168 kb
Host smart-c6ed948f-11ab-4c36-8fda-6a0029762db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266263646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2266263646
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.986689010
Short name T631
Test name
Test status
Simulation time 136131312 ps
CPU time 2.43 seconds
Started Jul 05 05:13:29 PM PDT 24
Finished Jul 05 05:13:33 PM PDT 24
Peak memory 207440 kb
Host smart-f02e4942-cbca-451f-b8da-6ebbb1139f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986689010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.986689010
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3699231510
Short name T842
Test name
Test status
Simulation time 50317520 ps
CPU time 2.91 seconds
Started Jul 05 05:13:31 PM PDT 24
Finished Jul 05 05:13:35 PM PDT 24
Peak memory 208812 kb
Host smart-e7d5664f-d6ad-4622-a0c3-aef3ab7650da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699231510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3699231510
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2593543846
Short name T433
Test name
Test status
Simulation time 48657210 ps
CPU time 2.81 seconds
Started Jul 05 05:14:24 PM PDT 24
Finished Jul 05 05:14:28 PM PDT 24
Peak memory 206856 kb
Host smart-938dfa6a-632f-4748-a022-cdaf0dc9a06c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593543846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2593543846
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2264824528
Short name T230
Test name
Test status
Simulation time 222443923 ps
CPU time 6.18 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 208556 kb
Host smart-7f9fcca0-4581-4637-bf00-dbc3d01f2683
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264824528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2264824528
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.127354132
Short name T399
Test name
Test status
Simulation time 308056867 ps
CPU time 3.91 seconds
Started Jul 05 05:13:34 PM PDT 24
Finished Jul 05 05:13:39 PM PDT 24
Peak memory 216024 kb
Host smart-81bf2471-a7c7-4e6b-bfd3-e5ea2e47b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127354132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.127354132
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3505819118
Short name T407
Test name
Test status
Simulation time 459532801 ps
CPU time 3.27 seconds
Started Jul 05 05:13:33 PM PDT 24
Finished Jul 05 05:13:37 PM PDT 24
Peak memory 208544 kb
Host smart-1eb2ac44-a720-41cf-a82b-75871ed72193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505819118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3505819118
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1726782178
Short name T50
Test name
Test status
Simulation time 1476081557 ps
CPU time 15.53 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 221416 kb
Host smart-a2203970-17a0-4b11-b81b-95b430e6bfa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726782178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1726782178
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2295988335
Short name T78
Test name
Test status
Simulation time 1077191834 ps
CPU time 18.4 seconds
Started Jul 05 05:13:47 PM PDT 24
Finished Jul 05 05:14:07 PM PDT 24
Peak memory 221000 kb
Host smart-c1bd6363-11b3-42eb-bba6-31627fd856ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295988335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2295988335
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.49166356
Short name T543
Test name
Test status
Simulation time 137772222 ps
CPU time 4.79 seconds
Started Jul 05 05:13:39 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 208296 kb
Host smart-e2870e45-d378-43ed-a812-4df87fa6eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49166356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.49166356
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1451617024
Short name T393
Test name
Test status
Simulation time 81900547 ps
CPU time 1.61 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 210228 kb
Host smart-971eef4c-6724-44cd-b019-933874045c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451617024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1451617024
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3994015560
Short name T472
Test name
Test status
Simulation time 23155571 ps
CPU time 0.83 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 206004 kb
Host smart-bb984876-6f2c-4bcb-8fcd-ae6371393554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994015560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3994015560
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1067328722
Short name T421
Test name
Test status
Simulation time 1020789347 ps
CPU time 5.1 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 215484 kb
Host smart-c14ceb64-77b5-474c-974d-5f67acef4ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067328722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1067328722
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.487286616
Short name T20
Test name
Test status
Simulation time 222618160 ps
CPU time 2.45 seconds
Started Jul 05 05:13:39 PM PDT 24
Finished Jul 05 05:13:43 PM PDT 24
Peak memory 222700 kb
Host smart-cafcfda9-01d8-4b21-b6f9-cd9b22f12afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487286616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.487286616
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.521941013
Short name T364
Test name
Test status
Simulation time 206550023 ps
CPU time 2.73 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 210080 kb
Host smart-ddf871b8-382e-40fd-b278-30b601c95eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521941013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.521941013
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1095627248
Short name T387
Test name
Test status
Simulation time 856485643 ps
CPU time 5.25 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 222504 kb
Host smart-a9e5228d-4820-4291-b085-987e2f9dcd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095627248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1095627248
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1343385043
Short name T288
Test name
Test status
Simulation time 378359195 ps
CPU time 3.3 seconds
Started Jul 05 05:13:40 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 214316 kb
Host smart-f3b21f9f-acba-4c6f-bf27-37f34cc5a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343385043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1343385043
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2564399089
Short name T508
Test name
Test status
Simulation time 208125256 ps
CPU time 6.2 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 214288 kb
Host smart-a54c6974-6567-4738-b436-73416d9ec173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564399089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2564399089
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2983471836
Short name T213
Test name
Test status
Simulation time 164155312 ps
CPU time 3.99 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 209600 kb
Host smart-3abaa7f3-627e-4ac4-91db-1eb96659af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983471836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2983471836
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2422244689
Short name T779
Test name
Test status
Simulation time 725274161 ps
CPU time 8.02 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:13:48 PM PDT 24
Peak memory 208016 kb
Host smart-5a10e421-dec5-40b4-95bd-2893d7da7026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422244689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2422244689
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.20854909
Short name T740
Test name
Test status
Simulation time 99819559 ps
CPU time 2.72 seconds
Started Jul 05 05:13:39 PM PDT 24
Finished Jul 05 05:13:44 PM PDT 24
Peak memory 206848 kb
Host smart-11d047f6-0936-4d2c-ac0a-39e3cc9187a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20854909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.20854909
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2443927655
Short name T601
Test name
Test status
Simulation time 10813155216 ps
CPU time 19.51 seconds
Started Jul 05 05:13:41 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 208724 kb
Host smart-e5fb37e3-addd-4dde-a542-d7a742065876
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443927655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2443927655
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1399656714
Short name T869
Test name
Test status
Simulation time 30820265 ps
CPU time 2.44 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 207300 kb
Host smart-81d0fe52-02f7-4a3b-8e73-e9d66a880ef7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399656714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1399656714
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.611674652
Short name T538
Test name
Test status
Simulation time 184939234 ps
CPU time 2.3 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 218316 kb
Host smart-c775f317-1e40-4b14-b303-10a0703535e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611674652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.611674652
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2779978402
Short name T437
Test name
Test status
Simulation time 171966493 ps
CPU time 4.07 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 208236 kb
Host smart-db21d94b-0ea4-4f11-b585-ed06d7fc6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779978402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2779978402
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1153783620
Short name T761
Test name
Test status
Simulation time 211660000 ps
CPU time 4.65 seconds
Started Jul 05 05:13:39 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 208564 kb
Host smart-5cc5917e-f762-4a43-9562-d991b089814c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153783620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1153783620
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2764283350
Short name T354
Test name
Test status
Simulation time 1000045461 ps
CPU time 10.8 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:51 PM PDT 24
Peak memory 214328 kb
Host smart-8e44ee85-0024-4de9-b5de-5357631b36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764283350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2764283350
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2817329696
Short name T572
Test name
Test status
Simulation time 2526263884 ps
CPU time 9.87 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 210720 kb
Host smart-658fef97-7b98-4642-ba49-956e22e8e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817329696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2817329696
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3826389543
Short name T902
Test name
Test status
Simulation time 29956296 ps
CPU time 0.83 seconds
Started Jul 05 05:13:39 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 206000 kb
Host smart-b1dad5eb-b167-439f-870f-f523cb117300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826389543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3826389543
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.106603560
Short name T350
Test name
Test status
Simulation time 250767617 ps
CPU time 3.66 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:43 PM PDT 24
Peak memory 215572 kb
Host smart-7e631702-f4ac-44bb-8b60-681b38fc58e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106603560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.106603560
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3437648489
Short name T38
Test name
Test status
Simulation time 504295439 ps
CPU time 3.13 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 209408 kb
Host smart-86c7b3ff-c580-4af9-bafc-6adf40bb62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437648489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3437648489
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2151857689
Short name T497
Test name
Test status
Simulation time 264046396 ps
CPU time 3.16 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:39 PM PDT 24
Peak memory 209416 kb
Host smart-80c98809-4ca7-4f3c-97ec-13519b837326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151857689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2151857689
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.316164658
Short name T249
Test name
Test status
Simulation time 1082923827 ps
CPU time 5.79 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 214428 kb
Host smart-4bd7e6f9-a9f2-4c3f-b9f3-d45fadb7be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316164658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.316164658
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.4233270034
Short name T781
Test name
Test status
Simulation time 149286167 ps
CPU time 4.13 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:43 PM PDT 24
Peak memory 222408 kb
Host smart-63a12bd1-6f81-4e69-83ce-e765b7f64559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233270034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4233270034
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2447847030
Short name T704
Test name
Test status
Simulation time 358129723 ps
CPU time 2.7 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:40 PM PDT 24
Peak memory 208064 kb
Host smart-dd92fee1-e541-4cc6-8674-5473643e50df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447847030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2447847030
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3293580822
Short name T608
Test name
Test status
Simulation time 106148232 ps
CPU time 5.08 seconds
Started Jul 05 05:13:40 PM PDT 24
Finished Jul 05 05:13:47 PM PDT 24
Peak memory 207164 kb
Host smart-d576f851-ec37-4f52-8d8f-27d4d5c116aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293580822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3293580822
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.672363735
Short name T438
Test name
Test status
Simulation time 233154650 ps
CPU time 3 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 207048 kb
Host smart-299ea098-fd87-44c8-b6f3-9f144bcd1222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672363735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.672363735
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3351784369
Short name T654
Test name
Test status
Simulation time 84013369 ps
CPU time 3.81 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 208812 kb
Host smart-85543131-e1f8-481c-bafd-aaf9965ef4a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351784369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3351784369
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1496965413
Short name T763
Test name
Test status
Simulation time 748486243 ps
CPU time 18.74 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 208856 kb
Host smart-86cfad5a-36b0-439d-bf9e-8d35182693d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496965413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1496965413
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3329417815
Short name T400
Test name
Test status
Simulation time 119475648 ps
CPU time 3.95 seconds
Started Jul 05 05:13:36 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 206888 kb
Host smart-a00d4146-ff0e-46fd-b4a7-2024322d2b9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329417815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3329417815
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1034248679
Short name T375
Test name
Test status
Simulation time 666094052 ps
CPU time 2.64 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 216432 kb
Host smart-c6b83927-9cd4-42ee-96ca-3aca119e74d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034248679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1034248679
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2712653271
Short name T431
Test name
Test status
Simulation time 406706162 ps
CPU time 2.5 seconds
Started Jul 05 05:13:37 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 208628 kb
Host smart-9f3344b2-7a88-460f-8605-5c3ac314e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712653271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2712653271
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2971048194
Short name T80
Test name
Test status
Simulation time 1270707911 ps
CPU time 19.01 seconds
Started Jul 05 05:13:38 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 222468 kb
Host smart-3d43869a-363d-4b83-8a71-aa58947dab1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971048194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2971048194
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2517191660
Short name T4
Test name
Test status
Simulation time 139485996 ps
CPU time 4.57 seconds
Started Jul 05 05:13:35 PM PDT 24
Finished Jul 05 05:13:41 PM PDT 24
Peak memory 209788 kb
Host smart-e15bc703-4d8b-4c9c-8bb7-333adf78eea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517191660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2517191660
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1488118629
Short name T557
Test name
Test status
Simulation time 123162674 ps
CPU time 2.14 seconds
Started Jul 05 05:13:41 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 210244 kb
Host smart-2f2632aa-0f55-4cf2-94db-b78ecbe77f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488118629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1488118629
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1394746829
Short name T609
Test name
Test status
Simulation time 13209902 ps
CPU time 0.73 seconds
Started Jul 05 05:13:47 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 205924 kb
Host smart-cd5c6157-b7fc-4c56-9dce-21ea8a310fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394746829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1394746829
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3685496783
Short name T806
Test name
Test status
Simulation time 147846883 ps
CPU time 3.67 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 214184 kb
Host smart-904c8fd9-722d-460b-a258-f14f3cf333dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685496783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3685496783
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3436388987
Short name T332
Test name
Test status
Simulation time 1035352203 ps
CPU time 22.79 seconds
Started Jul 05 05:13:46 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 219876 kb
Host smart-11c13292-0996-4336-afbd-8fed1437972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436388987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3436388987
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4228475659
Short name T97
Test name
Test status
Simulation time 142562151 ps
CPU time 4.04 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 209252 kb
Host smart-78f3ee70-f0a3-46fc-a440-2d1d9edd62a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228475659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4228475659
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_random.139147408
Short name T547
Test name
Test status
Simulation time 1434577913 ps
CPU time 25.95 seconds
Started Jul 05 05:13:48 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 214304 kb
Host smart-13257cf4-76eb-4030-9367-9ceff296c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139147408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.139147408
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3242776170
Short name T272
Test name
Test status
Simulation time 145177296 ps
CPU time 3.67 seconds
Started Jul 05 05:13:40 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 208652 kb
Host smart-b5a7e500-9cef-4967-b3f7-fc94058857b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242776170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3242776170
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3706696547
Short name T775
Test name
Test status
Simulation time 221949943 ps
CPU time 5.87 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:51 PM PDT 24
Peak memory 208164 kb
Host smart-dbf5e0ca-5cbc-4720-a7d8-d65dab8e8676
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706696547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3706696547
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2907706725
Short name T490
Test name
Test status
Simulation time 57720416 ps
CPU time 3.07 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:47 PM PDT 24
Peak memory 206940 kb
Host smart-ba5ee5c3-708c-42e8-bb83-9210386ee49c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907706725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2907706725
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3735577000
Short name T731
Test name
Test status
Simulation time 1066554895 ps
CPU time 8.87 seconds
Started Jul 05 05:13:46 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 208704 kb
Host smart-40a1ea15-2ffb-4d05-9b69-035c17ffb8a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735577000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3735577000
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2881517117
Short name T741
Test name
Test status
Simulation time 253455187 ps
CPU time 2.56 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 208972 kb
Host smart-eaeba88e-4e9e-4f77-a917-85b95816a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881517117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2881517117
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2079995032
Short name T16
Test name
Test status
Simulation time 4720080579 ps
CPU time 23.12 seconds
Started Jul 05 05:13:34 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 208132 kb
Host smart-0c0f9d78-5f6e-430f-9124-550d3d7de8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079995032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2079995032
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2564412856
Short name T725
Test name
Test status
Simulation time 773324508 ps
CPU time 36.24 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 222452 kb
Host smart-e9802b97-5d1c-472a-8748-3513d50b4579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564412856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2564412856
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1226740944
Short name T838
Test name
Test status
Simulation time 125140126 ps
CPU time 4.56 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 210040 kb
Host smart-906b31d9-0db9-4e8b-b0c7-63ebb9b28039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226740944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1226740944
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1273546100
Short name T408
Test name
Test status
Simulation time 216965240 ps
CPU time 1.96 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 210612 kb
Host smart-c3a63291-88f6-4c34-ac79-8c39667ad37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273546100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1273546100
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4093408931
Short name T209
Test name
Test status
Simulation time 22589458 ps
CPU time 0.71 seconds
Started Jul 05 05:13:40 PM PDT 24
Finished Jul 05 05:13:42 PM PDT 24
Peak memory 206244 kb
Host smart-2a55b807-a721-47f6-a095-deff8cca9501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093408931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4093408931
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2706684560
Short name T315
Test name
Test status
Simulation time 209231454 ps
CPU time 4.05 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 214336 kb
Host smart-18ddea12-754a-48ec-954a-30d1f5a9f485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706684560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2706684560
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.644508951
Short name T622
Test name
Test status
Simulation time 48012705 ps
CPU time 1.74 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 207608 kb
Host smart-9b1c2148-d3e9-449a-8948-8439bb7202f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644508951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.644508951
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2162416627
Short name T275
Test name
Test status
Simulation time 374295093 ps
CPU time 3.06 seconds
Started Jul 05 05:13:53 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 214516 kb
Host smart-06c105b5-1e37-4f9f-b027-f5b54a35e1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162416627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2162416627
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3272359698
Short name T42
Test name
Test status
Simulation time 872377202 ps
CPU time 3.95 seconds
Started Jul 05 05:13:46 PM PDT 24
Finished Jul 05 05:13:51 PM PDT 24
Peak memory 220564 kb
Host smart-d346a258-c546-4a2e-b41a-73e2b72053c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272359698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3272359698
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1811669388
Short name T655
Test name
Test status
Simulation time 295403898 ps
CPU time 3.83 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:48 PM PDT 24
Peak memory 207860 kb
Host smart-6c44c80b-bb50-437e-82c9-10f80db465f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811669388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1811669388
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1943215789
Short name T319
Test name
Test status
Simulation time 2650535504 ps
CPU time 20.23 seconds
Started Jul 05 05:13:48 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 218284 kb
Host smart-bddda316-557d-4b22-92a7-2c749bd2e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943215789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1943215789
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.926113681
Short name T489
Test name
Test status
Simulation time 77693027 ps
CPU time 3.14 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 208136 kb
Host smart-d4d6c026-7a61-4e0b-a1cb-8dffe152b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926113681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.926113681
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2534040451
Short name T808
Test name
Test status
Simulation time 43003700 ps
CPU time 1.87 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:47 PM PDT 24
Peak memory 206964 kb
Host smart-2a679b4a-3133-49de-85d0-6242e18df85b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534040451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2534040451
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.552761353
Short name T561
Test name
Test status
Simulation time 107470503 ps
CPU time 3.62 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:51 PM PDT 24
Peak memory 208692 kb
Host smart-bb50fae4-d13b-4c3a-b456-84e809acb243
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552761353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.552761353
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2376188169
Short name T862
Test name
Test status
Simulation time 92004053 ps
CPU time 2.67 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 206956 kb
Host smart-95a0cdc5-24e2-4df8-9772-99fee6d6b548
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376188169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2376188169
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1137095199
Short name T650
Test name
Test status
Simulation time 224177251 ps
CPU time 2.27 seconds
Started Jul 05 05:13:43 PM PDT 24
Finished Jul 05 05:13:47 PM PDT 24
Peak memory 207560 kb
Host smart-16da959d-e74e-43f4-8ee7-40c508671d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137095199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1137095199
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3759654079
Short name T85
Test name
Test status
Simulation time 28662655 ps
CPU time 2.26 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 208916 kb
Host smart-96bc0e1e-b58d-41f0-99d4-b945caac3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759654079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3759654079
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3043685183
Short name T373
Test name
Test status
Simulation time 354976192 ps
CPU time 11.85 seconds
Started Jul 05 05:13:46 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 222640 kb
Host smart-3bc795c8-0d40-4e51-9855-00436f534b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043685183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3043685183
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3854144523
Short name T258
Test name
Test status
Simulation time 30476640 ps
CPU time 2.46 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 207776 kb
Host smart-797b0495-a4e7-418d-a10c-43a56718311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854144523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3854144523
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1292603373
Short name T169
Test name
Test status
Simulation time 97190079 ps
CPU time 2.65 seconds
Started Jul 05 05:13:42 PM PDT 24
Finished Jul 05 05:13:47 PM PDT 24
Peak memory 210280 kb
Host smart-e862c679-b5f9-4052-ad7c-f38fa19a1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292603373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1292603373
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3299079465
Short name T498
Test name
Test status
Simulation time 30672959 ps
CPU time 0.91 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 205956 kb
Host smart-f45719e6-c937-4ebe-b071-4ac7e43a8f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299079465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3299079465
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.180540694
Short name T23
Test name
Test status
Simulation time 107867825 ps
CPU time 4.95 seconds
Started Jul 05 05:13:53 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 214776 kb
Host smart-fa637276-0f45-4b3a-b114-a487120fa57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180540694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.180540694
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1627299570
Short name T854
Test name
Test status
Simulation time 394783308 ps
CPU time 4.52 seconds
Started Jul 05 05:13:53 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 207120 kb
Host smart-ce9b8f17-3e6a-4ed8-8c73-6ca12af46937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627299570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1627299570
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3223286860
Short name T251
Test name
Test status
Simulation time 668453203 ps
CPU time 6.01 seconds
Started Jul 05 05:13:53 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 222416 kb
Host smart-b04a6f1e-06e5-49a2-b31e-2f11bb144e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223286860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3223286860
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2592541369
Short name T772
Test name
Test status
Simulation time 385230158 ps
CPU time 3.41 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 214224 kb
Host smart-ae03d8a8-c782-4e1b-a29a-a685d8d6d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592541369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2592541369
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2433611995
Short name T587
Test name
Test status
Simulation time 1132053967 ps
CPU time 16.05 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 209644 kb
Host smart-97fe363c-c106-4ebf-8efb-a1faaa426b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433611995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2433611995
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.4026297959
Short name T516
Test name
Test status
Simulation time 984601520 ps
CPU time 10.75 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 209384 kb
Host smart-238bcd47-7325-4fc3-bdee-5499160d5221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026297959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.4026297959
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1727408781
Short name T371
Test name
Test status
Simulation time 2322260242 ps
CPU time 17.82 seconds
Started Jul 05 05:13:41 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 208608 kb
Host smart-711f1450-9efd-4fd3-8f4e-dc095089fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727408781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1727408781
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1940751012
Short name T674
Test name
Test status
Simulation time 88237838 ps
CPU time 3.56 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 208432 kb
Host smart-f2f195e4-b58c-4759-bf45-b3f04b92bed0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940751012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1940751012
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3027578265
Short name T210
Test name
Test status
Simulation time 164148733 ps
CPU time 3.94 seconds
Started Jul 05 05:13:48 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 208524 kb
Host smart-6b6ce45a-a593-445b-b663-3b1a755cb477
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027578265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3027578265
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1591298259
Short name T759
Test name
Test status
Simulation time 714641100 ps
CPU time 24.04 seconds
Started Jul 05 05:13:44 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 208080 kb
Host smart-71a9704e-2ba9-428f-9494-698bac6b41c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591298259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1591298259
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2963946605
Short name T598
Test name
Test status
Simulation time 82484878 ps
CPU time 2.12 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 207448 kb
Host smart-9f37c2e7-6d24-4d88-8063-c921d0bdd5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963946605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2963946605
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2861083365
Short name T468
Test name
Test status
Simulation time 397658784 ps
CPU time 2.77 seconds
Started Jul 05 05:13:45 PM PDT 24
Finished Jul 05 05:13:50 PM PDT 24
Peak memory 206944 kb
Host smart-55de173e-af03-4490-8704-82e2aa7131e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861083365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2861083365
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1437478266
Short name T867
Test name
Test status
Simulation time 2013267135 ps
CPU time 39.87 seconds
Started Jul 05 05:13:49 PM PDT 24
Finished Jul 05 05:14:30 PM PDT 24
Peak memory 222484 kb
Host smart-8c433561-d178-4c19-8ad7-1c0c278656eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437478266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1437478266
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2613277421
Short name T405
Test name
Test status
Simulation time 1223387315 ps
CPU time 21.42 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 221284 kb
Host smart-29f2e8b0-1d9e-40c7-8997-e51f23fe0e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613277421 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2613277421
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1102709782
Short name T545
Test name
Test status
Simulation time 1936066613 ps
CPU time 7.17 seconds
Started Jul 05 05:13:49 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 209316 kb
Host smart-7896001b-6887-4fa1-a108-4d29b7713417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102709782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1102709782
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3568780256
Short name T555
Test name
Test status
Simulation time 177471602 ps
CPU time 2.19 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:55 PM PDT 24
Peak memory 210468 kb
Host smart-f5005661-7758-4ec7-859c-16d760db3f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568780256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3568780256
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1206914913
Short name T430
Test name
Test status
Simulation time 99048375 ps
CPU time 1.15 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 206116 kb
Host smart-2d88e0a4-3134-4ea8-a1ee-3928eedc5abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206914913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1206914913
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.384402033
Short name T411
Test name
Test status
Simulation time 126117623 ps
CPU time 7.33 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 214448 kb
Host smart-4d91b166-5f02-4e6c-964e-24bd00e775ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384402033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.384402033
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3478121534
Short name T27
Test name
Test status
Simulation time 28102616 ps
CPU time 1.77 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 214716 kb
Host smart-de382547-ded2-4d6d-bd3d-d62c289dc798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478121534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3478121534
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1589511237
Short name T915
Test name
Test status
Simulation time 51400396 ps
CPU time 2.1 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:55 PM PDT 24
Peak memory 209960 kb
Host smart-b736e633-b55f-4125-ae4a-e4ea309511b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589511237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1589511237
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1935524527
Short name T828
Test name
Test status
Simulation time 1131439854 ps
CPU time 8.32 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 214296 kb
Host smart-67672336-f60a-4744-99ef-d9b4b569d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935524527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1935524527
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2439657128
Short name T263
Test name
Test status
Simulation time 108532373 ps
CPU time 2.06 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:55 PM PDT 24
Peak memory 214284 kb
Host smart-0ef6bfad-8705-4864-ab37-83719b3939cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439657128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2439657128
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3601254216
Short name T268
Test name
Test status
Simulation time 107332240 ps
CPU time 5.24 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 210000 kb
Host smart-9e2f0c21-dc44-4843-99d8-efc720a6157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601254216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3601254216
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3704849455
Short name T17
Test name
Test status
Simulation time 52383948 ps
CPU time 2.85 seconds
Started Jul 05 05:13:54 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 206900 kb
Host smart-c54272e8-165f-4921-b375-0d9b5ad0d366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704849455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3704849455
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2377508234
Short name T870
Test name
Test status
Simulation time 254942527 ps
CPU time 3.76 seconds
Started Jul 05 05:13:49 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206904 kb
Host smart-080c7918-6a24-43b4-9ec4-3564d9c98afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377508234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2377508234
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3908788066
Short name T843
Test name
Test status
Simulation time 340432516 ps
CPU time 3.55 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 208752 kb
Host smart-e0c94810-9106-4c87-b337-d76c2714756f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908788066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3908788066
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4277874664
Short name T447
Test name
Test status
Simulation time 179913422 ps
CPU time 2.47 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 206776 kb
Host smart-a717bad9-2cc4-4792-91f2-5bb9e1b64616
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277874664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4277874664
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1661661235
Short name T459
Test name
Test status
Simulation time 362314564 ps
CPU time 4.17 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 208776 kb
Host smart-fa23cd01-17b9-41b7-b579-571d04533752
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661661235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1661661235
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1073741870
Short name T799
Test name
Test status
Simulation time 141612495 ps
CPU time 2.24 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 208248 kb
Host smart-be958f42-01c4-4f0b-b37a-a98c3c646e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073741870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1073741870
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4268142993
Short name T564
Test name
Test status
Simulation time 66704705 ps
CPU time 1.67 seconds
Started Jul 05 05:13:50 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 206812 kb
Host smart-0ea05b8b-1977-455f-a892-a4d1d53d9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268142993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4268142993
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3926665341
Short name T658
Test name
Test status
Simulation time 1034762124 ps
CPU time 10.85 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:14:07 PM PDT 24
Peak memory 220520 kb
Host smart-0b4e5c64-525f-433b-955c-3394a8df5bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926665341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3926665341
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.116353932
Short name T356
Test name
Test status
Simulation time 546945628 ps
CPU time 20.55 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:14:17 PM PDT 24
Peak memory 214324 kb
Host smart-a6af16a9-fea6-4aed-820c-2c5f7f5b5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116353932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.116353932
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1371322978
Short name T822
Test name
Test status
Simulation time 312864919 ps
CPU time 3.47 seconds
Started Jul 05 05:13:49 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 210952 kb
Host smart-eb192d41-7145-46e1-a54f-3d43444657e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371322978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1371322978
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.60213439
Short name T532
Test name
Test status
Simulation time 9452766 ps
CPU time 0.81 seconds
Started Jul 05 05:11:00 PM PDT 24
Finished Jul 05 05:11:02 PM PDT 24
Peak memory 206016 kb
Host smart-d701d9e2-9a66-44a9-859c-cf58a462c6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60213439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.60213439
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.917002427
Short name T140
Test name
Test status
Simulation time 223041494 ps
CPU time 6.66 seconds
Started Jul 05 05:10:59 PM PDT 24
Finished Jul 05 05:11:06 PM PDT 24
Peak memory 214360 kb
Host smart-dd50c11b-5f8d-43f6-a2d3-d2c1808fa9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917002427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.917002427
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2237186492
Short name T883
Test name
Test status
Simulation time 59609996 ps
CPU time 1.64 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:10:55 PM PDT 24
Peak memory 207908 kb
Host smart-9969de54-a90a-4077-8b17-bbdba36a49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237186492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2237186492
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.926475689
Short name T87
Test name
Test status
Simulation time 525659316 ps
CPU time 6.74 seconds
Started Jul 05 05:10:58 PM PDT 24
Finished Jul 05 05:11:06 PM PDT 24
Peak memory 209608 kb
Host smart-6e13195d-04b1-4280-815d-8086664ded7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926475689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.926475689
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1627109174
Short name T346
Test name
Test status
Simulation time 108630785 ps
CPU time 2.91 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:55 PM PDT 24
Peak memory 219824 kb
Host smart-8262d33d-d124-4f7e-9aba-66241ca1d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627109174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1627109174
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2506940426
Short name T835
Test name
Test status
Simulation time 70918787 ps
CPU time 2.93 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:10:58 PM PDT 24
Peak memory 209052 kb
Host smart-43625743-0e9f-4385-b9e0-dcd05fb4e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506940426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2506940426
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2379591862
Short name T592
Test name
Test status
Simulation time 976323569 ps
CPU time 7.75 seconds
Started Jul 05 05:10:51 PM PDT 24
Finished Jul 05 05:10:59 PM PDT 24
Peak memory 209140 kb
Host smart-28d84f99-2f85-473d-a55e-02a7ddfd9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379591862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2379591862
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3477439494
Short name T680
Test name
Test status
Simulation time 104559495 ps
CPU time 3.09 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:10:57 PM PDT 24
Peak memory 206780 kb
Host smart-95b1e905-7a7c-49b9-a9a2-01a472fe2787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477439494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3477439494
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4277282005
Short name T767
Test name
Test status
Simulation time 52067132 ps
CPU time 2.41 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:10:57 PM PDT 24
Peak memory 206852 kb
Host smart-a986c5d6-5e8f-4276-895d-eeddccfa3ba9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277282005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4277282005
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1276264287
Short name T303
Test name
Test status
Simulation time 87023788 ps
CPU time 2.93 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:10:57 PM PDT 24
Peak memory 206692 kb
Host smart-06d32a43-88b9-4e21-a2b6-abdb5b697c7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276264287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1276264287
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2718651686
Short name T133
Test name
Test status
Simulation time 163378413 ps
CPU time 2.4 seconds
Started Jul 05 05:10:52 PM PDT 24
Finished Jul 05 05:10:56 PM PDT 24
Peak memory 207012 kb
Host smart-b4f4894f-62cd-4a11-8410-117c8daa5ec9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718651686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2718651686
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1874765077
Short name T451
Test name
Test status
Simulation time 83794345 ps
CPU time 2.16 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:04 PM PDT 24
Peak memory 215864 kb
Host smart-415ea52c-0b5a-4ddd-9822-8d0cc15ce760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874765077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1874765077
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1983767610
Short name T904
Test name
Test status
Simulation time 69826682 ps
CPU time 3.1 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:10:58 PM PDT 24
Peak memory 208692 kb
Host smart-163c896f-ba4e-4291-9d11-dce72467e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983767610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1983767610
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2087036917
Short name T662
Test name
Test status
Simulation time 1709088173 ps
CPU time 22.44 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:24 PM PDT 24
Peak memory 215376 kb
Host smart-81c7e807-4be3-4a43-ac2c-ee8772218d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087036917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2087036917
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2495777729
Short name T349
Test name
Test status
Simulation time 236076038 ps
CPU time 14.92 seconds
Started Jul 05 05:11:03 PM PDT 24
Finished Jul 05 05:11:18 PM PDT 24
Peak memory 222568 kb
Host smart-b11f1c6d-4fd1-4d33-87ad-8b108d522c79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495777729 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2495777729
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2878982585
Short name T358
Test name
Test status
Simulation time 288402881 ps
CPU time 9 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:11:04 PM PDT 24
Peak memory 207612 kb
Host smart-d4af22e9-c927-47a2-90c7-a8450c5adf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878982585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2878982585
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3818748589
Short name T398
Test name
Test status
Simulation time 38083484 ps
CPU time 1.98 seconds
Started Jul 05 05:10:58 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 209852 kb
Host smart-6bcfacc9-4293-4cae-a14c-ee8615302b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818748589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3818748589
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3515905068
Short name T639
Test name
Test status
Simulation time 15463221 ps
CPU time 0.81 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:10 PM PDT 24
Peak memory 206000 kb
Host smart-1c4a7e0f-c0e0-49ba-a65e-8339ed781c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515905068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3515905068
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2933270224
Short name T267
Test name
Test status
Simulation time 176366668 ps
CPU time 3.3 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 215300 kb
Host smart-5551564f-1357-45d1-912d-cab6324a15c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933270224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2933270224
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2197135043
Short name T539
Test name
Test status
Simulation time 221465641 ps
CPU time 2.3 seconds
Started Jul 05 05:11:02 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 208424 kb
Host smart-8f66bf22-3920-434b-b819-e4ebb9fd21ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197135043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2197135043
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3788174636
Short name T101
Test name
Test status
Simulation time 292198848 ps
CPU time 5.69 seconds
Started Jul 05 05:10:59 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 221300 kb
Host smart-be6c30e4-a0ec-48be-906e-3e9b758e4e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788174636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3788174636
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.596939730
Short name T568
Test name
Test status
Simulation time 225188674 ps
CPU time 3.71 seconds
Started Jul 05 05:10:59 PM PDT 24
Finished Jul 05 05:11:03 PM PDT 24
Peak memory 222308 kb
Host smart-588503f4-6480-4c0e-aac1-a78308723aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596939730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.596939730
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2140261967
Short name T733
Test name
Test status
Simulation time 210199019 ps
CPU time 3.31 seconds
Started Jul 05 05:11:00 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 207988 kb
Host smart-1cebbabf-875f-4ebc-835e-53b2fdd66b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140261967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2140261967
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3044979484
Short name T418
Test name
Test status
Simulation time 320252874 ps
CPU time 4.87 seconds
Started Jul 05 05:11:02 PM PDT 24
Finished Jul 05 05:11:07 PM PDT 24
Peak memory 207304 kb
Host smart-3a4729ae-7978-434c-aec9-429948d3b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044979484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3044979484
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1865299821
Short name T533
Test name
Test status
Simulation time 1825776793 ps
CPU time 6.45 seconds
Started Jul 05 05:10:58 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 208712 kb
Host smart-5c408c06-4d3c-4ea6-a4b5-21fc55136c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865299821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1865299821
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2334655192
Short name T360
Test name
Test status
Simulation time 276369932 ps
CPU time 3.08 seconds
Started Jul 05 05:11:02 PM PDT 24
Finished Jul 05 05:11:06 PM PDT 24
Peak memory 206968 kb
Host smart-14746dff-1304-4165-8048-ce5fab9d9f12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334655192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2334655192
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.847942334
Short name T480
Test name
Test status
Simulation time 418093549 ps
CPU time 8.3 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:10 PM PDT 24
Peak memory 206952 kb
Host smart-9a870f1f-832b-4dc2-a531-a84ca7ffdd86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847942334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.847942334
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1549738127
Short name T536
Test name
Test status
Simulation time 35578833 ps
CPU time 2.31 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:04 PM PDT 24
Peak memory 206972 kb
Host smart-b4a11dd4-75f7-4f56-90f1-82cfdf47fa86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549738127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1549738127
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1430159832
Short name T773
Test name
Test status
Simulation time 124374862 ps
CPU time 3.5 seconds
Started Jul 05 05:11:01 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 209928 kb
Host smart-389b0c62-c8fc-4069-b8bd-d556e4beb794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430159832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1430159832
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2585476201
Short name T739
Test name
Test status
Simulation time 93927836 ps
CPU time 1.9 seconds
Started Jul 05 05:11:00 PM PDT 24
Finished Jul 05 05:11:03 PM PDT 24
Peak memory 206832 kb
Host smart-46d3f7af-89af-461f-80cf-b54a661e0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585476201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2585476201
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1851213763
Short name T826
Test name
Test status
Simulation time 1274332832 ps
CPU time 26.93 seconds
Started Jul 05 05:10:59 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 221892 kb
Host smart-40fc61df-eead-4d17-a1f7-4b86ee342e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851213763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1851213763
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1221174005
Short name T365
Test name
Test status
Simulation time 538049951 ps
CPU time 15.31 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 222556 kb
Host smart-74b154ba-d63f-45ae-99d9-94495024fc71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221174005 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1221174005
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.344906126
Short name T323
Test name
Test status
Simulation time 100620153 ps
CPU time 4.35 seconds
Started Jul 05 05:11:12 PM PDT 24
Finished Jul 05 05:11:17 PM PDT 24
Peak memory 214316 kb
Host smart-cf3a05ae-422b-427e-8ead-b3ea3873476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344906126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.344906126
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3289253242
Short name T205
Test name
Test status
Simulation time 100015196 ps
CPU time 3.65 seconds
Started Jul 05 05:11:00 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 209860 kb
Host smart-44f9afe7-66be-499b-9a06-db6de006f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289253242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3289253242
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4062562064
Short name T528
Test name
Test status
Simulation time 18299017 ps
CPU time 0.83 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:10 PM PDT 24
Peak memory 205996 kb
Host smart-601d57a7-c523-4f34-8a97-be8c37bfd74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062562064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4062562064
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3292251004
Short name T425
Test name
Test status
Simulation time 239524652 ps
CPU time 6.86 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 214344 kb
Host smart-a9fbdce9-b542-4f21-9ed4-e3df042a8cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292251004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3292251004
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2059486335
Short name T235
Test name
Test status
Simulation time 405936742 ps
CPU time 4.63 seconds
Started Jul 05 05:11:10 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 214688 kb
Host smart-b3ad2610-a1bb-449b-a3a6-ca2ec85d97ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059486335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2059486335
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1750261819
Short name T51
Test name
Test status
Simulation time 64173290 ps
CPU time 3.22 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 218400 kb
Host smart-86e810e2-f0c1-41af-848a-53404bdfbe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750261819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1750261819
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3384125153
Short name T677
Test name
Test status
Simulation time 71363981 ps
CPU time 2.32 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:12 PM PDT 24
Peak memory 222380 kb
Host smart-8f5fb176-36a2-4605-a7d3-80f0e9f282f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384125153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3384125153
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2516944737
Short name T384
Test name
Test status
Simulation time 519228859 ps
CPU time 4.37 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:14 PM PDT 24
Peak memory 222328 kb
Host smart-b6648f60-4f08-4ac1-9a6b-ecf9ec60b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516944737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2516944737
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.161680289
Short name T63
Test name
Test status
Simulation time 106629474 ps
CPU time 2.39 seconds
Started Jul 05 05:11:10 PM PDT 24
Finished Jul 05 05:11:14 PM PDT 24
Peak memory 216364 kb
Host smart-20c0e64a-7b12-4b38-93a5-dda879156808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161680289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.161680289
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1034741663
Short name T304
Test name
Test status
Simulation time 235012848 ps
CPU time 6.65 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 209204 kb
Host smart-9e01dbd7-f1dc-4b81-8bfb-57e179a8e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034741663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1034741663
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.939847546
Short name T446
Test name
Test status
Simulation time 283747414 ps
CPU time 2.87 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 206888 kb
Host smart-852908e9-1ba1-4ec7-a269-99a2f5911f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939847546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.939847546
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.186266741
Short name T697
Test name
Test status
Simulation time 234459322 ps
CPU time 6.89 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:17 PM PDT 24
Peak memory 207964 kb
Host smart-35e11c61-8b10-423a-8abc-8abd87857261
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186266741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.186266741
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3347285162
Short name T523
Test name
Test status
Simulation time 100786435 ps
CPU time 4.47 seconds
Started Jul 05 05:11:11 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 208884 kb
Host smart-dcaf5de9-926c-480a-91e9-0d768a3c5e71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347285162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3347285162
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2096808242
Short name T891
Test name
Test status
Simulation time 401342402 ps
CPU time 4.04 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 208828 kb
Host smart-a3a38d9d-6144-45ec-82e3-24e5a167f6f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096808242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2096808242
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2524409308
Short name T424
Test name
Test status
Simulation time 79767891 ps
CPU time 2.15 seconds
Started Jul 05 05:11:10 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 209312 kb
Host smart-292c1340-ba0e-4431-a862-6a6cd36f84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524409308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2524409308
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3061392925
Short name T690
Test name
Test status
Simulation time 111036829 ps
CPU time 2.96 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 206708 kb
Host smart-9652f806-996f-432d-a5f0-8d333423eed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061392925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3061392925
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2995089718
Short name T233
Test name
Test status
Simulation time 8165857465 ps
CPU time 85.99 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:12:37 PM PDT 24
Peak memory 216112 kb
Host smart-0a9c48cf-fc34-4fbc-bfe9-f8ab0e9ad01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995089718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2995089718
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1965871543
Short name T184
Test name
Test status
Simulation time 1882933135 ps
CPU time 17.78 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 219220 kb
Host smart-a9db889b-7aba-40a5-9d98-e7f12f804d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965871543 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1965871543
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2200443450
Short name T325
Test name
Test status
Simulation time 33389282 ps
CPU time 2.31 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 207732 kb
Host smart-57beb5ea-ee65-4cca-9660-d52dea95c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200443450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2200443450
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3096801901
Short name T647
Test name
Test status
Simulation time 47855313 ps
CPU time 1.88 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:12 PM PDT 24
Peak memory 209976 kb
Host smart-512114ec-32a3-4cb4-9754-7c18344ea74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096801901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3096801901
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.484396386
Short name T550
Test name
Test status
Simulation time 8855349 ps
CPU time 0.71 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 205924 kb
Host smart-0525052b-0099-4b28-a2c9-41674bbd777d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484396386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.484396386
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1547529034
Short name T415
Test name
Test status
Simulation time 7495730764 ps
CPU time 102.22 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:13:00 PM PDT 24
Peak memory 221108 kb
Host smart-3a6e0af1-28d3-47d1-98f0-ef5aff31ed17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547529034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1547529034
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3522605319
Short name T913
Test name
Test status
Simulation time 106608345 ps
CPU time 1.87 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:19 PM PDT 24
Peak memory 219152 kb
Host smart-912a1030-8d32-42bc-a632-3edbc7cbab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522605319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3522605319
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3054514938
Short name T718
Test name
Test status
Simulation time 341580299 ps
CPU time 2.8 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 208216 kb
Host smart-3f051552-0b23-4e3f-aa36-3efb51bb8eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054514938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3054514938
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.879949785
Short name T804
Test name
Test status
Simulation time 210456234 ps
CPU time 3.97 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 213680 kb
Host smart-bafd47d4-cf8d-4f3d-938f-b4e75de240c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879949785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.879949785
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.546297890
Short name T264
Test name
Test status
Simulation time 401333389 ps
CPU time 5.21 seconds
Started Jul 05 05:11:15 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 214520 kb
Host smart-54eb27c3-3171-4423-8d75-129e8c732382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546297890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.546297890
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2280287004
Short name T853
Test name
Test status
Simulation time 226339683 ps
CPU time 3.03 seconds
Started Jul 05 05:11:19 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 215616 kb
Host smart-d8a863a9-5308-4c48-8cd5-28f5aa8e1768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280287004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2280287004
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2995889387
Short name T857
Test name
Test status
Simulation time 196148362 ps
CPU time 7.53 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 209824 kb
Host smart-a687021b-97a9-4cee-800d-f03c6ea6df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995889387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2995889387
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4195709743
Short name T352
Test name
Test status
Simulation time 916640155 ps
CPU time 25 seconds
Started Jul 05 05:11:09 PM PDT 24
Finished Jul 05 05:11:36 PM PDT 24
Peak memory 208824 kb
Host smart-194a4d29-bfb9-41f7-bd3e-0d94b7dcbb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195709743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4195709743
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4206905692
Short name T577
Test name
Test status
Simulation time 292495131 ps
CPU time 3.72 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 208712 kb
Host smart-bd4e75f4-b356-4717-a9c0-f43e63bfed96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206905692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4206905692
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.187426970
Short name T595
Test name
Test status
Simulation time 616458178 ps
CPU time 16.77 seconds
Started Jul 05 05:11:07 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 208512 kb
Host smart-a57c7032-d16c-4983-9923-c98597598811
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187426970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.187426970
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3435543659
Short name T83
Test name
Test status
Simulation time 560525873 ps
CPU time 6.47 seconds
Started Jul 05 05:11:08 PM PDT 24
Finished Jul 05 05:11:15 PM PDT 24
Peak memory 207016 kb
Host smart-b49b89dd-8745-4e31-92a6-99c216e6ed11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435543659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3435543659
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3409658384
Short name T824
Test name
Test status
Simulation time 30332112 ps
CPU time 2.5 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:20 PM PDT 24
Peak memory 208312 kb
Host smart-49f55320-a11d-479f-bf12-54fdf6b2b922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409658384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3409658384
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2112318539
Short name T722
Test name
Test status
Simulation time 38750619 ps
CPU time 2.23 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:20 PM PDT 24
Peak memory 208456 kb
Host smart-104df789-8b8a-467b-849b-0e233d236035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112318539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2112318539
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3220892202
Short name T313
Test name
Test status
Simulation time 294271992 ps
CPU time 6.21 seconds
Started Jul 05 05:11:20 PM PDT 24
Finished Jul 05 05:11:27 PM PDT 24
Peak memory 219556 kb
Host smart-08724ebb-b364-400b-a1b3-6c31b34747c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220892202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3220892202
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3985031860
Short name T361
Test name
Test status
Simulation time 24660356 ps
CPU time 2.11 seconds
Started Jul 05 05:11:15 PM PDT 24
Finished Jul 05 05:11:18 PM PDT 24
Peak memory 207692 kb
Host smart-3ca920f5-f3c8-4275-837b-2cb7bc8fb543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985031860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3985031860
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3810624658
Short name T514
Test name
Test status
Simulation time 65814226 ps
CPU time 1.73 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:19 PM PDT 24
Peak memory 209940 kb
Host smart-c5173155-7753-4281-90a9-46699c784e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810624658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3810624658
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.652168095
Short name T444
Test name
Test status
Simulation time 40051940 ps
CPU time 0.73 seconds
Started Jul 05 05:11:24 PM PDT 24
Finished Jul 05 05:11:26 PM PDT 24
Peak memory 205392 kb
Host smart-4ae79b33-5e04-4f3f-8bb1-ec569ca5a585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652168095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.652168095
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2774379880
Short name T414
Test name
Test status
Simulation time 227534695 ps
CPU time 4.23 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 214620 kb
Host smart-d7739868-4017-4dc9-95a0-b3369e34220c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774379880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2774379880
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2317731113
Short name T917
Test name
Test status
Simulation time 658569423 ps
CPU time 3.6 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:11:23 PM PDT 24
Peak memory 208652 kb
Host smart-13bc188d-1edd-49ac-80ed-ed7e3832ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317731113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2317731113
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.674765172
Short name T486
Test name
Test status
Simulation time 58104784 ps
CPU time 1.91 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 206904 kb
Host smart-1a86fcb3-f3a6-466f-82ea-b0b7465825dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674765172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.674765172
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1570638644
Short name T247
Test name
Test status
Simulation time 2485201972 ps
CPU time 53.57 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:12:12 PM PDT 24
Peak memory 214396 kb
Host smart-b6ab4ea4-dbc9-4824-a8e5-0bb8382c7ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570638644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1570638644
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2692497327
Short name T682
Test name
Test status
Simulation time 72325029 ps
CPU time 3.55 seconds
Started Jul 05 05:11:25 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 214160 kb
Host smart-91afdd5a-24e4-4951-a150-7aa808a02876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692497327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2692497327
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1280243402
Short name T884
Test name
Test status
Simulation time 295011009 ps
CPU time 3.69 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 216288 kb
Host smart-809249b2-bd54-45f0-92da-e699c5f69eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280243402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1280243402
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.29758563
Short name T132
Test name
Test status
Simulation time 5910603949 ps
CPU time 37.65 seconds
Started Jul 05 05:11:15 PM PDT 24
Finished Jul 05 05:11:53 PM PDT 24
Peak memory 209692 kb
Host smart-0b2abba4-14bc-4900-8156-1c2f21aed7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29758563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.29758563
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1332741639
Short name T285
Test name
Test status
Simulation time 95383925 ps
CPU time 3.96 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 208692 kb
Host smart-5ff959d3-8cc2-4a13-9310-aa915f2af226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332741639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1332741639
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1795768331
Short name T627
Test name
Test status
Simulation time 487639873 ps
CPU time 3.67 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 206952 kb
Host smart-7c4a464f-e0f7-40c6-a1d0-c9f21420e8d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795768331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1795768331
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2884299893
Short name T479
Test name
Test status
Simulation time 227105685 ps
CPU time 3.26 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 206984 kb
Host smart-394545b0-e0f0-4808-bf0c-96dabb636f76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884299893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2884299893
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3153200568
Short name T582
Test name
Test status
Simulation time 68258172 ps
CPU time 2.7 seconds
Started Jul 05 05:11:22 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 208964 kb
Host smart-812cc5c6-da96-45a2-9046-8ca1d2427882
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153200568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3153200568
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1303038600
Short name T419
Test name
Test status
Simulation time 186486618 ps
CPU time 4.9 seconds
Started Jul 05 05:11:18 PM PDT 24
Finished Jul 05 05:11:24 PM PDT 24
Peak memory 210180 kb
Host smart-311f404f-ea7a-4d50-b88d-f300a18f4f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303038600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1303038600
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3101524571
Short name T643
Test name
Test status
Simulation time 12088822862 ps
CPU time 34.95 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:52 PM PDT 24
Peak memory 207976 kb
Host smart-39e41735-8ec0-48b4-8deb-3ec8e73ca30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101524571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3101524571
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1707993396
Short name T61
Test name
Test status
Simulation time 588347375 ps
CPU time 13.11 seconds
Started Jul 05 05:11:16 PM PDT 24
Finished Jul 05 05:11:31 PM PDT 24
Peak memory 222644 kb
Host smart-c32aa557-ccbf-4c9d-8256-f3aed00716d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707993396 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1707993396
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1002850185
Short name T876
Test name
Test status
Simulation time 181055188 ps
CPU time 6.87 seconds
Started Jul 05 05:11:17 PM PDT 24
Finished Jul 05 05:11:25 PM PDT 24
Peak memory 209364 kb
Host smart-0667e479-a0b4-4065-99b8-5b397acd6ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002850185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1002850185
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2133377149
Short name T581
Test name
Test status
Simulation time 37828696 ps
CPU time 1.52 seconds
Started Jul 05 05:11:21 PM PDT 24
Finished Jul 05 05:11:23 PM PDT 24
Peak memory 209908 kb
Host smart-477964c0-8c38-4da8-b0a4-9772ed182edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133377149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2133377149
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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