Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	40	1			T13	1		T37	1		T46	1
auto[OpGenId]	19	1			T7	1		T17	1		T53	1
auto[OpGenSwOut]	21	1			T23	2		T5	1		T183	1
auto[OpGenHwOut]	22	1			T4	1		T24	1		T5	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1894	1			T12	2		T13	1		T15	2
auto[StInit]	91	1			T13	1		T23	1		T36	1
auto[StCreatorRootKey]	81	1			T7	1		T12	1		T26	1
auto[StOwnerIntKey]	42	1			T1	1		T15	1		T23	1
auto[StOwnerKey]	32	1			T15	1		T37	1		T40	1
auto[StDisabled]	479	1			T12	2		T13	3		T15	6
auto[StInvalid]	50	1			T34	1		T49	1		T35	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3653

1

T1

2

T2

1

T3

1

auto[1]

102

1

T7

1

T13

1

T37

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1893	1			T12	2		T13	1		T15	2
auto[StReset]	auto[1]	1	1			T50	1		-	-		-	-
auto[StInit]	auto[0]	52	1			T36	1		T52	1		T59	2
auto[StInit]	auto[1]	39	1			T13	1		T23	1		T17	1
auto[StCreatorRootKey]	auto[0]	54	1			T12	1		T26	1		T59	2
auto[StCreatorRootKey]	auto[1]	27	1			T7	1		T53	1		T54	1
auto[StOwnerIntKey]	auto[0]	28	1			T1	1		T15	1		T57	1
auto[StOwnerIntKey]	auto[1]	14	1			T23	1		T46	1		T183	1
auto[StOwnerKey]	auto[0]	22	1			T15	1		T40	1		T41	1
auto[StOwnerKey]	auto[1]	10	1			T37	1		T5	2		T60	1
auto[StDisabled]	auto[0]	468	1			T12	2		T13	3		T15	6
auto[StDisabled]	auto[1]	11	1			T4	1		T183	1		T196	1
auto[StInvalid]	auto[0]	50	1			T34	1		T49	1		T35	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	1	1			T50	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	17	1			T13	1		T47	1		T183	1
auto[StInit]	auto[OpGenId]	7	1			T17	1		T197	1		T198	1
auto[StInit]	auto[OpGenSwOut]	6	1			T23	1		T198	1		T199	1
auto[StInit]	auto[OpGenHwOut]	9	1			T6	1		T200	1		T201	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T56	1		T39	1		T99	1
auto[StCreatorRootKey]	auto[OpGenId]	6	1			T7	1		T53	1		T54	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T202	1		T99	1		T203	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T24	1		T204	1		T99	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T46	1		T175	1		T196	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T60	1		T200	1		T205	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T23	1		T183	1		T206	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T207	1		T205	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	3	1			T37	1		T60	1		T20	1
auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T5	1		T50	1		T208	1
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T5	1		T209	1		T210	1
auto[StDisabled]	auto[OpAdvance]	4	1			T183	1		T205	1		T211	1
auto[StDisabled]	auto[OpGenId]	3	1			T196	1		T212	1		T213	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T214	1		T215	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T4	1		T50	1		-	-