Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4799

1

T2

3

T3

6

T7

1

auto[1]

560

1

T12

1

T14

1

T15

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4799

1

T2

3

T3

6

T7

1

auto[1]

560

1

T12

1

T14

1

T15

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4843

1

T2

3

T3

6

T7

1

auto[1]

516

1

T15

1

T45

3

T23

5

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4843

1

T2

3

T3

6

T7

1

auto[1]

516

1

T15

1

T45

3

T23

5

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	1		T3	1		T12	1
auto[OpGenId]	1147	1			T2	2		T3	2		T12	1
auto[OpGenSwOut]	1181	1			T3	2		T12	3		T13	3
auto[OpGenHwOut]	2523	1			T3	1		T7	1		T12	3
auto[OpDisable]	76	1			T23	1		T51	1		T54	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	1		T3	1		T12	1
auto[OpGenId]	1147	1			T2	2		T3	2		T12	1
auto[OpGenSwOut]	1181	1			T3	2		T12	3		T13	3
auto[OpGenHwOut]	2523	1			T3	1		T7	1		T12	3
auto[OpDisable]	76	1			T23	1		T51	1		T54	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4823

1

T2

3

T3

6

T7

1

auto[1]

536

1

T15

1

T44

6

T23

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4823

1

T2

3

T3

6

T7

1

auto[1]

536

1

T15

1

T44

6

T23

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5054

1

T2

3

T3

6

T7

1

auto[1]

305

1

T123

6

T124

5

T125

13

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1806	1			T2	1		T3	2		T7	1
auto[1]	694	1			T2	1		T3	1		T12	2
auto[2]	729	1			T15	3		T45	2		T34	1
auto[3]	763	1			T2	1		T3	1		T12	1
auto[4]	364	1			T3	1		T15	3		T44	2
auto[5]	354	1			T3	1		T12	1		T13	1
auto[6]	326	1			T15	2		T45	1		T49	1
auto[7]	323	1			T16	1		T45	1		T81	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1367	1			T3	2		T12	1		T13	1
clear_one[1]	694	1			T2	1		T3	1		T12	2
clear_one[2]	729	1			T15	3		T45	2		T34	1
clear_one[3]	763	1			T2	1		T3	1		T12	1
clear_none	1806	1			T2	1		T3	2		T7	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1050	1			T2	1		T12	3		T15	5
auto[StInit]	662	1			T3	4		T7	1		T12	2
auto[StCreatorRootKey]	598	1			T2	1		T3	1		T12	2
auto[StOwnerIntKey]	502	1			T2	1		T3	1		T13	1
auto[StOwnerKey]	476	1			T12	1		T13	1		T15	3
auto[StDisabled]	1801	1			T13	3		T15	9		T79	2
auto[StInvalid]	270	1			T16	3		T34	2		T49	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1050	1			T2	1		T12	3		T15	5
auto[StInit]	662	1			T3	4		T7	1		T12	2
auto[StCreatorRootKey]	598	1			T2	1		T3	1		T12	2
auto[StOwnerIntKey]	502	1			T2	1		T3	1		T13	1
auto[StOwnerKey]	476	1			T12	1		T13	1		T15	3
auto[StDisabled]	1801	1			T13	3		T15	9		T79	2
auto[StInvalid]	270	1			T16	3		T34	2		T49	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	6
[auto[1] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	6
[auto[1] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	24
[auto[1] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	6
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T124	1		T76	1		T216	1
auto[0]	auto[StReset]	auto[OpGenId]	187	1			T2	1		T15	1		T23	4
auto[0]	auto[StReset]	auto[OpGenSwOut]	178	1			T12	1		T15	1		T33	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	244	1			T12	1		T15	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T123	1		T143	1		T217	2
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T3	1		T15	1		T51	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	95	1			T13	1		T15	1		T79	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	177	1			T3	1		T7	1		T12	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	18	1			T124	1		T195	1		T76	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	48	1			T14	1		T15	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	43	1			T12	1		T13	1		T218	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	89	1			T23	1		T137	1		T140	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T124	1		T71	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T219	1		T196	1		T220	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T33	1		T124	1		T59	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	69	1			T44	1		T23	1		T137	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T124	1		T174	1		T221	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T15	1		T174	1		T175	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T23	1		T54	1		T47	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T44	1		T23	1		T139	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	27	1			T71	1		T78	1		T47	1
auto[0]	auto[StDisabled]	auto[OpGenId]	54	1			T51	1		T195	1		T78	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T120	1		T78	2		T47	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T44	1		T189	1		T23	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T23	1		T54	1		T73	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T222	1		T100	1		T83	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T16	1		T58	1		T222	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T49	1		T223	1		T224	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	23	1			T34	1		T49	1		T35	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T183	1		T225	1		T61	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	27	1			T12	1		T21	1		T5	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	46	1			T44	2		T226	1		T227	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T33	1		T5	1		T63	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T15	1		T126	1		T87	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T198	1		T228	1		T177	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	20	1			T126	1		T54	1		T85	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T143	1		T217	1		T175	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T2	1		T15	1		T35	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T85	1		T196	1		T99	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T47	1		T5	1		T229	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T23	1		T230	1		T217	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T47	1		T196	1		T231	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T3	1		T183	1		T175	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T15	1		T45	1		T51	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	16	1			T12	1		T66	2		T50	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	18	1			T23	1		T143	1		T183	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T23	1		T232	1		T233	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T37	1		T81	1		T59	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T123	1		T195	1		T143	2
auto[1]	auto[StDisabled]	auto[OpGenId]	49	1			T13	1		T15	2		T79	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T15	1		T51	1		T54	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T15	1		T45	1		T23	2
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T234	1		T60	1		T64	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T223	1		T224	1		T235	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T236	1		T237	1		T83	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T16	1		T49	1		T222	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T86	1		T83	1		T238	1
auto[2]	auto[StReset]	auto[OpGenId]	20	1			T51	1		T73	1		T47	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T15	1		T26	1		T226	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T34	1		T194	1		T227	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T175	1		T220	1		T239	2
auto[2]	auto[StInit]	auto[OpGenId]	4	1			T87	1		T240	1		T241	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T56	1		T5	1		T87	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T194	1		T85	1		T75	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T82	1		T242	1		T243	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	25	1			T59	1		T142	1		T244	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T142	1		T22	1		T219	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T45	1		T81	1		T75	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T50	1		T245	1		T198	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T126	1		T195	1		T54	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T246	1		T247	1		T200	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T81	1		T139	1		T248	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T249	1		T250	1		T251	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T252	1		T253	1		T254	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T126	1		T255	1		T54	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T45	1		T141	1		T190	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T126	2		T127	1		T54	1
auto[2]	auto[StDisabled]	auto[OpGenId]	58	1			T15	1		T23	3		T54	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T15	1		T23	2		T141	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T44	3		T81	1		T23	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T62	1		T256	1		T103	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T226	1		T104	1		T257	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T258	1		T83	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T49	1		T260	1		T83	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T226	1		T261	1		T262	1
auto[3]	auto[StReset]	auto[OpGenId]	17	1			T56	1		T263	1		T264	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	24	1			T53	1		T54	1		T56	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	62	1			T44	1		T120	1		T21	2
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T3	1		T85	1		T78	2
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T247	1		T265	1		T266	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	15	1			T22	1		T197	1		T175	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T15	1		T189	1		T122	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T59	1		T78	1		T56	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T54	1		T267	1		T247	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T15	1		T79	1		T23	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T12	1		T139	1		T268	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T2	1		T140	1		T129	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T117	2		T221	1		T87	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	26	1			T13	1		T78	1		T269	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T189	1		T121	1		T75	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T33	1		T125	1		T196	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	20	1			T13	1		T182	1		T78	2
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T54	1		T78	3		T270	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T15	1		T194	1		T195	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	35	1			T137	1		T125	2		T218	1
auto[3]	auto[StDisabled]	auto[OpGenId]	42	1			T141	1		T125	2		T255	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T15	1		T141	1		T125	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T13	1		T45	1		T81	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T117	1		T63	1		T66	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T16	1		T259	1		T271	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T236	1		T223	1		T262	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T261	1		T84	1		T272	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T58	1		T273	1		T100	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T15	1		T60	1		T274	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T23	1		T50	1		T261	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T44	1		T226	1		T75	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T177	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T22	1		T275	1		T117	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T246	1		T67	1		T276	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T73	1		T275	1		T174	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T60	1		T277	1		T278	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T56	1		T60	1		T63	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T3	1		T15	1		T51	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T44	1		T279	1		T280	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T47	1		T60	1		T99	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T116	1		T281	1		T282	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T283	1		T196	1		T64	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T191	1		T284	1		T285	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T228	1		T286	1		T287	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T60	2		T288	1		T289	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T283	1		T247	1		T290	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T121	1		T51	1		T191	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T123	1		T291	2		T278	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T23	2		T292	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T15	1		T218	1		T54	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	62	1			T81	1		T189	1		T143	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T293	1		T175	1		T294	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T295	1		T296	1		T297	1
auto[4]	auto[StInvalid]	auto[OpGenId]	9	1			T237	1		T298	1		T299	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T104	1		T300	1		T295	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T236	1		T104	1		T301	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T26	1		T23	1		T54	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T182	1		T64	1		T302	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T23	1		T194	1		T54	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T125	1		T103	1		T90	1
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T3	1		T12	1		T303	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	9	1			T142	2		T220	1		T200	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T44	1		T121	1		T56	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T82	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T125	1		T62	1		T263	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T119	1		T175	1		T50	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T189	1		T248	1		T304	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T76	1		T305	4		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T125	2		T183	1		T103	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T125	1		T306	1		T307	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T308	1		T309	1		T64	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T123	3		T310	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T174	1		T66	1		T205	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T76	1		T5	1		T116	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T79	1		T140	1		T74	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T275	1		T117	1		T60	2
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T13	1		T311	1		T275	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T123	1		T183	1		T174	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	65	1			T79	1		T23	1		T121	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T65	1		T50	1		T312	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T313	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T298	1		T259	1		T261	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T34	1		T58	1		T258	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T35	1		T260	1		T100	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T234	1		T117	1		T240	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T221	1		T267	1		T200	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T284	2		T314	1		T315	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T174	1		T50	1		T316	1
auto[6]	auto[StInit]	auto[OpGenId]	12	1			T252	1		T60	1		T288	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T77	1		T204	1		T317	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T318	1		T227	1		T280	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T319	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T19	1		T176	1		T320	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T26	1		T247	1		T19	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T191	1		T321	1		T256	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T230	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T82	1		T174	1		T64	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T176	1		T322	1		T323	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T194	1		T229	1		T117	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T324	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T15	1		T176	1		T325	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T230	1		T60	1		T99	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T189	1		T314	1		T326	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T117	1		T200	1		T327	2
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T15	1		T23	1		T74	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T255	1		T232	1		T174	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T45	1		T75	1		T318	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T60	1		T328	1		T312	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T235	1		T329	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T273	1		T330	1		T331	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T49	1		T35	1		T329	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T332	1		T261	1		T302	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T64	1		T333	1		T327	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	15	1			T23	1		T54	1		T334	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	15	1			T16	1		T23	1		T60	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T119	1		T64	1		T65	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T183	1		T117	1		T196	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T335	1		T198	1		T336	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T305	1		T287	1		T337	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T126	2		T117	1		T196	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T123	2		T196	1		T220	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T121	1		T338	1		T339	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T123	1		T211	1		T340	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T255	1		T275	3		T64	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T275	1		T47	1		T317	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	14	1			T23	1		T304	1		T341	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T291	1		T342	1		T343	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T175	1		T344	1		T345	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T183	1		T346	1		T196	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T339	1		T279	1		T347	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T124	1		T142	1		T64	1
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T124	2		T54	1		T77	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T74	1		T5	1		T174	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T45	1		T81	1		T23	2
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T51	1		T63	1		T64	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T58	1		T298	1		T299	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T260	1		T104	1		T348	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T349	1		T350	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T236	1		T299	1		T348	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1367

1

T3

2

T12

1

T13

1

clear_one[1]

auto[0]

auto[0]

auto[0]

426

1

T2

1

T3

1

T12

2

clear_one[1]

auto[0]

auto[0]

auto[1]

133

1

T15

1

T23

1

T268

2

clear_one[1]

auto[0]

auto[1]

auto[0]

106

1

T15

1

T45

2

T23

1

clear_one[1]

auto[0]

auto[1]

auto[1]

29

1

T23

1

T59

1

T56

1

clear_one[2]

auto[0]

auto[0]

auto[0]

423

1

T15

1

T45

2

T34

1

clear_one[2]

auto[0]

auto[0]

auto[1]

118

1

T44

3

T23

2

T141

1

clear_one[2]

auto[1]

auto[0]

auto[0]

131

1

T15

2

T81

3

T23

1

clear_one[2]

auto[1]

auto[0]

auto[1]

57

1

T137

1

T192

1

T190

1

clear_one[3]

auto[0]

auto[0]

auto[0]

440

1

T2

1

T3

1

T13

3

clear_one[3]

auto[0]

auto[1]

auto[0]

148

1

T45

1

T23

1

T194

2

clear_one[3]

auto[1]

auto[0]

auto[0]

141

1

T12

1

T15

1

T33

1

clear_one[3]

auto[1]

auto[1]

auto[0]

34

1

T352

1

T5

2

T183

1

clear_none

auto[0]

auto[0]

auto[0]

1335

1

T2

1

T3

2

T7

1

clear_none

auto[0]

auto[0]

auto[1]

120

1

T44

3

T191

1

T195

1

clear_none

auto[0]

auto[1]

auto[0]

121

1

T194

1

T54

2

T71

2

clear_none

auto[0]

auto[1]

auto[1]

33

1

T192

1

T95

1

T188

1

clear_none

auto[1]

auto[0]

auto[0]

119

1

T14

1

T33

1

T189

1

clear_none

auto[1]

auto[0]

auto[1]

33

1

T21

1

T352

1

T183

1

clear_none

auto[1]

auto[1]

auto[0]

32

1

T23

2

T78

4

T5

1

clear_none

auto[1]

auto[1]

auto[1]

13

1

T120

1

T192

1

T5

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1272	1			T3	2		T12	1		T13	1
clear_all	auto[1]	95	1			T123	6		T124	1		T125	8
clear_one[1]	auto[0]	645	1			T2	1		T3	1		T12	2
clear_one[1]	auto[1]	49	1			T126	1		T143	5		T217	3
clear_one[2]	auto[0]	668	1			T15	3		T45	2		T34	1
clear_one[2]	auto[1]	61	1			T126	4		T142	1		T127	3
clear_one[3]	auto[0]	724	1			T2	1		T3	1		T12	1
clear_one[3]	auto[1]	39	1			T125	5		T230	6		T78	10
clear_none	auto[0]	1745	1			T2	1		T3	2		T7	1
clear_none	auto[1]	61	1			T124	4		T127	4		T76	2