Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11300

1

T1

13

T2

16

T3

13

auto[Attestation]

7986

1

T1

7

T2

3

T3

9

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2801	1			T1	3		T2	3		T3	2
auto[Aes]	3431	1			T1	5		T2	7		T3	8
auto[Kmac]	3418	1			T1	2		T2	1		T3	2
auto[Otbn]	3471	1			T1	6		T2	2		T3	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7766	1			T1	3		T2	3		T3	8
auto[OpGenId]	6165	1			T1	4		T2	6		T3	6
auto[OpGenSwOut]	6149	1			T1	7		T2	1		T3	11
auto[OpGenHwOut]	6972	1			T1	9		T2	12		T3	5
auto[OpDisable]	156	1			T12	1		T23	2		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10890

1

T1

10

T2

8

T3

10

auto[OpDoneFail]

16318

1

T1

13

T2

14

T3

20

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6750	1			T1	11		T2	12		T3	1
auto[StInit]	3925	1			T1	4		T2	4		T3	20
auto[StCreatorRootKey]	3304	1			T1	4		T2	3		T3	5
auto[StOwnerIntKey]	2789	1			T1	4		T2	3		T3	4
auto[StOwnerKey]	2507	1			T11	2		T12	1		T13	5
auto[StDisabled]	7933	1			T11	7		T12	13		T13	15

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	345	1			T12	1		T13	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T3	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T11	1		T14	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	81	1			T12	1		T15	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T182	1		T76	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	204	1			T12	1		T13	2		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	343	1			T1	1		T12	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T3	2		T38	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	84	1			T3	1		T23	4		T138	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T3	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	48	1			T23	1		T122	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	218	1			T11	1		T15	2		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	362	1			T12	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	87	1			T12	1		T15	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T15	1		T80	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T3	1		T185	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T80	1		T23	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	230	1			T80	1		T186	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	347	1			T1	1		T12	2		T33	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	98	1			T23	2		T4	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T13	1		T33	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T1	1		T13	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	69	1			T119	1		T54	2		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	209	1			T11	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	112	1			T23	3		T51	2		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T1	1		T15	2		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T33	1		T26	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	80	1			T1	1		T33	2		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	69	1			T15	1		T137	1		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	208	1			T15	1		T186	1		T23	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	94	1			T15	4		T23	3		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T1	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T13	1		T15	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	67	1			T3	1		T13	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T13	1		T15	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	238	1			T186	1		T23	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T23	1		T35	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	112	1			T3	1		T12	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T12	1		T15	2		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T15	1		T23	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	54	1			T23	1		T137	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	238	1			T13	2		T15	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	97	1			T15	1		T23	5		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T3	2		T12	2		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T2	1		T15	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T1	1		T15	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T23	2		T138	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	223	1			T11	1		T12	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	281	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	85	1			T2	2		T14	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T3	1		T141	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T54	1		T5	2		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T23	1		T141	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	169	1			T12	1		T23	4		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	444	1			T1	3		T2	4		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	124	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T12	1		T14	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T2	1		T15	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T37	1		T189	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	279	1			T12	2		T15	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	445	1			T1	1		T12	1		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T7	1		T45	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	130	1			T45	1		T23	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T2	1		T45	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	82	1			T33	1		T190	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	284	1			T12	1		T15	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	485	1			T1	2		T2	1		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T3	1		T14	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	122	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T15	1		T141	1		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	95	1			T44	1		T23	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	255	1			T15	1		T44	3		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T23	1		T51	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T23	1		T137	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T1	1		T140	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T35	1		T48	2		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T23	1		T140	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	185	1			T12	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T15	1		T23	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	136	1			T3	1		T12	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	116	1			T14	2		T37	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T2	1		T15	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T15	1		T33	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	265	1			T81	3		T189	2		T23	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T15	1		T23	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T1	1		T13	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T14	1		T57	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T23	2		T194	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	102	1			T45	1		T140	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	259	1			T45	2		T23	4		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T23	4		T59	2		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T15	1		T23	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	122	1			T15	2		T191	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T44	1		T23	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T23	1		T122	1		T195	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	306	1			T44	1		T23	7		T4	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	214	1			T11	1		T12	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	668	1			T3	1		T12	2		T13	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T3	2		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	679	1			T1	1		T3	2		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T3	1		T80	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	697	1			T12	2		T13	1		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T1	1		T13	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	670	1			T1	1		T11	1		T12	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	221	1			T1	1		T15	1		T33	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	444	1			T1	1		T15	3		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	202	1			T3	1		T13	3		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	478	1			T1	1		T3	1		T15	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	188	1			T12	1		T15	3		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	429	1			T3	1		T12	1		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	461	1			T3	2		T11	1		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T3	1		T23	1		T141	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	553	1			T2	3		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	264	1			T2	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	856	1			T1	3		T2	5		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	290	1			T2	1		T33	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	855	1			T1	1		T7	1		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	294	1			T1	1		T15	2		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	876	1			T1	2		T2	1		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	168	1			T1	1		T23	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	358	1			T12	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T2	1		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	480	1			T3	1		T12	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T14	1		T45	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	483	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	264	1			T15	2		T44	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	506	1			T15	1		T44	1		T23	13