Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33276

1

T1

25

T2

23

T3

35

auto[1]

247

1

T123

2

T124

5

T125

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33287	1			T1	25		T2	23		T3	35
auto[134217728:268435455]	4	1			T239	1		T251	1		T376	1
auto[268435456:402653183]	7	1			T123	1		T230	1		T129	1
auto[402653184:536870911]	9	1			T366	2		T364	1		T291	1
auto[536870912:671088639]	5	1			T124	1		T78	1		T307	1
auto[671088640:805306367]	11	1			T142	2		T127	1		T76	2
auto[805306368:939524095]	10	1			T124	1		T126	1		T230	1
auto[939524096:1073741823]	6	1			T126	1		T230	1		T76	1
auto[1073741824:1207959551]	7	1			T124	1		T126	1		T364	1
auto[1207959552:1342177279]	6	1			T142	1		T291	1		T239	1
auto[1342177280:1476395007]	7	1			T124	1		T78	1		T129	2
auto[1476395008:1610612735]	2	1			T76	1		T377	1		-	-
auto[1610612736:1744830463]	6	1			T126	1		T275	1		T364	1
auto[1744830464:1879048191]	7	1			T230	1		T127	3		T366	1
auto[1879048192:2013265919]	9	1			T126	1		T143	1		T275	1
auto[2013265920:2147483647]	10	1			T125	1		T364	1		T367	1
auto[2147483648:2281701375]	8	1			T367	1		T291	1		T307	2
auto[2281701376:2415919103]	10	1			T230	1		T127	1		T78	1
auto[2415919104:2550136831]	6	1			T143	1		T78	1		T275	1
auto[2550136832:2684354559]	13	1			T143	1		T76	1		T275	1
auto[2684354560:2818572287]	12	1			T230	1		T127	1		T76	1
auto[2818572288:2952790015]	9	1			T127	2		T275	1		T307	1
auto[2952790016:3087007743]	8	1			T124	1		T125	1		T142	1
auto[3087007744:3221225471]	8	1			T76	2		T78	1		T307	1
auto[3221225472:3355443199]	8	1			T123	1		T76	1		T305	1
auto[3355443200:3489660927]	9	1			T366	1		T367	1		T368	1
auto[3489660928:3623878655]	9	1			T125	1		T230	1		T78	1
auto[3623878656:3758096383]	9	1			T125	1		T76	1		T275	1
auto[3758096384:3892314111]	6	1			T217	1		T364	1		T291	1
auto[3892314112:4026531839]	7	1			T125	1		T78	1		T240	1
auto[4026531840:4160749567]	3	1			T143	1		T378	1		T376	1
auto[4160749568:4294967295]	5	1			T125	1		T378	1		T305	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33276	1			T1	25		T2	23		T3	35
auto[0:134217727]	auto[1]	11	1			T125	1		T126	2		T217	1
auto[134217728:268435455]	auto[1]	4	1			T239	1		T251	1		T376	1
auto[268435456:402653183]	auto[1]	7	1			T123	1		T230	1		T129	1
auto[402653184:536870911]	auto[1]	9	1			T366	2		T364	1		T291	1
auto[536870912:671088639]	auto[1]	5	1			T124	1		T78	1		T307	1
auto[671088640:805306367]	auto[1]	11	1			T142	2		T127	1		T76	2
auto[805306368:939524095]	auto[1]	10	1			T124	1		T126	1		T230	1
auto[939524096:1073741823]	auto[1]	6	1			T126	1		T230	1		T76	1
auto[1073741824:1207959551]	auto[1]	7	1			T124	1		T126	1		T364	1
auto[1207959552:1342177279]	auto[1]	6	1			T142	1		T291	1		T239	1
auto[1342177280:1476395007]	auto[1]	7	1			T124	1		T78	1		T129	2
auto[1476395008:1610612735]	auto[1]	2	1			T76	1		T377	1		-	-
auto[1610612736:1744830463]	auto[1]	6	1			T126	1		T275	1		T364	1
auto[1744830464:1879048191]	auto[1]	7	1			T230	1		T127	3		T366	1
auto[1879048192:2013265919]	auto[1]	9	1			T126	1		T143	1		T275	1
auto[2013265920:2147483647]	auto[1]	10	1			T125	1		T364	1		T367	1
auto[2147483648:2281701375]	auto[1]	8	1			T367	1		T291	1		T307	2
auto[2281701376:2415919103]	auto[1]	10	1			T230	1		T127	1		T78	1
auto[2415919104:2550136831]	auto[1]	6	1			T143	1		T78	1		T275	1
auto[2550136832:2684354559]	auto[1]	13	1			T143	1		T76	1		T275	1
auto[2684354560:2818572287]	auto[1]	12	1			T230	1		T127	1		T76	1
auto[2818572288:2952790015]	auto[1]	9	1			T127	2		T275	1		T307	1
auto[2952790016:3087007743]	auto[1]	8	1			T124	1		T125	1		T142	1
auto[3087007744:3221225471]	auto[1]	8	1			T76	2		T78	1		T307	1
auto[3221225472:3355443199]	auto[1]	8	1			T123	1		T76	1		T305	1
auto[3355443200:3489660927]	auto[1]	9	1			T366	1		T367	1		T368	1
auto[3489660928:3623878655]	auto[1]	9	1			T125	1		T230	1		T78	1
auto[3623878656:3758096383]	auto[1]	9	1			T125	1		T76	1		T275	1
auto[3758096384:3892314111]	auto[1]	6	1			T217	1		T364	1		T291	1
auto[3892314112:4026531839]	auto[1]	7	1			T125	1		T78	1		T240	1
auto[4026531840:4160749567]	auto[1]	3	1			T143	1		T378	1		T376	1
auto[4160749568:4294967295]	auto[1]	5	1			T125	1		T378	1		T305	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1697

1

T3

3

T12

5

T13

6

auto[1]

1788

1

T2

1

T3

1

T7

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T12	2		T23	2		T122	1
auto[134217728:268435455]	110	1			T23	1		T48	1		T182	2
auto[268435456:402653183]	94	1			T13	1		T49	2		T140	1
auto[402653184:536870911]	112	1			T15	1		T34	1		T23	1
auto[536870912:671088639]	118	1			T13	1		T37	1		T122	1
auto[671088640:805306367]	98	1			T34	2		T35	1		T21	1
auto[805306368:939524095]	125	1			T16	1		T23	3		T120	1
auto[939524096:1073741823]	108	1			T12	1		T13	1		T26	1
auto[1073741824:1207959551]	97	1			T33	1		T49	1		T23	1
auto[1207959552:1342177279]	102	1			T7	1		T12	2		T13	1
auto[1342177280:1476395007]	126	1			T13	1		T23	3		T137	1
auto[1476395008:1610612735]	114	1			T3	1		T15	1		T16	2
auto[1610612736:1744830463]	120	1			T3	1		T16	1		T23	1
auto[1744830464:1879048191]	103	1			T12	1		T23	1		T51	1
auto[1879048192:2013265919]	101	1			T3	1		T12	1		T15	2
auto[2013265920:2147483647]	124	1			T15	1		T16	1		T23	2
auto[2147483648:2281701375]	115	1			T12	2		T13	2		T15	1
auto[2281701376:2415919103]	99	1			T23	2		T137	1		T57	1
auto[2415919104:2550136831]	101	1			T12	1		T23	3		T59	1
auto[2550136832:2684354559]	133	1			T3	1		T12	1		T15	1
auto[2684354560:2818572287]	107	1			T34	1		T37	1		T26	1
auto[2818572288:2952790015]	123	1			T12	2		T13	1		T23	1
auto[2952790016:3087007743]	93	1			T12	1		T21	1		T230	1
auto[3087007744:3221225471]	109	1			T16	1		T23	1		T218	1
auto[3221225472:3355443199]	100	1			T35	1		T57	1		T182	1
auto[3355443200:3489660927]	106	1			T16	1		T23	3		T140	1
auto[3489660928:3623878655]	113	1			T2	1		T33	1		T34	1
auto[3623878656:3758096383]	109	1			T12	1		T33	1		T49	1
auto[3758096384:3892314111]	126	1			T34	1		T35	2		T184	1
auto[3892314112:4026531839]	96	1			T13	1		T23	4		T120	1
auto[4026531840:4160749567]	100	1			T23	1		T140	1		T120	1
auto[4160749568:4294967295]	91	1			T15	1		T37	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T12	1		T184	1		T182	1
auto[0:134217727]	auto[1]	55	1			T12	1		T23	2		T122	1
auto[134217728:268435455]	auto[0]	53	1			T182	1		T352	1		T5	1
auto[134217728:268435455]	auto[1]	57	1			T23	1		T48	1		T182	1
auto[268435456:402653183]	auto[0]	47	1			T49	1		T122	1		T127	1
auto[268435456:402653183]	auto[1]	47	1			T13	1		T49	1		T140	1
auto[402653184:536870911]	auto[0]	56	1			T15	1		T34	1		T126	1
auto[402653184:536870911]	auto[1]	56	1			T23	1		T122	2		T218	1
auto[536870912:671088639]	auto[0]	55	1			T13	1		T37	1		T122	1
auto[536870912:671088639]	auto[1]	63	1			T59	1		T143	1		T47	1
auto[671088640:805306367]	auto[0]	48	1			T34	1		T35	1		T21	1
auto[671088640:805306367]	auto[1]	50	1			T34	1		T236	1		T195	1
auto[805306368:939524095]	auto[0]	58	1			T16	1		T23	1		T120	1
auto[805306368:939524095]	auto[1]	67	1			T23	2		T192	1		T59	1
auto[939524096:1073741823]	auto[0]	54	1			T137	1		T182	1		T58	1
auto[939524096:1073741823]	auto[1]	54	1			T12	1		T13	1		T26	1
auto[1073741824:1207959551]	auto[0]	50	1			T33	1		T49	1		T23	1
auto[1073741824:1207959551]	auto[1]	47	1			T48	1		T142	1		T352	1
auto[1207959552:1342177279]	auto[0]	42	1			T13	1		T23	1		T35	1
auto[1207959552:1342177279]	auto[1]	60	1			T7	1		T12	2		T137	1
auto[1342177280:1476395007]	auto[0]	52	1			T13	1		T23	2		T140	1
auto[1342177280:1476395007]	auto[1]	74	1			T23	1		T137	1		T21	1
auto[1476395008:1610612735]	auto[0]	59	1			T3	1		T15	1		T16	2
auto[1476395008:1610612735]	auto[1]	55	1			T37	1		T23	2		T22	1
auto[1610612736:1744830463]	auto[0]	64	1			T3	1		T140	1		T57	1
auto[1610612736:1744830463]	auto[1]	56	1			T16	1		T23	1		T192	1
auto[1744830464:1879048191]	auto[0]	42	1			T23	1		T17	1		T226	1
auto[1744830464:1879048191]	auto[1]	61	1			T12	1		T51	1		T125	1
auto[1879048192:2013265919]	auto[0]	44	1			T59	1		T236	1		T222	1
auto[1879048192:2013265919]	auto[1]	57	1			T3	1		T12	1		T15	2
auto[2013265920:2147483647]	auto[0]	56	1			T15	1		T21	1		T192	1
auto[2013265920:2147483647]	auto[1]	68	1			T16	1		T23	2		T46	1
auto[2147483648:2281701375]	auto[0]	51	1			T13	1		T34	1		T23	1
auto[2147483648:2281701375]	auto[1]	64	1			T12	2		T13	1		T15	1
auto[2281701376:2415919103]	auto[0]	51	1			T23	2		T59	1		T54	1
auto[2281701376:2415919103]	auto[1]	48	1			T137	1		T57	1		T54	1
auto[2415919104:2550136831]	auto[0]	43	1			T23	2		T174	1		T204	1
auto[2415919104:2550136831]	auto[1]	58	1			T12	1		T23	1		T59	1
auto[2550136832:2684354559]	auto[0]	71	1			T3	1		T12	1		T23	1
auto[2550136832:2684354559]	auto[1]	62	1			T15	1		T23	1		T57	1
auto[2684354560:2818572287]	auto[0]	49	1			T37	1		T26	1		T184	1
auto[2684354560:2818572287]	auto[1]	58	1			T34	1		T23	1		T72	1
auto[2818572288:2952790015]	auto[0]	54	1			T12	2		T13	1		T122	1
auto[2818572288:2952790015]	auto[1]	69	1			T23	1		T57	1		T4	1
auto[2952790016:3087007743]	auto[0]	43	1			T12	1		T21	1		T39	1
auto[2952790016:3087007743]	auto[1]	50	1			T230	1		T78	2		T47	1
auto[3087007744:3221225471]	auto[0]	55	1			T16	1		T218	1		T190	1
auto[3087007744:3221225471]	auto[1]	54	1			T23	1		T143	1		T54	1
auto[3221225472:3355443199]	auto[0]	55	1			T35	1		T182	1		T82	1
auto[3221225472:3355443199]	auto[1]	45	1			T57	1		T54	2		T77	1
auto[3355443200:3489660927]	auto[0]	51	1			T16	1		T23	2		T122	1
auto[3355443200:3489660927]	auto[1]	55	1			T23	1		T140	1		T54	1
auto[3489660928:3623878655]	auto[0]	64	1			T34	1		T38	2		T51	1
auto[3489660928:3623878655]	auto[1]	49	1			T2	1		T33	1		T4	1
auto[3623878656:3758096383]	auto[0]	57	1			T33	1		T49	1		T126	1
auto[3623878656:3758096383]	auto[1]	52	1			T12	1		T57	1		T124	1
auto[3758096384:3892314111]	auto[0]	67	1			T34	1		T35	1		T184	1
auto[3758096384:3892314111]	auto[1]	59	1			T35	1		T124	1		T195	1
auto[3892314112:4026531839]	auto[0]	46	1			T13	1		T23	1		T21	1
auto[3892314112:4026531839]	auto[1]	50	1			T23	3		T120	1		T85	1
auto[4026531840:4160749567]	auto[0]	55	1			T23	1		T51	1		T236	1
auto[4026531840:4160749567]	auto[1]	45	1			T140	1		T120	1		T184	1
auto[4160749568:4294967295]	auto[0]	48	1			T37	1		T49	1		T23	1
auto[4160749568:4294967295]	auto[1]	43	1			T15	1		T137	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1703

1

T3

3

T12

4

T13

6

auto[1]

1781

1

T2

1

T3

1

T7

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T13	1		T23	2		T35	1
auto[134217728:268435455]	119	1			T34	1		T23	3		T122	1
auto[268435456:402653183]	113	1			T13	1		T15	1		T137	1
auto[402653184:536870911]	117	1			T16	1		T33	1		T140	1
auto[536870912:671088639]	95	1			T3	1		T33	1		T23	1
auto[671088640:805306367]	91	1			T12	3		T13	1		T34	1
auto[805306368:939524095]	105	1			T2	1		T54	1		T72	1
auto[939524096:1073741823]	112	1			T3	1		T34	1		T26	1
auto[1073741824:1207959551]	112	1			T12	1		T16	1		T218	1
auto[1207959552:1342177279]	113	1			T15	1		T122	1		T21	1
auto[1342177280:1476395007]	98	1			T12	1		T13	1		T15	1
auto[1476395008:1610612735]	117	1			T34	1		T23	1		T184	1
auto[1610612736:1744830463]	116	1			T15	1		T23	1		T123	1
auto[1744830464:1879048191]	109	1			T7	1		T12	2		T33	1
auto[1879048192:2013265919]	122	1			T12	1		T13	1		T23	1
auto[2013265920:2147483647]	117	1			T12	1		T34	1		T23	1
auto[2147483648:2281701375]	96	1			T49	1		T59	1		T236	1
auto[2281701376:2415919103]	89	1			T23	1		T137	1		T4	1
auto[2415919104:2550136831]	111	1			T15	1		T49	1		T23	2
auto[2550136832:2684354559]	112	1			T15	1		T23	4		T192	1
auto[2684354560:2818572287]	116	1			T12	1		T15	1		T23	2
auto[2818572288:2952790015]	94	1			T3	1		T48	1		T218	1
auto[2952790016:3087007743]	99	1			T13	1		T37	1		T23	3
auto[3087007744:3221225471]	110	1			T16	1		T37	2		T49	1
auto[3221225472:3355443199]	121	1			T13	1		T34	1		T23	2
auto[3355443200:3489660927]	110	1			T3	1		T16	1		T34	1
auto[3489660928:3623878655]	122	1			T12	1		T16	1		T23	3
auto[3623878656:3758096383]	93	1			T16	1		T49	1		T23	2
auto[3758096384:3892314111]	114	1			T12	1		T15	1		T23	3
auto[3892314112:4026531839]	89	1			T12	1		T13	1		T35	1
auto[4026531840:4160749567]	114	1			T12	1		T13	1		T37	1
auto[4160749568:4294967295]	117	1			T12	1		T16	1		T35	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	68	1			T13	1		T23	1		T35	1
auto[0:134217727]	auto[1]	53	1			T23	1		T54	1		T183	1
auto[134217728:268435455]	auto[0]	62	1			T34	1		T23	3		T126	1
auto[134217728:268435455]	auto[1]	57	1			T122	1		T124	1		T59	1
auto[268435456:402653183]	auto[0]	55	1			T13	1		T183	2		T273	1
auto[268435456:402653183]	auto[1]	58	1			T15	1		T137	1		T244	1
auto[402653184:536870911]	auto[0]	59	1			T16	1		T33	1		T140	1
auto[402653184:536870911]	auto[1]	58	1			T192	1		T59	1		T46	1
auto[536870912:671088639]	auto[0]	42	1			T3	1		T140	1		T122	1
auto[536870912:671088639]	auto[1]	53	1			T33	1		T23	1		T57	1
auto[671088640:805306367]	auto[0]	35	1			T34	1		T35	1		T182	1
auto[671088640:805306367]	auto[1]	56	1			T12	3		T13	1		T26	1
auto[805306368:939524095]	auto[0]	45	1			T72	1		T56	1		T183	1
auto[805306368:939524095]	auto[1]	60	1			T2	1		T54	1		T56	1
auto[939524096:1073741823]	auto[0]	50	1			T3	1		T34	1		T26	1
auto[939524096:1073741823]	auto[1]	62	1			T23	1		T38	1		T195	1
auto[1073741824:1207959551]	auto[0]	54	1			T218	1		T58	1		T234	2
auto[1073741824:1207959551]	auto[1]	58	1			T12	1		T16	1		T76	1
auto[1207959552:1342177279]	auto[0]	57	1			T21	1		T127	1		T54	2
auto[1207959552:1342177279]	auto[1]	56	1			T15	1		T122	1		T230	1
auto[1342177280:1476395007]	auto[0]	50	1			T12	1		T15	1		T4	1
auto[1342177280:1476395007]	auto[1]	48	1			T13	1		T23	1		T48	1
auto[1476395008:1610612735]	auto[0]	60	1			T34	1		T23	1		T21	1
auto[1476395008:1610612735]	auto[1]	57	1			T184	1		T192	1		T59	1
auto[1610612736:1744830463]	auto[0]	57	1			T23	1		T123	1		T21	1
auto[1610612736:1744830463]	auto[1]	59	1			T15	1		T236	1		T127	1
auto[1744830464:1879048191]	auto[0]	48	1			T23	2		T57	1		T21	1
auto[1744830464:1879048191]	auto[1]	61	1			T7	1		T12	2		T33	1
auto[1879048192:2013265919]	auto[0]	55	1			T12	1		T13	1		T54	1
auto[1879048192:2013265919]	auto[1]	67	1			T23	1		T124	1		T125	1
auto[2013265920:2147483647]	auto[0]	67	1			T34	1		T57	1		T120	1
auto[2013265920:2147483647]	auto[1]	50	1			T12	1		T23	1		T137	1
auto[2147483648:2281701375]	auto[0]	47	1			T49	1		T236	1		T190	1
auto[2147483648:2281701375]	auto[1]	49	1			T59	1		T142	1		T72	1
auto[2281701376:2415919103]	auto[0]	40	1			T48	1		T51	1		T54	1
auto[2281701376:2415919103]	auto[1]	49	1			T23	1		T137	1		T4	1
auto[2415919104:2550136831]	auto[0]	57	1			T49	1		T23	1		T192	1
auto[2415919104:2550136831]	auto[1]	54	1			T15	1		T23	1		T57	1
auto[2550136832:2684354559]	auto[0]	55	1			T23	1		T182	1		T78	1
auto[2550136832:2684354559]	auto[1]	57	1			T15	1		T23	3		T192	1
auto[2684354560:2818572287]	auto[0]	54	1			T15	1		T23	2		T140	1
auto[2684354560:2818572287]	auto[1]	62	1			T12	1		T137	1		T59	1
auto[2818572288:2952790015]	auto[0]	52	1			T218	1		T236	2		T53	1
auto[2818572288:2952790015]	auto[1]	42	1			T3	1		T48	1		T22	1
auto[2952790016:3087007743]	auto[0]	49	1			T13	1		T37	1		T23	1
auto[2952790016:3087007743]	auto[1]	50	1			T23	2		T120	1		T184	1
auto[3087007744:3221225471]	auto[0]	50	1			T16	1		T37	1		T142	1
auto[3087007744:3221225471]	auto[1]	60	1			T37	1		T49	1		T140	1
auto[3221225472:3355443199]	auto[0]	72	1			T13	1		T34	1		T23	1
auto[3221225472:3355443199]	auto[1]	49	1			T23	1		T54	1		T174	2
auto[3355443200:3489660927]	auto[0]	54	1			T3	1		T16	1		T49	1
auto[3355443200:3489660927]	auto[1]	56	1			T34	1		T35	1		T57	1
auto[3489660928:3623878655]	auto[0]	66	1			T122	1		T142	1		T54	1
auto[3489660928:3623878655]	auto[1]	56	1			T12	1		T16	1		T23	3
auto[3623878656:3758096383]	auto[0]	42	1			T16	1		T49	1		T23	1
auto[3623878656:3758096383]	auto[1]	51	1			T23	1		T57	1		T51	1
auto[3758096384:3892314111]	auto[0]	52	1			T12	1		T15	1		T59	1
auto[3758096384:3892314111]	auto[1]	62	1			T23	3		T137	1		T184	1
auto[3892314112:4026531839]	auto[0]	39	1			T59	1		T127	1		T58	1
auto[3892314112:4026531839]	auto[1]	50	1			T12	1		T13	1		T35	1
auto[4026531840:4160749567]	auto[0]	60	1			T12	1		T13	1		T37	1
auto[4026531840:4160749567]	auto[1]	54	1			T23	1		T218	1		T182	1
auto[4160749568:4294967295]	auto[0]	50	1			T16	1		T21	2		T236	1
auto[4160749568:4294967295]	auto[1]	67	1			T12	1		T35	1		T124	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1707

1

T3

3

T12

6

T13

6

auto[1]

1778

1

T2

1

T3

1

T7

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T12	1		T49	1		T23	2
auto[134217728:268435455]	103	1			T3	1		T23	1		T35	1
auto[268435456:402653183]	114	1			T37	1		T49	1		T23	2
auto[402653184:536870911]	81	1			T12	1		T23	2		T120	1
auto[536870912:671088639]	118	1			T15	1		T23	2		T122	1
auto[671088640:805306367]	119	1			T15	1		T23	2		T35	1
auto[805306368:939524095]	105	1			T12	1		T15	1		T23	3
auto[939524096:1073741823]	123	1			T12	1		T13	1		T15	1
auto[1073741824:1207959551]	104	1			T3	1		T48	1		T143	1
auto[1207959552:1342177279]	107	1			T2	1		T16	1		T35	1
auto[1342177280:1476395007]	113	1			T37	1		T48	1		T51	1
auto[1476395008:1610612735]	108	1			T12	2		T37	1		T122	1
auto[1610612736:1744830463]	105	1			T34	1		T137	1		T140	1
auto[1744830464:1879048191]	110	1			T12	1		T23	1		T126	1
auto[1879048192:2013265919]	106	1			T13	1		T16	1		T33	1
auto[2013265920:2147483647]	128	1			T12	1		T13	1		T16	1
auto[2147483648:2281701375]	111	1			T3	1		T15	1		T34	1
auto[2281701376:2415919103]	114	1			T12	1		T13	1		T15	1
auto[2415919104:2550136831]	103	1			T35	1		T57	1		T190	2
auto[2550136832:2684354559]	104	1			T12	1		T33	1		T49	1
auto[2684354560:2818572287]	104	1			T23	2		T122	1		T21	1
auto[2818572288:2952790015]	116	1			T13	1		T37	1		T23	3
auto[2952790016:3087007743]	104	1			T12	1		T23	2		T35	1
auto[3087007744:3221225471]	115	1			T23	1		T137	1		T140	1
auto[3221225472:3355443199]	108	1			T13	1		T15	1		T57	1
auto[3355443200:3489660927]	81	1			T23	2		T236	1		T143	1
auto[3489660928:3623878655]	116	1			T23	4		T140	1		T48	1
auto[3623878656:3758096383]	129	1			T3	1		T12	2		T13	2
auto[3758096384:3892314111]	101	1			T7	1		T13	1		T16	1
auto[3892314112:4026531839]	106	1			T12	1		T16	1		T125	1
auto[4026531840:4160749567]	115	1			T12	1		T21	2		T244	1
auto[4160749568:4294967295]	105	1			T16	1		T34	1		T140	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T12	1		T49	1		T23	1
auto[0:134217727]	auto[1]	56	1			T23	1		T137	1		T38	1
auto[134217728:268435455]	auto[0]	55	1			T23	1		T51	1		T59	1
auto[134217728:268435455]	auto[1]	48	1			T3	1		T35	1		T46	1
auto[268435456:402653183]	auto[0]	56	1			T37	1		T49	1		T23	2
auto[268435456:402653183]	auto[1]	58	1			T218	1		T59	1		T54	1
auto[402653184:536870911]	auto[0]	45	1			T23	1		T124	1		T126	2
auto[402653184:536870911]	auto[1]	36	1			T12	1		T23	1		T120	1
auto[536870912:671088639]	auto[0]	51	1			T122	1		T236	1		T53	1
auto[536870912:671088639]	auto[1]	67	1			T15	1		T23	2		T126	1
auto[671088640:805306367]	auto[0]	58	1			T15	1		T35	1		T140	1
auto[671088640:805306367]	auto[1]	61	1			T23	2		T192	1		T59	1
auto[805306368:939524095]	auto[0]	46	1			T15	1		T4	1		T142	1
auto[805306368:939524095]	auto[1]	59	1			T12	1		T23	3		T54	1
auto[939524096:1073741823]	auto[0]	63	1			T12	1		T13	1		T16	1
auto[939524096:1073741823]	auto[1]	60	1			T15	1		T184	1		T124	1
auto[1073741824:1207959551]	auto[0]	44	1			T3	1		T53	1		T5	1
auto[1073741824:1207959551]	auto[1]	60	1			T48	1		T143	1		T54	2
auto[1207959552:1342177279]	auto[0]	64	1			T16	1		T35	1		T123	1
auto[1207959552:1342177279]	auto[1]	43	1			T2	1		T71	1		T183	1
auto[1342177280:1476395007]	auto[0]	59	1			T37	1		T226	1		T5	1
auto[1342177280:1476395007]	auto[1]	54	1			T48	1		T51	1		T192	1
auto[1476395008:1610612735]	auto[0]	59	1			T12	1		T122	1		T218	1
auto[1476395008:1610612735]	auto[1]	49	1			T12	1		T37	1		T218	1
auto[1610612736:1744830463]	auto[0]	49	1			T34	1		T21	1		T59	1
auto[1610612736:1744830463]	auto[1]	56	1			T137	1		T140	1		T54	1
auto[1744830464:1879048191]	auto[0]	54	1			T23	1		T126	1		T127	1
auto[1744830464:1879048191]	auto[1]	56	1			T12	1		T59	1		T174	1
auto[1879048192:2013265919]	auto[0]	53	1			T13	1		T16	1		T34	1
auto[1879048192:2013265919]	auto[1]	53	1			T33	1		T23	2		T21	1
auto[2013265920:2147483647]	auto[0]	61	1			T34	1		T49	1		T142	1
auto[2013265920:2147483647]	auto[1]	67	1			T12	1		T13	1		T16	1
auto[2147483648:2281701375]	auto[0]	56	1			T3	1		T34	1		T184	1
auto[2147483648:2281701375]	auto[1]	55	1			T15	1		T23	1		T195	1
auto[2281701376:2415919103]	auto[0]	57	1			T12	1		T23	2		T122	1
auto[2281701376:2415919103]	auto[1]	57	1			T13	1		T15	1		T33	1
auto[2415919104:2550136831]	auto[0]	51	1			T190	2		T54	2		T183	2
auto[2415919104:2550136831]	auto[1]	52	1			T35	1		T57	1		T78	1
auto[2550136832:2684354559]	auto[0]	51	1			T12	1		T33	1		T49	1
auto[2550136832:2684354559]	auto[1]	53	1			T23	2		T195	1		T54	1
auto[2684354560:2818572287]	auto[0]	48	1			T23	1		T122	1		T21	1
auto[2684354560:2818572287]	auto[1]	56	1			T23	1		T124	1		T85	1
auto[2818572288:2952790015]	auto[0]	55	1			T23	1		T54	1		T95	1
auto[2818572288:2952790015]	auto[1]	61	1			T13	1		T37	1		T23	2
auto[2952790016:3087007743]	auto[0]	56	1			T23	1		T35	1		T142	1
auto[2952790016:3087007743]	auto[1]	48	1			T12	1		T23	1		T137	1
auto[3087007744:3221225471]	auto[0]	54	1			T23	1		T122	1		T184	1
auto[3087007744:3221225471]	auto[1]	61	1			T137	1		T140	1		T57	1
auto[3221225472:3355443199]	auto[0]	50	1			T13	1		T57	1		T125	1
auto[3221225472:3355443199]	auto[1]	58	1			T15	1		T122	1		T142	1
auto[3355443200:3489660927]	auto[0]	41	1			T23	1		T236	1		T24	1
auto[3355443200:3489660927]	auto[1]	40	1			T23	1		T143	1		T237	1
auto[3489660928:3623878655]	auto[0]	59	1			T23	2		T140	1		T122	1
auto[3489660928:3623878655]	auto[1]	57	1			T23	2		T48	1		T59	1
auto[3623878656:3758096383]	auto[0]	59	1			T3	1		T12	1		T13	2
auto[3623878656:3758096383]	auto[1]	70	1			T12	1		T15	1		T34	1
auto[3758096384:3892314111]	auto[0]	44	1			T13	1		T16	1		T49	1
auto[3758096384:3892314111]	auto[1]	57	1			T7	1		T34	1		T137	1
auto[3892314112:4026531839]	auto[0]	50	1			T16	1		T182	1		T54	1
auto[3892314112:4026531839]	auto[1]	56	1			T12	1		T125	1		T58	1
auto[4026531840:4160749567]	auto[0]	65	1			T21	1		T182	1		T230	1
auto[4026531840:4160749567]	auto[1]	50	1			T12	1		T21	1		T244	1
auto[4160749568:4294967295]	auto[0]	41	1			T21	1		T182	1		T127	1
auto[4160749568:4294967295]	auto[1]	64	1			T16	1		T34	1		T140	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1685

1

T3

3

T12

7

T13

6

auto[1]

1800

1

T2

1

T3

1

T7

1