Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3076

1

T2

1

T3

4

T7

1

auto[1]

270

1

T123

7

T124

2

T125

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T23	2		T122	1		T125	1
auto[134217728:268435455]	96	1			T37	1		T23	1		T140	1
auto[268435456:402653183]	104	1			T13	1		T34	1		T23	2
auto[402653184:536870911]	108	1			T13	1		T57	1		T122	1
auto[536870912:671088639]	102	1			T15	2		T16	1		T33	1
auto[671088640:805306367]	109	1			T12	1		T35	1		T122	1
auto[805306368:939524095]	126	1			T15	1		T49	1		T137	2
auto[939524096:1073741823]	113	1			T15	1		T33	1		T23	1
auto[1073741824:1207959551]	123	1			T13	1		T23	2		T137	1
auto[1207959552:1342177279]	98	1			T3	1		T35	1		T124	1
auto[1342177280:1476395007]	97	1			T2	1		T12	2		T37	1
auto[1476395008:1610612735]	105	1			T12	1		T23	3		T218	1
auto[1610612736:1744830463]	90	1			T23	1		T35	1		T137	1
auto[1744830464:1879048191]	85	1			T23	1		T236	1		T143	1
auto[1879048192:2013265919]	106	1			T12	1		T4	1		T48	1
auto[2013265920:2147483647]	96	1			T12	1		T35	1		T123	1
auto[2147483648:2281701375]	102	1			T15	1		T23	1		T184	1
auto[2281701376:2415919103]	110	1			T3	1		T12	1		T13	1
auto[2415919104:2550136831]	88	1			T143	1		T127	1		T54	3
auto[2550136832:2684354559]	98	1			T12	1		T33	1		T37	1
auto[2684354560:2818572287]	112	1			T3	1		T12	1		T48	1
auto[2818572288:2952790015]	109	1			T3	1		T12	2		T16	1
auto[2952790016:3087007743]	110	1			T7	1		T12	1		T13	1
auto[3087007744:3221225471]	112	1			T34	1		T23	2		T184	1
auto[3221225472:3355443199]	109	1			T120	2		T184	1		T236	1
auto[3355443200:3489660927]	122	1			T34	1		T23	3		T123	1
auto[3489660928:3623878655]	96	1			T12	1		T49	2		T23	2
auto[3623878656:3758096383]	101	1			T34	2		T23	2		T140	1
auto[3758096384:3892314111]	109	1			T12	2		T16	1		T23	1
auto[3892314112:4026531839]	86	1			T15	2		T16	1		T34	1
auto[4026531840:4160749567]	97	1			T26	1		T23	1		T120	1
auto[4160749568:4294967295]	130	1			T23	2		T21	1		T218	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	87	1			T23	2		T122	1		T59	2
auto[0:134217727]	auto[1]	10	1			T125	1		T364	1		T277	2
auto[134217728:268435455]	auto[0]	84	1			T37	1		T23	1		T140	1
auto[134217728:268435455]	auto[1]	12	1			T123	1		T76	2		T364	1
auto[268435456:402653183]	auto[0]	97	1			T13	1		T34	1		T23	2
auto[268435456:402653183]	auto[1]	7	1			T123	1		T125	1		T126	1
auto[402653184:536870911]	auto[0]	99	1			T13	1		T57	1		T122	1
auto[402653184:536870911]	auto[1]	9	1			T143	1		T366	1		T364	1
auto[536870912:671088639]	auto[0]	94	1			T15	2		T16	1		T33	1
auto[536870912:671088639]	auto[1]	8	1			T125	1		T76	1		T275	1
auto[671088640:805306367]	auto[0]	99	1			T12	1		T35	1		T122	1
auto[671088640:805306367]	auto[1]	10	1			T275	1		T217	2		T366	1
auto[805306368:939524095]	auto[0]	117	1			T15	1		T49	1		T137	2
auto[805306368:939524095]	auto[1]	9	1			T125	1		T127	1		T217	2
auto[939524096:1073741823]	auto[0]	107	1			T15	1		T33	1		T23	1
auto[939524096:1073741823]	auto[1]	6	1			T123	1		T240	1		T305	1
auto[1073741824:1207959551]	auto[0]	111	1			T13	1		T23	2		T137	1
auto[1073741824:1207959551]	auto[1]	12	1			T123	1		T125	1		T230	1
auto[1207959552:1342177279]	auto[0]	94	1			T3	1		T35	1		T124	1
auto[1207959552:1342177279]	auto[1]	4	1			T78	1		T275	1		T364	1
auto[1342177280:1476395007]	auto[0]	91	1			T2	1		T12	2		T37	1
auto[1342177280:1476395007]	auto[1]	6	1			T127	1		T78	1		T367	1
auto[1476395008:1610612735]	auto[0]	99	1			T12	1		T23	3		T218	1
auto[1476395008:1610612735]	auto[1]	6	1			T277	1		T380	1		T305	1
auto[1610612736:1744830463]	auto[0]	79	1			T23	1		T35	1		T137	1
auto[1610612736:1744830463]	auto[1]	11	1			T124	1		T126	1		T127	1
auto[1744830464:1879048191]	auto[0]	77	1			T23	1		T236	1		T143	1
auto[1744830464:1879048191]	auto[1]	8	1			T275	1		T277	1		T380	1
auto[1879048192:2013265919]	auto[0]	99	1			T12	1		T4	1		T48	1
auto[1879048192:2013265919]	auto[1]	7	1			T123	1		T129	1		T366	1
auto[2013265920:2147483647]	auto[0]	85	1			T12	1		T35	1		T124	1
auto[2013265920:2147483647]	auto[1]	11	1			T123	1		T364	2		T277	1
auto[2147483648:2281701375]	auto[0]	94	1			T15	1		T23	1		T184	1
auto[2147483648:2281701375]	auto[1]	8	1			T127	2		T76	2		T307	1
auto[2281701376:2415919103]	auto[0]	104	1			T3	1		T12	1		T13	1
auto[2281701376:2415919103]	auto[1]	6	1			T127	1		T367	1		T239	1
auto[2415919104:2550136831]	auto[0]	80	1			T54	3		T72	1		T56	1
auto[2415919104:2550136831]	auto[1]	8	1			T143	1		T127	1		T291	1
auto[2550136832:2684354559]	auto[0]	90	1			T12	1		T33	1		T37	1
auto[2550136832:2684354559]	auto[1]	8	1			T142	1		T275	1		T367	1
auto[2684354560:2818572287]	auto[0]	103	1			T3	1		T12	1		T48	1
auto[2684354560:2818572287]	auto[1]	9	1			T127	1		T76	1		T275	1
auto[2818572288:2952790015]	auto[0]	96	1			T3	1		T12	2		T16	1
auto[2818572288:2952790015]	auto[1]	13	1			T123	1		T217	1		T366	1
auto[2952790016:3087007743]	auto[0]	104	1			T7	1		T12	1		T13	1
auto[2952790016:3087007743]	auto[1]	6	1			T125	1		T126	1		T217	1
auto[3087007744:3221225471]	auto[0]	105	1			T34	1		T23	2		T184	1
auto[3087007744:3221225471]	auto[1]	7	1			T230	1		T78	1		T275	1
auto[3221225472:3355443199]	auto[0]	99	1			T120	2		T184	1		T236	1
auto[3221225472:3355443199]	auto[1]	10	1			T127	1		T129	2		T291	1
auto[3355443200:3489660927]	auto[0]	112	1			T34	1		T23	3		T123	1
auto[3355443200:3489660927]	auto[1]	10	1			T126	1		T143	1		T217	1
auto[3489660928:3623878655]	auto[0]	87	1			T12	1		T49	2		T23	2
auto[3489660928:3623878655]	auto[1]	9	1			T143	1		T129	1		T366	1
auto[3623878656:3758096383]	auto[0]	90	1			T34	2		T23	2		T140	1
auto[3623878656:3758096383]	auto[1]	11	1			T124	1		T275	2		T217	1
auto[3758096384:3892314111]	auto[0]	102	1			T12	2		T16	1		T23	1
auto[3758096384:3892314111]	auto[1]	7	1			T127	1		T379	1		T380	1
auto[3892314112:4026531839]	auto[0]	80	1			T15	2		T16	1		T34	1
auto[3892314112:4026531839]	auto[1]	6	1			T78	1		T217	1		T380	2
auto[4026531840:4160749567]	auto[0]	91	1			T26	1		T23	1		T120	1
auto[4026531840:4160749567]	auto[1]	6	1			T76	1		T78	1		T291	1
auto[4160749568:4294967295]	auto[0]	120	1			T23	2		T21	1		T218	1
auto[4160749568:4294967295]	auto[1]	10	1			T240	1		T368	1		T228	1