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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3078 1 T2 1 T3 4 T7 1
auto[1] 275 1 T123 8 T124 5 T125 9



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 113 1 T4 1 T51 1 T124 1
auto[134217728:268435455] 83 1 T49 1 T23 2 T35 1
auto[268435456:402653183] 94 1 T12 1 T13 1 T33 1
auto[402653184:536870911] 109 1 T3 1 T12 1 T23 1
auto[536870912:671088639] 114 1 T12 1 T16 2 T49 1
auto[671088640:805306367] 114 1 T12 1 T16 1 T23 1
auto[805306368:939524095] 116 1 T12 1 T34 1 T23 2
auto[939524096:1073741823] 120 1 T12 1 T15 1 T37 1
auto[1073741824:1207959551] 93 1 T33 1 T140 1 T236 2
auto[1207959552:1342177279] 113 1 T13 1 T23 1 T126 1
auto[1342177280:1476395007] 97 1 T15 1 T23 1 T35 1
auto[1476395008:1610612735] 100 1 T16 2 T137 1 T21 1
auto[1610612736:1744830463] 110 1 T15 1 T35 1 T184 1
auto[1744830464:1879048191] 106 1 T34 1 T21 1 T59 1
auto[1879048192:2013265919] 118 1 T37 1 T49 1 T23 2
auto[2013265920:2147483647] 116 1 T12 2 T37 1 T23 1
auto[2147483648:2281701375] 81 1 T13 1 T16 1 T26 1
auto[2281701376:2415919103] 111 1 T7 1 T13 1 T37 1
auto[2415919104:2550136831] 115 1 T12 1 T15 1 T123 1
auto[2550136832:2684354559] 102 1 T49 1 T23 3 T124 1
auto[2684354560:2818572287] 104 1 T23 1 T122 3 T21 1
auto[2818572288:2952790015] 113 1 T12 1 T23 2 T125 1
auto[2952790016:3087007743] 105 1 T3 2 T35 1 T48 1
auto[3087007744:3221225471] 87 1 T13 1 T34 1 T35 1
auto[3221225472:3355443199] 116 1 T34 1 T38 1 T120 1
auto[3355443200:3489660927] 91 1 T15 2 T49 1 T23 1
auto[3489660928:3623878655] 91 1 T127 1 T58 1 T82 1
auto[3623878656:3758096383] 95 1 T3 1 T12 1 T15 2
auto[3758096384:3892314111] 108 1 T12 1 T23 3 T21 2
auto[3892314112:4026531839] 92 1 T12 2 T33 1 T34 1
auto[4026531840:4160749567] 125 1 T12 1 T23 3 T57 1
auto[4160749568:4294967295] 101 1 T2 1 T34 1 T23 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 102 1 T4 1 T51 1 T124 1
auto[0:134217727] auto[1] 11 1 T142 1 T127 1 T78 1
auto[134217728:268435455] auto[0] 75 1 T49 1 T23 2 T35 1
auto[134217728:268435455] auto[1] 8 1 T125 1 T366 1 T367 1
auto[268435456:402653183] auto[0] 89 1 T12 1 T13 1 T33 1
auto[268435456:402653183] auto[1] 5 1 T364 1 T305 1 T388 1
auto[402653184:536870911] auto[0] 102 1 T3 1 T12 1 T23 1
auto[402653184:536870911] auto[1] 7 1 T124 1 T76 1 T240 1
auto[536870912:671088639] auto[0] 100 1 T12 1 T16 2 T49 1
auto[536870912:671088639] auto[1] 14 1 T123 1 T125 1 T127 1
auto[671088640:805306367] auto[0] 102 1 T12 1 T16 1 T23 1
auto[671088640:805306367] auto[1] 12 1 T230 1 T127 1 T76 1
auto[805306368:939524095] auto[0] 105 1 T12 1 T34 1 T23 2
auto[805306368:939524095] auto[1] 11 1 T123 1 T124 1 T129 1
auto[939524096:1073741823] auto[0] 111 1 T12 1 T15 1 T37 1
auto[939524096:1073741823] auto[1] 9 1 T126 1 T275 1 T129 1
auto[1073741824:1207959551] auto[0] 89 1 T33 1 T140 1 T236 2
auto[1073741824:1207959551] auto[1] 4 1 T239 1 T376 1 T386 2
auto[1207959552:1342177279] auto[0] 105 1 T13 1 T23 1 T59 1
auto[1207959552:1342177279] auto[1] 8 1 T126 1 T127 1 T76 1
auto[1342177280:1476395007] auto[0] 90 1 T15 1 T23 1 T35 1
auto[1342177280:1476395007] auto[1] 7 1 T275 1 T367 2 T389 1
auto[1476395008:1610612735] auto[0] 96 1 T16 2 T137 1 T21 1
auto[1476395008:1610612735] auto[1] 4 1 T125 1 T143 1 T275 1
auto[1610612736:1744830463] auto[0] 103 1 T15 1 T35 1 T184 1
auto[1610612736:1744830463] auto[1] 7 1 T78 1 T239 1 T251 2
auto[1744830464:1879048191] auto[0] 100 1 T34 1 T21 1 T59 1
auto[1744830464:1879048191] auto[1] 6 1 T76 1 T78 1 T239 1
auto[1879048192:2013265919] auto[0] 106 1 T37 1 T49 1 T23 2
auto[1879048192:2013265919] auto[1] 12 1 T123 1 T125 1 T142 1
auto[2013265920:2147483647] auto[0] 104 1 T12 2 T37 1 T23 1
auto[2013265920:2147483647] auto[1] 12 1 T123 1 T126 1 T143 1
auto[2147483648:2281701375] auto[0] 74 1 T13 1 T16 1 T26 1
auto[2147483648:2281701375] auto[1] 7 1 T124 1 T327 1 T379 1
auto[2281701376:2415919103] auto[0] 103 1 T7 1 T13 1 T37 1
auto[2281701376:2415919103] auto[1] 8 1 T366 1 T277 1 T327 1
auto[2415919104:2550136831] auto[0] 106 1 T12 1 T15 1 T184 1
auto[2415919104:2550136831] auto[1] 9 1 T123 1 T76 1 T364 1
auto[2550136832:2684354559] auto[0] 95 1 T49 1 T23 3 T54 1
auto[2550136832:2684354559] auto[1] 7 1 T124 1 T78 1 T275 1
auto[2684354560:2818572287] auto[0] 98 1 T23 1 T122 3 T21 1
auto[2684354560:2818572287] auto[1] 6 1 T126 1 T366 1 T291 1
auto[2818572288:2952790015] auto[0] 101 1 T12 1 T23 2 T236 1
auto[2818572288:2952790015] auto[1] 12 1 T125 1 T129 1 T217 1
auto[2952790016:3087007743] auto[0] 99 1 T3 2 T35 1 T48 1
auto[2952790016:3087007743] auto[1] 6 1 T123 1 T78 1 T251 1
auto[3087007744:3221225471] auto[0] 79 1 T13 1 T34 1 T35 1
auto[3087007744:3221225471] auto[1] 8 1 T367 1 T291 1 T239 1
auto[3221225472:3355443199] auto[0] 109 1 T34 1 T38 1 T120 1
auto[3221225472:3355443199] auto[1] 7 1 T123 1 T127 1 T275 1
auto[3355443200:3489660927] auto[0] 81 1 T15 2 T49 1 T23 1
auto[3355443200:3489660927] auto[1] 10 1 T143 1 T127 1 T78 2
auto[3489660928:3623878655] auto[0] 78 1 T127 1 T58 1 T82 1
auto[3489660928:3623878655] auto[1] 13 1 T217 1 T240 1 T364 1
auto[3623878656:3758096383] auto[0] 88 1 T3 1 T12 1 T15 2
auto[3623878656:3758096383] auto[1] 7 1 T327 1 T291 1 T380 1
auto[3758096384:3892314111] auto[0] 100 1 T12 1 T23 3 T21 2
auto[3758096384:3892314111] auto[1] 8 1 T124 1 T275 2 T129 1
auto[3892314112:4026531839] auto[0] 83 1 T12 2 T33 1 T34 1
auto[3892314112:4026531839] auto[1] 9 1 T125 1 T275 1 T239 1
auto[4026531840:4160749567] auto[0] 114 1 T12 1 T23 3 T57 1
auto[4026531840:4160749567] auto[1] 11 1 T123 1 T125 1 T366 1
auto[4160749568:4294967295] auto[0] 91 1 T2 1 T34 1 T23 1
auto[4160749568:4294967295] auto[1] 10 1 T125 2 T127 1 T76 1

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